1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * VFIO PCI config space virtualization 4 * 5 * Copyright (C) 2012 Red Hat, Inc. All rights reserved. 6 * Author: Alex Williamson <alex.williamson@redhat.com> 7 * 8 * Derived from original vfio: 9 * Copyright 2010 Cisco Systems, Inc. All rights reserved. 10 * Author: Tom Lyon, pugs@cisco.com 11 */ 12 13 /* 14 * This code handles reading and writing of PCI configuration registers. 15 * This is hairy because we want to allow a lot of flexibility to the 16 * user driver, but cannot trust it with all of the config fields. 17 * Tables determine which fields can be read and written, as well as 18 * which fields are 'virtualized' - special actions and translations to 19 * make it appear to the user that he has control, when in fact things 20 * must be negotiated with the underlying OS. 21 */ 22 23 #include <linux/fs.h> 24 #include <linux/pci.h> 25 #include <linux/uaccess.h> 26 #include <linux/vfio.h> 27 #include <linux/slab.h> 28 29 #include "vfio_pci_private.h" 30 31 /* Fake capability ID for standard config space */ 32 #define PCI_CAP_ID_BASIC 0 33 34 #define is_bar(offset) \ 35 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \ 36 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4)) 37 38 /* 39 * Lengths of PCI Config Capabilities 40 * 0: Removed from the user visible capability list 41 * FF: Variable length 42 */ 43 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = { 44 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */ 45 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF, 46 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF, 47 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF, 48 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */ 49 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */ 50 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */ 51 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */ 52 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */ 53 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */ 54 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */ 55 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */ 56 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */ 57 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */ 58 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */ 59 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */ 60 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */ 61 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF, 62 [PCI_CAP_ID_SATA] = 0xFF, 63 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF, 64 }; 65 66 /* 67 * Lengths of PCIe/PCI-X Extended Config Capabilities 68 * 0: Removed or masked from the user visible capability list 69 * FF: Variable length 70 */ 71 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = { 72 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND, 73 [PCI_EXT_CAP_ID_VC] = 0xFF, 74 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF, 75 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF, 76 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */ 77 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */ 78 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */ 79 [PCI_EXT_CAP_ID_MFVC] = 0xFF, 80 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */ 81 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */ 82 [PCI_EXT_CAP_ID_VNDR] = 0xFF, 83 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */ 84 [PCI_EXT_CAP_ID_ACS] = 0xFF, 85 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF, 86 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF, 87 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF, 88 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */ 89 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF, 90 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF, 91 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */ 92 [PCI_EXT_CAP_ID_REBAR] = 0xFF, 93 [PCI_EXT_CAP_ID_DPA] = 0xFF, 94 [PCI_EXT_CAP_ID_TPH] = 0xFF, 95 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF, 96 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */ 97 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */ 98 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */ 99 }; 100 101 /* 102 * Read/Write Permission Bits - one bit for each bit in capability 103 * Any field can be read if it exists, but what is read depends on 104 * whether the field is 'virtualized', or just pass thru to the 105 * hardware. Any virtualized field is also virtualized for writes. 106 * Writes are only permitted if they have a 1 bit here. 107 */ 108 struct perm_bits { 109 u8 *virt; /* read/write virtual data, not hw */ 110 u8 *write; /* writeable bits */ 111 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count, 112 struct perm_bits *perm, int offset, __le32 *val); 113 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count, 114 struct perm_bits *perm, int offset, __le32 val); 115 }; 116 117 #define NO_VIRT 0 118 #define ALL_VIRT 0xFFFFFFFFU 119 #define NO_WRITE 0 120 #define ALL_WRITE 0xFFFFFFFFU 121 122 static int vfio_user_config_read(struct pci_dev *pdev, int offset, 123 __le32 *val, int count) 124 { 125 int ret = -EINVAL; 126 u32 tmp_val = 0; 127 128 switch (count) { 129 case 1: 130 { 131 u8 tmp; 132 ret = pci_user_read_config_byte(pdev, offset, &tmp); 133 tmp_val = tmp; 134 break; 135 } 136 case 2: 137 { 138 u16 tmp; 139 ret = pci_user_read_config_word(pdev, offset, &tmp); 140 tmp_val = tmp; 141 break; 142 } 143 case 4: 144 ret = pci_user_read_config_dword(pdev, offset, &tmp_val); 145 break; 146 } 147 148 *val = cpu_to_le32(tmp_val); 149 150 return ret; 151 } 152 153 static int vfio_user_config_write(struct pci_dev *pdev, int offset, 154 __le32 val, int count) 155 { 156 int ret = -EINVAL; 157 u32 tmp_val = le32_to_cpu(val); 158 159 switch (count) { 160 case 1: 161 ret = pci_user_write_config_byte(pdev, offset, tmp_val); 162 break; 163 case 2: 164 ret = pci_user_write_config_word(pdev, offset, tmp_val); 165 break; 166 case 4: 167 ret = pci_user_write_config_dword(pdev, offset, tmp_val); 168 break; 169 } 170 171 return ret; 172 } 173 174 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos, 175 int count, struct perm_bits *perm, 176 int offset, __le32 *val) 177 { 178 __le32 virt = 0; 179 180 memcpy(val, vdev->vconfig + pos, count); 181 182 memcpy(&virt, perm->virt + offset, count); 183 184 /* Any non-virtualized bits? */ 185 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) { 186 struct pci_dev *pdev = vdev->pdev; 187 __le32 phys_val = 0; 188 int ret; 189 190 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 191 if (ret) 192 return ret; 193 194 *val = (phys_val & ~virt) | (*val & virt); 195 } 196 197 return count; 198 } 199 200 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos, 201 int count, struct perm_bits *perm, 202 int offset, __le32 val) 203 { 204 __le32 virt = 0, write = 0; 205 206 memcpy(&write, perm->write + offset, count); 207 208 if (!write) 209 return count; /* drop, no writable bits */ 210 211 memcpy(&virt, perm->virt + offset, count); 212 213 /* Virtualized and writable bits go to vconfig */ 214 if (write & virt) { 215 __le32 virt_val = 0; 216 217 memcpy(&virt_val, vdev->vconfig + pos, count); 218 219 virt_val &= ~(write & virt); 220 virt_val |= (val & (write & virt)); 221 222 memcpy(vdev->vconfig + pos, &virt_val, count); 223 } 224 225 /* Non-virtualzed and writable bits go to hardware */ 226 if (write & ~virt) { 227 struct pci_dev *pdev = vdev->pdev; 228 __le32 phys_val = 0; 229 int ret; 230 231 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 232 if (ret) 233 return ret; 234 235 phys_val &= ~(write & ~virt); 236 phys_val |= (val & (write & ~virt)); 237 238 ret = vfio_user_config_write(pdev, pos, phys_val, count); 239 if (ret) 240 return ret; 241 } 242 243 return count; 244 } 245 246 /* Allow direct read from hardware, except for capability next pointer */ 247 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos, 248 int count, struct perm_bits *perm, 249 int offset, __le32 *val) 250 { 251 int ret; 252 253 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 254 if (ret) 255 return ret; 256 257 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */ 258 if (offset < 4) 259 memcpy(val, vdev->vconfig + pos, count); 260 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */ 261 if (offset == PCI_CAP_LIST_ID && count > 1) 262 memcpy(val, vdev->vconfig + pos, 263 min(PCI_CAP_FLAGS, count)); 264 else if (offset == PCI_CAP_LIST_NEXT) 265 memcpy(val, vdev->vconfig + pos, 1); 266 } 267 268 return count; 269 } 270 271 /* Raw access skips any kind of virtualization */ 272 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos, 273 int count, struct perm_bits *perm, 274 int offset, __le32 val) 275 { 276 int ret; 277 278 ret = vfio_user_config_write(vdev->pdev, pos, val, count); 279 if (ret) 280 return ret; 281 282 return count; 283 } 284 285 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos, 286 int count, struct perm_bits *perm, 287 int offset, __le32 *val) 288 { 289 int ret; 290 291 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 292 if (ret) 293 return ret; 294 295 return count; 296 } 297 298 /* Virt access uses only virtualization */ 299 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos, 300 int count, struct perm_bits *perm, 301 int offset, __le32 val) 302 { 303 memcpy(vdev->vconfig + pos, &val, count); 304 return count; 305 } 306 307 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos, 308 int count, struct perm_bits *perm, 309 int offset, __le32 *val) 310 { 311 memcpy(val, vdev->vconfig + pos, count); 312 return count; 313 } 314 315 /* Default capability regions to read-only, no-virtualization */ 316 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = { 317 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 318 }; 319 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = { 320 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 321 }; 322 /* 323 * Default unassigned regions to raw read-write access. Some devices 324 * require this to function as they hide registers between the gaps in 325 * config space (be2net). Like MMIO and I/O port registers, we have 326 * to trust the hardware isolation. 327 */ 328 static struct perm_bits unassigned_perms = { 329 .readfn = vfio_raw_config_read, 330 .writefn = vfio_raw_config_write 331 }; 332 333 static struct perm_bits virt_perms = { 334 .readfn = vfio_virt_config_read, 335 .writefn = vfio_virt_config_write 336 }; 337 338 static void free_perm_bits(struct perm_bits *perm) 339 { 340 kfree(perm->virt); 341 kfree(perm->write); 342 perm->virt = NULL; 343 perm->write = NULL; 344 } 345 346 static int alloc_perm_bits(struct perm_bits *perm, int size) 347 { 348 /* 349 * Round up all permission bits to the next dword, this lets us 350 * ignore whether a read/write exceeds the defined capability 351 * structure. We can do this because: 352 * - Standard config space is already dword aligned 353 * - Capabilities are all dword aligned (bits 0:1 of next reserved) 354 * - Express capabilities defined as dword aligned 355 */ 356 size = round_up(size, 4); 357 358 /* 359 * Zero state is 360 * - All Readable, None Writeable, None Virtualized 361 */ 362 perm->virt = kzalloc(size, GFP_KERNEL); 363 perm->write = kzalloc(size, GFP_KERNEL); 364 if (!perm->virt || !perm->write) { 365 free_perm_bits(perm); 366 return -ENOMEM; 367 } 368 369 perm->readfn = vfio_default_config_read; 370 perm->writefn = vfio_default_config_write; 371 372 return 0; 373 } 374 375 /* 376 * Helper functions for filling in permission tables 377 */ 378 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write) 379 { 380 p->virt[off] = virt; 381 p->write[off] = write; 382 } 383 384 /* Handle endian-ness - pci and tables are little-endian */ 385 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write) 386 { 387 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt); 388 *(__le16 *)(&p->write[off]) = cpu_to_le16(write); 389 } 390 391 /* Handle endian-ness - pci and tables are little-endian */ 392 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write) 393 { 394 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt); 395 *(__le32 *)(&p->write[off]) = cpu_to_le32(write); 396 } 397 398 /* Caller should hold memory_lock semaphore */ 399 bool __vfio_pci_memory_enabled(struct vfio_pci_device *vdev) 400 { 401 struct pci_dev *pdev = vdev->pdev; 402 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]); 403 404 /* 405 * SR-IOV VF memory enable is handled by the MSE bit in the 406 * PF SR-IOV capability, there's therefore no need to trigger 407 * faults based on the virtual value. 408 */ 409 return pdev->is_virtfn || (cmd & PCI_COMMAND_MEMORY); 410 } 411 412 /* 413 * Restore the *real* BARs after we detect a FLR or backdoor reset. 414 * (backdoor = some device specific technique that we didn't catch) 415 */ 416 static void vfio_bar_restore(struct vfio_pci_device *vdev) 417 { 418 struct pci_dev *pdev = vdev->pdev; 419 u32 *rbar = vdev->rbar; 420 u16 cmd; 421 int i; 422 423 if (pdev->is_virtfn) 424 return; 425 426 pci_info(pdev, "%s: reset recovery - restoring BARs\n", __func__); 427 428 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++) 429 pci_user_write_config_dword(pdev, i, *rbar); 430 431 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); 432 433 if (vdev->nointx) { 434 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd); 435 cmd |= PCI_COMMAND_INTX_DISABLE; 436 pci_user_write_config_word(pdev, PCI_COMMAND, cmd); 437 } 438 } 439 440 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar) 441 { 442 unsigned long flags = pci_resource_flags(pdev, bar); 443 u32 val; 444 445 if (flags & IORESOURCE_IO) 446 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO); 447 448 val = PCI_BASE_ADDRESS_SPACE_MEMORY; 449 450 if (flags & IORESOURCE_PREFETCH) 451 val |= PCI_BASE_ADDRESS_MEM_PREFETCH; 452 453 if (flags & IORESOURCE_MEM_64) 454 val |= PCI_BASE_ADDRESS_MEM_TYPE_64; 455 456 return cpu_to_le32(val); 457 } 458 459 /* 460 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs 461 * to reflect the hardware capabilities. This implements BAR sizing. 462 */ 463 static void vfio_bar_fixup(struct vfio_pci_device *vdev) 464 { 465 struct pci_dev *pdev = vdev->pdev; 466 int i; 467 __le32 *vbar; 468 u64 mask; 469 470 vbar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0]; 471 472 for (i = 0; i < PCI_STD_NUM_BARS; i++, vbar++) { 473 int bar = i + PCI_STD_RESOURCES; 474 475 if (!pci_resource_start(pdev, bar)) { 476 *vbar = 0; /* Unmapped by host = unimplemented to user */ 477 continue; 478 } 479 480 mask = ~(pci_resource_len(pdev, bar) - 1); 481 482 *vbar &= cpu_to_le32((u32)mask); 483 *vbar |= vfio_generate_bar_flags(pdev, bar); 484 485 if (*vbar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) { 486 vbar++; 487 *vbar &= cpu_to_le32((u32)(mask >> 32)); 488 i++; 489 } 490 } 491 492 vbar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS]; 493 494 /* 495 * NB. REGION_INFO will have reported zero size if we weren't able 496 * to read the ROM, but we still return the actual BAR size here if 497 * it exists (or the shadow ROM space). 498 */ 499 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) { 500 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); 501 mask |= PCI_ROM_ADDRESS_ENABLE; 502 *vbar &= cpu_to_le32((u32)mask); 503 } else if (pdev->resource[PCI_ROM_RESOURCE].flags & 504 IORESOURCE_ROM_SHADOW) { 505 mask = ~(0x20000 - 1); 506 mask |= PCI_ROM_ADDRESS_ENABLE; 507 *vbar &= cpu_to_le32((u32)mask); 508 } else 509 *vbar = 0; 510 511 vdev->bardirty = false; 512 } 513 514 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos, 515 int count, struct perm_bits *perm, 516 int offset, __le32 *val) 517 { 518 if (is_bar(offset)) /* pos == offset for basic config */ 519 vfio_bar_fixup(vdev); 520 521 count = vfio_default_config_read(vdev, pos, count, perm, offset, val); 522 523 /* Mask in virtual memory enable for SR-IOV devices */ 524 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) { 525 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]); 526 u32 tmp_val = le32_to_cpu(*val); 527 528 tmp_val |= cmd & PCI_COMMAND_MEMORY; 529 *val = cpu_to_le32(tmp_val); 530 } 531 532 return count; 533 } 534 535 /* Test whether BARs match the value we think they should contain */ 536 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev) 537 { 538 int i = 0, pos = PCI_BASE_ADDRESS_0, ret; 539 u32 bar; 540 541 for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) { 542 if (vdev->rbar[i]) { 543 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar); 544 if (ret || vdev->rbar[i] != bar) 545 return true; 546 } 547 } 548 549 return false; 550 } 551 552 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, 553 int count, struct perm_bits *perm, 554 int offset, __le32 val) 555 { 556 struct pci_dev *pdev = vdev->pdev; 557 __le16 *virt_cmd; 558 u16 new_cmd = 0; 559 int ret; 560 561 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND]; 562 563 if (offset == PCI_COMMAND) { 564 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io; 565 u16 phys_cmd; 566 567 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd); 568 if (ret) 569 return ret; 570 571 new_cmd = le32_to_cpu(val); 572 573 phys_io = !!(phys_cmd & PCI_COMMAND_IO); 574 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO); 575 new_io = !!(new_cmd & PCI_COMMAND_IO); 576 577 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY); 578 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY); 579 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY); 580 581 if (!new_mem) 582 vfio_pci_zap_and_down_write_memory_lock(vdev); 583 else 584 down_write(&vdev->memory_lock); 585 586 /* 587 * If the user is writing mem/io enable (new_mem/io) and we 588 * think it's already enabled (virt_mem/io), but the hardware 589 * shows it disabled (phys_mem/io, then the device has 590 * undergone some kind of backdoor reset and needs to be 591 * restored before we allow it to enable the bars. 592 * SR-IOV devices will trigger this, but we catch them later 593 */ 594 if ((new_mem && virt_mem && !phys_mem) || 595 (new_io && virt_io && !phys_io) || 596 vfio_need_bar_restore(vdev)) 597 vfio_bar_restore(vdev); 598 } 599 600 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 601 if (count < 0) { 602 if (offset == PCI_COMMAND) 603 up_write(&vdev->memory_lock); 604 return count; 605 } 606 607 /* 608 * Save current memory/io enable bits in vconfig to allow for 609 * the test above next time. 610 */ 611 if (offset == PCI_COMMAND) { 612 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO; 613 614 *virt_cmd &= cpu_to_le16(~mask); 615 *virt_cmd |= cpu_to_le16(new_cmd & mask); 616 617 up_write(&vdev->memory_lock); 618 } 619 620 /* Emulate INTx disable */ 621 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) { 622 bool virt_intx_disable; 623 624 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) & 625 PCI_COMMAND_INTX_DISABLE); 626 627 if (virt_intx_disable && !vdev->virq_disabled) { 628 vdev->virq_disabled = true; 629 vfio_pci_intx_mask(vdev); 630 } else if (!virt_intx_disable && vdev->virq_disabled) { 631 vdev->virq_disabled = false; 632 vfio_pci_intx_unmask(vdev); 633 } 634 } 635 636 if (is_bar(offset)) 637 vdev->bardirty = true; 638 639 return count; 640 } 641 642 /* Permissions for the Basic PCI Header */ 643 static int __init init_pci_cap_basic_perm(struct perm_bits *perm) 644 { 645 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF)) 646 return -ENOMEM; 647 648 perm->readfn = vfio_basic_config_read; 649 perm->writefn = vfio_basic_config_write; 650 651 /* Virtualized for SR-IOV functions, which just have FFFF */ 652 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE); 653 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE); 654 655 /* 656 * Virtualize INTx disable, we use it internally for interrupt 657 * control and can emulate it for non-PCI 2.3 devices. 658 */ 659 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE); 660 661 /* Virtualize capability list, we might want to skip/disable */ 662 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE); 663 664 /* No harm to write */ 665 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE); 666 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE); 667 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE); 668 669 /* Virtualize all bars, can't touch the real ones */ 670 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE); 671 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE); 672 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE); 673 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE); 674 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE); 675 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE); 676 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE); 677 678 /* Allow us to adjust capability chain */ 679 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE); 680 681 /* Sometimes used by sw, just virtualize */ 682 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE); 683 684 /* Virtualize interrupt pin to allow hiding INTx */ 685 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE); 686 687 return 0; 688 } 689 690 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos, 691 int count, struct perm_bits *perm, 692 int offset, __le32 val) 693 { 694 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 695 if (count < 0) 696 return count; 697 698 if (offset == PCI_PM_CTRL) { 699 pci_power_t state; 700 701 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { 702 case 0: 703 state = PCI_D0; 704 break; 705 case 1: 706 state = PCI_D1; 707 break; 708 case 2: 709 state = PCI_D2; 710 break; 711 case 3: 712 state = PCI_D3hot; 713 break; 714 } 715 716 vfio_pci_set_power_state(vdev, state); 717 } 718 719 return count; 720 } 721 722 /* Permissions for the Power Management capability */ 723 static int __init init_pci_cap_pm_perm(struct perm_bits *perm) 724 { 725 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM])) 726 return -ENOMEM; 727 728 perm->writefn = vfio_pm_config_write; 729 730 /* 731 * We always virtualize the next field so we can remove 732 * capabilities from the chain if we want to. 733 */ 734 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 735 736 /* 737 * Power management is defined *per function*, so we can let 738 * the user change power state, but we trap and initiate the 739 * change ourselves, so the state bits are read-only. 740 */ 741 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK); 742 return 0; 743 } 744 745 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos, 746 int count, struct perm_bits *perm, 747 int offset, __le32 val) 748 { 749 struct pci_dev *pdev = vdev->pdev; 750 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR); 751 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA); 752 u16 addr; 753 u32 data; 754 755 /* 756 * Write through to emulation. If the write includes the upper byte 757 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we 758 * have work to do. 759 */ 760 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 761 if (count < 0 || offset > PCI_VPD_ADDR + 1 || 762 offset + count <= PCI_VPD_ADDR + 1) 763 return count; 764 765 addr = le16_to_cpu(*paddr); 766 767 if (addr & PCI_VPD_ADDR_F) { 768 data = le32_to_cpu(*pdata); 769 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4) 770 return count; 771 } else { 772 data = 0; 773 if (pci_read_vpd(pdev, addr, 4, &data) < 0) 774 return count; 775 *pdata = cpu_to_le32(data); 776 } 777 778 /* 779 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to 780 * signal completion. If an error occurs above, we assume that not 781 * toggling this bit will induce a driver timeout. 782 */ 783 addr ^= PCI_VPD_ADDR_F; 784 *paddr = cpu_to_le16(addr); 785 786 return count; 787 } 788 789 /* Permissions for Vital Product Data capability */ 790 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm) 791 { 792 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD])) 793 return -ENOMEM; 794 795 perm->writefn = vfio_vpd_config_write; 796 797 /* 798 * We always virtualize the next field so we can remove 799 * capabilities from the chain if we want to. 800 */ 801 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 802 803 /* 804 * Both the address and data registers are virtualized to 805 * enable access through the pci_vpd_read/write functions 806 */ 807 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE); 808 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE); 809 810 return 0; 811 } 812 813 /* Permissions for PCI-X capability */ 814 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm) 815 { 816 /* Alloc 24, but only 8 are used in v0 */ 817 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2)) 818 return -ENOMEM; 819 820 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 821 822 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE); 823 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE); 824 return 0; 825 } 826 827 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos, 828 int count, struct perm_bits *perm, 829 int offset, __le32 val) 830 { 831 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos - 832 offset + PCI_EXP_DEVCTL); 833 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ; 834 835 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 836 if (count < 0) 837 return count; 838 839 /* 840 * The FLR bit is virtualized, if set and the device supports PCIe 841 * FLR, issue a reset_function. Regardless, clear the bit, the spec 842 * requires it to be always read as zero. NB, reset_function might 843 * not use a PCIe FLR, we don't have that level of granularity. 844 */ 845 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) { 846 u32 cap; 847 int ret; 848 849 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR); 850 851 ret = pci_user_read_config_dword(vdev->pdev, 852 pos - offset + PCI_EXP_DEVCAP, 853 &cap); 854 855 if (!ret && (cap & PCI_EXP_DEVCAP_FLR)) { 856 vfio_pci_zap_and_down_write_memory_lock(vdev); 857 pci_try_reset_function(vdev->pdev); 858 up_write(&vdev->memory_lock); 859 } 860 } 861 862 /* 863 * MPS is virtualized to the user, writes do not change the physical 864 * register since determining a proper MPS value requires a system wide 865 * device view. The MRRS is largely independent of MPS, but since the 866 * user does not have that system-wide view, they might set a safe, but 867 * inefficiently low value. Here we allow writes through to hardware, 868 * but we set the floor to the physical device MPS setting, so that 869 * we can at least use full TLPs, as defined by the MPS value. 870 * 871 * NB, if any devices actually depend on an artificially low MRRS 872 * setting, this will need to be revisited, perhaps with a quirk 873 * though pcie_set_readrq(). 874 */ 875 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) { 876 readrq = 128 << 877 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12); 878 readrq = max(readrq, pcie_get_mps(vdev->pdev)); 879 880 pcie_set_readrq(vdev->pdev, readrq); 881 } 882 883 return count; 884 } 885 886 /* Permissions for PCI Express capability */ 887 static int __init init_pci_cap_exp_perm(struct perm_bits *perm) 888 { 889 /* Alloc largest of possible sizes */ 890 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2)) 891 return -ENOMEM; 892 893 perm->writefn = vfio_exp_config_write; 894 895 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 896 897 /* 898 * Allow writes to device control fields, except devctl_phantom, 899 * which could confuse IOMMU, MPS, which can break communication 900 * with other physical devices, and the ARI bit in devctl2, which 901 * is set at probe time. FLR and MRRS get virtualized via our 902 * writefn. 903 */ 904 p_setw(perm, PCI_EXP_DEVCTL, 905 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD | 906 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM); 907 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI); 908 return 0; 909 } 910 911 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos, 912 int count, struct perm_bits *perm, 913 int offset, __le32 val) 914 { 915 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL; 916 917 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 918 if (count < 0) 919 return count; 920 921 /* 922 * The FLR bit is virtualized, if set and the device supports AF 923 * FLR, issue a reset_function. Regardless, clear the bit, the spec 924 * requires it to be always read as zero. NB, reset_function might 925 * not use an AF FLR, we don't have that level of granularity. 926 */ 927 if (*ctrl & PCI_AF_CTRL_FLR) { 928 u8 cap; 929 int ret; 930 931 *ctrl &= ~PCI_AF_CTRL_FLR; 932 933 ret = pci_user_read_config_byte(vdev->pdev, 934 pos - offset + PCI_AF_CAP, 935 &cap); 936 937 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP)) { 938 vfio_pci_zap_and_down_write_memory_lock(vdev); 939 pci_try_reset_function(vdev->pdev); 940 up_write(&vdev->memory_lock); 941 } 942 } 943 944 return count; 945 } 946 947 /* Permissions for Advanced Function capability */ 948 static int __init init_pci_cap_af_perm(struct perm_bits *perm) 949 { 950 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF])) 951 return -ENOMEM; 952 953 perm->writefn = vfio_af_config_write; 954 955 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 956 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR); 957 return 0; 958 } 959 960 /* Permissions for Advanced Error Reporting extended capability */ 961 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm) 962 { 963 u32 mask; 964 965 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR])) 966 return -ENOMEM; 967 968 /* 969 * Virtualize the first dword of all express capabilities 970 * because it includes the next pointer. This lets us later 971 * remove capabilities from the chain if we need to. 972 */ 973 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 974 975 /* Writable bits mask */ 976 mask = PCI_ERR_UNC_UND | /* Undefined */ 977 PCI_ERR_UNC_DLP | /* Data Link Protocol */ 978 PCI_ERR_UNC_SURPDN | /* Surprise Down */ 979 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */ 980 PCI_ERR_UNC_FCP | /* Flow Control Protocol */ 981 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */ 982 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */ 983 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */ 984 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */ 985 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */ 986 PCI_ERR_UNC_ECRC | /* ECRC Error Status */ 987 PCI_ERR_UNC_UNSUP | /* Unsupported Request */ 988 PCI_ERR_UNC_ACSV | /* ACS Violation */ 989 PCI_ERR_UNC_INTN | /* internal error */ 990 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */ 991 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */ 992 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */ 993 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask); 994 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask); 995 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask); 996 997 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */ 998 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */ 999 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */ 1000 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */ 1001 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */ 1002 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */ 1003 PCI_ERR_COR_INTERNAL | /* Corrected Internal */ 1004 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */ 1005 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask); 1006 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask); 1007 1008 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */ 1009 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */ 1010 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask); 1011 return 0; 1012 } 1013 1014 /* Permissions for Power Budgeting extended capability */ 1015 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm) 1016 { 1017 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR])) 1018 return -ENOMEM; 1019 1020 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 1021 1022 /* Writing the data selector is OK, the info is still read-only */ 1023 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE); 1024 return 0; 1025 } 1026 1027 /* 1028 * Initialize the shared permission tables 1029 */ 1030 void vfio_pci_uninit_perm_bits(void) 1031 { 1032 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]); 1033 1034 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]); 1035 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]); 1036 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]); 1037 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]); 1038 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]); 1039 1040 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 1041 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 1042 } 1043 1044 int __init vfio_pci_init_perm_bits(void) 1045 { 1046 int ret; 1047 1048 /* Basic config space */ 1049 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]); 1050 1051 /* Capabilities */ 1052 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]); 1053 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]); 1054 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]); 1055 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write; 1056 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]); 1057 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]); 1058 1059 /* Extended capabilities */ 1060 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 1061 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 1062 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write; 1063 1064 if (ret) 1065 vfio_pci_uninit_perm_bits(); 1066 1067 return ret; 1068 } 1069 1070 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos) 1071 { 1072 u8 cap; 1073 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE : 1074 PCI_STD_HEADER_SIZEOF; 1075 cap = vdev->pci_config_map[pos]; 1076 1077 if (cap == PCI_CAP_ID_BASIC) 1078 return 0; 1079 1080 /* XXX Can we have to abutting capabilities of the same type? */ 1081 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap) 1082 pos--; 1083 1084 return pos; 1085 } 1086 1087 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos, 1088 int count, struct perm_bits *perm, 1089 int offset, __le32 *val) 1090 { 1091 /* Update max available queue size from msi_qmax */ 1092 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 1093 __le16 *flags; 1094 int start; 1095 1096 start = vfio_find_cap_start(vdev, pos); 1097 1098 flags = (__le16 *)&vdev->vconfig[start]; 1099 1100 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK); 1101 *flags |= cpu_to_le16(vdev->msi_qmax << 1); 1102 } 1103 1104 return vfio_default_config_read(vdev, pos, count, perm, offset, val); 1105 } 1106 1107 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos, 1108 int count, struct perm_bits *perm, 1109 int offset, __le32 val) 1110 { 1111 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 1112 if (count < 0) 1113 return count; 1114 1115 /* Fixup and write configured queue size and enable to hardware */ 1116 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 1117 __le16 *pflags; 1118 u16 flags; 1119 int start, ret; 1120 1121 start = vfio_find_cap_start(vdev, pos); 1122 1123 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS]; 1124 1125 flags = le16_to_cpu(*pflags); 1126 1127 /* MSI is enabled via ioctl */ 1128 if (!is_msi(vdev)) 1129 flags &= ~PCI_MSI_FLAGS_ENABLE; 1130 1131 /* Check queue size */ 1132 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) { 1133 flags &= ~PCI_MSI_FLAGS_QSIZE; 1134 flags |= vdev->msi_qmax << 4; 1135 } 1136 1137 /* Write back to virt and to hardware */ 1138 *pflags = cpu_to_le16(flags); 1139 ret = pci_user_write_config_word(vdev->pdev, 1140 start + PCI_MSI_FLAGS, 1141 flags); 1142 if (ret) 1143 return ret; 1144 } 1145 1146 return count; 1147 } 1148 1149 /* 1150 * MSI determination is per-device, so this routine gets used beyond 1151 * initialization time. Don't add __init 1152 */ 1153 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags) 1154 { 1155 if (alloc_perm_bits(perm, len)) 1156 return -ENOMEM; 1157 1158 perm->readfn = vfio_msi_config_read; 1159 perm->writefn = vfio_msi_config_write; 1160 1161 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 1162 1163 /* 1164 * The upper byte of the control register is reserved, 1165 * just setup the lower byte. 1166 */ 1167 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE); 1168 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE); 1169 if (flags & PCI_MSI_FLAGS_64BIT) { 1170 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE); 1171 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE); 1172 if (flags & PCI_MSI_FLAGS_MASKBIT) { 1173 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE); 1174 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE); 1175 } 1176 } else { 1177 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE); 1178 if (flags & PCI_MSI_FLAGS_MASKBIT) { 1179 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE); 1180 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE); 1181 } 1182 } 1183 return 0; 1184 } 1185 1186 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */ 1187 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos) 1188 { 1189 struct pci_dev *pdev = vdev->pdev; 1190 int len, ret; 1191 u16 flags; 1192 1193 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags); 1194 if (ret) 1195 return pcibios_err_to_errno(ret); 1196 1197 len = 10; /* Minimum size */ 1198 if (flags & PCI_MSI_FLAGS_64BIT) 1199 len += 4; 1200 if (flags & PCI_MSI_FLAGS_MASKBIT) 1201 len += 10; 1202 1203 if (vdev->msi_perm) 1204 return len; 1205 1206 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL); 1207 if (!vdev->msi_perm) 1208 return -ENOMEM; 1209 1210 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags); 1211 if (ret) { 1212 kfree(vdev->msi_perm); 1213 return ret; 1214 } 1215 1216 return len; 1217 } 1218 1219 /* Determine extended capability length for VC (2 & 9) and MFVC */ 1220 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos) 1221 { 1222 struct pci_dev *pdev = vdev->pdev; 1223 u32 tmp; 1224 int ret, evcc, phases, vc_arb; 1225 int len = PCI_CAP_VC_BASE_SIZEOF; 1226 1227 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp); 1228 if (ret) 1229 return pcibios_err_to_errno(ret); 1230 1231 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */ 1232 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp); 1233 if (ret) 1234 return pcibios_err_to_errno(ret); 1235 1236 if (tmp & PCI_VC_CAP2_128_PHASE) 1237 phases = 128; 1238 else if (tmp & PCI_VC_CAP2_64_PHASE) 1239 phases = 64; 1240 else if (tmp & PCI_VC_CAP2_32_PHASE) 1241 phases = 32; 1242 else 1243 phases = 0; 1244 1245 vc_arb = phases * 4; 1246 1247 /* 1248 * Port arbitration tables are root & switch only; 1249 * function arbitration tables are function 0 only. 1250 * In either case, we'll never let user write them so 1251 * we don't care how big they are 1252 */ 1253 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF; 1254 if (vc_arb) { 1255 len = round_up(len, 16); 1256 len += vc_arb / 8; 1257 } 1258 return len; 1259 } 1260 1261 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos) 1262 { 1263 struct pci_dev *pdev = vdev->pdev; 1264 u32 dword; 1265 u16 word; 1266 u8 byte; 1267 int ret; 1268 1269 switch (cap) { 1270 case PCI_CAP_ID_MSI: 1271 return vfio_msi_cap_len(vdev, pos); 1272 case PCI_CAP_ID_PCIX: 1273 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word); 1274 if (ret) 1275 return pcibios_err_to_errno(ret); 1276 1277 if (PCI_X_CMD_VERSION(word)) { 1278 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) { 1279 /* Test for extended capabilities */ 1280 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, 1281 &dword); 1282 vdev->extended_caps = (dword != 0); 1283 } 1284 return PCI_CAP_PCIX_SIZEOF_V2; 1285 } else 1286 return PCI_CAP_PCIX_SIZEOF_V0; 1287 case PCI_CAP_ID_VNDR: 1288 /* length follows next field */ 1289 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte); 1290 if (ret) 1291 return pcibios_err_to_errno(ret); 1292 1293 return byte; 1294 case PCI_CAP_ID_EXP: 1295 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) { 1296 /* Test for extended capabilities */ 1297 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); 1298 vdev->extended_caps = (dword != 0); 1299 } 1300 1301 /* length based on version and type */ 1302 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) { 1303 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END) 1304 return 0xc; /* "All Devices" only, no link */ 1305 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1; 1306 } else { 1307 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END) 1308 return 0x2c; /* No link */ 1309 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2; 1310 } 1311 case PCI_CAP_ID_HT: 1312 ret = pci_read_config_byte(pdev, pos + 3, &byte); 1313 if (ret) 1314 return pcibios_err_to_errno(ret); 1315 1316 return (byte & HT_3BIT_CAP_MASK) ? 1317 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG; 1318 case PCI_CAP_ID_SATA: 1319 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte); 1320 if (ret) 1321 return pcibios_err_to_errno(ret); 1322 1323 byte &= PCI_SATA_REGS_MASK; 1324 if (byte == PCI_SATA_REGS_INLINE) 1325 return PCI_SATA_SIZEOF_LONG; 1326 else 1327 return PCI_SATA_SIZEOF_SHORT; 1328 default: 1329 pci_warn(pdev, "%s: unknown length for PCI cap %#x@%#x\n", 1330 __func__, cap, pos); 1331 } 1332 1333 return 0; 1334 } 1335 1336 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos) 1337 { 1338 struct pci_dev *pdev = vdev->pdev; 1339 u8 byte; 1340 u32 dword; 1341 int ret; 1342 1343 switch (ecap) { 1344 case PCI_EXT_CAP_ID_VNDR: 1345 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword); 1346 if (ret) 1347 return pcibios_err_to_errno(ret); 1348 1349 return dword >> PCI_VSEC_HDR_LEN_SHIFT; 1350 case PCI_EXT_CAP_ID_VC: 1351 case PCI_EXT_CAP_ID_VC9: 1352 case PCI_EXT_CAP_ID_MFVC: 1353 return vfio_vc_cap_len(vdev, epos); 1354 case PCI_EXT_CAP_ID_ACS: 1355 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte); 1356 if (ret) 1357 return pcibios_err_to_errno(ret); 1358 1359 if (byte & PCI_ACS_EC) { 1360 int bits; 1361 1362 ret = pci_read_config_byte(pdev, 1363 epos + PCI_ACS_EGRESS_BITS, 1364 &byte); 1365 if (ret) 1366 return pcibios_err_to_errno(ret); 1367 1368 bits = byte ? round_up(byte, 32) : 256; 1369 return 8 + (bits / 8); 1370 } 1371 return 8; 1372 1373 case PCI_EXT_CAP_ID_REBAR: 1374 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte); 1375 if (ret) 1376 return pcibios_err_to_errno(ret); 1377 1378 byte &= PCI_REBAR_CTRL_NBAR_MASK; 1379 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT; 1380 1381 return 4 + (byte * 8); 1382 case PCI_EXT_CAP_ID_DPA: 1383 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte); 1384 if (ret) 1385 return pcibios_err_to_errno(ret); 1386 1387 byte &= PCI_DPA_CAP_SUBSTATE_MASK; 1388 return PCI_DPA_BASE_SIZEOF + byte + 1; 1389 case PCI_EXT_CAP_ID_TPH: 1390 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword); 1391 if (ret) 1392 return pcibios_err_to_errno(ret); 1393 1394 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) { 1395 int sts; 1396 1397 sts = dword & PCI_TPH_CAP_ST_MASK; 1398 sts >>= PCI_TPH_CAP_ST_SHIFT; 1399 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2; 1400 } 1401 return PCI_TPH_BASE_SIZEOF; 1402 default: 1403 pci_warn(pdev, "%s: unknown length for PCI ecap %#x@%#x\n", 1404 __func__, ecap, epos); 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev, 1411 int offset, int size) 1412 { 1413 struct pci_dev *pdev = vdev->pdev; 1414 int ret = 0; 1415 1416 /* 1417 * We try to read physical config space in the largest chunks 1418 * we can, assuming that all of the fields support dword access. 1419 * pci_save_state() makes this same assumption and seems to do ok. 1420 */ 1421 while (size) { 1422 int filled; 1423 1424 if (size >= 4 && !(offset % 4)) { 1425 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset]; 1426 u32 dword; 1427 1428 ret = pci_read_config_dword(pdev, offset, &dword); 1429 if (ret) 1430 return ret; 1431 *dwordp = cpu_to_le32(dword); 1432 filled = 4; 1433 } else if (size >= 2 && !(offset % 2)) { 1434 __le16 *wordp = (__le16 *)&vdev->vconfig[offset]; 1435 u16 word; 1436 1437 ret = pci_read_config_word(pdev, offset, &word); 1438 if (ret) 1439 return ret; 1440 *wordp = cpu_to_le16(word); 1441 filled = 2; 1442 } else { 1443 u8 *byte = &vdev->vconfig[offset]; 1444 ret = pci_read_config_byte(pdev, offset, byte); 1445 if (ret) 1446 return ret; 1447 filled = 1; 1448 } 1449 1450 offset += filled; 1451 size -= filled; 1452 } 1453 1454 return ret; 1455 } 1456 1457 static int vfio_cap_init(struct vfio_pci_device *vdev) 1458 { 1459 struct pci_dev *pdev = vdev->pdev; 1460 u8 *map = vdev->pci_config_map; 1461 u16 status; 1462 u8 pos, *prev, cap; 1463 int loops, ret, caps = 0; 1464 1465 /* Any capabilities? */ 1466 ret = pci_read_config_word(pdev, PCI_STATUS, &status); 1467 if (ret) 1468 return ret; 1469 1470 if (!(status & PCI_STATUS_CAP_LIST)) 1471 return 0; /* Done */ 1472 1473 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos); 1474 if (ret) 1475 return ret; 1476 1477 /* Mark the previous position in case we want to skip a capability */ 1478 prev = &vdev->vconfig[PCI_CAPABILITY_LIST]; 1479 1480 /* We can bound our loop, capabilities are dword aligned */ 1481 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF; 1482 while (pos && loops--) { 1483 u8 next; 1484 int i, len = 0; 1485 1486 ret = pci_read_config_byte(pdev, pos, &cap); 1487 if (ret) 1488 return ret; 1489 1490 ret = pci_read_config_byte(pdev, 1491 pos + PCI_CAP_LIST_NEXT, &next); 1492 if (ret) 1493 return ret; 1494 1495 /* 1496 * ID 0 is a NULL capability, conflicting with our fake 1497 * PCI_CAP_ID_BASIC. As it has no content, consider it 1498 * hidden for now. 1499 */ 1500 if (cap && cap <= PCI_CAP_ID_MAX) { 1501 len = pci_cap_length[cap]; 1502 if (len == 0xFF) { /* Variable length */ 1503 len = vfio_cap_len(vdev, cap, pos); 1504 if (len < 0) 1505 return len; 1506 } 1507 } 1508 1509 if (!len) { 1510 pci_info(pdev, "%s: hiding cap %#x@%#x\n", __func__, 1511 cap, pos); 1512 *prev = next; 1513 pos = next; 1514 continue; 1515 } 1516 1517 /* Sanity check, do we overlap other capabilities? */ 1518 for (i = 0; i < len; i++) { 1519 if (likely(map[pos + i] == PCI_CAP_ID_INVALID)) 1520 continue; 1521 1522 pci_warn(pdev, "%s: PCI config conflict @%#x, was cap %#x now cap %#x\n", 1523 __func__, pos + i, map[pos + i], cap); 1524 } 1525 1526 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT); 1527 1528 memset(map + pos, cap, len); 1529 ret = vfio_fill_vconfig_bytes(vdev, pos, len); 1530 if (ret) 1531 return ret; 1532 1533 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT]; 1534 pos = next; 1535 caps++; 1536 } 1537 1538 /* If we didn't fill any capabilities, clear the status flag */ 1539 if (!caps) { 1540 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS]; 1541 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST); 1542 } 1543 1544 return 0; 1545 } 1546 1547 static int vfio_ecap_init(struct vfio_pci_device *vdev) 1548 { 1549 struct pci_dev *pdev = vdev->pdev; 1550 u8 *map = vdev->pci_config_map; 1551 u16 epos; 1552 __le32 *prev = NULL; 1553 int loops, ret, ecaps = 0; 1554 1555 if (!vdev->extended_caps) 1556 return 0; 1557 1558 epos = PCI_CFG_SPACE_SIZE; 1559 1560 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF; 1561 1562 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) { 1563 u32 header; 1564 u16 ecap; 1565 int i, len = 0; 1566 bool hidden = false; 1567 1568 ret = pci_read_config_dword(pdev, epos, &header); 1569 if (ret) 1570 return ret; 1571 1572 ecap = PCI_EXT_CAP_ID(header); 1573 1574 if (ecap <= PCI_EXT_CAP_ID_MAX) { 1575 len = pci_ext_cap_length[ecap]; 1576 if (len == 0xFF) { 1577 len = vfio_ext_cap_len(vdev, ecap, epos); 1578 if (len < 0) 1579 return ret; 1580 } 1581 } 1582 1583 if (!len) { 1584 pci_info(pdev, "%s: hiding ecap %#x@%#x\n", 1585 __func__, ecap, epos); 1586 1587 /* If not the first in the chain, we can skip over it */ 1588 if (prev) { 1589 u32 val = epos = PCI_EXT_CAP_NEXT(header); 1590 *prev &= cpu_to_le32(~(0xffcU << 20)); 1591 *prev |= cpu_to_le32(val << 20); 1592 continue; 1593 } 1594 1595 /* 1596 * Otherwise, fill in a placeholder, the direct 1597 * readfn will virtualize this automatically 1598 */ 1599 len = PCI_CAP_SIZEOF; 1600 hidden = true; 1601 } 1602 1603 for (i = 0; i < len; i++) { 1604 if (likely(map[epos + i] == PCI_CAP_ID_INVALID)) 1605 continue; 1606 1607 pci_warn(pdev, "%s: PCI config conflict @%#x, was ecap %#x now ecap %#x\n", 1608 __func__, epos + i, map[epos + i], ecap); 1609 } 1610 1611 /* 1612 * Even though ecap is 2 bytes, we're currently a long way 1613 * from exceeding 1 byte capabilities. If we ever make it 1614 * up to 0xFE we'll need to up this to a two-byte, byte map. 1615 */ 1616 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT); 1617 1618 memset(map + epos, ecap, len); 1619 ret = vfio_fill_vconfig_bytes(vdev, epos, len); 1620 if (ret) 1621 return ret; 1622 1623 /* 1624 * If we're just using this capability to anchor the list, 1625 * hide the real ID. Only count real ecaps. XXX PCI spec 1626 * indicates to use cap id = 0, version = 0, next = 0 if 1627 * ecaps are absent, hope users check all the way to next. 1628 */ 1629 if (hidden) 1630 *(__le32 *)&vdev->vconfig[epos] &= 1631 cpu_to_le32((0xffcU << 20)); 1632 else 1633 ecaps++; 1634 1635 prev = (__le32 *)&vdev->vconfig[epos]; 1636 epos = PCI_EXT_CAP_NEXT(header); 1637 } 1638 1639 if (!ecaps) 1640 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0; 1641 1642 return 0; 1643 } 1644 1645 /* 1646 * Nag about hardware bugs, hopefully to have vendors fix them, but at least 1647 * to collect a list of dependencies for the VF INTx pin quirk below. 1648 */ 1649 static const struct pci_device_id known_bogus_vf_intx_pin[] = { 1650 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) }, 1651 {} 1652 }; 1653 1654 /* 1655 * For each device we allocate a pci_config_map that indicates the 1656 * capability occupying each dword and thus the struct perm_bits we 1657 * use for read and write. We also allocate a virtualized config 1658 * space which tracks reads and writes to bits that we emulate for 1659 * the user. Initial values filled from device. 1660 * 1661 * Using shared struct perm_bits between all vfio-pci devices saves 1662 * us from allocating cfg_size buffers for virt and write for every 1663 * device. We could remove vconfig and allocate individual buffers 1664 * for each area requiring emulated bits, but the array of pointers 1665 * would be comparable in size (at least for standard config space). 1666 */ 1667 int vfio_config_init(struct vfio_pci_device *vdev) 1668 { 1669 struct pci_dev *pdev = vdev->pdev; 1670 u8 *map, *vconfig; 1671 int ret; 1672 1673 /* 1674 * Config space, caps and ecaps are all dword aligned, so we could 1675 * use one byte per dword to record the type. However, there are 1676 * no requiremenst on the length of a capability, so the gap between 1677 * capabilities needs byte granularity. 1678 */ 1679 map = kmalloc(pdev->cfg_size, GFP_KERNEL); 1680 if (!map) 1681 return -ENOMEM; 1682 1683 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL); 1684 if (!vconfig) { 1685 kfree(map); 1686 return -ENOMEM; 1687 } 1688 1689 vdev->pci_config_map = map; 1690 vdev->vconfig = vconfig; 1691 1692 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF); 1693 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID, 1694 pdev->cfg_size - PCI_STD_HEADER_SIZEOF); 1695 1696 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF); 1697 if (ret) 1698 goto out; 1699 1700 vdev->bardirty = true; 1701 1702 /* 1703 * XXX can we just pci_load_saved_state/pci_restore_state? 1704 * may need to rebuild vconfig after that 1705 */ 1706 1707 /* For restore after reset */ 1708 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]); 1709 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]); 1710 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]); 1711 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]); 1712 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]); 1713 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]); 1714 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]); 1715 1716 if (pdev->is_virtfn) { 1717 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor); 1718 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device); 1719 1720 /* 1721 * Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register 1722 * does not apply to VFs and VFs must implement this register 1723 * as read-only with value zero. Userspace is not readily able 1724 * to identify whether a device is a VF and thus that the pin 1725 * definition on the device is bogus should it violate this 1726 * requirement. We already virtualize the pin register for 1727 * other purposes, so we simply need to replace the bogus value 1728 * and consider VFs when we determine INTx IRQ count. 1729 */ 1730 if (vconfig[PCI_INTERRUPT_PIN] && 1731 !pci_match_id(known_bogus_vf_intx_pin, pdev)) 1732 pci_warn(pdev, 1733 "Hardware bug: VF reports bogus INTx pin %d\n", 1734 vconfig[PCI_INTERRUPT_PIN]); 1735 1736 vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */ 1737 1738 /* 1739 * VFs do no implement the memory enable bit of the COMMAND 1740 * register therefore we'll not have it set in our initial 1741 * copy of config space after pci_enable_device(). For 1742 * consistency with PFs, set the virtual enable bit here. 1743 */ 1744 *(__le16 *)&vconfig[PCI_COMMAND] |= 1745 cpu_to_le16(PCI_COMMAND_MEMORY); 1746 } 1747 1748 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx) 1749 vconfig[PCI_INTERRUPT_PIN] = 0; 1750 1751 ret = vfio_cap_init(vdev); 1752 if (ret) 1753 goto out; 1754 1755 ret = vfio_ecap_init(vdev); 1756 if (ret) 1757 goto out; 1758 1759 return 0; 1760 1761 out: 1762 kfree(map); 1763 vdev->pci_config_map = NULL; 1764 kfree(vconfig); 1765 vdev->vconfig = NULL; 1766 return pcibios_err_to_errno(ret); 1767 } 1768 1769 void vfio_config_free(struct vfio_pci_device *vdev) 1770 { 1771 kfree(vdev->vconfig); 1772 vdev->vconfig = NULL; 1773 kfree(vdev->pci_config_map); 1774 vdev->pci_config_map = NULL; 1775 if (vdev->msi_perm) { 1776 free_perm_bits(vdev->msi_perm); 1777 kfree(vdev->msi_perm); 1778 vdev->msi_perm = NULL; 1779 } 1780 } 1781 1782 /* 1783 * Find the remaining number of bytes in a dword that match the given 1784 * position. Stop at either the end of the capability or the dword boundary. 1785 */ 1786 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev, 1787 loff_t pos) 1788 { 1789 u8 cap = vdev->pci_config_map[pos]; 1790 size_t i; 1791 1792 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++) 1793 /* nop */; 1794 1795 return i; 1796 } 1797 1798 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf, 1799 size_t count, loff_t *ppos, bool iswrite) 1800 { 1801 struct pci_dev *pdev = vdev->pdev; 1802 struct perm_bits *perm; 1803 __le32 val = 0; 1804 int cap_start = 0, offset; 1805 u8 cap_id; 1806 ssize_t ret; 1807 1808 if (*ppos < 0 || *ppos >= pdev->cfg_size || 1809 *ppos + count > pdev->cfg_size) 1810 return -EFAULT; 1811 1812 /* 1813 * Chop accesses into aligned chunks containing no more than a 1814 * single capability. Caller increments to the next chunk. 1815 */ 1816 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos)); 1817 if (count >= 4 && !(*ppos % 4)) 1818 count = 4; 1819 else if (count >= 2 && !(*ppos % 2)) 1820 count = 2; 1821 else 1822 count = 1; 1823 1824 ret = count; 1825 1826 cap_id = vdev->pci_config_map[*ppos]; 1827 1828 if (cap_id == PCI_CAP_ID_INVALID) { 1829 perm = &unassigned_perms; 1830 cap_start = *ppos; 1831 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) { 1832 perm = &virt_perms; 1833 cap_start = *ppos; 1834 } else { 1835 if (*ppos >= PCI_CFG_SPACE_SIZE) { 1836 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX); 1837 1838 perm = &ecap_perms[cap_id]; 1839 cap_start = vfio_find_cap_start(vdev, *ppos); 1840 } else { 1841 WARN_ON(cap_id > PCI_CAP_ID_MAX); 1842 1843 perm = &cap_perms[cap_id]; 1844 1845 if (cap_id == PCI_CAP_ID_MSI) 1846 perm = vdev->msi_perm; 1847 1848 if (cap_id > PCI_CAP_ID_BASIC) 1849 cap_start = vfio_find_cap_start(vdev, *ppos); 1850 } 1851 } 1852 1853 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC); 1854 WARN_ON(cap_start > *ppos); 1855 1856 offset = *ppos - cap_start; 1857 1858 if (iswrite) { 1859 if (!perm->writefn) 1860 return ret; 1861 1862 if (copy_from_user(&val, buf, count)) 1863 return -EFAULT; 1864 1865 ret = perm->writefn(vdev, *ppos, count, perm, offset, val); 1866 } else { 1867 if (perm->readfn) { 1868 ret = perm->readfn(vdev, *ppos, count, 1869 perm, offset, &val); 1870 if (ret < 0) 1871 return ret; 1872 } 1873 1874 if (copy_to_user(buf, &val, count)) 1875 return -EFAULT; 1876 } 1877 1878 return ret; 1879 } 1880 1881 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf, 1882 size_t count, loff_t *ppos, bool iswrite) 1883 { 1884 size_t done = 0; 1885 int ret = 0; 1886 loff_t pos = *ppos; 1887 1888 pos &= VFIO_PCI_OFFSET_MASK; 1889 1890 while (count) { 1891 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite); 1892 if (ret < 0) 1893 return ret; 1894 1895 count -= ret; 1896 done += ret; 1897 buf += ret; 1898 pos += ret; 1899 } 1900 1901 *ppos += done; 1902 1903 return done; 1904 } 1905