1# SPDX-License-Identifier: GPL-2.0-only 2config CLK_BAIKAL_T1 3 bool "Baikal-T1 Clocks Control Unit interface" 4 depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST 5 default MIPS_BAIKAL_T1 6 help 7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller 8 responsible for the chip subsystems clocking and resetting. It 9 consists of multiple global clock domains, which can be reset by 10 means of the CCU control registers. These domains and devices placed 11 in them are fed with clocks generated by a hierarchy of PLLs, 12 configurable and fixed clock dividers. Enable this option to be able 13 to select Baikal-T1 CCU PLLs and Dividers drivers. 14 15if CLK_BAIKAL_T1 16 17config CLK_BT1_CCU_PLL 18 bool "Baikal-T1 CCU PLLs support" 19 select MFD_SYSCON 20 default MIPS_BAIKAL_T1 21 help 22 Enable this to support the PLLs embedded into the Baikal-T1 SoC 23 System Controller. These are five PLLs placed at the root of the 24 clocks hierarchy, right after an external reference oscillator 25 (normally of 25MHz). They are used to generate high frequency 26 signals, which are either directly wired to the consumers (like 27 CPUs, DDR, etc.) or passed over the clock dividers to be only 28 then used as an individual reference clock of a target device. 29 30config CLK_BT1_CCU_DIV 31 bool "Baikal-T1 CCU Dividers support" 32 select RESET_CONTROLLER 33 select MFD_SYSCON 34 default MIPS_BAIKAL_T1 35 help 36 Enable this to support the CCU dividers used to distribute clocks 37 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1 38 SoC. CCU dividers can be either configurable or with fixed divider, 39 either gateable or ungateable. Some of the CCU dividers can be as well 40 used to reset the domains they're supplying clock to. 41 42endif 43