1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * saa711x - Philips SAA711x video decoder register specifications 4 * 5 * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@kernel.org> 6 */ 7 8 #define R_00_CHIP_VERSION 0x00 9 /* Video Decoder */ 10 /* Video Decoder - Frontend part */ 11 #define R_01_INC_DELAY 0x01 12 #define R_02_INPUT_CNTL_1 0x02 13 #define R_03_INPUT_CNTL_2 0x03 14 #define R_04_INPUT_CNTL_3 0x04 15 #define R_05_INPUT_CNTL_4 0x05 16 /* Video Decoder - Decoder part */ 17 #define R_06_H_SYNC_START 0x06 18 #define R_07_H_SYNC_STOP 0x07 19 #define R_08_SYNC_CNTL 0x08 20 #define R_09_LUMA_CNTL 0x09 21 #define R_0A_LUMA_BRIGHT_CNTL 0x0a 22 #define R_0B_LUMA_CONTRAST_CNTL 0x0b 23 #define R_0C_CHROMA_SAT_CNTL 0x0c 24 #define R_0D_CHROMA_HUE_CNTL 0x0d 25 #define R_0E_CHROMA_CNTL_1 0x0e 26 #define R_0F_CHROMA_GAIN_CNTL 0x0f 27 #define R_10_CHROMA_CNTL_2 0x10 28 #define R_11_MODE_DELAY_CNTL 0x11 29 #define R_12_RT_SIGNAL_CNTL 0x12 30 #define R_13_RT_X_PORT_OUT_CNTL 0x13 31 #define R_14_ANAL_ADC_COMPAT_CNTL 0x14 32 #define R_15_VGATE_START_FID_CHG 0x15 33 #define R_16_VGATE_STOP 0x16 34 #define R_17_MISC_VGATE_CONF_AND_MSB 0x17 35 #define R_18_RAW_DATA_GAIN_CNTL 0x18 36 #define R_19_RAW_DATA_OFF_CNTL 0x19 37 #define R_1A_COLOR_KILL_LVL_CNTL 0x1a 38 #define R_1B_MISC_TVVCRDET 0x1b 39 #define R_1C_ENHAN_COMB_CTRL1 0x1c 40 #define R_1D_ENHAN_COMB_CTRL2 0x1d 41 #define R_1E_STATUS_BYTE_1_VD_DEC 0x1e 42 #define R_1F_STATUS_BYTE_2_VD_DEC 0x1f 43 44 /* Component processing and interrupt masking part */ 45 #define R_23_INPUT_CNTL_5 0x23 46 #define R_24_INPUT_CNTL_6 0x24 47 #define R_25_INPUT_CNTL_7 0x25 48 #define R_29_COMP_DELAY 0x29 49 #define R_2A_COMP_BRIGHT_CNTL 0x2a 50 #define R_2B_COMP_CONTRAST_CNTL 0x2b 51 #define R_2C_COMP_SAT_CNTL 0x2c 52 #define R_2D_INTERRUPT_MASK_1 0x2d 53 #define R_2E_INTERRUPT_MASK_2 0x2e 54 #define R_2F_INTERRUPT_MASK_3 0x2f 55 56 /* Audio clock generator part */ 57 #define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD 0x30 58 #define R_34_AUD_MAST_CLK_NOMINAL_INC 0x34 59 #define R_38_CLK_RATIO_AMXCLK_TO_ASCLK 0x38 60 #define R_39_CLK_RATIO_ASCLK_TO_ALRCLK 0x39 61 #define R_3A_AUD_CLK_GEN_BASIC_SETUP 0x3a 62 63 /* General purpose VBI data slicer part */ 64 #define R_40_SLICER_CNTL_1 0x40 65 #define R_41_LCR_BASE 0x41 66 #define R_58_PROGRAM_FRAMING_CODE 0x58 67 #define R_59_H_OFF_FOR_SLICER 0x59 68 #define R_5A_V_OFF_FOR_SLICER 0x5a 69 #define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF 0x5b 70 #define R_5D_DID 0x5d 71 #define R_5E_SDID 0x5e 72 #define R_60_SLICER_STATUS_BYTE_0 0x60 73 #define R_61_SLICER_STATUS_BYTE_1 0x61 74 #define R_62_SLICER_STATUS_BYTE_2 0x62 75 76 /* X port, I port and the scaler part */ 77 /* Task independent global settings */ 78 #define R_80_GLOBAL_CNTL_1 0x80 79 #define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81 80 #define R_83_X_PORT_I_O_ENA_AND_OUT_CLK 0x83 81 #define R_84_I_PORT_SIGNAL_DEF 0x84 82 #define R_85_I_PORT_SIGNAL_POLAR 0x85 83 #define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT 0x86 84 #define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED 0x87 85 #define R_88_POWER_SAVE_ADC_PORT_CNTL 0x88 86 #define R_8F_STATUS_INFO_SCALER 0x8f 87 /* Task A definition */ 88 /* Basic settings and acquisition window definition */ 89 #define R_90_A_TASK_HANDLING_CNTL 0x90 90 #define R_91_A_X_PORT_FORMATS_AND_CONF 0x91 91 #define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL 0x92 92 #define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF 0x93 93 #define R_94_A_HORIZ_INPUT_WINDOW_START 0x94 94 #define R_95_A_HORIZ_INPUT_WINDOW_START_MSB 0x95 95 #define R_96_A_HORIZ_INPUT_WINDOW_LENGTH 0x96 96 #define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB 0x97 97 #define R_98_A_VERT_INPUT_WINDOW_START 0x98 98 #define R_99_A_VERT_INPUT_WINDOW_START_MSB 0x99 99 #define R_9A_A_VERT_INPUT_WINDOW_LENGTH 0x9a 100 #define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB 0x9b 101 #define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH 0x9c 102 #define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0x9d 103 #define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH 0x9e 104 #define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB 0x9f 105 /* FIR filtering and prescaling */ 106 #define R_A0_A_HORIZ_PRESCALING 0xa0 107 #define R_A1_A_ACCUMULATION_LENGTH 0xa1 108 #define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xa2 109 #define R_A4_A_LUMA_BRIGHTNESS_CNTL 0xa4 110 #define R_A5_A_LUMA_CONTRAST_CNTL 0xa5 111 #define R_A6_A_CHROMA_SATURATION_CNTL 0xa6 112 /* Horizontal phase scaling */ 113 #define R_A8_A_HORIZ_LUMA_SCALING_INC 0xa8 114 #define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB 0xa9 115 #define R_AA_A_HORIZ_LUMA_PHASE_OFF 0xaa 116 #define R_AC_A_HORIZ_CHROMA_SCALING_INC 0xac 117 #define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB 0xad 118 #define R_AE_A_HORIZ_CHROMA_PHASE_OFF 0xae 119 #define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB 0xaf 120 /* Vertical scaling */ 121 #define R_B0_A_VERT_LUMA_SCALING_INC 0xb0 122 #define R_B1_A_VERT_LUMA_SCALING_INC_MSB 0xb1 123 #define R_B2_A_VERT_CHROMA_SCALING_INC 0xb2 124 #define R_B3_A_VERT_CHROMA_SCALING_INC_MSB 0xb3 125 #define R_B4_A_VERT_SCALING_MODE_CNTL 0xb4 126 #define R_B8_A_VERT_CHROMA_PHASE_OFF_00 0xb8 127 #define R_B9_A_VERT_CHROMA_PHASE_OFF_01 0xb9 128 #define R_BA_A_VERT_CHROMA_PHASE_OFF_10 0xba 129 #define R_BB_A_VERT_CHROMA_PHASE_OFF_11 0xbb 130 #define R_BC_A_VERT_LUMA_PHASE_OFF_00 0xbc 131 #define R_BD_A_VERT_LUMA_PHASE_OFF_01 0xbd 132 #define R_BE_A_VERT_LUMA_PHASE_OFF_10 0xbe 133 #define R_BF_A_VERT_LUMA_PHASE_OFF_11 0xbf 134 /* Task B definition */ 135 /* Basic settings and acquisition window definition */ 136 #define R_C0_B_TASK_HANDLING_CNTL 0xc0 137 #define R_C1_B_X_PORT_FORMATS_AND_CONF 0xc1 138 #define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION 0xc2 139 #define R_C3_B_I_PORT_FORMATS_AND_CONF 0xc3 140 #define R_C4_B_HORIZ_INPUT_WINDOW_START 0xc4 141 #define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB 0xc5 142 #define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH 0xc6 143 #define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB 0xc7 144 #define R_C8_B_VERT_INPUT_WINDOW_START 0xc8 145 #define R_C9_B_VERT_INPUT_WINDOW_START_MSB 0xc9 146 #define R_CA_B_VERT_INPUT_WINDOW_LENGTH 0xca 147 #define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB 0xcb 148 #define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH 0xcc 149 #define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0xcd 150 #define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH 0xce 151 #define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB 0xcf 152 /* FIR filtering and prescaling */ 153 #define R_D0_B_HORIZ_PRESCALING 0xd0 154 #define R_D1_B_ACCUMULATION_LENGTH 0xd1 155 #define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xd2 156 #define R_D4_B_LUMA_BRIGHTNESS_CNTL 0xd4 157 #define R_D5_B_LUMA_CONTRAST_CNTL 0xd5 158 #define R_D6_B_CHROMA_SATURATION_CNTL 0xd6 159 /* Horizontal phase scaling */ 160 #define R_D8_B_HORIZ_LUMA_SCALING_INC 0xd8 161 #define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB 0xd9 162 #define R_DA_B_HORIZ_LUMA_PHASE_OFF 0xda 163 #define R_DC_B_HORIZ_CHROMA_SCALING 0xdc 164 #define R_DD_B_HORIZ_CHROMA_SCALING_MSB 0xdd 165 #define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA 0xde 166 /* Vertical scaling */ 167 #define R_E0_B_VERT_LUMA_SCALING_INC 0xe0 168 #define R_E1_B_VERT_LUMA_SCALING_INC_MSB 0xe1 169 #define R_E2_B_VERT_CHROMA_SCALING_INC 0xe2 170 #define R_E3_B_VERT_CHROMA_SCALING_INC_MSB 0xe3 171 #define R_E4_B_VERT_SCALING_MODE_CNTL 0xe4 172 #define R_E8_B_VERT_CHROMA_PHASE_OFF_00 0xe8 173 #define R_E9_B_VERT_CHROMA_PHASE_OFF_01 0xe9 174 #define R_EA_B_VERT_CHROMA_PHASE_OFF_10 0xea 175 #define R_EB_B_VERT_CHROMA_PHASE_OFF_11 0xeb 176 #define R_EC_B_VERT_LUMA_PHASE_OFF_00 0xec 177 #define R_ED_B_VERT_LUMA_PHASE_OFF_01 0xed 178 #define R_EE_B_VERT_LUMA_PHASE_OFF_10 0xee 179 #define R_EF_B_VERT_LUMA_PHASE_OFF_11 0xef 180 181 /* second PLL (PLL2) and Pulsegenerator Programming */ 182 #define R_F0_LFCO_PER_LINE 0xf0 183 #define R_F1_P_I_PARAM_SELECT 0xf1 184 #define R_F2_NOMINAL_PLL2_DTO 0xf2 185 #define R_F3_PLL_INCREMENT 0xf3 186 #define R_F4_PLL2_STATUS 0xf4 187 #define R_F5_PULSGEN_LINE_LENGTH 0xf5 188 #define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG 0xf6 189 #define R_F7_PULSE_A_POS_MSB 0xf7 190 #define R_F8_PULSE_B_POS 0xf8 191 #define R_F9_PULSE_B_POS_MSB 0xf9 192 #define R_FA_PULSE_C_POS 0xfa 193 #define R_FB_PULSE_C_POS_MSB 0xfb 194 #define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES 0xff 195 196 /* SAA7113 bit-masks */ 197 #define SAA7113_R_08_HTC_OFFSET 3 198 #define SAA7113_R_08_HTC_MASK (0x3 << SAA7113_R_08_HTC_OFFSET) 199 #define SAA7113_R_08_FSEL 0x40 200 #define SAA7113_R_08_AUFD 0x80 201 202 #define SAA7113_R_10_VRLN_OFFSET 3 203 #define SAA7113_R_10_VRLN_MASK (0x1 << SAA7113_R_10_VRLN_OFFSET) 204 #define SAA7113_R_10_OFTS_OFFSET 6 205 #define SAA7113_R_10_OFTS_MASK (0x3 << SAA7113_R_10_OFTS_OFFSET) 206 207 #define SAA7113_R_12_RTS0_OFFSET 0 208 #define SAA7113_R_12_RTS0_MASK (0xf << SAA7113_R_12_RTS0_OFFSET) 209 #define SAA7113_R_12_RTS1_OFFSET 4 210 #define SAA7113_R_12_RTS1_MASK (0xf << SAA7113_R_12_RTS1_OFFSET) 211 212 #define SAA7113_R_13_ADLSB_OFFSET 7 213 #define SAA7113_R_13_ADLSB_MASK (0x1 << SAA7113_R_13_ADLSB_OFFSET) 214 215 #if 0 216 /* Those structs will be used in the future for debug purposes */ 217 struct saa711x_reg_descr { 218 u8 reg; 219 int count; 220 char *name; 221 }; 222 223 struct saa711x_reg_descr saa711x_regs[] = { 224 /* REG COUNT NAME */ 225 {R_00_CHIP_VERSION,1, 226 "Chip version"}, 227 228 /* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */ 229 230 /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */ 231 {R_01_INC_DELAY,1, 232 "Increment delay"}, 233 {R_02_INPUT_CNTL_1,1, 234 "Analog input control 1"}, 235 {R_03_INPUT_CNTL_2,1, 236 "Analog input control 2"}, 237 {R_04_INPUT_CNTL_3,1, 238 "Analog input control 3"}, 239 {R_05_INPUT_CNTL_4,1, 240 "Analog input control 4"}, 241 242 /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */ 243 {R_06_H_SYNC_START,1, 244 "Horizontal sync start"}, 245 {R_07_H_SYNC_STOP,1, 246 "Horizontal sync stop"}, 247 {R_08_SYNC_CNTL,1, 248 "Sync control"}, 249 {R_09_LUMA_CNTL,1, 250 "Luminance control"}, 251 {R_0A_LUMA_BRIGHT_CNTL,1, 252 "Luminance brightness control"}, 253 {R_0B_LUMA_CONTRAST_CNTL,1, 254 "Luminance contrast control"}, 255 {R_0C_CHROMA_SAT_CNTL,1, 256 "Chrominance saturation control"}, 257 {R_0D_CHROMA_HUE_CNTL,1, 258 "Chrominance hue control"}, 259 {R_0E_CHROMA_CNTL_1,1, 260 "Chrominance control 1"}, 261 {R_0F_CHROMA_GAIN_CNTL,1, 262 "Chrominance gain control"}, 263 {R_10_CHROMA_CNTL_2,1, 264 "Chrominance control 2"}, 265 {R_11_MODE_DELAY_CNTL,1, 266 "Mode/delay control"}, 267 {R_12_RT_SIGNAL_CNTL,1, 268 "RT signal control"}, 269 {R_13_RT_X_PORT_OUT_CNTL,1, 270 "RT/X port output control"}, 271 {R_14_ANAL_ADC_COMPAT_CNTL,1, 272 "Analog/ADC/compatibility control"}, 273 {R_15_VGATE_START_FID_CHG, 1, 274 "VGATE start FID change"}, 275 {R_16_VGATE_STOP,1, 276 "VGATE stop"}, 277 {R_17_MISC_VGATE_CONF_AND_MSB, 1, 278 "Miscellaneous VGATE configuration and MSBs"}, 279 {R_18_RAW_DATA_GAIN_CNTL,1, 280 "Raw data gain control",}, 281 {R_19_RAW_DATA_OFF_CNTL,1, 282 "Raw data offset control",}, 283 {R_1A_COLOR_KILL_LVL_CNTL,1, 284 "Color Killer Level Control"}, 285 { R_1B_MISC_TVVCRDET, 1, 286 "MISC /TVVCRDET"}, 287 { R_1C_ENHAN_COMB_CTRL1, 1, 288 "Enhanced comb ctrl1"}, 289 { R_1D_ENHAN_COMB_CTRL2, 1, 290 "Enhanced comb ctrl1"}, 291 {R_1E_STATUS_BYTE_1_VD_DEC,1, 292 "Status byte 1 video decoder"}, 293 {R_1F_STATUS_BYTE_2_VD_DEC,1, 294 "Status byte 2 video decoder"}, 295 296 /* Component processing and interrupt masking part: 0x20h to R_2F_INTERRUPT_MASK_3 */ 297 /* 0x20 to 0x22 - Reserved */ 298 {R_23_INPUT_CNTL_5,1, 299 "Analog input control 5"}, 300 {R_24_INPUT_CNTL_6,1, 301 "Analog input control 6"}, 302 {R_25_INPUT_CNTL_7,1, 303 "Analog input control 7"}, 304 /* 0x26 to 0x28 - Reserved */ 305 {R_29_COMP_DELAY,1, 306 "Component delay"}, 307 {R_2A_COMP_BRIGHT_CNTL,1, 308 "Component brightness control"}, 309 {R_2B_COMP_CONTRAST_CNTL,1, 310 "Component contrast control"}, 311 {R_2C_COMP_SAT_CNTL,1, 312 "Component saturation control"}, 313 {R_2D_INTERRUPT_MASK_1,1, 314 "Interrupt mask 1"}, 315 {R_2E_INTERRUPT_MASK_2,1, 316 "Interrupt mask 2"}, 317 {R_2F_INTERRUPT_MASK_3,1, 318 "Interrupt mask 3"}, 319 320 /* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */ 321 {R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3, 322 "Audio master clock cycles per field"}, 323 /* 0x33 - Reserved */ 324 {R_34_AUD_MAST_CLK_NOMINAL_INC,3, 325 "Audio master clock nominal increment"}, 326 /* 0x37 - Reserved */ 327 {R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1, 328 "Clock ratio AMXCLK to ASCLK"}, 329 {R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1, 330 "Clock ratio ASCLK to ALRCLK"}, 331 {R_3A_AUD_CLK_GEN_BASIC_SETUP,1, 332 "Audio clock generator basic setup"}, 333 /* 0x3b-0x3f - Reserved */ 334 335 /* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */ 336 {R_40_SLICER_CNTL_1,1, 337 "Slicer control 1"}, 338 {R_41_LCR,23, 339 "R_41_LCR"}, 340 {R_58_PROGRAM_FRAMING_CODE,1, 341 "Programmable framing code"}, 342 {R_59_H_OFF_FOR_SLICER,1, 343 "Horizontal offset for slicer"}, 344 {R_5A_V_OFF_FOR_SLICER,1, 345 "Vertical offset for slicer"}, 346 {R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1, 347 "Field offset and MSBs for horizontal and vertical offset"}, 348 {R_5D_DID,1, 349 "Header and data identification (R_5D_DID)"}, 350 {R_5E_SDID,1, 351 "Sliced data identification (R_5E_SDID) code"}, 352 {R_60_SLICER_STATUS_BYTE_0,1, 353 "Slicer status byte 0"}, 354 {R_61_SLICER_STATUS_BYTE_1,1, 355 "Slicer status byte 1"}, 356 {R_62_SLICER_STATUS_BYTE_2,1, 357 "Slicer status byte 2"}, 358 /* 0x63-0x7f - Reserved */ 359 360 /* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */ 361 /* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */ 362 {R_80_GLOBAL_CNTL_1,1, 363 "Global control 1"}, 364 {R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1, 365 "Vertical sync and Field ID source selection, retimed V and F signals"}, 366 /* 0x82 - Reserved */ 367 {R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1, 368 "X port I/O enable and output clock"}, 369 {R_84_I_PORT_SIGNAL_DEF,1, 370 "I port signal definitions"}, 371 {R_85_I_PORT_SIGNAL_POLAR,1, 372 "I port signal polarities"}, 373 {R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1, 374 "I port FIFO flag control and arbitration"}, 375 {R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 1, 376 "I port I/O enable output clock and gated"}, 377 {R_88_POWER_SAVE_ADC_PORT_CNTL,1, 378 "Power save/ADC port control"}, 379 /* 089-0x8e - Reserved */ 380 {R_8F_STATUS_INFO_SCALER,1, 381 "Status information scaler part"}, 382 383 /* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */ 384 /* Task A: Basic settings and acquisition window definition */ 385 {R_90_A_TASK_HANDLING_CNTL,1, 386 "Task A: Task handling control"}, 387 {R_91_A_X_PORT_FORMATS_AND_CONF,1, 388 "Task A: X port formats and configuration"}, 389 {R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1, 390 "Task A: X port input reference signal definition"}, 391 {R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1, 392 "Task A: I port output formats and configuration"}, 393 {R_94_A_HORIZ_INPUT_WINDOW_START,2, 394 "Task A: Horizontal input window start"}, 395 {R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2, 396 "Task A: Horizontal input window length"}, 397 {R_98_A_VERT_INPUT_WINDOW_START,2, 398 "Task A: Vertical input window start"}, 399 {R_9A_A_VERT_INPUT_WINDOW_LENGTH,2, 400 "Task A: Vertical input window length"}, 401 {R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2, 402 "Task A: Horizontal output window length"}, 403 {R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2, 404 "Task A: Vertical output window length"}, 405 406 /* Task A: FIR filtering and prescaling */ 407 {R_A0_A_HORIZ_PRESCALING,1, 408 "Task A: Horizontal prescaling"}, 409 {R_A1_A_ACCUMULATION_LENGTH,1, 410 "Task A: Accumulation length"}, 411 {R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1, 412 "Task A: Prescaler DC gain and FIR prefilter"}, 413 /* 0xa3 - Reserved */ 414 {R_A4_A_LUMA_BRIGHTNESS_CNTL,1, 415 "Task A: Luminance brightness control"}, 416 {R_A5_A_LUMA_CONTRAST_CNTL,1, 417 "Task A: Luminance contrast control"}, 418 {R_A6_A_CHROMA_SATURATION_CNTL,1, 419 "Task A: Chrominance saturation control"}, 420 /* 0xa7 - Reserved */ 421 422 /* Task A: Horizontal phase scaling */ 423 {R_A8_A_HORIZ_LUMA_SCALING_INC,2, 424 "Task A: Horizontal luminance scaling increment"}, 425 {R_AA_A_HORIZ_LUMA_PHASE_OFF,1, 426 "Task A: Horizontal luminance phase offset"}, 427 /* 0xab - Reserved */ 428 {R_AC_A_HORIZ_CHROMA_SCALING_INC,2, 429 "Task A: Horizontal chrominance scaling increment"}, 430 {R_AE_A_HORIZ_CHROMA_PHASE_OFF,1, 431 "Task A: Horizontal chrominance phase offset"}, 432 /* 0xaf - Reserved */ 433 434 /* Task A: Vertical scaling */ 435 {R_B0_A_VERT_LUMA_SCALING_INC,2, 436 "Task A: Vertical luminance scaling increment"}, 437 {R_B2_A_VERT_CHROMA_SCALING_INC,2, 438 "Task A: Vertical chrominance scaling increment"}, 439 {R_B4_A_VERT_SCALING_MODE_CNTL,1, 440 "Task A: Vertical scaling mode control"}, 441 /* 0xb5-0xb7 - Reserved */ 442 {R_B8_A_VERT_CHROMA_PHASE_OFF_00,1, 443 "Task A: Vertical chrominance phase offset '00'"}, 444 {R_B9_A_VERT_CHROMA_PHASE_OFF_01,1, 445 "Task A: Vertical chrominance phase offset '01'"}, 446 {R_BA_A_VERT_CHROMA_PHASE_OFF_10,1, 447 "Task A: Vertical chrominance phase offset '10'"}, 448 {R_BB_A_VERT_CHROMA_PHASE_OFF_11,1, 449 "Task A: Vertical chrominance phase offset '11'"}, 450 {R_BC_A_VERT_LUMA_PHASE_OFF_00,1, 451 "Task A: Vertical luminance phase offset '00'"}, 452 {R_BD_A_VERT_LUMA_PHASE_OFF_01,1, 453 "Task A: Vertical luminance phase offset '01'"}, 454 {R_BE_A_VERT_LUMA_PHASE_OFF_10,1, 455 "Task A: Vertical luminance phase offset '10'"}, 456 {R_BF_A_VERT_LUMA_PHASE_OFF_11,1, 457 "Task A: Vertical luminance phase offset '11'"}, 458 459 /* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */ 460 /* Task B: Basic settings and acquisition window definition */ 461 {R_C0_B_TASK_HANDLING_CNTL,1, 462 "Task B: Task handling control"}, 463 {R_C1_B_X_PORT_FORMATS_AND_CONF,1, 464 "Task B: X port formats and configuration"}, 465 {R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1, 466 "Task B: Input reference signal definition"}, 467 {R_C3_B_I_PORT_FORMATS_AND_CONF,1, 468 "Task B: I port formats and configuration"}, 469 {R_C4_B_HORIZ_INPUT_WINDOW_START,2, 470 "Task B: Horizontal input window start"}, 471 {R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2, 472 "Task B: Horizontal input window length"}, 473 {R_C8_B_VERT_INPUT_WINDOW_START,2, 474 "Task B: Vertical input window start"}, 475 {R_CA_B_VERT_INPUT_WINDOW_LENGTH,2, 476 "Task B: Vertical input window length"}, 477 {R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2, 478 "Task B: Horizontal output window length"}, 479 {R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2, 480 "Task B: Vertical output window length"}, 481 482 /* Task B: FIR filtering and prescaling */ 483 {R_D0_B_HORIZ_PRESCALING,1, 484 "Task B: Horizontal prescaling"}, 485 {R_D1_B_ACCUMULATION_LENGTH,1, 486 "Task B: Accumulation length"}, 487 {R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1, 488 "Task B: Prescaler DC gain and FIR prefilter"}, 489 /* 0xd3 - Reserved */ 490 {R_D4_B_LUMA_BRIGHTNESS_CNTL,1, 491 "Task B: Luminance brightness control"}, 492 {R_D5_B_LUMA_CONTRAST_CNTL,1, 493 "Task B: Luminance contrast control"}, 494 {R_D6_B_CHROMA_SATURATION_CNTL,1, 495 "Task B: Chrominance saturation control"}, 496 /* 0xd7 - Reserved */ 497 498 /* Task B: Horizontal phase scaling */ 499 {R_D8_B_HORIZ_LUMA_SCALING_INC,2, 500 "Task B: Horizontal luminance scaling increment"}, 501 {R_DA_B_HORIZ_LUMA_PHASE_OFF,1, 502 "Task B: Horizontal luminance phase offset"}, 503 /* 0xdb - Reserved */ 504 {R_DC_B_HORIZ_CHROMA_SCALING,2, 505 "Task B: Horizontal chrominance scaling"}, 506 {R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1, 507 "Task B: Horizontal Phase Offset Chroma"}, 508 /* 0xdf - Reserved */ 509 510 /* Task B: Vertical scaling */ 511 {R_E0_B_VERT_LUMA_SCALING_INC,2, 512 "Task B: Vertical luminance scaling increment"}, 513 {R_E2_B_VERT_CHROMA_SCALING_INC,2, 514 "Task B: Vertical chrominance scaling increment"}, 515 {R_E4_B_VERT_SCALING_MODE_CNTL,1, 516 "Task B: Vertical scaling mode control"}, 517 /* 0xe5-0xe7 - Reserved */ 518 {R_E8_B_VERT_CHROMA_PHASE_OFF_00,1, 519 "Task B: Vertical chrominance phase offset '00'"}, 520 {R_E9_B_VERT_CHROMA_PHASE_OFF_01,1, 521 "Task B: Vertical chrominance phase offset '01'"}, 522 {R_EA_B_VERT_CHROMA_PHASE_OFF_10,1, 523 "Task B: Vertical chrominance phase offset '10'"}, 524 {R_EB_B_VERT_CHROMA_PHASE_OFF_11,1, 525 "Task B: Vertical chrominance phase offset '11'"}, 526 {R_EC_B_VERT_LUMA_PHASE_OFF_00,1, 527 "Task B: Vertical luminance phase offset '00'"}, 528 {R_ED_B_VERT_LUMA_PHASE_OFF_01,1, 529 "Task B: Vertical luminance phase offset '01'"}, 530 {R_EE_B_VERT_LUMA_PHASE_OFF_10,1, 531 "Task B: Vertical luminance phase offset '10'"}, 532 {R_EF_B_VERT_LUMA_PHASE_OFF_11,1, 533 "Task B: Vertical luminance phase offset '11'"}, 534 535 /* second PLL (PLL2) and Pulsegenerator Programming */ 536 { R_F0_LFCO_PER_LINE, 1, 537 "LFCO's per line"}, 538 { R_F1_P_I_PARAM_SELECT,1, 539 "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"}, 540 { R_F2_NOMINAL_PLL2_DTO,1, 541 "Nominal PLL2 DTO"}, 542 {R_F3_PLL_INCREMENT,1, 543 "PLL2 Increment"}, 544 {R_F4_PLL2_STATUS,1, 545 "PLL2 Status"}, 546 {R_F5_PULSGEN_LINE_LENGTH,1, 547 "Pulsgen. line length"}, 548 {R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1, 549 "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"}, 550 {R_F7_PULSE_A_POS_MSB,1, 551 "Pulse A Position"}, 552 {R_F8_PULSE_B_POS,2, 553 "Pulse B Position"}, 554 {R_FA_PULSE_C_POS,2, 555 "Pulse C Position"}, 556 /* 0xfc to 0xfe - Reserved */ 557 {R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1, 558 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"}, 559 }; 560 #endif 561