1# SPDX-License-Identifier: GPL-2.0 2# Intel pin control drivers 3 4if (X86 || COMPILE_TEST) 5 6config PINCTRL_BAYTRAIL 7 bool "Intel Baytrail GPIO pin control" 8 depends on ACPI 9 select GPIOLIB 10 select GPIOLIB_IRQCHIP 11 select PINMUX 12 select PINCONF 13 select GENERIC_PINCONF 14 help 15 driver for memory mapped GPIO functionality on Intel Baytrail 16 platforms. Supports 3 banks with 102, 28 and 44 gpios. 17 Most pins are usually muxed to some other functionality by firmware, 18 so only a small amount is available for gpio use. 19 20 Requires ACPI device enumeration code to set up a platform device. 21 22config PINCTRL_CHERRYVIEW 23 tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" 24 depends on ACPI 25 select PINMUX 26 select PINCONF 27 select GENERIC_PINCONF 28 select GPIOLIB 29 select GPIOLIB_IRQCHIP 30 help 31 Cherryview/Braswell pinctrl driver provides an interface that 32 allows configuring of SoC pins and using them as GPIOs. 33 34config PINCTRL_LYNXPOINT 35 tristate "Intel Lynxpoint pinctrl and GPIO driver" 36 depends on ACPI 37 select PINMUX 38 select PINCONF 39 select GENERIC_PINCONF 40 select GPIOLIB 41 select GPIOLIB_IRQCHIP 42 help 43 Lynxpoint is the PCH of Intel Haswell. This pinctrl driver 44 provides an interface that allows configuring of PCH pins and 45 using them as GPIOs. 46 47config PINCTRL_MERRIFIELD 48 tristate "Intel Merrifield pinctrl driver" 49 depends on X86_INTEL_MID 50 select PINMUX 51 select PINCONF 52 select GENERIC_PINCONF 53 help 54 Merrifield Family-Level Interface Shim (FLIS) driver provides an 55 interface that allows configuring of SoC pins and using them as 56 GPIOs. 57 58config PINCTRL_INTEL 59 tristate 60 select PINMUX 61 select PINCONF 62 select GENERIC_PINCONF 63 select GPIOLIB 64 select GPIOLIB_IRQCHIP 65 66config PINCTRL_BROXTON 67 tristate "Intel Broxton pinctrl and GPIO driver" 68 depends on ACPI 69 select PINCTRL_INTEL 70 help 71 Broxton pinctrl driver provides an interface that allows 72 configuring of SoC pins and using them as GPIOs. 73 74config PINCTRL_CANNONLAKE 75 tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" 76 depends on ACPI 77 select PINCTRL_INTEL 78 help 79 This pinctrl driver provides an interface that allows configuring 80 of Intel Cannon Lake PCH pins and using them as GPIOs. 81 82config PINCTRL_CEDARFORK 83 tristate "Intel Cedar Fork pinctrl and GPIO driver" 84 depends on ACPI 85 select PINCTRL_INTEL 86 help 87 This pinctrl driver provides an interface that allows configuring 88 of Intel Cedar Fork PCH pins and using them as GPIOs. 89 90config PINCTRL_DENVERTON 91 tristate "Intel Denverton pinctrl and GPIO driver" 92 depends on ACPI 93 select PINCTRL_INTEL 94 help 95 This pinctrl driver provides an interface that allows configuring 96 of Intel Denverton SoC pins and using them as GPIOs. 97 98config PINCTRL_GEMINILAKE 99 tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" 100 depends on ACPI 101 select PINCTRL_INTEL 102 help 103 This pinctrl driver provides an interface that allows configuring 104 of Intel Gemini Lake SoC pins and using them as GPIOs. 105 106config PINCTRL_ICELAKE 107 tristate "Intel Ice Lake PCH pinctrl and GPIO driver" 108 depends on ACPI 109 select PINCTRL_INTEL 110 help 111 This pinctrl driver provides an interface that allows configuring 112 of Intel Ice Lake PCH pins and using them as GPIOs. 113 114config PINCTRL_LEWISBURG 115 tristate "Intel Lewisburg pinctrl and GPIO driver" 116 depends on ACPI 117 select PINCTRL_INTEL 118 help 119 This pinctrl driver provides an interface that allows configuring 120 of Intel Lewisburg pins and using them as GPIOs. 121 122config PINCTRL_SUNRISEPOINT 123 tristate "Intel Sunrisepoint pinctrl and GPIO driver" 124 depends on ACPI 125 select PINCTRL_INTEL 126 help 127 Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver 128 provides an interface that allows configuring of PCH pins and 129 using them as GPIOs. 130 131config PINCTRL_TIGERLAKE 132 tristate "Intel Tiger Lake pinctrl and GPIO driver" 133 depends on ACPI 134 select PINCTRL_INTEL 135 help 136 This pinctrl driver provides an interface that allows configuring 137 of Intel Tiger Lake PCH pins and using them as GPIOs. 138endif 139