1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 65 #ifndef __iwl_fw_api_rx_h__ 66 #define __iwl_fw_api_rx_h__ 67 68 /* API for pre-9000 hardware */ 69 70 #define IWL_RX_INFO_PHY_CNT 8 71 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 72 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 73 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 74 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 75 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 76 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 77 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 78 79 enum iwl_mac_context_info { 80 MAC_CONTEXT_INFO_NONE, 81 MAC_CONTEXT_INFO_GSCAN, 82 }; 83 84 /** 85 * struct iwl_rx_phy_info - phy info 86 * (REPLY_RX_PHY_CMD = 0xc0) 87 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 88 * @cfg_phy_cnt: configurable DSP phy data byte count 89 * @stat_id: configurable DSP phy data set ID 90 * @reserved1: reserved 91 * @system_timestamp: GP2 at on air rise 92 * @timestamp: TSF at on air rise 93 * @beacon_time_stamp: beacon at on-air rise 94 * @phy_flags: general phy flags: band, modulation, ... 95 * @channel: channel number 96 * @non_cfg_phy: for various implementations of non_cfg_phy 97 * @rate_n_flags: RATE_MCS_* 98 * @byte_count: frame's byte-count 99 * @frame_time: frame's time on the air, based on byte count and frame rate 100 * calculation 101 * @mac_active_msk: what MACs were active when the frame was received 102 * @mac_context_info: additional info on the context in which the frame was 103 * received as defined in &enum iwl_mac_context_info 104 * 105 * Before each Rx, the device sends this data. It contains PHY information 106 * about the reception of the packet. 107 */ 108 struct iwl_rx_phy_info { 109 u8 non_cfg_phy_cnt; 110 u8 cfg_phy_cnt; 111 u8 stat_id; 112 u8 reserved1; 113 __le32 system_timestamp; 114 __le64 timestamp; 115 __le32 beacon_time_stamp; 116 __le16 phy_flags; 117 __le16 channel; 118 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 119 __le32 rate_n_flags; 120 __le32 byte_count; 121 u8 mac_active_msk; 122 u8 mac_context_info; 123 __le16 frame_time; 124 } __packed; 125 126 /* 127 * TCP offload Rx assist info 128 * 129 * bits 0:3 - reserved 130 * bits 4:7 - MIC CRC length 131 * bits 8:12 - MAC header length 132 * bit 13 - Padding indication 133 * bit 14 - A-AMSDU indication 134 * bit 15 - Offload enabled 135 */ 136 enum iwl_csum_rx_assist_info { 137 CSUM_RXA_RESERVED_MASK = 0x000f, 138 CSUM_RXA_MICSIZE_MASK = 0x00f0, 139 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 140 CSUM_RXA_PADD = BIT(13), 141 CSUM_RXA_AMSDU = BIT(14), 142 CSUM_RXA_ENA = BIT(15) 143 }; 144 145 /** 146 * struct iwl_rx_mpdu_res_start - phy info 147 * @byte_count: byte count of the frame 148 * @assist: see &enum iwl_csum_rx_assist_info 149 */ 150 struct iwl_rx_mpdu_res_start { 151 __le16 byte_count; 152 __le16 assist; 153 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 154 155 /** 156 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 157 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 158 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 159 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 160 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 161 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 162 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 163 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 164 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 165 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 166 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 167 */ 168 enum iwl_rx_phy_flags { 169 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 170 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 171 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 172 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 173 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 174 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 175 RX_RES_PHY_FLAGS_AGG = BIT(7), 176 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 177 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 178 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 179 }; 180 181 /** 182 * enum iwl_mvm_rx_status - written by fw for each Rx packet 183 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 184 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 185 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 186 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 187 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable 188 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 189 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 190 * in the driver. 191 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 192 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 193 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 194 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 195 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 196 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 197 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 198 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 199 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 200 * algorithm 201 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 202 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 203 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 204 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 205 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP) 206 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done 207 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 208 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 209 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 210 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 211 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 212 */ 213 enum iwl_mvm_rx_status { 214 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 215 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 216 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 217 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 218 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4), 219 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 220 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 221 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 222 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 223 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 224 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 225 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 226 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 227 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 228 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 229 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 230 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 231 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 232 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13), 233 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14), 234 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15), 235 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 236 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 237 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 238 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 239 }; 240 241 /* 9000 series API */ 242 enum iwl_rx_mpdu_mac_flags1 { 243 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 244 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 245 /* shift should be 4, but the length is measured in 2-byte 246 * words, so shifting only by 3 gives a byte result 247 */ 248 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 249 }; 250 251 enum iwl_rx_mpdu_mac_flags2 { 252 /* in 2-byte words */ 253 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 254 IWL_RX_MPDU_MFLG2_PAD = 0x20, 255 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 256 }; 257 258 enum iwl_rx_mpdu_amsdu_info { 259 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 260 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 261 }; 262 263 #define RX_MPDU_BAND_POS 6 264 #define RX_MPDU_BAND_MASK 0xC0 265 #define BAND_IN_RX_STATUS(_val) \ 266 (((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS) 267 268 enum iwl_rx_l3_proto_values { 269 IWL_RX_L3_TYPE_NONE, 270 IWL_RX_L3_TYPE_IPV4, 271 IWL_RX_L3_TYPE_IPV4_FRAG, 272 IWL_RX_L3_TYPE_IPV6_FRAG, 273 IWL_RX_L3_TYPE_IPV6, 274 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 275 IWL_RX_L3_TYPE_ARP, 276 IWL_RX_L3_TYPE_EAPOL, 277 }; 278 279 #define IWL_RX_L3_PROTO_POS 4 280 281 enum iwl_rx_l3l4_flags { 282 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 283 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 284 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 285 IWL_RX_L3L4_TCP_ACK = BIT(3), 286 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 287 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 288 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 289 }; 290 291 enum iwl_rx_mpdu_status { 292 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 293 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 294 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 295 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 296 IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4), 297 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 298 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 299 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 300 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 301 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 302 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 303 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 304 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 305 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 306 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 307 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 308 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 309 IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12), 310 IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13), 311 IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14), 312 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 313 }; 314 315 enum iwl_rx_mpdu_hash_filter { 316 IWL_RX_MPDU_HF_A1_HASH_MASK = 0x3f, 317 IWL_RX_MPDU_HF_FILTER_STATUS_MASK = 0xc0, 318 }; 319 320 enum iwl_rx_mpdu_sta_id_flags { 321 IWL_RX_MPDU_SIF_STA_ID_MASK = 0x1f, 322 IWL_RX_MPDU_SIF_RRF_ABORT = 0x20, 323 IWL_RX_MPDU_SIF_FILTER_STATUS_MASK = 0xc0, 324 }; 325 326 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 327 328 enum iwl_rx_mpdu_reorder_data { 329 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 330 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 331 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 332 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 333 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 334 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 335 }; 336 337 enum iwl_rx_mpdu_phy_info { 338 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 339 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 340 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 341 /* short preamble is only for CCK, for non-CCK overridden by this */ 342 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 343 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 344 }; 345 346 enum iwl_rx_mpdu_mac_info { 347 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 348 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 349 }; 350 351 /* TSF overload low dword */ 352 enum iwl_rx_phy_data0 { 353 /* info type: HE any */ 354 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 355 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 356 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 357 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 358 /* 1 bit reserved */ 359 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 360 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 361 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 362 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 363 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 364 /* 6 bits reserved */ 365 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 366 }; 367 368 enum iwl_rx_phy_info_type { 369 IWL_RX_PHY_INFO_TYPE_NONE = 0, 370 IWL_RX_PHY_INFO_TYPE_CCK = 1, 371 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 372 IWL_RX_PHY_INFO_TYPE_HT = 3, 373 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 374 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 375 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 376 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 377 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 378 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 379 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 380 }; 381 382 /* TSF overload high dword */ 383 enum iwl_rx_phy_data1 { 384 /* 385 * check this first - if TSF overload is set, 386 * see &enum iwl_rx_phy_info_type 387 */ 388 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 389 390 /* info type: HT/VHT/HE any */ 391 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 392 393 /* info type: HE MU/MU-EXT */ 394 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 395 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 396 397 /* info type: HE any */ 398 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 399 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 400 /* trigger encoded */ 401 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 402 403 /* info type: HE TB/TX-EXT */ 404 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 405 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 406 }; 407 408 /* goes into Metadata DW 7 */ 409 enum iwl_rx_phy_data2 { 410 /* info type: HE MU-EXT */ 411 /* the a1/a2/... is what the PHY/firmware calls the values */ 412 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 413 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 414 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 415 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 416 417 /* info type: HE TB-EXT */ 418 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 419 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 420 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 421 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 422 }; 423 424 /* goes into Metadata DW 8 */ 425 enum iwl_rx_phy_data3 { 426 /* info type: HE MU-EXT */ 427 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 428 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 429 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 430 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 431 }; 432 433 /* goes into Metadata DW 4 high 16 bits */ 434 enum iwl_rx_phy_data4 { 435 /* info type: HE MU-EXT */ 436 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 437 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 438 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 439 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 440 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 441 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 442 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 443 }; 444 445 /** 446 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 447 */ 448 struct iwl_rx_mpdu_desc_v1 { 449 /* DW7 - carries rss_hash only when rpa_en == 1 */ 450 union { 451 /** 452 * @rss_hash: RSS hash value 453 */ 454 __le32 rss_hash; 455 456 /** 457 * @phy_data2: depends on info type (see @phy_data1) 458 */ 459 __le32 phy_data2; 460 }; 461 462 /* DW8 - carries filter_match only when rpa_en == 1 */ 463 union { 464 /** 465 * @filter_match: filter match value 466 */ 467 __le32 filter_match; 468 469 /** 470 * @phy_data3: depends on info type (see @phy_data1) 471 */ 472 __le32 phy_data3; 473 }; 474 475 /* DW9 */ 476 /** 477 * @rate_n_flags: RX rate/flags encoding 478 */ 479 __le32 rate_n_flags; 480 /* DW10 */ 481 /** 482 * @energy_a: energy chain A 483 */ 484 u8 energy_a; 485 /** 486 * @energy_b: energy chain B 487 */ 488 u8 energy_b; 489 /** 490 * @channel: channel number 491 */ 492 u8 channel; 493 /** 494 * @mac_context: MAC context mask 495 */ 496 u8 mac_context; 497 /* DW11 */ 498 /** 499 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 500 */ 501 __le32 gp2_on_air_rise; 502 /* DW12 & DW13 */ 503 union { 504 /** 505 * @tsf_on_air_rise: 506 * TSF value on air rise (INA), only valid if 507 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 508 */ 509 __le64 tsf_on_air_rise; 510 511 struct { 512 /** 513 * @phy_data0: depends on info_type, see @phy_data1 514 */ 515 __le32 phy_data0; 516 /** 517 * @phy_data1: valid only if 518 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 519 * see &enum iwl_rx_phy_data1. 520 */ 521 __le32 phy_data1; 522 }; 523 }; 524 } __packed; 525 526 /** 527 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 528 */ 529 struct iwl_rx_mpdu_desc_v3 { 530 /* DW7 - carries filter_match only when rpa_en == 1 */ 531 union { 532 /** 533 * @filter_match: filter match value 534 */ 535 __le32 filter_match; 536 537 /** 538 * @phy_data2: depends on info type (see @phy_data1) 539 */ 540 __le32 phy_data2; 541 }; 542 543 /* DW8 - carries rss_hash only when rpa_en == 1 */ 544 union { 545 /** 546 * @rss_hash: RSS hash value 547 */ 548 __le32 rss_hash; 549 550 /** 551 * @phy_data3: depends on info type (see @phy_data1) 552 */ 553 __le32 phy_data3; 554 }; 555 /* DW9 */ 556 /** 557 * @partial_hash: 31:0 ip/tcp header hash 558 * w/o some fields (such as IP SRC addr) 559 */ 560 __le32 partial_hash; 561 /* DW10 */ 562 /** 563 * @raw_xsum: raw xsum value 564 */ 565 __le32 raw_xsum; 566 /* DW11 */ 567 /** 568 * @rate_n_flags: RX rate/flags encoding 569 */ 570 __le32 rate_n_flags; 571 /* DW12 */ 572 /** 573 * @energy_a: energy chain A 574 */ 575 u8 energy_a; 576 /** 577 * @energy_b: energy chain B 578 */ 579 u8 energy_b; 580 /** 581 * @channel: channel number 582 */ 583 u8 channel; 584 /** 585 * @mac_context: MAC context mask 586 */ 587 u8 mac_context; 588 /* DW13 */ 589 /** 590 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 591 */ 592 __le32 gp2_on_air_rise; 593 /* DW14 & DW15 */ 594 union { 595 /** 596 * @tsf_on_air_rise: 597 * TSF value on air rise (INA), only valid if 598 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 599 */ 600 __le64 tsf_on_air_rise; 601 602 struct { 603 /** 604 * @phy_data0: depends on info_type, see @phy_data1 605 */ 606 __le32 phy_data0; 607 /** 608 * @phy_data1: valid only if 609 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 610 * see &enum iwl_rx_phy_data1. 611 */ 612 __le32 phy_data1; 613 }; 614 }; 615 /* DW16 & DW17 */ 616 /** 617 * @reserved: reserved 618 */ 619 __le32 reserved[2]; 620 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 621 622 /** 623 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 624 */ 625 struct iwl_rx_mpdu_desc { 626 /* DW2 */ 627 /** 628 * @mpdu_len: MPDU length 629 */ 630 __le16 mpdu_len; 631 /** 632 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 633 */ 634 u8 mac_flags1; 635 /** 636 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 637 */ 638 u8 mac_flags2; 639 /* DW3 */ 640 /** 641 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 642 */ 643 u8 amsdu_info; 644 /** 645 * @phy_info: &enum iwl_rx_mpdu_phy_info 646 */ 647 __le16 phy_info; 648 /** 649 * @mac_phy_idx: MAC/PHY index 650 */ 651 u8 mac_phy_idx; 652 /* DW4 - carries csum data only when rpa_en == 1 */ 653 /** 654 * @raw_csum: raw checksum (alledgedly unreliable) 655 */ 656 __le16 raw_csum; 657 658 union { 659 /** 660 * @l3l4_flags: &enum iwl_rx_l3l4_flags 661 */ 662 __le16 l3l4_flags; 663 664 /** 665 * @phy_data4: depends on info type, see phy_data1 666 */ 667 __le16 phy_data4; 668 }; 669 /* DW5 */ 670 /** 671 * @status: &enum iwl_rx_mpdu_status 672 */ 673 __le16 status; 674 /** 675 * @hash_filter: hash filter value 676 */ 677 u8 hash_filter; 678 /** 679 * @sta_id_flags: &enum iwl_rx_mpdu_sta_id_flags 680 */ 681 u8 sta_id_flags; 682 /* DW6 */ 683 /** 684 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 685 */ 686 __le32 reorder_data; 687 688 union { 689 struct iwl_rx_mpdu_desc_v1 v1; 690 struct iwl_rx_mpdu_desc_v3 v3; 691 }; 692 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 693 694 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 695 696 #define RX_NO_DATA_CHAIN_A_POS 0 697 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 698 #define RX_NO_DATA_CHAIN_B_POS 8 699 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 700 #define RX_NO_DATA_CHANNEL_POS 16 701 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 702 703 #define RX_NO_DATA_INFO_TYPE_POS 0 704 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 705 #define RX_NO_DATA_INFO_TYPE_NONE 0 706 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 707 #define RX_NO_DATA_INFO_TYPE_NDP 2 708 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 709 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED 4 710 711 #define RX_NO_DATA_INFO_ERR_POS 8 712 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 713 #define RX_NO_DATA_INFO_ERR_NONE 0 714 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 715 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 716 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 717 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 718 719 #define RX_NO_DATA_FRAME_TIME_POS 0 720 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 721 722 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 723 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 724 725 /** 726 * struct iwl_rx_no_data - RX no data descriptor 727 * @info: 7:0 frame type, 15:8 RX error type 728 * @rssi: 7:0 energy chain-A, 729 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 730 * @on_air_rise_time: GP2 during on air rise 731 * @fr_time: frame time 732 * @rate: rate/mcs of frame 733 * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type 734 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 735 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 736 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 737 */ 738 struct iwl_rx_no_data { 739 __le32 info; 740 __le32 rssi; 741 __le32 on_air_rise_time; 742 __le32 fr_time; 743 __le32 rate; 744 __le32 phy_info[2]; 745 __le32 rx_vec[2]; 746 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1 */ 747 748 struct iwl_frame_release { 749 u8 baid; 750 u8 reserved; 751 __le16 nssn; 752 }; 753 754 /** 755 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 756 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 757 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 758 */ 759 enum iwl_bar_frame_release_sta_tid { 760 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 761 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 762 }; 763 764 /** 765 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 766 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 767 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 768 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 769 */ 770 enum iwl_bar_frame_release_ba_info { 771 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 772 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 773 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 774 }; 775 776 /** 777 * struct iwl_bar_frame_release - frame release from BAR info 778 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 779 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 780 */ 781 struct iwl_bar_frame_release { 782 __le32 sta_tid; 783 __le32 ba_info; 784 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 785 786 enum iwl_rss_hash_func_en { 787 IWL_RSS_HASH_TYPE_IPV4_TCP, 788 IWL_RSS_HASH_TYPE_IPV4_UDP, 789 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 790 IWL_RSS_HASH_TYPE_IPV6_TCP, 791 IWL_RSS_HASH_TYPE_IPV6_UDP, 792 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 793 }; 794 795 #define IWL_RSS_HASH_KEY_CNT 10 796 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 797 #define IWL_RSS_ENABLE 1 798 799 /** 800 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 801 * 802 * @flags: 1 - enable, 0 - disable 803 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 804 * @reserved: reserved 805 * @secret_key: 320 bit input of random key configuration from driver 806 * @indirection_table: indirection table 807 */ 808 struct iwl_rss_config_cmd { 809 __le32 flags; 810 u8 hash_mask; 811 u8 reserved[3]; 812 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 813 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 814 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 815 816 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 817 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 818 819 /** 820 * struct iwl_rxq_sync_cmd - RXQ notification trigger 821 * 822 * @flags: flags of the notification. bit 0:3 are the sender queue 823 * @rxq_mask: rx queues to send the notification on 824 * @count: number of bytes in payload, should be DWORD aligned 825 * @payload: data to send to rx queues 826 */ 827 struct iwl_rxq_sync_cmd { 828 __le32 flags; 829 __le32 rxq_mask; 830 __le32 count; 831 u8 payload[]; 832 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 833 834 /** 835 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 836 * sync command 837 * 838 * @count: number of bytes in payload 839 * @payload: data to send to rx queues 840 */ 841 struct iwl_rxq_sync_notification { 842 __le32 count; 843 u8 payload[]; 844 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 845 846 /** 847 * enum iwl_mvm_rxq_notif_type - Internal message identifier 848 * 849 * @IWL_MVM_RXQ_EMPTY: empty sync notification 850 * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA 851 * @IWL_MVM_RXQ_NSSN_SYNC: notify all the RSS queues with the new NSSN 852 */ 853 enum iwl_mvm_rxq_notif_type { 854 IWL_MVM_RXQ_EMPTY, 855 IWL_MVM_RXQ_NOTIF_DEL_BA, 856 IWL_MVM_RXQ_NSSN_SYNC, 857 }; 858 859 /** 860 * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent 861 * in &iwl_rxq_sync_cmd. Should be DWORD aligned. 862 * FW is agnostic to the payload, so there are no endianity requirements. 863 * 864 * @type: value from &iwl_mvm_rxq_notif_type 865 * @sync: ctrl path is waiting for all notifications to be received 866 * @cookie: internal cookie to identify old notifications 867 * @data: payload 868 */ 869 struct iwl_mvm_internal_rxq_notif { 870 u16 type; 871 u16 sync; 872 u32 cookie; 873 u8 data[]; 874 } __packed; 875 876 /** 877 * enum iwl_mvm_pm_event - type of station PM event 878 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 879 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 880 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 881 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 882 */ 883 enum iwl_mvm_pm_event { 884 IWL_MVM_PM_EVENT_AWAKE, 885 IWL_MVM_PM_EVENT_ASLEEP, 886 IWL_MVM_PM_EVENT_UAPSD, 887 IWL_MVM_PM_EVENT_PS_POLL, 888 }; /* PEER_PM_NTFY_API_E_VER_1 */ 889 890 /** 891 * struct iwl_mvm_pm_state_notification - station PM state notification 892 * @sta_id: station ID of the station changing state 893 * @type: the new powersave state, see &enum iwl_mvm_pm_event 894 */ 895 struct iwl_mvm_pm_state_notification { 896 u8 sta_id; 897 u8 type; 898 /* private: */ 899 __le16 reserved; 900 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 901 902 #define BA_WINDOW_STREAMS_MAX 16 903 #define BA_WINDOW_STATUS_TID_MSK 0x000F 904 #define BA_WINDOW_STATUS_STA_ID_POS 4 905 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 906 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 907 908 /** 909 * struct iwl_ba_window_status_notif - reordering window's status notification 910 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 911 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 912 * @start_seq_num: the start sequence number of the bitmap 913 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 914 */ 915 struct iwl_ba_window_status_notif { 916 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 917 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 918 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 919 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 920 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 921 922 /** 923 * struct iwl_rfh_queue_config - RX queue configuration 924 * @q_num: Q num 925 * @enable: enable queue 926 * @reserved: alignment 927 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 928 * @fr_bd_cb: DMA address of freeRB table 929 * @ur_bd_cb: DMA address of used RB table 930 * @fr_bd_wid: Initial index of the free table 931 */ 932 struct iwl_rfh_queue_data { 933 u8 q_num; 934 u8 enable; 935 __le16 reserved; 936 __le64 urbd_stts_wrptr; 937 __le64 fr_bd_cb; 938 __le64 ur_bd_cb; 939 __le32 fr_bd_wid; 940 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 941 942 /** 943 * struct iwl_rfh_queue_config - RX queue configuration 944 * @num_queues: number of queues configured 945 * @reserved: alignment 946 * @data: DMA addresses per-queue 947 */ 948 struct iwl_rfh_queue_config { 949 u8 num_queues; 950 u8 reserved[3]; 951 struct iwl_rfh_queue_data data[]; 952 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 953 954 #endif /* __iwl_fw_api_rx_h__ */ 955