1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Roy Luo <royluo@google.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 */ 7 8 #include <linux/firmware.h> 9 #include "mt7615.h" 10 #include "mcu.h" 11 #include "mac.h" 12 #include "eeprom.h" 13 14 struct mt7615_patch_hdr { 15 char build_date[16]; 16 char platform[4]; 17 __be32 hw_sw_ver; 18 __be32 patch_ver; 19 __be16 checksum; 20 } __packed; 21 22 struct mt7615_fw_trailer { 23 __le32 addr; 24 u8 chip_id; 25 u8 feature_set; 26 u8 eco_code; 27 char fw_ver[10]; 28 char build_date[15]; 29 __le32 len; 30 } __packed; 31 32 #define FW_V3_COMMON_TAILER_SIZE 36 33 #define FW_V3_REGION_TAILER_SIZE 40 34 #define FW_START_OVERRIDE BIT(0) 35 #define FW_START_DLYCAL BIT(1) 36 #define FW_START_WORKING_PDA_CR4 BIT(2) 37 38 struct mt7663_fw_trailer { 39 u8 chip_id; 40 u8 eco_code; 41 u8 n_region; 42 u8 format_ver; 43 u8 format_flag; 44 u8 reserv[2]; 45 char fw_ver[10]; 46 char build_date[15]; 47 __le32 crc; 48 } __packed; 49 50 struct mt7663_fw_buf { 51 __le32 crc; 52 __le32 d_img_size; 53 __le32 block_size; 54 u8 rsv[4]; 55 __le32 img_dest_addr; 56 __le32 img_size; 57 u8 feature_set; 58 }; 59 60 #define MT7615_PATCH_ADDRESS 0x80000 61 #define MT7622_PATCH_ADDRESS 0x9c000 62 #define MT7663_PATCH_ADDRESS 0xdc000 63 64 #define N9_REGION_NUM 2 65 #define CR4_REGION_NUM 1 66 67 #define IMG_CRC_LEN 4 68 69 #define FW_FEATURE_SET_ENCRYPT BIT(0) 70 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 71 72 #define DL_MODE_ENCRYPT BIT(0) 73 #define DL_MODE_KEY_IDX GENMASK(2, 1) 74 #define DL_MODE_RESET_SEC_IV BIT(3) 75 #define DL_MODE_WORKING_PDA_CR4 BIT(4) 76 #define DL_MODE_VALID_RAM_ENTRY BIT(5) 77 #define DL_MODE_NEED_RSP BIT(31) 78 79 #define FW_START_OVERRIDE BIT(0) 80 #define FW_START_WORKING_PDA_CR4 BIT(2) 81 82 void mt7615_mcu_fill_msg(struct mt7615_dev *dev, struct sk_buff *skb, 83 int cmd, int *wait_seq) 84 { 85 int txd_len, mcu_cmd = cmd & MCU_CMD_MASK; 86 struct mt7615_uni_txd *uni_txd; 87 struct mt7615_mcu_txd *mcu_txd; 88 u8 seq, q_idx, pkt_fmt; 89 __le32 *txd; 90 u32 val; 91 92 seq = ++dev->mt76.mcu.msg_seq & 0xf; 93 if (!seq) 94 seq = ++dev->mt76.mcu.msg_seq & 0xf; 95 if (wait_seq) 96 *wait_seq = seq; 97 98 txd_len = cmd & MCU_UNI_PREFIX ? sizeof(*uni_txd) : sizeof(*mcu_txd); 99 txd = (__le32 *)skb_push(skb, txd_len); 100 101 if (cmd != MCU_CMD_FW_SCATTER) { 102 q_idx = MT_TX_MCU_PORT_RX_Q0; 103 pkt_fmt = MT_TX_TYPE_CMD; 104 } else { 105 q_idx = MT_TX_MCU_PORT_RX_FWDL; 106 pkt_fmt = MT_TX_TYPE_FW; 107 } 108 109 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) | 110 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_MCU) | 111 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 112 txd[0] = cpu_to_le32(val); 113 114 val = MT_TXD1_LONG_FORMAT | 115 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_CMD) | 116 FIELD_PREP(MT_TXD1_PKT_FMT, pkt_fmt); 117 txd[1] = cpu_to_le32(val); 118 119 if (cmd & MCU_UNI_PREFIX) { 120 uni_txd = (struct mt7615_uni_txd *)txd; 121 uni_txd->len = cpu_to_le16(skb->len - sizeof(uni_txd->txd)); 122 uni_txd->option = MCU_CMD_UNI_EXT_ACK; 123 uni_txd->cid = cpu_to_le16(mcu_cmd); 124 uni_txd->s2d_index = MCU_S2D_H2N; 125 uni_txd->pkt_type = MCU_PKT_ID; 126 uni_txd->seq = seq; 127 128 return; 129 } 130 131 mcu_txd = (struct mt7615_mcu_txd *)txd; 132 mcu_txd->len = cpu_to_le16(skb->len - sizeof(mcu_txd->txd)); 133 mcu_txd->pq_id = cpu_to_le16(MCU_PQ_ID(MT_TX_PORT_IDX_MCU, q_idx)); 134 mcu_txd->s2d_index = MCU_S2D_H2N; 135 mcu_txd->pkt_type = MCU_PKT_ID; 136 mcu_txd->seq = seq; 137 138 if (cmd & MCU_FW_PREFIX) { 139 mcu_txd->set_query = MCU_Q_NA; 140 mcu_txd->cid = mcu_cmd; 141 } else { 142 mcu_txd->cid = MCU_CMD_EXT_CID; 143 mcu_txd->set_query = MCU_Q_SET; 144 mcu_txd->ext_cid = cmd; 145 mcu_txd->ext_cid_ack = 1; 146 } 147 } 148 149 static int __mt7615_mcu_msg_send(struct mt7615_dev *dev, struct sk_buff *skb, 150 int cmd, int *wait_seq) 151 { 152 enum mt76_txq_id qid; 153 154 mt7615_mcu_fill_msg(dev, skb, cmd, wait_seq); 155 if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state)) 156 qid = MT_TXQ_MCU; 157 else 158 qid = MT_TXQ_FWDL; 159 160 return mt76_tx_queue_skb_raw(dev, qid, skb, 0); 161 } 162 163 static int 164 mt7615_mcu_parse_response(struct mt7615_dev *dev, int cmd, 165 struct sk_buff *skb, int seq) 166 { 167 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 168 int ret = 0; 169 170 if (seq != rxd->seq) 171 return -EAGAIN; 172 173 switch (cmd) { 174 case MCU_CMD_PATCH_SEM_CONTROL: 175 skb_pull(skb, sizeof(*rxd) - 4); 176 ret = *skb->data; 177 break; 178 case MCU_EXT_CMD_GET_TEMP: 179 skb_pull(skb, sizeof(*rxd)); 180 ret = le32_to_cpu(*(__le32 *)skb->data); 181 break; 182 default: 183 break; 184 } 185 dev_kfree_skb(skb); 186 187 return ret; 188 } 189 190 int mt7615_mcu_wait_response(struct mt7615_dev *dev, int cmd, int seq) 191 { 192 unsigned long expires = jiffies + 20 * HZ; 193 struct sk_buff *skb; 194 int ret = 0; 195 196 while (true) { 197 skb = mt76_mcu_get_response(&dev->mt76, expires); 198 if (!skb) { 199 dev_err(dev->mt76.dev, "Message %ld (seq %d) timeout\n", 200 cmd & MCU_CMD_MASK, seq); 201 return -ETIMEDOUT; 202 } 203 204 ret = mt7615_mcu_parse_response(dev, cmd, skb, seq); 205 if (ret != -EAGAIN) 206 break; 207 } 208 209 return ret; 210 } 211 212 static int 213 mt7615_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, 214 int cmd, bool wait_resp) 215 { 216 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 217 int ret, seq; 218 219 mutex_lock(&mdev->mcu.mutex); 220 221 ret = __mt7615_mcu_msg_send(dev, skb, cmd, &seq); 222 if (ret) 223 goto out; 224 225 if (wait_resp) 226 ret = mt7615_mcu_wait_response(dev, cmd, seq); 227 228 out: 229 mutex_unlock(&mdev->mcu.mutex); 230 231 return ret; 232 } 233 234 static int 235 mt7615_mcu_msg_send(struct mt76_dev *mdev, int cmd, const void *data, 236 int len, bool wait_resp) 237 { 238 struct sk_buff *skb; 239 240 skb = mt7615_mcu_msg_alloc(data, len); 241 if (!skb) 242 return -ENOMEM; 243 244 return __mt76_mcu_skb_send_msg(mdev, skb, cmd, wait_resp); 245 } 246 247 static void 248 mt7615_mcu_csa_finish(void *priv, u8 *mac, struct ieee80211_vif *vif) 249 { 250 if (vif->csa_active) 251 ieee80211_csa_finish(vif); 252 } 253 254 static void 255 mt7615_mcu_rx_radar_detected(struct mt7615_dev *dev, struct sk_buff *skb) 256 { 257 struct mt76_phy *mphy = &dev->mt76.phy; 258 struct mt7615_mcu_rdd_report *r; 259 260 r = (struct mt7615_mcu_rdd_report *)skb->data; 261 262 if (r->idx && dev->mt76.phy2) 263 mphy = dev->mt76.phy2; 264 265 ieee80211_radar_detected(mphy->hw); 266 dev->hw_pattern++; 267 } 268 269 static void 270 mt7615_mcu_rx_log_message(struct mt7615_dev *dev, struct sk_buff *skb) 271 { 272 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 273 const char *data = (char *)&rxd[1]; 274 const char *type; 275 276 switch (rxd->s2d_index) { 277 case 0: 278 type = "N9"; 279 break; 280 case 2: 281 type = "CR4"; 282 break; 283 default: 284 type = "unknown"; 285 break; 286 } 287 288 wiphy_info(mt76_hw(dev)->wiphy, "%s: %s", type, data); 289 } 290 291 static void 292 mt7615_mcu_rx_ext_event(struct mt7615_dev *dev, struct sk_buff *skb) 293 { 294 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 295 296 switch (rxd->ext_eid) { 297 case MCU_EXT_EVENT_RDD_REPORT: 298 mt7615_mcu_rx_radar_detected(dev, skb); 299 break; 300 case MCU_EXT_EVENT_CSA_NOTIFY: 301 ieee80211_iterate_active_interfaces_atomic(dev->mt76.hw, 302 IEEE80211_IFACE_ITER_RESUME_ALL, 303 mt7615_mcu_csa_finish, dev); 304 break; 305 case MCU_EXT_EVENT_FW_LOG_2_HOST: 306 mt7615_mcu_rx_log_message(dev, skb); 307 break; 308 default: 309 break; 310 } 311 } 312 313 static void 314 mt7615_mcu_rx_unsolicited_event(struct mt7615_dev *dev, struct sk_buff *skb) 315 { 316 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 317 318 switch (rxd->eid) { 319 case MCU_EVENT_EXT: 320 mt7615_mcu_rx_ext_event(dev, skb); 321 break; 322 default: 323 break; 324 } 325 dev_kfree_skb(skb); 326 } 327 328 void mt7615_mcu_rx_event(struct mt7615_dev *dev, struct sk_buff *skb) 329 { 330 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 331 332 if (rxd->ext_eid == MCU_EXT_EVENT_THERMAL_PROTECT || 333 rxd->ext_eid == MCU_EXT_EVENT_FW_LOG_2_HOST || 334 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP || 335 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC || 336 !rxd->seq) 337 mt7615_mcu_rx_unsolicited_event(dev, skb); 338 else 339 mt76_mcu_rx_event(&dev->mt76, skb); 340 } 341 342 static int mt7615_mcu_init_download(struct mt7615_dev *dev, u32 addr, 343 u32 len, u32 mode) 344 { 345 struct { 346 __le32 addr; 347 __le32 len; 348 __le32 mode; 349 } req = { 350 .addr = cpu_to_le32(addr), 351 .len = cpu_to_le32(len), 352 .mode = cpu_to_le32(mode), 353 }; 354 355 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_TARGET_ADDRESS_LEN_REQ, 356 &req, sizeof(req), true); 357 } 358 359 static int 360 mt7615_mcu_add_dev(struct mt7615_dev *dev, struct ieee80211_vif *vif, 361 bool enable) 362 { 363 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 364 struct { 365 struct req_hdr { 366 u8 omac_idx; 367 u8 band_idx; 368 __le16 tlv_num; 369 u8 is_tlv_append; 370 u8 rsv[3]; 371 } __packed hdr; 372 struct req_tlv { 373 __le16 tag; 374 __le16 len; 375 u8 active; 376 u8 band_idx; 377 u8 omac_addr[ETH_ALEN]; 378 } __packed tlv; 379 } data = { 380 .hdr = { 381 .omac_idx = mvif->omac_idx, 382 .band_idx = mvif->band_idx, 383 .tlv_num = cpu_to_le16(1), 384 .is_tlv_append = 1, 385 }, 386 .tlv = { 387 .tag = cpu_to_le16(DEV_INFO_ACTIVE), 388 .len = cpu_to_le16(sizeof(struct req_tlv)), 389 .active = enable, 390 .band_idx = mvif->band_idx, 391 }, 392 }; 393 394 memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN); 395 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_DEV_INFO_UPDATE, 396 &data, sizeof(data), true); 397 } 398 399 static int 400 mt7615_mcu_add_beacon_offload(struct mt7615_dev *dev, 401 struct ieee80211_hw *hw, 402 struct ieee80211_vif *vif, bool enable) 403 { 404 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 405 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 406 struct ieee80211_mutable_offsets offs; 407 struct ieee80211_tx_info *info; 408 struct req { 409 u8 omac_idx; 410 u8 enable; 411 u8 wlan_idx; 412 u8 band_idx; 413 u8 pkt_type; 414 u8 need_pre_tbtt_int; 415 __le16 csa_ie_pos; 416 __le16 pkt_len; 417 __le16 tim_ie_pos; 418 u8 pkt[512]; 419 u8 csa_cnt; 420 /* bss color change */ 421 u8 bcc_cnt; 422 __le16 bcc_ie_pos; 423 } __packed req = { 424 .omac_idx = mvif->omac_idx, 425 .enable = enable, 426 .wlan_idx = wcid->idx, 427 .band_idx = mvif->band_idx, 428 }; 429 struct sk_buff *skb; 430 431 skb = ieee80211_beacon_get_template(hw, vif, &offs); 432 if (!skb) 433 return -EINVAL; 434 435 if (skb->len > 512 - MT_TXD_SIZE) { 436 dev_err(dev->mt76.dev, "Bcn size limit exceed\n"); 437 dev_kfree_skb(skb); 438 return -EINVAL; 439 } 440 441 if (mvif->band_idx) { 442 info = IEEE80211_SKB_CB(skb); 443 info->hw_queue |= MT_TX_HW_QUEUE_EXT_PHY; 444 } 445 446 mt7615_mac_write_txwi(dev, (__le32 *)(req.pkt), skb, wcid, NULL, 447 0, NULL, true); 448 memcpy(req.pkt + MT_TXD_SIZE, skb->data, skb->len); 449 req.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len); 450 req.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset); 451 if (offs.csa_counter_offs[0]) { 452 u16 csa_offs; 453 454 csa_offs = MT_TXD_SIZE + offs.csa_counter_offs[0] - 4; 455 req.csa_ie_pos = cpu_to_le16(csa_offs); 456 req.csa_cnt = skb->data[offs.csa_counter_offs[0]]; 457 } 458 dev_kfree_skb(skb); 459 460 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_BCN_OFFLOAD, 461 &req, sizeof(req), true); 462 } 463 464 static int 465 mt7615_mcu_ctrl_pm_state(struct mt7615_dev *dev, int band, int state) 466 { 467 #define ENTER_PM_STATE 1 468 #define EXIT_PM_STATE 2 469 struct { 470 u8 pm_number; 471 u8 pm_state; 472 u8 bssid[ETH_ALEN]; 473 u8 dtim_period; 474 u8 wlan_idx; 475 __le16 bcn_interval; 476 __le32 aid; 477 __le32 rx_filter; 478 u8 band_idx; 479 u8 rsv[3]; 480 __le32 feature; 481 u8 omac_idx; 482 u8 wmm_idx; 483 u8 bcn_loss_cnt; 484 u8 bcn_sp_duration; 485 } __packed req = { 486 .pm_number = 5, 487 .pm_state = state ? ENTER_PM_STATE : EXIT_PM_STATE, 488 .band_idx = band, 489 }; 490 491 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_PM_STATE_CTRL, 492 &req, sizeof(req), true); 493 } 494 495 static struct sk_buff * 496 mt7615_mcu_alloc_sta_req(struct mt7615_vif *mvif, struct mt7615_sta *msta) 497 { 498 struct sta_req_hdr hdr = { 499 .bss_idx = mvif->idx, 500 .wlan_idx = msta ? msta->wcid.idx : 0, 501 .muar_idx = msta ? mvif->omac_idx : 0, 502 .is_tlv_append = 1, 503 }; 504 struct sk_buff *skb; 505 506 skb = mt7615_mcu_msg_alloc(NULL, MT7615_STA_UPDATE_MAX_SIZE); 507 if (!skb) 508 return ERR_PTR(-ENOMEM); 509 510 skb_put_data(skb, &hdr, sizeof(hdr)); 511 512 return skb; 513 } 514 515 static struct wtbl_req_hdr * 516 mt7615_mcu_alloc_wtbl_req(struct mt7615_sta *msta, int cmd, 517 void *sta_wtbl, struct sk_buff **skb) 518 { 519 struct tlv *sta_hdr = sta_wtbl; 520 struct wtbl_req_hdr hdr = { 521 .wlan_idx = msta->wcid.idx, 522 .operation = cmd, 523 }; 524 struct sk_buff *nskb = *skb; 525 526 if (!nskb) { 527 nskb = mt7615_mcu_msg_alloc(NULL, MT7615_WTBL_UPDATE_BA_SIZE); 528 if (!nskb) 529 return ERR_PTR(-ENOMEM); 530 531 *skb = nskb; 532 } 533 534 if (sta_hdr) 535 sta_hdr->len = cpu_to_le16(sizeof(hdr)); 536 537 return skb_put_data(nskb, &hdr, sizeof(hdr)); 538 } 539 540 static struct tlv * 541 mt7615_mcu_add_nested_tlv(struct sk_buff *skb, int tag, int len, 542 void *sta_ntlv, void *sta_wtbl) 543 { 544 struct sta_ntlv_hdr *ntlv_hdr = sta_ntlv; 545 struct tlv *sta_hdr = sta_wtbl; 546 struct tlv *ptlv, tlv = { 547 .tag = cpu_to_le16(tag), 548 .len = cpu_to_le16(len), 549 }; 550 u16 ntlv; 551 552 ptlv = skb_put(skb, len); 553 memcpy(ptlv, &tlv, sizeof(tlv)); 554 555 ntlv = le16_to_cpu(ntlv_hdr->tlv_num); 556 ntlv_hdr->tlv_num = cpu_to_le16(ntlv + 1); 557 558 if (sta_hdr) { 559 u16 size = le16_to_cpu(sta_hdr->len); 560 561 sta_hdr->len = cpu_to_le16(size + len); 562 } 563 564 return ptlv; 565 } 566 567 static struct tlv * 568 mt7615_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 569 { 570 return mt7615_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 571 } 572 573 static int 574 mt7615_mcu_bss_basic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif, 575 bool enable) 576 { 577 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 578 struct bss_info_basic *bss; 579 u8 wlan_idx = mvif->sta.wcid.idx; 580 u32 type = NETWORK_INFRA; 581 struct tlv *tlv; 582 583 tlv = mt7615_mcu_add_tlv(skb, BSS_INFO_BASIC, sizeof(*bss)); 584 585 switch (vif->type) { 586 case NL80211_IFTYPE_MESH_POINT: 587 case NL80211_IFTYPE_AP: 588 break; 589 case NL80211_IFTYPE_STATION: 590 /* TODO: enable BSS_INFO_UAPSD & BSS_INFO_PM */ 591 if (enable) { 592 struct ieee80211_sta *sta; 593 struct mt7615_sta *msta; 594 595 rcu_read_lock(); 596 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 597 if (!sta) { 598 rcu_read_unlock(); 599 return -EINVAL; 600 } 601 602 msta = (struct mt7615_sta *)sta->drv_priv; 603 wlan_idx = msta->wcid.idx; 604 rcu_read_unlock(); 605 } 606 break; 607 case NL80211_IFTYPE_ADHOC: 608 type = NETWORK_IBSS; 609 break; 610 default: 611 WARN_ON(1); 612 break; 613 } 614 615 bss = (struct bss_info_basic *)tlv; 616 memcpy(bss->bssid, vif->bss_conf.bssid, ETH_ALEN); 617 bss->bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int); 618 bss->network_type = cpu_to_le32(type); 619 bss->dtim_period = vif->bss_conf.dtim_period; 620 bss->bmc_tx_wlan_idx = wlan_idx; 621 bss->wmm_idx = mvif->wmm_idx; 622 bss->active = enable; 623 624 return 0; 625 } 626 627 static void 628 mt7615_mcu_bss_omac_tlv(struct sk_buff *skb, struct ieee80211_vif *vif) 629 { 630 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 631 struct bss_info_omac *omac; 632 struct tlv *tlv; 633 u32 type = 0; 634 u8 idx; 635 636 tlv = mt7615_mcu_add_tlv(skb, BSS_INFO_OMAC, sizeof(*omac)); 637 638 switch (vif->type) { 639 case NL80211_IFTYPE_MESH_POINT: 640 case NL80211_IFTYPE_AP: 641 type = CONNECTION_INFRA_AP; 642 break; 643 case NL80211_IFTYPE_STATION: 644 type = CONNECTION_INFRA_STA; 645 break; 646 case NL80211_IFTYPE_ADHOC: 647 type = CONNECTION_IBSS_ADHOC; 648 break; 649 default: 650 WARN_ON(1); 651 break; 652 } 653 654 omac = (struct bss_info_omac *)tlv; 655 idx = mvif->omac_idx > EXT_BSSID_START ? HW_BSSID_0 : mvif->omac_idx; 656 omac->conn_type = cpu_to_le32(type); 657 omac->omac_idx = mvif->omac_idx; 658 omac->band_idx = mvif->band_idx; 659 omac->hw_bss_idx = idx; 660 } 661 662 /* SIFS 20us + 512 byte beacon tranmitted by 1Mbps (3906us) */ 663 #define BCN_TX_ESTIMATE_TIME (4096 + 20) 664 static void 665 mt7615_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt7615_vif *mvif) 666 { 667 struct bss_info_ext_bss *ext; 668 int ext_bss_idx, tsf_offset; 669 struct tlv *tlv; 670 671 ext_bss_idx = mvif->omac_idx - EXT_BSSID_START; 672 if (ext_bss_idx < 0) 673 return; 674 675 tlv = mt7615_mcu_add_tlv(skb, BSS_INFO_EXT_BSS, sizeof(*ext)); 676 677 ext = (struct bss_info_ext_bss *)tlv; 678 tsf_offset = ext_bss_idx * BCN_TX_ESTIMATE_TIME; 679 ext->mbss_tsf_offset = cpu_to_le32(tsf_offset); 680 } 681 682 static void 683 mt7615_mcu_sta_ba_tlv(struct sk_buff *skb, 684 struct ieee80211_ampdu_params *params, 685 bool enable, bool tx) 686 { 687 struct sta_rec_ba *ba; 688 struct tlv *tlv; 689 690 tlv = mt7615_mcu_add_tlv(skb, STA_REC_BA, sizeof(*ba)); 691 692 ba = (struct sta_rec_ba *)tlv; 693 ba->ba_type = tx ? MT_BA_TYPE_ORIGINATOR : MT_BA_TYPE_RECIPIENT, 694 ba->winsize = cpu_to_le16(params->buf_size); 695 ba->ssn = cpu_to_le16(params->ssn); 696 ba->ba_en = enable << params->tid; 697 ba->amsdu = params->amsdu; 698 ba->tid = params->tid; 699 } 700 701 static void 702 mt7615_mcu_sta_basic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif, 703 struct ieee80211_sta *sta, bool enable) 704 { 705 struct sta_rec_basic *basic; 706 struct tlv *tlv; 707 708 tlv = mt7615_mcu_add_tlv(skb, STA_REC_BASIC, sizeof(*basic)); 709 710 basic = (struct sta_rec_basic *)tlv; 711 basic->extra_info = cpu_to_le16(EXTRA_INFO_VER); 712 713 if (enable) { 714 basic->extra_info |= cpu_to_le16(EXTRA_INFO_NEW); 715 basic->conn_state = CONN_STATE_PORT_SECURE; 716 } else { 717 basic->conn_state = CONN_STATE_DISCONNECT; 718 } 719 720 if (!sta) { 721 basic->conn_type = cpu_to_le32(CONNECTION_INFRA_BC); 722 eth_broadcast_addr(basic->peer_addr); 723 return; 724 } 725 726 switch (vif->type) { 727 case NL80211_IFTYPE_MESH_POINT: 728 case NL80211_IFTYPE_AP: 729 basic->conn_type = cpu_to_le32(CONNECTION_INFRA_STA); 730 break; 731 case NL80211_IFTYPE_STATION: 732 basic->conn_type = cpu_to_le32(CONNECTION_INFRA_AP); 733 break; 734 case NL80211_IFTYPE_ADHOC: 735 basic->conn_type = cpu_to_le32(CONNECTION_IBSS_ADHOC); 736 break; 737 default: 738 WARN_ON(1); 739 break; 740 } 741 742 memcpy(basic->peer_addr, sta->addr, ETH_ALEN); 743 basic->aid = cpu_to_le16(sta->aid); 744 basic->qos = sta->wme; 745 } 746 747 static void 748 mt7615_mcu_sta_ht_tlv(struct sk_buff *skb, struct ieee80211_sta *sta) 749 { 750 struct tlv *tlv; 751 752 if (sta->ht_cap.ht_supported) { 753 struct sta_rec_ht *ht; 754 755 tlv = mt7615_mcu_add_tlv(skb, STA_REC_HT, sizeof(*ht)); 756 ht = (struct sta_rec_ht *)tlv; 757 ht->ht_cap = cpu_to_le16(sta->ht_cap.cap); 758 } 759 if (sta->vht_cap.vht_supported) { 760 struct sta_rec_vht *vht; 761 762 tlv = mt7615_mcu_add_tlv(skb, STA_REC_VHT, sizeof(*vht)); 763 vht = (struct sta_rec_vht *)tlv; 764 vht->vht_rx_mcs_map = sta->vht_cap.vht_mcs.rx_mcs_map; 765 vht->vht_tx_mcs_map = sta->vht_cap.vht_mcs.tx_mcs_map; 766 vht->vht_cap = cpu_to_le32(sta->vht_cap.cap); 767 } 768 } 769 770 static void 771 mt7615_mcu_wtbl_ba_tlv(struct sk_buff *skb, 772 struct ieee80211_ampdu_params *params, 773 bool enable, bool tx, void *sta_wtbl, 774 void *wtbl_tlv) 775 { 776 struct wtbl_ba *ba; 777 struct tlv *tlv; 778 779 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_BA, sizeof(*ba), 780 wtbl_tlv, sta_wtbl); 781 782 ba = (struct wtbl_ba *)tlv; 783 ba->tid = params->tid; 784 785 if (tx) { 786 ba->ba_type = MT_BA_TYPE_ORIGINATOR; 787 ba->sn = enable ? cpu_to_le16(params->ssn) : 0; 788 ba->ba_winsize = cpu_to_le16(params->buf_size); 789 ba->ba_en = enable; 790 } else { 791 memcpy(ba->peer_addr, params->sta->addr, ETH_ALEN); 792 ba->ba_type = MT_BA_TYPE_RECIPIENT; 793 ba->rst_ba_tid = params->tid; 794 ba->rst_ba_sel = RST_BA_MAC_TID_MATCH; 795 ba->rst_ba_sb = 1; 796 } 797 798 if (enable && tx) { 799 u8 ba_range[] = { 4, 8, 12, 24, 36, 48, 54, 64 }; 800 int i; 801 802 for (i = 7; i > 0; i--) { 803 if (params->buf_size >= ba_range[i]) 804 break; 805 } 806 ba->ba_winsize_idx = i; 807 } 808 } 809 810 static void 811 mt7615_mcu_wtbl_generic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif, 812 struct ieee80211_sta *sta, void *sta_wtbl, 813 void *wtbl_tlv) 814 { 815 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 816 struct wtbl_generic *generic; 817 struct wtbl_rx *rx; 818 struct tlv *tlv; 819 820 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_GENERIC, sizeof(*generic), 821 wtbl_tlv, sta_wtbl); 822 823 generic = (struct wtbl_generic *)tlv; 824 825 if (sta) { 826 memcpy(generic->peer_addr, sta->addr, ETH_ALEN); 827 generic->partial_aid = cpu_to_le16(sta->aid); 828 generic->muar_idx = mvif->omac_idx; 829 generic->qos = sta->wme; 830 } else { 831 eth_broadcast_addr(generic->peer_addr); 832 generic->muar_idx = 0xe; 833 } 834 835 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_RX, sizeof(*rx), 836 wtbl_tlv, sta_wtbl); 837 838 rx = (struct wtbl_rx *)tlv; 839 rx->rca1 = sta ? vif->type != NL80211_IFTYPE_AP : 1; 840 rx->rca2 = 1; 841 rx->rv = 1; 842 } 843 844 static void 845 mt7615_mcu_wtbl_ht_tlv(struct sk_buff *skb, struct ieee80211_sta *sta, 846 void *sta_wtbl, void *wtbl_tlv) 847 { 848 struct tlv *tlv; 849 u32 flags = 0; 850 851 if (sta->ht_cap.ht_supported) { 852 struct wtbl_ht *ht; 853 854 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_HT, sizeof(*ht), 855 wtbl_tlv, sta_wtbl); 856 ht = (struct wtbl_ht *)tlv; 857 ht->ldpc = sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING; 858 ht->af = sta->ht_cap.ampdu_factor; 859 ht->mm = sta->ht_cap.ampdu_density; 860 ht->ht = 1; 861 862 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) 863 flags |= MT_WTBL_W5_SHORT_GI_20; 864 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) 865 flags |= MT_WTBL_W5_SHORT_GI_40; 866 } 867 868 if (sta->vht_cap.vht_supported) { 869 struct wtbl_vht *vht; 870 871 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_VHT, sizeof(*vht), 872 wtbl_tlv, sta_wtbl); 873 vht = (struct wtbl_vht *)tlv; 874 vht->ldpc = sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC, 875 vht->vht = 1; 876 877 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80) 878 flags |= MT_WTBL_W5_SHORT_GI_80; 879 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160) 880 flags |= MT_WTBL_W5_SHORT_GI_160; 881 } 882 883 /* wtbl smps */ 884 if (sta->smps_mode == IEEE80211_SMPS_DYNAMIC) { 885 struct wtbl_smps *smps; 886 887 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_SMPS, sizeof(*smps), 888 wtbl_tlv, sta_wtbl); 889 smps = (struct wtbl_smps *)tlv; 890 smps->smps = 1; 891 } 892 893 if (sta->ht_cap.ht_supported) { 894 /* sgi */ 895 u32 msk = MT_WTBL_W5_SHORT_GI_20 | MT_WTBL_W5_SHORT_GI_40 | 896 MT_WTBL_W5_SHORT_GI_80 | MT_WTBL_W5_SHORT_GI_160; 897 struct wtbl_raw *raw; 898 899 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_RAW_DATA, 900 sizeof(*raw), wtbl_tlv, 901 sta_wtbl); 902 raw = (struct wtbl_raw *)tlv; 903 raw->val = cpu_to_le32(flags); 904 raw->msk = cpu_to_le32(~msk); 905 raw->wtbl_idx = 1; 906 raw->dw = 5; 907 } 908 } 909 910 static int 911 mt7615_mcu_add_bss(struct mt7615_dev *dev, struct ieee80211_vif *vif, 912 bool enable) 913 { 914 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 915 struct sk_buff *skb; 916 917 skb = mt7615_mcu_alloc_sta_req(mvif, NULL); 918 if (IS_ERR(skb)) 919 return PTR_ERR(skb); 920 921 if (enable) 922 mt7615_mcu_bss_omac_tlv(skb, vif); 923 924 mt7615_mcu_bss_basic_tlv(skb, vif, enable); 925 926 if (enable && mvif->omac_idx > EXT_BSSID_START) 927 mt7615_mcu_bss_ext_tlv(skb, mvif); 928 929 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 930 MCU_EXT_CMD_BSS_INFO_UPDATE, true); 931 } 932 933 static int 934 mt7615_mcu_wtbl_tx_ba(struct mt7615_dev *dev, 935 struct ieee80211_ampdu_params *params, 936 bool enable) 937 { 938 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 939 struct mt7615_vif *mvif = msta->vif; 940 struct wtbl_req_hdr *wtbl_hdr; 941 struct sk_buff *skb = NULL; 942 int err; 943 944 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(msta, WTBL_SET, NULL, &skb); 945 if (IS_ERR(wtbl_hdr)) 946 return PTR_ERR(wtbl_hdr); 947 948 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, true, NULL, wtbl_hdr); 949 950 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, 951 MCU_EXT_CMD_WTBL_UPDATE, true); 952 if (err < 0) 953 return err; 954 955 skb = mt7615_mcu_alloc_sta_req(mvif, msta); 956 if (IS_ERR(skb)) 957 return PTR_ERR(skb); 958 959 mt7615_mcu_sta_ba_tlv(skb, params, enable, true); 960 961 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 962 MCU_EXT_CMD_STA_REC_UPDATE, true); 963 } 964 965 static int 966 mt7615_mcu_wtbl_rx_ba(struct mt7615_dev *dev, 967 struct ieee80211_ampdu_params *params, 968 bool enable) 969 { 970 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 971 struct mt7615_vif *mvif = msta->vif; 972 struct wtbl_req_hdr *wtbl_hdr; 973 struct sk_buff *skb; 974 int err; 975 976 skb = mt7615_mcu_alloc_sta_req(mvif, msta); 977 if (IS_ERR(skb)) 978 return PTR_ERR(skb); 979 980 mt7615_mcu_sta_ba_tlv(skb, params, enable, false); 981 982 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, 983 MCU_EXT_CMD_STA_REC_UPDATE, true); 984 if (err < 0 || !enable) 985 return err; 986 987 skb = NULL; 988 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(msta, WTBL_SET, NULL, &skb); 989 if (IS_ERR(wtbl_hdr)) 990 return PTR_ERR(wtbl_hdr); 991 992 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, false, NULL, wtbl_hdr); 993 994 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 995 MCU_EXT_CMD_WTBL_UPDATE, true); 996 } 997 998 static int 999 mt7615_mcu_wtbl_sta_add(struct mt7615_dev *dev, struct ieee80211_vif *vif, 1000 struct ieee80211_sta *sta, bool enable) 1001 { 1002 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1003 struct sk_buff *skb, *sskb, *wskb = NULL; 1004 struct wtbl_req_hdr *wtbl_hdr; 1005 struct mt7615_sta *msta; 1006 int cmd, err; 1007 1008 msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta; 1009 1010 sskb = mt7615_mcu_alloc_sta_req(mvif, msta); 1011 if (IS_ERR(sskb)) 1012 return PTR_ERR(sskb); 1013 1014 mt7615_mcu_sta_basic_tlv(sskb, vif, sta, enable); 1015 if (enable && sta) 1016 mt7615_mcu_sta_ht_tlv(sskb, sta); 1017 1018 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(msta, WTBL_RESET_AND_SET, NULL, 1019 &wskb); 1020 if (IS_ERR(wtbl_hdr)) 1021 return PTR_ERR(wtbl_hdr); 1022 1023 if (enable) { 1024 mt7615_mcu_wtbl_generic_tlv(wskb, vif, sta, NULL, wtbl_hdr); 1025 if (sta) 1026 mt7615_mcu_wtbl_ht_tlv(wskb, sta, NULL, wtbl_hdr); 1027 } 1028 1029 cmd = enable ? MCU_EXT_CMD_WTBL_UPDATE : MCU_EXT_CMD_STA_REC_UPDATE; 1030 skb = enable ? wskb : sskb; 1031 1032 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 1033 if (err < 0) 1034 return err; 1035 1036 cmd = enable ? MCU_EXT_CMD_STA_REC_UPDATE : MCU_EXT_CMD_WTBL_UPDATE; 1037 skb = enable ? sskb : wskb; 1038 1039 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 1040 } 1041 1042 static const struct mt7615_mcu_ops wtbl_update_ops = { 1043 .add_beacon_offload = mt7615_mcu_add_beacon_offload, 1044 .set_pm_state = mt7615_mcu_ctrl_pm_state, 1045 .add_dev_info = mt7615_mcu_add_dev, 1046 .add_bss_info = mt7615_mcu_add_bss, 1047 .add_tx_ba = mt7615_mcu_wtbl_tx_ba, 1048 .add_rx_ba = mt7615_mcu_wtbl_rx_ba, 1049 .sta_add = mt7615_mcu_wtbl_sta_add, 1050 }; 1051 1052 static int 1053 mt7615_mcu_sta_ba(struct mt7615_dev *dev, 1054 struct ieee80211_ampdu_params *params, 1055 bool enable, bool tx) 1056 { 1057 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1058 struct mt7615_vif *mvif = msta->vif; 1059 struct wtbl_req_hdr *wtbl_hdr; 1060 struct tlv *sta_wtbl; 1061 struct sk_buff *skb; 1062 1063 skb = mt7615_mcu_alloc_sta_req(mvif, msta); 1064 if (IS_ERR(skb)) 1065 return PTR_ERR(skb); 1066 1067 mt7615_mcu_sta_ba_tlv(skb, params, enable, tx); 1068 1069 sta_wtbl = mt7615_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1070 1071 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(msta, WTBL_SET, sta_wtbl, &skb); 1072 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, tx, sta_wtbl, wtbl_hdr); 1073 1074 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1075 MCU_EXT_CMD_STA_REC_UPDATE, true); 1076 } 1077 1078 static int 1079 mt7615_mcu_sta_tx_ba(struct mt7615_dev *dev, 1080 struct ieee80211_ampdu_params *params, 1081 bool enable) 1082 { 1083 return mt7615_mcu_sta_ba(dev, params, enable, true); 1084 } 1085 1086 static int 1087 mt7615_mcu_sta_rx_ba(struct mt7615_dev *dev, 1088 struct ieee80211_ampdu_params *params, 1089 bool enable) 1090 { 1091 return mt7615_mcu_sta_ba(dev, params, enable, false); 1092 } 1093 1094 static int 1095 mt7615_mcu_add_sta_cmd(struct mt7615_dev *dev, struct ieee80211_vif *vif, 1096 struct ieee80211_sta *sta, bool enable, int cmd) 1097 { 1098 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1099 struct wtbl_req_hdr *wtbl_hdr; 1100 struct mt7615_sta *msta; 1101 struct tlv *sta_wtbl; 1102 struct sk_buff *skb; 1103 1104 msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta; 1105 1106 skb = mt7615_mcu_alloc_sta_req(mvif, msta); 1107 if (IS_ERR(skb)) 1108 return PTR_ERR(skb); 1109 1110 mt7615_mcu_sta_basic_tlv(skb, vif, sta, enable); 1111 if (enable && sta) 1112 mt7615_mcu_sta_ht_tlv(skb, sta); 1113 1114 sta_wtbl = mt7615_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1115 1116 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(msta, WTBL_RESET_AND_SET, 1117 sta_wtbl, &skb); 1118 if (enable) { 1119 mt7615_mcu_wtbl_generic_tlv(skb, vif, sta, sta_wtbl, wtbl_hdr); 1120 if (sta) 1121 mt7615_mcu_wtbl_ht_tlv(skb, sta, sta_wtbl, wtbl_hdr); 1122 } 1123 1124 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 1125 } 1126 1127 static int 1128 mt7615_mcu_add_sta(struct mt7615_dev *dev, struct ieee80211_vif *vif, 1129 struct ieee80211_sta *sta, bool enable) 1130 { 1131 return mt7615_mcu_add_sta_cmd(dev, vif, sta, enable, 1132 MCU_EXT_CMD_STA_REC_UPDATE); 1133 } 1134 1135 static const struct mt7615_mcu_ops sta_update_ops = { 1136 .add_beacon_offload = mt7615_mcu_add_beacon_offload, 1137 .set_pm_state = mt7615_mcu_ctrl_pm_state, 1138 .add_dev_info = mt7615_mcu_add_dev, 1139 .add_bss_info = mt7615_mcu_add_bss, 1140 .add_tx_ba = mt7615_mcu_sta_tx_ba, 1141 .add_rx_ba = mt7615_mcu_sta_rx_ba, 1142 .sta_add = mt7615_mcu_add_sta, 1143 }; 1144 1145 static int 1146 mt7615_mcu_uni_add_dev(struct mt7615_dev *dev, 1147 struct ieee80211_vif *vif, bool enable) 1148 { 1149 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1150 struct { 1151 struct req_hdr { 1152 u8 omac_idx; 1153 u8 band_idx; 1154 __le16 pad; 1155 } __packed hdr; 1156 struct req_tlv { 1157 __le16 tag; 1158 __le16 len; 1159 u8 active; 1160 u8 pad; 1161 u8 omac_addr[ETH_ALEN]; 1162 } __packed tlv; 1163 } data = { 1164 .hdr = { 1165 .omac_idx = mvif->omac_idx, 1166 .band_idx = mvif->band_idx, 1167 }, 1168 .tlv = { 1169 .tag = cpu_to_le16(DEV_INFO_ACTIVE), 1170 .len = cpu_to_le16(sizeof(struct req_tlv)), 1171 .active = enable, 1172 }, 1173 }; 1174 1175 memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN); 1176 1177 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_DEV_INFO_UPDATE, 1178 &data, sizeof(data), true); 1179 } 1180 1181 static int 1182 mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev *dev, int band, int state) 1183 { 1184 return 0; 1185 } 1186 1187 static int 1188 mt7615_mcu_uni_add_bss(struct mt7615_dev *dev, 1189 struct ieee80211_vif *vif, bool enable) 1190 { 1191 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1192 struct { 1193 struct req_hdr { 1194 u8 bss_idx; 1195 u8 pad[3]; 1196 } __packed hdr; 1197 struct basic_tlv { 1198 __le16 tag; 1199 __le16 len; 1200 u8 active; 1201 u8 omac_idx; 1202 u8 hw_bss_idx; 1203 u8 band_idx; 1204 __le32 conn_type; 1205 u8 conn_state; 1206 u8 wmm_idx; 1207 u8 bssid[ETH_ALEN]; 1208 __le16 bmc_tx_wlan_idx; 1209 __le16 bcn_interval; 1210 u8 dtim_period; 1211 u8 phymode; 1212 __le16 sta_idx; 1213 u8 nonht_basic_phy; 1214 u8 pad[3]; 1215 } __packed basic; 1216 } req = { 1217 .hdr = { 1218 .bss_idx = mvif->idx, 1219 }, 1220 .basic = { 1221 .tag = cpu_to_le16(UNI_BSS_INFO_BASIC), 1222 .len = cpu_to_le16(sizeof(struct basic_tlv)), 1223 .bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int), 1224 .dtim_period = vif->bss_conf.dtim_period, 1225 .omac_idx = mvif->omac_idx, 1226 .band_idx = mvif->band_idx, 1227 .wmm_idx = mvif->wmm_idx, 1228 .active = enable, 1229 }, 1230 }; 1231 u8 idx, tx_wlan_idx = 0; 1232 1233 idx = mvif->omac_idx > EXT_BSSID_START ? HW_BSSID_0 : mvif->omac_idx; 1234 req.basic.hw_bss_idx = idx; 1235 1236 switch (vif->type) { 1237 case NL80211_IFTYPE_MESH_POINT: 1238 case NL80211_IFTYPE_AP: 1239 req.basic.conn_type = cpu_to_le32(CONNECTION_INFRA_AP); 1240 tx_wlan_idx = mvif->sta.wcid.idx; 1241 break; 1242 case NL80211_IFTYPE_STATION: 1243 if (enable) { 1244 struct ieee80211_sta *sta; 1245 struct mt7615_sta *msta; 1246 1247 rcu_read_lock(); 1248 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 1249 if (!sta) { 1250 rcu_read_unlock(); 1251 return -EINVAL; 1252 } 1253 1254 msta = (struct mt7615_sta *)sta->drv_priv; 1255 tx_wlan_idx = msta->wcid.idx; 1256 rcu_read_unlock(); 1257 } 1258 req.basic.conn_type = cpu_to_le32(CONNECTION_INFRA_STA); 1259 break; 1260 default: 1261 WARN_ON(1); 1262 break; 1263 } 1264 1265 memcpy(req.basic.bssid, vif->bss_conf.bssid, ETH_ALEN); 1266 req.basic.bmc_tx_wlan_idx = cpu_to_le16(tx_wlan_idx); 1267 req.basic.sta_idx = cpu_to_le16(tx_wlan_idx); 1268 req.basic.conn_state = !enable; 1269 1270 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_BSS_INFO_UPDATE, 1271 &req, sizeof(req), true); 1272 } 1273 1274 static int 1275 mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev *dev, 1276 struct ieee80211_hw *hw, 1277 struct ieee80211_vif *vif, 1278 bool enable) 1279 { 1280 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1281 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 1282 struct ieee80211_mutable_offsets offs; 1283 struct { 1284 struct req_hdr { 1285 u8 bss_idx; 1286 u8 pad[3]; 1287 } __packed hdr; 1288 struct bcn_content_tlv { 1289 __le16 tag; 1290 __le16 len; 1291 __le16 tim_ie_pos; 1292 __le16 csa_ie_pos; 1293 __le16 bcc_ie_pos; 1294 /* 0: enable beacon offload 1295 * 1: disable beacon offload 1296 * 2: update probe respond offload 1297 */ 1298 u8 enable; 1299 /* 0: legacy format (TXD + payload) 1300 * 1: only cap field IE 1301 */ 1302 u8 type; 1303 __le16 pkt_len; 1304 u8 pkt[512]; 1305 } __packed beacon_tlv; 1306 } req = { 1307 .hdr = { 1308 .bss_idx = mvif->idx, 1309 }, 1310 .beacon_tlv = { 1311 .tag = cpu_to_le16(UNI_BSS_INFO_BCN_CONTENT), 1312 .len = cpu_to_le16(sizeof(struct bcn_content_tlv)), 1313 .enable = enable, 1314 }, 1315 }; 1316 struct sk_buff *skb; 1317 1318 skb = ieee80211_beacon_get_template(mt76_hw(dev), vif, &offs); 1319 if (!skb) 1320 return -EINVAL; 1321 1322 if (skb->len > 512 - MT_TXD_SIZE) { 1323 dev_err(dev->mt76.dev, "beacon size limit exceed\n"); 1324 dev_kfree_skb(skb); 1325 return -EINVAL; 1326 } 1327 1328 mt7615_mac_write_txwi(dev, (__le32 *)(req.beacon_tlv.pkt), skb, 1329 wcid, NULL, 0, NULL, true); 1330 memcpy(req.beacon_tlv.pkt + MT_TXD_SIZE, skb->data, skb->len); 1331 req.beacon_tlv.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len); 1332 req.beacon_tlv.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset); 1333 1334 if (offs.csa_counter_offs[0]) { 1335 u16 csa_offs; 1336 1337 csa_offs = MT_TXD_SIZE + offs.csa_counter_offs[0] - 4; 1338 req.beacon_tlv.csa_ie_pos = cpu_to_le16(csa_offs); 1339 } 1340 dev_kfree_skb(skb); 1341 1342 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_BSS_INFO_UPDATE, 1343 &req, sizeof(req), true); 1344 } 1345 1346 static int 1347 mt7615_mcu_uni_tx_ba(struct mt7615_dev *dev, 1348 struct ieee80211_ampdu_params *params, 1349 bool enable) 1350 { 1351 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1352 struct mt7615_vif *mvif = msta->vif; 1353 struct wtbl_req_hdr *wtbl_hdr; 1354 struct tlv *sta_wtbl; 1355 struct sk_buff *skb; 1356 int err; 1357 1358 skb = mt7615_mcu_alloc_sta_req(mvif, msta); 1359 if (IS_ERR(skb)) 1360 return PTR_ERR(skb); 1361 1362 sta_wtbl = mt7615_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1363 1364 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(msta, WTBL_SET, sta_wtbl, &skb); 1365 if (IS_ERR(wtbl_hdr)) 1366 return PTR_ERR(wtbl_hdr); 1367 1368 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, true, sta_wtbl, 1369 wtbl_hdr); 1370 1371 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1372 MCU_UNI_CMD_STA_REC_UPDATE, true); 1373 if (err < 0) 1374 return err; 1375 1376 skb = mt7615_mcu_alloc_sta_req(mvif, msta); 1377 if (IS_ERR(skb)) 1378 return PTR_ERR(skb); 1379 1380 mt7615_mcu_sta_ba_tlv(skb, params, enable, true); 1381 1382 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1383 MCU_UNI_CMD_STA_REC_UPDATE, true); 1384 } 1385 1386 static int 1387 mt7615_mcu_uni_rx_ba(struct mt7615_dev *dev, 1388 struct ieee80211_ampdu_params *params, 1389 bool enable) 1390 { 1391 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1392 struct mt7615_vif *mvif = msta->vif; 1393 struct wtbl_req_hdr *wtbl_hdr; 1394 struct tlv *sta_wtbl; 1395 struct sk_buff *skb; 1396 int err; 1397 1398 skb = mt7615_mcu_alloc_sta_req(mvif, msta); 1399 if (IS_ERR(skb)) 1400 return PTR_ERR(skb); 1401 1402 mt7615_mcu_sta_ba_tlv(skb, params, enable, false); 1403 1404 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1405 MCU_UNI_CMD_STA_REC_UPDATE, true); 1406 if (err < 0 || !enable) 1407 return err; 1408 1409 skb = mt7615_mcu_alloc_sta_req(mvif, msta); 1410 if (IS_ERR(skb)) 1411 return PTR_ERR(skb); 1412 1413 sta_wtbl = mt7615_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1414 1415 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(msta, WTBL_SET, sta_wtbl, &skb); 1416 if (IS_ERR(wtbl_hdr)) 1417 return PTR_ERR(wtbl_hdr); 1418 1419 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, false, sta_wtbl, 1420 wtbl_hdr); 1421 1422 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1423 MCU_UNI_CMD_STA_REC_UPDATE, true); 1424 } 1425 1426 static int 1427 mt7615_mcu_uni_add_sta(struct mt7615_dev *dev, struct ieee80211_vif *vif, 1428 struct ieee80211_sta *sta, bool enable) 1429 { 1430 return mt7615_mcu_add_sta_cmd(dev, vif, sta, enable, 1431 MCU_UNI_CMD_STA_REC_UPDATE); 1432 } 1433 1434 static const struct mt7615_mcu_ops uni_update_ops = { 1435 .add_beacon_offload = mt7615_mcu_uni_add_beacon_offload, 1436 .set_pm_state = mt7615_mcu_uni_ctrl_pm_state, 1437 .add_dev_info = mt7615_mcu_uni_add_dev, 1438 .add_bss_info = mt7615_mcu_uni_add_bss, 1439 .add_tx_ba = mt7615_mcu_uni_tx_ba, 1440 .add_rx_ba = mt7615_mcu_uni_rx_ba, 1441 .sta_add = mt7615_mcu_uni_add_sta, 1442 }; 1443 1444 static int mt7615_mcu_send_firmware(struct mt7615_dev *dev, const void *data, 1445 int len) 1446 { 1447 int ret = 0, cur_len; 1448 1449 while (len > 0) { 1450 cur_len = min_t(int, 4096 - sizeof(struct mt7615_mcu_txd), 1451 len); 1452 1453 ret = __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_FW_SCATTER, 1454 data, cur_len, false); 1455 if (ret) 1456 break; 1457 1458 data += cur_len; 1459 len -= cur_len; 1460 1461 if (mt76_is_mmio(&dev->mt76)) 1462 mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false); 1463 } 1464 1465 return ret; 1466 } 1467 1468 static int mt7615_mcu_start_firmware(struct mt7615_dev *dev, u32 addr, 1469 u32 option) 1470 { 1471 struct { 1472 __le32 option; 1473 __le32 addr; 1474 } req = { 1475 .option = cpu_to_le32(option), 1476 .addr = cpu_to_le32(addr), 1477 }; 1478 1479 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_FW_START_REQ, 1480 &req, sizeof(req), true); 1481 } 1482 1483 static int mt7615_mcu_restart(struct mt76_dev *dev) 1484 { 1485 return __mt76_mcu_send_msg(dev, MCU_CMD_RESTART_DL_REQ, NULL, 1486 0, true); 1487 } 1488 1489 static int mt7615_mcu_patch_sem_ctrl(struct mt7615_dev *dev, bool get) 1490 { 1491 struct { 1492 __le32 op; 1493 } req = { 1494 .op = cpu_to_le32(get ? PATCH_SEM_GET : PATCH_SEM_RELEASE), 1495 }; 1496 1497 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_PATCH_SEM_CONTROL, 1498 &req, sizeof(req), true); 1499 } 1500 1501 static int mt7615_mcu_start_patch(struct mt7615_dev *dev) 1502 { 1503 struct { 1504 u8 check_crc; 1505 u8 reserved[3]; 1506 } req = { 1507 .check_crc = 0, 1508 }; 1509 1510 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_PATCH_FINISH_REQ, 1511 &req, sizeof(req), true); 1512 } 1513 1514 static void mt7622_trigger_hif_int(struct mt7615_dev *dev, bool en) 1515 { 1516 if (!is_mt7622(&dev->mt76)) 1517 return; 1518 1519 regmap_update_bits(dev->infracfg, MT_INFRACFG_MISC, 1520 MT_INFRACFG_MISC_AP2CONN_WAKE, 1521 !en * MT_INFRACFG_MISC_AP2CONN_WAKE); 1522 } 1523 1524 static int mt7615_driver_own(struct mt7615_dev *dev) 1525 { 1526 u32 addr; 1527 1528 addr = is_mt7663(&dev->mt76) ? MT_CONN_HIF_ON_LPCTL : MT_CFG_LPCR_HOST; 1529 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_DRV_OWN); 1530 1531 mt7622_trigger_hif_int(dev, true); 1532 if (!mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000)) { 1533 dev_err(dev->mt76.dev, "Timeout for driver own\n"); 1534 return -EIO; 1535 } 1536 mt7622_trigger_hif_int(dev, false); 1537 1538 return 0; 1539 } 1540 1541 static int mt7615_firmware_own(struct mt7615_dev *dev) 1542 { 1543 u32 addr; 1544 1545 addr = is_mt7663(&dev->mt76) ? MT_CONN_HIF_ON_LPCTL : MT_CFG_LPCR_HOST; 1546 mt7622_trigger_hif_int(dev, true); 1547 1548 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_FW_OWN); 1549 1550 if (is_mt7622(&dev->mt76) && 1551 !mt76_poll_msec(dev, MT_CFG_LPCR_HOST, 1552 MT_CFG_LPCR_HOST_FW_OWN, 1553 MT_CFG_LPCR_HOST_FW_OWN, 3000)) { 1554 dev_err(dev->mt76.dev, "Timeout for firmware own\n"); 1555 return -EIO; 1556 } 1557 mt7622_trigger_hif_int(dev, false); 1558 1559 return 0; 1560 } 1561 1562 static int mt7615_load_patch(struct mt7615_dev *dev, u32 addr, const char *name) 1563 { 1564 const struct mt7615_patch_hdr *hdr; 1565 const struct firmware *fw = NULL; 1566 int len, ret, sem; 1567 1568 sem = mt7615_mcu_patch_sem_ctrl(dev, 1); 1569 switch (sem) { 1570 case PATCH_IS_DL: 1571 return 0; 1572 case PATCH_NOT_DL_SEM_SUCCESS: 1573 break; 1574 default: 1575 dev_err(dev->mt76.dev, "Failed to get patch semaphore\n"); 1576 return -EAGAIN; 1577 } 1578 1579 ret = request_firmware(&fw, name, dev->mt76.dev); 1580 if (ret) 1581 goto out; 1582 1583 if (!fw || !fw->data || fw->size < sizeof(*hdr)) { 1584 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1585 ret = -EINVAL; 1586 goto out; 1587 } 1588 1589 hdr = (const struct mt7615_patch_hdr *)(fw->data); 1590 1591 dev_info(dev->mt76.dev, "HW/SW Version: 0x%x, Build Time: %.16s\n", 1592 be32_to_cpu(hdr->hw_sw_ver), hdr->build_date); 1593 1594 len = fw->size - sizeof(*hdr); 1595 1596 ret = mt7615_mcu_init_download(dev, addr, len, DL_MODE_NEED_RSP); 1597 if (ret) { 1598 dev_err(dev->mt76.dev, "Download request failed\n"); 1599 goto out; 1600 } 1601 1602 ret = mt7615_mcu_send_firmware(dev, fw->data + sizeof(*hdr), len); 1603 if (ret) { 1604 dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); 1605 goto out; 1606 } 1607 1608 ret = mt7615_mcu_start_patch(dev); 1609 if (ret) 1610 dev_err(dev->mt76.dev, "Failed to start patch\n"); 1611 1612 out: 1613 release_firmware(fw); 1614 1615 sem = mt7615_mcu_patch_sem_ctrl(dev, 0); 1616 switch (sem) { 1617 case PATCH_REL_SEM_SUCCESS: 1618 break; 1619 default: 1620 ret = -EAGAIN; 1621 dev_err(dev->mt76.dev, "Failed to release patch semaphore\n"); 1622 break; 1623 } 1624 1625 return ret; 1626 } 1627 1628 static u32 mt7615_mcu_gen_dl_mode(u8 feature_set, bool is_cr4) 1629 { 1630 u32 ret = 0; 1631 1632 ret |= (feature_set & FW_FEATURE_SET_ENCRYPT) ? 1633 (DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV) : 0; 1634 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 1635 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 1636 ret |= DL_MODE_NEED_RSP; 1637 ret |= is_cr4 ? DL_MODE_WORKING_PDA_CR4 : 0; 1638 1639 return ret; 1640 } 1641 1642 static int 1643 mt7615_mcu_send_ram_firmware(struct mt7615_dev *dev, 1644 const struct mt7615_fw_trailer *hdr, 1645 const u8 *data, bool is_cr4) 1646 { 1647 int n_region = is_cr4 ? CR4_REGION_NUM : N9_REGION_NUM; 1648 int err, i, offset = 0; 1649 u32 len, addr, mode; 1650 1651 for (i = 0; i < n_region; i++) { 1652 mode = mt7615_mcu_gen_dl_mode(hdr[i].feature_set, is_cr4); 1653 len = le32_to_cpu(hdr[i].len) + IMG_CRC_LEN; 1654 addr = le32_to_cpu(hdr[i].addr); 1655 1656 err = mt7615_mcu_init_download(dev, addr, len, mode); 1657 if (err) { 1658 dev_err(dev->mt76.dev, "Download request failed\n"); 1659 return err; 1660 } 1661 1662 err = mt7615_mcu_send_firmware(dev, data + offset, len); 1663 if (err) { 1664 dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); 1665 return err; 1666 } 1667 1668 offset += len; 1669 } 1670 1671 return 0; 1672 } 1673 1674 static int mt7615_load_n9(struct mt7615_dev *dev, const char *name) 1675 { 1676 const struct mt7615_fw_trailer *hdr; 1677 const struct firmware *fw; 1678 int ret; 1679 1680 ret = request_firmware(&fw, name, dev->mt76.dev); 1681 if (ret) 1682 return ret; 1683 1684 if (!fw || !fw->data || fw->size < N9_REGION_NUM * sizeof(*hdr)) { 1685 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1686 ret = -EINVAL; 1687 goto out; 1688 } 1689 1690 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size - 1691 N9_REGION_NUM * sizeof(*hdr)); 1692 1693 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n", 1694 hdr->fw_ver, hdr->build_date); 1695 1696 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, false); 1697 if (ret) 1698 goto out; 1699 1700 ret = mt7615_mcu_start_firmware(dev, le32_to_cpu(hdr->addr), 1701 FW_START_OVERRIDE); 1702 if (ret) { 1703 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n"); 1704 goto out; 1705 } 1706 1707 snprintf(dev->mt76.hw->wiphy->fw_version, 1708 sizeof(dev->mt76.hw->wiphy->fw_version), 1709 "%.10s-%.15s", hdr->fw_ver, hdr->build_date); 1710 1711 if (!strncmp(hdr->fw_ver, "2.0", sizeof(hdr->fw_ver))) { 1712 dev->fw_ver = MT7615_FIRMWARE_V2; 1713 dev->mcu_ops = &sta_update_ops; 1714 } else { 1715 dev->fw_ver = MT7615_FIRMWARE_V1; 1716 dev->mcu_ops = &wtbl_update_ops; 1717 } 1718 1719 out: 1720 release_firmware(fw); 1721 return ret; 1722 } 1723 1724 static int mt7615_load_cr4(struct mt7615_dev *dev, const char *name) 1725 { 1726 const struct mt7615_fw_trailer *hdr; 1727 const struct firmware *fw; 1728 int ret; 1729 1730 ret = request_firmware(&fw, name, dev->mt76.dev); 1731 if (ret) 1732 return ret; 1733 1734 if (!fw || !fw->data || fw->size < CR4_REGION_NUM * sizeof(*hdr)) { 1735 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1736 ret = -EINVAL; 1737 goto out; 1738 } 1739 1740 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size - 1741 CR4_REGION_NUM * sizeof(*hdr)); 1742 1743 dev_info(dev->mt76.dev, "CR4 Firmware Version: %.10s, Build Time: %.15s\n", 1744 hdr->fw_ver, hdr->build_date); 1745 1746 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, true); 1747 if (ret) 1748 goto out; 1749 1750 ret = mt7615_mcu_start_firmware(dev, 0, FW_START_WORKING_PDA_CR4); 1751 if (ret) { 1752 dev_err(dev->mt76.dev, "Failed to start CR4 firmware\n"); 1753 goto out; 1754 } 1755 1756 out: 1757 release_firmware(fw); 1758 1759 return ret; 1760 } 1761 1762 static int mt7615_load_ram(struct mt7615_dev *dev) 1763 { 1764 int ret; 1765 1766 ret = mt7615_load_n9(dev, MT7615_FIRMWARE_N9); 1767 if (ret) 1768 return ret; 1769 1770 return mt7615_load_cr4(dev, MT7615_FIRMWARE_CR4); 1771 } 1772 1773 static int mt7615_load_firmware(struct mt7615_dev *dev) 1774 { 1775 int ret; 1776 u32 val; 1777 1778 val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE); 1779 1780 if (val != FW_STATE_FW_DOWNLOAD) { 1781 dev_err(dev->mt76.dev, "Firmware is not ready for download\n"); 1782 return -EIO; 1783 } 1784 1785 ret = mt7615_load_patch(dev, MT7615_PATCH_ADDRESS, MT7615_ROM_PATCH); 1786 if (ret) 1787 return ret; 1788 1789 ret = mt7615_load_ram(dev); 1790 if (ret) 1791 return ret; 1792 1793 if (!mt76_poll_msec(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE, 1794 FIELD_PREP(MT_TOP_MISC2_FW_STATE, 1795 FW_STATE_CR4_RDY), 500)) { 1796 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1797 return -EIO; 1798 } 1799 1800 return 0; 1801 } 1802 1803 static int mt7622_load_firmware(struct mt7615_dev *dev) 1804 { 1805 int ret; 1806 u32 val; 1807 1808 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1809 1810 val = mt76_get_field(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE); 1811 if (val != FW_STATE_FW_DOWNLOAD) { 1812 dev_err(dev->mt76.dev, "Firmware is not ready for download\n"); 1813 return -EIO; 1814 } 1815 1816 ret = mt7615_load_patch(dev, MT7622_PATCH_ADDRESS, MT7622_ROM_PATCH); 1817 if (ret) 1818 return ret; 1819 1820 ret = mt7615_load_n9(dev, MT7622_FIRMWARE_N9); 1821 if (ret) 1822 return ret; 1823 1824 if (!mt76_poll_msec(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE, 1825 FIELD_PREP(MT_TOP_OFF_RSV_FW_STATE, 1826 FW_STATE_NORMAL_TRX), 1500)) { 1827 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1828 return -EIO; 1829 } 1830 1831 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1832 1833 return 0; 1834 } 1835 1836 int mt7615_mcu_fw_log_2_host(struct mt7615_dev *dev, u8 ctrl) 1837 { 1838 struct { 1839 u8 ctrl_val; 1840 u8 pad[3]; 1841 } data = { 1842 .ctrl_val = ctrl 1843 }; 1844 1845 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_FW_LOG_2_HOST, 1846 &data, sizeof(data), true); 1847 } 1848 1849 static int mt7663_load_n9(struct mt7615_dev *dev, const char *name) 1850 { 1851 u32 offset = 0, override_addr = 0, flag = 0; 1852 const struct mt7663_fw_trailer *hdr; 1853 const struct mt7663_fw_buf *buf; 1854 const struct firmware *fw; 1855 const u8 *base_addr; 1856 int i, ret; 1857 1858 ret = request_firmware(&fw, name, dev->mt76.dev); 1859 if (ret) 1860 return ret; 1861 1862 if (!fw || !fw->data || fw->size < FW_V3_COMMON_TAILER_SIZE) { 1863 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1864 ret = -EINVAL; 1865 goto out; 1866 } 1867 1868 hdr = (const struct mt7663_fw_trailer *)(fw->data + fw->size - 1869 FW_V3_COMMON_TAILER_SIZE); 1870 1871 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n", 1872 hdr->fw_ver, hdr->build_date); 1873 dev_info(dev->mt76.dev, "Region number: 0x%x\n", hdr->n_region); 1874 1875 base_addr = fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE; 1876 for (i = 0; i < hdr->n_region; i++) { 1877 u32 shift = (hdr->n_region - i) * FW_V3_REGION_TAILER_SIZE; 1878 u32 len, addr, mode; 1879 1880 dev_info(dev->mt76.dev, "Parsing tailer Region: %d\n", i); 1881 1882 buf = (const struct mt7663_fw_buf *)(base_addr - shift); 1883 mode = mt7615_mcu_gen_dl_mode(buf->feature_set, false); 1884 addr = le32_to_cpu(buf->img_dest_addr); 1885 len = le32_to_cpu(buf->img_size); 1886 1887 ret = mt7615_mcu_init_download(dev, addr, len, mode); 1888 if (ret) { 1889 dev_err(dev->mt76.dev, "Download request failed\n"); 1890 goto out; 1891 } 1892 1893 ret = mt7615_mcu_send_firmware(dev, fw->data + offset, len); 1894 if (ret) { 1895 dev_err(dev->mt76.dev, "Failed to send firmware\n"); 1896 goto out; 1897 } 1898 1899 offset += le32_to_cpu(buf->img_size); 1900 if (buf->feature_set & DL_MODE_VALID_RAM_ENTRY) { 1901 override_addr = le32_to_cpu(buf->img_dest_addr); 1902 dev_info(dev->mt76.dev, "Region %d, override_addr = 0x%08x\n", 1903 i, override_addr); 1904 } 1905 } 1906 1907 if (is_mt7663(&dev->mt76)) { 1908 flag |= FW_START_DLYCAL; 1909 if (override_addr) 1910 flag |= FW_START_OVERRIDE; 1911 1912 dev_info(dev->mt76.dev, "override_addr = 0x%08x, option = %d\n", 1913 override_addr, flag); 1914 } 1915 1916 ret = mt7615_mcu_start_firmware(dev, override_addr, flag); 1917 if (ret) 1918 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n"); 1919 1920 out: 1921 release_firmware(fw); 1922 1923 return ret; 1924 } 1925 1926 static int mt7663_load_firmware(struct mt7615_dev *dev) 1927 { 1928 int ret; 1929 1930 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1931 1932 ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY); 1933 if (ret) { 1934 dev_dbg(dev->mt76.dev, "Firmware is already download\n"); 1935 return -EIO; 1936 } 1937 1938 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, MT7663_ROM_PATCH); 1939 if (ret) 1940 return ret; 1941 1942 dev->fw_ver = MT7615_FIRMWARE_V3; 1943 dev->mcu_ops = &uni_update_ops; 1944 1945 ret = mt7663_load_n9(dev, MT7663_FIRMWARE_N9); 1946 if (ret) 1947 return ret; 1948 1949 if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY, 1950 MT_TOP_MISC2_FW_N9_RDY, 1500)) { 1951 ret = mt76_get_field(dev, MT_CONN_ON_MISC, 1952 MT7663_TOP_MISC2_FW_STATE); 1953 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1954 return -EIO; 1955 } 1956 1957 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1958 1959 dev_dbg(dev->mt76.dev, "Firmware init done\n"); 1960 1961 return 0; 1962 } 1963 1964 int mt7615_mcu_init(struct mt7615_dev *dev) 1965 { 1966 static const struct mt76_mcu_ops mt7615_mcu_ops = { 1967 .mcu_skb_send_msg = mt7615_mcu_send_message, 1968 .mcu_send_msg = mt7615_mcu_msg_send, 1969 .mcu_restart = mt7615_mcu_restart, 1970 }; 1971 int ret; 1972 1973 dev->mt76.mcu_ops = &mt7615_mcu_ops, 1974 1975 ret = mt7615_driver_own(dev); 1976 if (ret) 1977 return ret; 1978 1979 switch (mt76_chip(&dev->mt76)) { 1980 case 0x7622: 1981 ret = mt7622_load_firmware(dev); 1982 break; 1983 case 0x7663: 1984 ret = mt7663_load_firmware(dev); 1985 break; 1986 default: 1987 ret = mt7615_load_firmware(dev); 1988 break; 1989 } 1990 if (ret) 1991 return ret; 1992 1993 mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false); 1994 dev_dbg(dev->mt76.dev, "Firmware init done\n"); 1995 set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1996 mt7615_mcu_fw_log_2_host(dev, 0); 1997 1998 return 0; 1999 } 2000 2001 void mt7615_mcu_exit(struct mt7615_dev *dev) 2002 { 2003 __mt76_mcu_restart(&dev->mt76); 2004 mt7615_firmware_own(dev); 2005 skb_queue_purge(&dev->mt76.mcu.res_q); 2006 } 2007 2008 int mt7615_mcu_set_eeprom(struct mt7615_dev *dev) 2009 { 2010 struct { 2011 u8 buffer_mode; 2012 u8 content_format; 2013 __le16 len; 2014 } __packed req_hdr = { 2015 .buffer_mode = 1, 2016 }; 2017 u8 *eep = (u8 *)dev->mt76.eeprom.data; 2018 struct sk_buff *skb; 2019 int eep_len, offset; 2020 2021 switch (mt76_chip(&dev->mt76)) { 2022 case 0x7622: 2023 eep_len = MT7622_EE_MAX - MT_EE_NIC_CONF_0; 2024 offset = MT_EE_NIC_CONF_0; 2025 break; 2026 case 0x7663: 2027 eep_len = MT7663_EE_MAX - MT_EE_CHIP_ID; 2028 req_hdr.content_format = 1; 2029 offset = MT_EE_CHIP_ID; 2030 break; 2031 default: 2032 eep_len = MT7615_EE_MAX - MT_EE_NIC_CONF_0; 2033 offset = MT_EE_NIC_CONF_0; 2034 break; 2035 } 2036 2037 req_hdr.len = cpu_to_le16(eep_len); 2038 2039 skb = mt7615_mcu_msg_alloc(NULL, sizeof(req_hdr) + eep_len); 2040 if (!skb) 2041 return -ENOMEM; 2042 2043 skb_put_data(skb, &req_hdr, sizeof(req_hdr)); 2044 skb_put_data(skb, eep + offset, eep_len); 2045 2046 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 2047 MCU_EXT_CMD_EFUSE_BUFFER_MODE, true); 2048 } 2049 2050 int mt7615_mcu_set_mac_enable(struct mt7615_dev *dev, int band, bool enable) 2051 { 2052 struct { 2053 u8 enable; 2054 u8 band; 2055 u8 rsv[2]; 2056 } __packed req = { 2057 .enable = enable, 2058 .band = band, 2059 }; 2060 2061 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_MAC_INIT_CTRL, 2062 &req, sizeof(req), true); 2063 } 2064 2065 int mt7615_mcu_set_rts_thresh(struct mt7615_phy *phy, u32 val) 2066 { 2067 struct mt7615_dev *dev = phy->dev; 2068 struct { 2069 u8 prot_idx; 2070 u8 band; 2071 u8 rsv[2]; 2072 __le32 len_thresh; 2073 __le32 pkt_thresh; 2074 } __packed req = { 2075 .prot_idx = 1, 2076 .band = phy != &dev->phy, 2077 .len_thresh = cpu_to_le32(val), 2078 .pkt_thresh = cpu_to_le32(0x2), 2079 }; 2080 2081 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_PROTECT_CTRL, 2082 &req, sizeof(req), true); 2083 } 2084 2085 int mt7615_mcu_set_wmm(struct mt7615_dev *dev, u8 queue, 2086 const struct ieee80211_tx_queue_params *params) 2087 { 2088 #define WMM_AIFS_SET BIT(0) 2089 #define WMM_CW_MIN_SET BIT(1) 2090 #define WMM_CW_MAX_SET BIT(2) 2091 #define WMM_TXOP_SET BIT(3) 2092 #define WMM_PARAM_SET (WMM_AIFS_SET | WMM_CW_MIN_SET | \ 2093 WMM_CW_MAX_SET | WMM_TXOP_SET) 2094 struct req_data { 2095 u8 number; 2096 u8 rsv[3]; 2097 u8 queue; 2098 u8 valid; 2099 u8 aifs; 2100 u8 cw_min; 2101 __le16 cw_max; 2102 __le16 txop; 2103 } __packed req = { 2104 .number = 1, 2105 .queue = queue, 2106 .valid = WMM_PARAM_SET, 2107 .aifs = params->aifs, 2108 .cw_min = 5, 2109 .cw_max = cpu_to_le16(10), 2110 .txop = cpu_to_le16(params->txop), 2111 }; 2112 2113 if (params->cw_min) 2114 req.cw_min = fls(params->cw_min); 2115 if (params->cw_max) 2116 req.cw_max = cpu_to_le16(fls(params->cw_max)); 2117 2118 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_EDCA_UPDATE, 2119 &req, sizeof(req), true); 2120 } 2121 2122 int mt7615_mcu_set_dbdc(struct mt7615_dev *dev) 2123 { 2124 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev); 2125 struct dbdc_entry { 2126 u8 type; 2127 u8 index; 2128 u8 band; 2129 u8 _rsv; 2130 }; 2131 struct { 2132 u8 enable; 2133 u8 num; 2134 u8 _rsv[2]; 2135 struct dbdc_entry entry[64]; 2136 } req = { 2137 .enable = !!ext_phy, 2138 }; 2139 int i; 2140 2141 if (!ext_phy) 2142 goto out; 2143 2144 #define ADD_DBDC_ENTRY(_type, _idx, _band) \ 2145 do { \ 2146 req.entry[req.num].type = _type; \ 2147 req.entry[req.num].index = _idx; \ 2148 req.entry[req.num++].band = _band; \ 2149 } while (0) 2150 2151 for (i = 0; i < 4; i++) { 2152 bool band = !!(ext_phy->omac_mask & BIT(i)); 2153 2154 ADD_DBDC_ENTRY(DBDC_TYPE_BSS, i, band); 2155 } 2156 2157 for (i = 0; i < 14; i++) { 2158 bool band = !!(ext_phy->omac_mask & BIT(0x11 + i)); 2159 2160 ADD_DBDC_ENTRY(DBDC_TYPE_MBSS, i, band); 2161 } 2162 2163 ADD_DBDC_ENTRY(DBDC_TYPE_MU, 0, 1); 2164 2165 for (i = 0; i < 3; i++) 2166 ADD_DBDC_ENTRY(DBDC_TYPE_BF, i, 1); 2167 2168 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 0, 0); 2169 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 1, 0); 2170 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 2, 1); 2171 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 3, 1); 2172 2173 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 0, 0); 2174 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 1, 1); 2175 2176 out: 2177 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_DBDC_CTRL, 2178 &req, sizeof(req), true); 2179 } 2180 2181 int mt7615_mcu_del_wtbl_all(struct mt7615_dev *dev) 2182 { 2183 struct wtbl_req_hdr req = { 2184 .operation = WTBL_RESET_ALL, 2185 }; 2186 2187 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_WTBL_UPDATE, 2188 &req, sizeof(req), true); 2189 } 2190 2191 int mt7615_mcu_rdd_cmd(struct mt7615_dev *dev, 2192 enum mt7615_rdd_cmd cmd, u8 index, 2193 u8 rx_sel, u8 val) 2194 { 2195 struct { 2196 u8 ctrl; 2197 u8 rdd_idx; 2198 u8 rdd_rx_sel; 2199 u8 val; 2200 u8 rsv[4]; 2201 } req = { 2202 .ctrl = cmd, 2203 .rdd_idx = index, 2204 .rdd_rx_sel = rx_sel, 2205 .val = val, 2206 }; 2207 2208 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_CTRL, 2209 &req, sizeof(req), true); 2210 } 2211 2212 int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val) 2213 { 2214 struct { 2215 u16 tag; 2216 u16 min_lpn; 2217 } req = { 2218 .tag = 0x1, 2219 .min_lpn = val, 2220 }; 2221 2222 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, 2223 &req, sizeof(req), true); 2224 } 2225 2226 int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev, 2227 const struct mt7615_dfs_pulse *pulse) 2228 { 2229 struct { 2230 u16 tag; 2231 struct mt7615_dfs_pulse pulse; 2232 } req = { 2233 .tag = 0x3, 2234 }; 2235 2236 memcpy(&req.pulse, pulse, sizeof(*pulse)); 2237 2238 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, 2239 &req, sizeof(req), true); 2240 } 2241 2242 int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index, 2243 const struct mt7615_dfs_pattern *pattern) 2244 { 2245 struct { 2246 u16 tag; 2247 u16 radar_type; 2248 struct mt7615_dfs_pattern pattern; 2249 } req = { 2250 .tag = 0x2, 2251 .radar_type = index, 2252 }; 2253 2254 memcpy(&req.pattern, pattern, sizeof(*pattern)); 2255 2256 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, 2257 &req, sizeof(req), true); 2258 } 2259 2260 int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev) 2261 { 2262 struct { 2263 u8 pulse_num; 2264 u8 rsv[3]; 2265 struct { 2266 u32 start_time; 2267 u16 width; 2268 s16 power; 2269 } pattern[32]; 2270 } req = { 2271 .pulse_num = dev->radar_pattern.n_pulses, 2272 }; 2273 u32 start_time = ktime_to_ms(ktime_get_boottime()); 2274 int i; 2275 2276 if (dev->radar_pattern.n_pulses > ARRAY_SIZE(req.pattern)) 2277 return -EINVAL; 2278 2279 /* TODO: add some noise here */ 2280 for (i = 0; i < dev->radar_pattern.n_pulses; i++) { 2281 req.pattern[i].width = dev->radar_pattern.width; 2282 req.pattern[i].power = dev->radar_pattern.power; 2283 req.pattern[i].start_time = start_time + 2284 i * dev->radar_pattern.period; 2285 } 2286 2287 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_PATTERN, 2288 &req, sizeof(req), false); 2289 } 2290 2291 static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku) 2292 { 2293 struct mt76_phy *mphy = phy->mt76; 2294 struct ieee80211_hw *hw = mphy->hw; 2295 int n_chains = hweight8(mphy->antenna_mask); 2296 int tx_power; 2297 int i; 2298 2299 tx_power = hw->conf.power_level * 2 - 2300 mt76_tx_power_nss_delta(n_chains); 2301 mphy->txpower_cur = tx_power; 2302 2303 for (i = 0; i < MT_SKU_1SS_DELTA; i++) 2304 sku[i] = tx_power; 2305 2306 for (i = 0; i < 4; i++) { 2307 int delta = 0; 2308 2309 if (i < n_chains - 1) 2310 delta = mt76_tx_power_nss_delta(n_chains) - 2311 mt76_tx_power_nss_delta(i + 1); 2312 sku[MT_SKU_1SS_DELTA + i] = delta; 2313 } 2314 } 2315 2316 int mt7615_mcu_set_chan_info(struct mt7615_phy *phy, int cmd) 2317 { 2318 struct mt7615_dev *dev = phy->dev; 2319 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2320 int freq1 = chandef->center_freq1, freq2 = chandef->center_freq2; 2321 struct { 2322 u8 control_chan; 2323 u8 center_chan; 2324 u8 bw; 2325 u8 tx_streams; 2326 u8 rx_streams_mask; 2327 u8 switch_reason; 2328 u8 band_idx; 2329 /* for 80+80 only */ 2330 u8 center_chan2; 2331 __le16 cac_case; 2332 u8 channel_band; 2333 u8 rsv0; 2334 __le32 outband_freq; 2335 u8 txpower_drop; 2336 u8 rsv1[3]; 2337 u8 txpower_sku[53]; 2338 u8 rsv2[3]; 2339 } req = { 2340 .control_chan = chandef->chan->hw_value, 2341 .center_chan = ieee80211_frequency_to_channel(freq1), 2342 .tx_streams = hweight8(phy->mt76->antenna_mask), 2343 .rx_streams_mask = phy->chainmask, 2344 .center_chan2 = ieee80211_frequency_to_channel(freq2), 2345 }; 2346 2347 if (dev->mt76.hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 2348 req.switch_reason = CH_SWITCH_SCAN_BYPASS_DPD; 2349 else if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) && 2350 chandef->chan->dfs_state != NL80211_DFS_AVAILABLE) 2351 req.switch_reason = CH_SWITCH_DFS; 2352 else 2353 req.switch_reason = CH_SWITCH_NORMAL; 2354 2355 req.band_idx = phy != &dev->phy; 2356 2357 switch (chandef->width) { 2358 case NL80211_CHAN_WIDTH_40: 2359 req.bw = CMD_CBW_40MHZ; 2360 break; 2361 case NL80211_CHAN_WIDTH_80: 2362 req.bw = CMD_CBW_80MHZ; 2363 break; 2364 case NL80211_CHAN_WIDTH_80P80: 2365 req.bw = CMD_CBW_8080MHZ; 2366 break; 2367 case NL80211_CHAN_WIDTH_160: 2368 req.bw = CMD_CBW_160MHZ; 2369 break; 2370 case NL80211_CHAN_WIDTH_5: 2371 req.bw = CMD_CBW_5MHZ; 2372 break; 2373 case NL80211_CHAN_WIDTH_10: 2374 req.bw = CMD_CBW_10MHZ; 2375 break; 2376 case NL80211_CHAN_WIDTH_20_NOHT: 2377 case NL80211_CHAN_WIDTH_20: 2378 default: 2379 req.bw = CMD_CBW_20MHZ; 2380 break; 2381 } 2382 2383 mt7615_mcu_set_txpower_sku(phy, req.txpower_sku); 2384 2385 return __mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), true); 2386 } 2387 2388 int mt7615_mcu_get_temperature(struct mt7615_dev *dev, int index) 2389 { 2390 struct { 2391 u8 action; 2392 u8 rsv[3]; 2393 } req = { 2394 .action = index, 2395 }; 2396 2397 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_GET_TEMP, &req, 2398 sizeof(req), true); 2399 } 2400 2401 int mt7615_mcu_set_sku_en(struct mt7615_phy *phy, bool enable) 2402 { 2403 struct mt7615_dev *dev = phy->dev; 2404 struct { 2405 u8 format_id; 2406 u8 sku_enable; 2407 u8 band_idx; 2408 u8 rsv; 2409 } req = { 2410 .format_id = 0, 2411 .band_idx = phy != &dev->phy, 2412 .sku_enable = enable, 2413 }; 2414 2415 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_TX_POWER_FEATURE_CTRL, &req, 2416 sizeof(req), true); 2417 } 2418