1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 9 #include <linux/arm-smccc.h> 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <uapi/linux/psci.h> 14 15 #include <kvm/arm_psci.h> 16 17 #include <asm/barrier.h> 18 #include <asm/cpufeature.h> 19 #include <asm/kprobes.h> 20 #include <asm/kvm_asm.h> 21 #include <asm/kvm_emulate.h> 22 #include <asm/kvm_hyp.h> 23 #include <asm/kvm_mmu.h> 24 #include <asm/fpsimd.h> 25 #include <asm/debug-monitors.h> 26 #include <asm/processor.h> 27 #include <asm/thread_info.h> 28 29 const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n"; 30 31 static void __activate_traps(struct kvm_vcpu *vcpu) 32 { 33 u64 val; 34 35 ___activate_traps(vcpu); 36 37 val = read_sysreg(cpacr_el1); 38 val |= CPACR_EL1_TTA; 39 val &= ~CPACR_EL1_ZEN; 40 41 /* 42 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 43 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 44 * except for some missing controls, such as TAM. 45 * In this case, CPTR_EL2.TAM has the same position with or without 46 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 47 * shift value for trapping the AMU accesses. 48 */ 49 50 val |= CPTR_EL2_TAM; 51 52 if (update_fp_enabled(vcpu)) { 53 if (vcpu_has_sve(vcpu)) 54 val |= CPACR_EL1_ZEN; 55 } else { 56 val &= ~CPACR_EL1_FPEN; 57 __activate_traps_fpsimd32(vcpu); 58 } 59 60 write_sysreg(val, cpacr_el1); 61 62 write_sysreg(kvm_get_hyp_vector(), vbar_el1); 63 } 64 NOKPROBE_SYMBOL(__activate_traps); 65 66 static void __deactivate_traps(struct kvm_vcpu *vcpu) 67 { 68 extern char vectors[]; /* kernel exception vectors */ 69 70 ___deactivate_traps(vcpu); 71 72 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 73 74 /* 75 * ARM errata 1165522 and 1530923 require the actual execution of the 76 * above before we can switch to the EL2/EL0 translation regime used by 77 * the host. 78 */ 79 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 80 81 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); 82 write_sysreg(vectors, vbar_el1); 83 } 84 NOKPROBE_SYMBOL(__deactivate_traps); 85 86 void activate_traps_vhe_load(struct kvm_vcpu *vcpu) 87 { 88 __activate_traps_common(vcpu); 89 } 90 91 void deactivate_traps_vhe_put(void) 92 { 93 u64 mdcr_el2 = read_sysreg(mdcr_el2); 94 95 mdcr_el2 &= MDCR_EL2_HPMN_MASK | 96 MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT | 97 MDCR_EL2_TPMS; 98 99 write_sysreg(mdcr_el2, mdcr_el2); 100 101 __deactivate_traps_common(); 102 } 103 104 /* Switch to the guest for VHE systems running in EL2 */ 105 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 106 { 107 struct kvm_cpu_context *host_ctxt; 108 struct kvm_cpu_context *guest_ctxt; 109 u64 exit_code; 110 111 host_ctxt = &__hyp_this_cpu_ptr(kvm_host_data)->host_ctxt; 112 host_ctxt->__hyp_running_vcpu = vcpu; 113 guest_ctxt = &vcpu->arch.ctxt; 114 115 sysreg_save_host_state_vhe(host_ctxt); 116 117 /* 118 * ARM erratum 1165522 requires us to configure both stage 1 and 119 * stage 2 translation for the guest context before we clear 120 * HCR_EL2.TGE. 121 * 122 * We have already configured the guest's stage 1 translation in 123 * kvm_vcpu_load_sysregs_vhe above. We must now call __activate_vm 124 * before __activate_traps, because __activate_vm configures 125 * stage 2 translation, and __activate_traps clear HCR_EL2.TGE 126 * (among other things). 127 */ 128 __activate_vm(vcpu->arch.hw_mmu); 129 __activate_traps(vcpu); 130 131 sysreg_restore_guest_state_vhe(guest_ctxt); 132 __debug_switch_to_guest(vcpu); 133 134 __set_guest_arch_workaround_state(vcpu); 135 136 do { 137 /* Jump in the fire! */ 138 exit_code = __guest_enter(vcpu, host_ctxt); 139 140 /* And we're baaack! */ 141 } while (fixup_guest_exit(vcpu, &exit_code)); 142 143 __set_host_arch_workaround_state(vcpu); 144 145 sysreg_save_guest_state_vhe(guest_ctxt); 146 147 __deactivate_traps(vcpu); 148 149 sysreg_restore_host_state_vhe(host_ctxt); 150 151 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 152 __fpsimd_save_fpexc32(vcpu); 153 154 __debug_switch_to_host(vcpu); 155 156 return exit_code; 157 } 158 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 159 160 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 161 { 162 int ret; 163 164 local_daif_mask(); 165 166 /* 167 * Having IRQs masked via PMR when entering the guest means the GIC 168 * will not signal the CPU of interrupts of lower priority, and the 169 * only way to get out will be via guest exceptions. 170 * Naturally, we want to avoid this. 171 * 172 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 173 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 174 */ 175 pmr_sync(); 176 177 ret = __kvm_vcpu_run_vhe(vcpu); 178 179 /* 180 * local_daif_restore() takes care to properly restore PSTATE.DAIF 181 * and the GIC PMR if the host is using IRQ priorities. 182 */ 183 local_daif_restore(DAIF_PROCCTX_NOIRQ); 184 185 /* 186 * When we exit from the guest we change a number of CPU configuration 187 * parameters, such as traps. Make sure these changes take effect 188 * before running the host or additional guests. 189 */ 190 isb(); 191 192 return ret; 193 } 194 195 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par, 196 struct kvm_cpu_context *host_ctxt) 197 { 198 struct kvm_vcpu *vcpu; 199 vcpu = host_ctxt->__hyp_running_vcpu; 200 201 __deactivate_traps(vcpu); 202 sysreg_restore_host_state_vhe(host_ctxt); 203 204 panic(__hyp_panic_string, 205 spsr, elr, 206 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 207 read_sysreg(hpfar_el2), par, vcpu); 208 } 209 NOKPROBE_SYMBOL(__hyp_call_panic); 210 211 void __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt) 212 { 213 u64 spsr = read_sysreg_el2(SYS_SPSR); 214 u64 elr = read_sysreg_el2(SYS_ELR); 215 u64 par = read_sysreg(par_el1); 216 217 __hyp_call_panic(spsr, elr, par, host_ctxt); 218 unreachable(); 219 } 220