1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DEVMEM_IS_ALLOWED 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_REMAP if MMU 45 select EDAC_SUPPORT 46 select EDAC_ATOMIC_SCRUB 47 select GENERIC_ALLOCATOR 48 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 49 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 50 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 51 select GENERIC_CPU_AUTOPROBE 52 select GENERIC_EARLY_IOREMAP 53 select GENERIC_IDLE_POLL_SETUP 54 select GENERIC_IRQ_PROBE 55 select GENERIC_IRQ_SHOW 56 select GENERIC_IRQ_SHOW_LEVEL 57 select GENERIC_PCI_IOMAP 58 select GENERIC_SCHED_CLOCK 59 select GENERIC_SMP_IDLE_THREAD 60 select GENERIC_STRNCPY_FROM_USER 61 select GENERIC_STRNLEN_USER 62 select HANDLE_DOMAIN_IRQ 63 select HARDIRQS_SW_RESEND 64 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 65 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 66 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 67 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 68 select HAVE_ARCH_MMAP_RND_BITS if MMU 69 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 71 select HAVE_ARCH_TRACEHOOK 72 select HAVE_ARM_SMCCC if CPU_V7 73 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 74 select HAVE_CONTEXT_TRACKING 75 select HAVE_COPY_THREAD_TLS 76 select HAVE_C_RECORDMCOUNT 77 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 78 select HAVE_DMA_CONTIGUOUS if MMU 79 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 80 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 81 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 82 select HAVE_EXIT_THREAD 83 select HAVE_FAST_GUP if ARM_LPAE 84 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 85 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 86 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000) 87 select HAVE_GCC_PLUGINS 88 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 89 select HAVE_IDE if PCI || ISA || PCMCIA 90 select HAVE_IRQ_TIME_ACCOUNTING 91 select HAVE_KERNEL_GZIP 92 select HAVE_KERNEL_LZ4 93 select HAVE_KERNEL_LZMA 94 select HAVE_KERNEL_LZO 95 select HAVE_KERNEL_XZ 96 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 97 select HAVE_KRETPROBES if HAVE_KPROBES 98 select HAVE_MOD_ARCH_SPECIFIC 99 select HAVE_NMI 100 select HAVE_OPROFILE if HAVE_PERF_EVENTS 101 select HAVE_OPTPROBES if !THUMB2_KERNEL 102 select HAVE_PERF_EVENTS 103 select HAVE_PERF_REGS 104 select HAVE_PERF_USER_STACK_DUMP 105 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 106 select HAVE_REGS_AND_STACK_ACCESS_API 107 select HAVE_RSEQ 108 select HAVE_STACKPROTECTOR 109 select HAVE_SYSCALL_TRACEPOINTS 110 select HAVE_UID16 111 select HAVE_VIRT_CPU_ACCOUNTING_GEN 112 select IRQ_FORCED_THREADING 113 select MODULES_USE_ELF_REL 114 select NEED_DMA_MAP_STATE 115 select OF_EARLY_FLATTREE if OF 116 select OLD_SIGACTION 117 select OLD_SIGSUSPEND3 118 select PCI_SYSCALL if PCI 119 select PERF_USE_VMALLOC 120 select RTC_LIB 121 select SYS_SUPPORTS_APM_EMULATION 122 # Above selects are sorted alphabetically; please add new ones 123 # according to that. Thanks. 124 help 125 The ARM series is a line of low-power-consumption RISC chip designs 126 licensed by ARM Ltd and targeted at embedded applications and 127 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 128 manufactured, but legacy ARM-based PC hardware remains popular in 129 Europe. There is an ARM Linux project with a web page at 130 <http://www.arm.linux.org.uk/>. 131 132config ARM_HAS_SG_CHAIN 133 bool 134 135config ARM_DMA_USE_IOMMU 136 bool 137 select ARM_HAS_SG_CHAIN 138 select NEED_SG_DMA_LENGTH 139 140if ARM_DMA_USE_IOMMU 141 142config ARM_DMA_IOMMU_ALIGNMENT 143 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 144 range 4 9 145 default 8 146 help 147 DMA mapping framework by default aligns all buffers to the smallest 148 PAGE_SIZE order which is greater than or equal to the requested buffer 149 size. This works well for buffers up to a few hundreds kilobytes, but 150 for larger buffers it just a waste of address space. Drivers which has 151 relatively small addressing window (like 64Mib) might run out of 152 virtual space with just a few allocations. 153 154 With this parameter you can specify the maximum PAGE_SIZE order for 155 DMA IOMMU buffers. Larger buffers will be aligned only to this 156 specified order. The order is expressed as a power of two multiplied 157 by the PAGE_SIZE. 158 159endif 160 161config SYS_SUPPORTS_APM_EMULATION 162 bool 163 164config HAVE_TCM 165 bool 166 select GENERIC_ALLOCATOR 167 168config HAVE_PROC_CPU 169 bool 170 171config NO_IOPORT_MAP 172 bool 173 174config SBUS 175 bool 176 177config STACKTRACE_SUPPORT 178 bool 179 default y 180 181config LOCKDEP_SUPPORT 182 bool 183 default y 184 185config TRACE_IRQFLAGS_SUPPORT 186 bool 187 default !CPU_V7M 188 189config ARCH_HAS_ILOG2_U32 190 bool 191 192config ARCH_HAS_ILOG2_U64 193 bool 194 195config ARCH_HAS_BANDGAP 196 bool 197 198config FIX_EARLYCON_MEM 199 def_bool y if MMU 200 201config GENERIC_HWEIGHT 202 bool 203 default y 204 205config GENERIC_CALIBRATE_DELAY 206 bool 207 default y 208 209config ARCH_MAY_HAVE_PC_FDC 210 bool 211 212config ZONE_DMA 213 bool 214 215config ARCH_SUPPORTS_UPROBES 216 def_bool y 217 218config ARCH_HAS_DMA_SET_COHERENT_MASK 219 bool 220 221config GENERIC_ISA_DMA 222 bool 223 224config FIQ 225 bool 226 227config NEED_RET_TO_USER 228 bool 229 230config ARCH_MTD_XIP 231 bool 232 233config ARM_PATCH_PHYS_VIRT 234 bool "Patch physical to virtual translations at runtime" if EMBEDDED 235 default y 236 depends on !XIP_KERNEL && MMU 237 help 238 Patch phys-to-virt and virt-to-phys translation functions at 239 boot and module load time according to the position of the 240 kernel in system memory. 241 242 This can only be used with non-XIP MMU kernels where the base 243 of physical memory is at a 16MB boundary. 244 245 Only disable this option if you know that you do not require 246 this feature (eg, building a kernel for a single machine) and 247 you need to shrink the kernel to the minimal size. 248 249config NEED_MACH_IO_H 250 bool 251 help 252 Select this when mach/io.h is required to provide special 253 definitions for this platform. The need for mach/io.h should 254 be avoided when possible. 255 256config NEED_MACH_MEMORY_H 257 bool 258 help 259 Select this when mach/memory.h is required to provide special 260 definitions for this platform. The need for mach/memory.h should 261 be avoided when possible. 262 263config PHYS_OFFSET 264 hex "Physical address of main memory" if MMU 265 depends on !ARM_PATCH_PHYS_VIRT 266 default DRAM_BASE if !MMU 267 default 0x00000000 if ARCH_EBSA110 || \ 268 ARCH_FOOTBRIDGE || \ 269 ARCH_INTEGRATOR || \ 270 ARCH_REALVIEW 271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 272 default 0x20000000 if ARCH_S5PV210 273 default 0xc0000000 if ARCH_SA1100 274 help 275 Please provide the physical address corresponding to the 276 location of main memory in your system. 277 278config GENERIC_BUG 279 def_bool y 280 depends on BUG 281 282config PGTABLE_LEVELS 283 int 284 default 3 if ARM_LPAE 285 default 2 286 287menu "System Type" 288 289config MMU 290 bool "MMU-based Paged Memory Management Support" 291 default y 292 help 293 Select if you want MMU-based virtualised addressing space 294 support by paged memory management. If unsure, say 'Y'. 295 296config ARCH_MMAP_RND_BITS_MIN 297 default 8 298 299config ARCH_MMAP_RND_BITS_MAX 300 default 14 if PAGE_OFFSET=0x40000000 301 default 15 if PAGE_OFFSET=0x80000000 302 default 16 303 304# 305# The "ARM system type" choice list is ordered alphabetically by option 306# text. Please add new entries in the option alphabetic order. 307# 308choice 309 prompt "ARM system type" 310 default ARM_SINGLE_ARMV7M if !MMU 311 default ARCH_MULTIPLATFORM if MMU 312 313config ARCH_MULTIPLATFORM 314 bool "Allow multiple platforms to be selected" 315 depends on MMU 316 select ARM_HAS_SG_CHAIN 317 select ARM_PATCH_PHYS_VIRT 318 select AUTO_ZRELADDR 319 select TIMER_OF 320 select COMMON_CLK 321 select GENERIC_CLOCKEVENTS 322 select GENERIC_IRQ_MULTI_HANDLER 323 select HAVE_PCI 324 select PCI_DOMAINS_GENERIC if PCI 325 select SPARSE_IRQ 326 select USE_OF 327 328config ARM_SINGLE_ARMV7M 329 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 330 depends on !MMU 331 select ARM_NVIC 332 select AUTO_ZRELADDR 333 select TIMER_OF 334 select COMMON_CLK 335 select CPU_V7M 336 select GENERIC_CLOCKEVENTS 337 select NO_IOPORT_MAP 338 select SPARSE_IRQ 339 select USE_OF 340 341config ARCH_EBSA110 342 bool "EBSA-110" 343 select ARCH_USES_GETTIMEOFFSET 344 select CPU_SA110 345 select ISA 346 select NEED_MACH_IO_H 347 select NEED_MACH_MEMORY_H 348 select NO_IOPORT_MAP 349 help 350 This is an evaluation board for the StrongARM processor available 351 from Digital. It has limited hardware on-board, including an 352 Ethernet interface, two PCMCIA sockets, two serial ports and a 353 parallel port. 354 355config ARCH_EP93XX 356 bool "EP93xx-based" 357 select ARCH_SPARSEMEM_ENABLE 358 select ARM_AMBA 359 imply ARM_PATCH_PHYS_VIRT 360 select ARM_VIC 361 select AUTO_ZRELADDR 362 select CLKDEV_LOOKUP 363 select CLKSRC_MMIO 364 select CPU_ARM920T 365 select GENERIC_CLOCKEVENTS 366 select GPIOLIB 367 help 368 This enables support for the Cirrus EP93xx series of CPUs. 369 370config ARCH_FOOTBRIDGE 371 bool "FootBridge" 372 select CPU_SA110 373 select FOOTBRIDGE 374 select GENERIC_CLOCKEVENTS 375 select HAVE_IDE 376 select NEED_MACH_IO_H if !MMU 377 select NEED_MACH_MEMORY_H 378 help 379 Support for systems based on the DC21285 companion chip 380 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 381 382config ARCH_IOP32X 383 bool "IOP32x-based" 384 depends on MMU 385 select CPU_XSCALE 386 select GPIO_IOP 387 select GPIOLIB 388 select NEED_RET_TO_USER 389 select FORCE_PCI 390 select PLAT_IOP 391 help 392 Support for Intel's 80219 and IOP32X (XScale) family of 393 processors. 394 395config ARCH_IXP4XX 396 bool "IXP4xx-based" 397 depends on MMU 398 select ARCH_HAS_DMA_SET_COHERENT_MASK 399 select ARCH_SUPPORTS_BIG_ENDIAN 400 select CPU_XSCALE 401 select DMABOUNCE if PCI 402 select GENERIC_CLOCKEVENTS 403 select GENERIC_IRQ_MULTI_HANDLER 404 select GPIO_IXP4XX 405 select GPIOLIB 406 select HAVE_PCI 407 select IXP4XX_IRQ 408 select IXP4XX_TIMER 409 select NEED_MACH_IO_H 410 select USB_EHCI_BIG_ENDIAN_DESC 411 select USB_EHCI_BIG_ENDIAN_MMIO 412 help 413 Support for Intel's IXP4XX (XScale) family of processors. 414 415config ARCH_DOVE 416 bool "Marvell Dove" 417 select CPU_PJ4 418 select GENERIC_CLOCKEVENTS 419 select GENERIC_IRQ_MULTI_HANDLER 420 select GPIOLIB 421 select HAVE_PCI 422 select MVEBU_MBUS 423 select PINCTRL 424 select PINCTRL_DOVE 425 select PLAT_ORION_LEGACY 426 select SPARSE_IRQ 427 select PM_GENERIC_DOMAINS if PM 428 help 429 Support for the Marvell Dove SoC 88AP510 430 431config ARCH_PXA 432 bool "PXA2xx/PXA3xx-based" 433 depends on MMU 434 select ARCH_MTD_XIP 435 select ARM_CPU_SUSPEND if PM 436 select AUTO_ZRELADDR 437 select COMMON_CLK 438 select CLKDEV_LOOKUP 439 select CLKSRC_PXA 440 select CLKSRC_MMIO 441 select TIMER_OF 442 select CPU_XSCALE if !CPU_XSC3 443 select GENERIC_CLOCKEVENTS 444 select GENERIC_IRQ_MULTI_HANDLER 445 select GPIO_PXA 446 select GPIOLIB 447 select HAVE_IDE 448 select IRQ_DOMAIN 449 select PLAT_PXA 450 select SPARSE_IRQ 451 help 452 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 453 454config ARCH_RPC 455 bool "RiscPC" 456 depends on MMU 457 select ARCH_ACORN 458 select ARCH_MAY_HAVE_PC_FDC 459 select ARCH_SPARSEMEM_ENABLE 460 select ARM_HAS_SG_CHAIN 461 select CPU_SA110 462 select FIQ 463 select HAVE_IDE 464 select HAVE_PATA_PLATFORM 465 select ISA_DMA_API 466 select NEED_MACH_IO_H 467 select NEED_MACH_MEMORY_H 468 select NO_IOPORT_MAP 469 help 470 On the Acorn Risc-PC, Linux can support the internal IDE disk and 471 CD-ROM interface, serial and parallel port, and the floppy drive. 472 473config ARCH_SA1100 474 bool "SA1100-based" 475 select ARCH_MTD_XIP 476 select ARCH_SPARSEMEM_ENABLE 477 select CLKDEV_LOOKUP 478 select CLKSRC_MMIO 479 select CLKSRC_PXA 480 select TIMER_OF if OF 481 select COMMON_CLK 482 select CPU_FREQ 483 select CPU_SA1100 484 select GENERIC_CLOCKEVENTS 485 select GENERIC_IRQ_MULTI_HANDLER 486 select GPIOLIB 487 select HAVE_IDE 488 select IRQ_DOMAIN 489 select ISA 490 select NEED_MACH_MEMORY_H 491 select SPARSE_IRQ 492 help 493 Support for StrongARM 11x0 based boards. 494 495config ARCH_S3C24XX 496 bool "Samsung S3C24XX SoCs" 497 select ATAGS 498 select CLKDEV_LOOKUP 499 select CLKSRC_SAMSUNG_PWM 500 select GENERIC_CLOCKEVENTS 501 select GPIO_SAMSUNG 502 select GPIOLIB 503 select GENERIC_IRQ_MULTI_HANDLER 504 select HAVE_S3C2410_I2C if I2C 505 select HAVE_S3C2410_WATCHDOG if WATCHDOG 506 select HAVE_S3C_RTC if RTC_CLASS 507 select NEED_MACH_IO_H 508 select SAMSUNG_ATAGS 509 select USE_OF 510 help 511 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 512 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 513 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 514 Samsung SMDK2410 development board (and derivatives). 515 516config ARCH_OMAP1 517 bool "TI OMAP1" 518 depends on MMU 519 select ARCH_HAS_HOLES_MEMORYMODEL 520 select ARCH_OMAP 521 select CLKDEV_LOOKUP 522 select CLKSRC_MMIO 523 select GENERIC_CLOCKEVENTS 524 select GENERIC_IRQ_CHIP 525 select GENERIC_IRQ_MULTI_HANDLER 526 select GPIOLIB 527 select HAVE_IDE 528 select IRQ_DOMAIN 529 select NEED_MACH_IO_H if PCCARD 530 select NEED_MACH_MEMORY_H 531 select SPARSE_IRQ 532 help 533 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 534 535endchoice 536 537menu "Multiple platform selection" 538 depends on ARCH_MULTIPLATFORM 539 540comment "CPU Core family selection" 541 542config ARCH_MULTI_V4 543 bool "ARMv4 based platforms (FA526)" 544 depends on !ARCH_MULTI_V6_V7 545 select ARCH_MULTI_V4_V5 546 select CPU_FA526 547 548config ARCH_MULTI_V4T 549 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 550 depends on !ARCH_MULTI_V6_V7 551 select ARCH_MULTI_V4_V5 552 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 553 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 554 CPU_ARM925T || CPU_ARM940T) 555 556config ARCH_MULTI_V5 557 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 558 depends on !ARCH_MULTI_V6_V7 559 select ARCH_MULTI_V4_V5 560 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 561 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 562 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 563 564config ARCH_MULTI_V4_V5 565 bool 566 567config ARCH_MULTI_V6 568 bool "ARMv6 based platforms (ARM11)" 569 select ARCH_MULTI_V6_V7 570 select CPU_V6K 571 572config ARCH_MULTI_V7 573 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 574 default y 575 select ARCH_MULTI_V6_V7 576 select CPU_V7 577 select HAVE_SMP 578 579config ARCH_MULTI_V6_V7 580 bool 581 select MIGHT_HAVE_CACHE_L2X0 582 583config ARCH_MULTI_CPU_AUTO 584 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 585 select ARCH_MULTI_V5 586 587endmenu 588 589config ARCH_VIRT 590 bool "Dummy Virtual Machine" 591 depends on ARCH_MULTI_V7 592 select ARM_AMBA 593 select ARM_GIC 594 select ARM_GIC_V2M if PCI 595 select ARM_GIC_V3 596 select ARM_GIC_V3_ITS if PCI 597 select ARM_PSCI 598 select HAVE_ARM_ARCH_TIMER 599 select ARCH_SUPPORTS_BIG_ENDIAN 600 601# 602# This is sorted alphabetically by mach-* pathname. However, plat-* 603# Kconfigs may be included either alphabetically (according to the 604# plat- suffix) or along side the corresponding mach-* source. 605# 606source "arch/arm/mach-actions/Kconfig" 607 608source "arch/arm/mach-alpine/Kconfig" 609 610source "arch/arm/mach-artpec/Kconfig" 611 612source "arch/arm/mach-asm9260/Kconfig" 613 614source "arch/arm/mach-aspeed/Kconfig" 615 616source "arch/arm/mach-at91/Kconfig" 617 618source "arch/arm/mach-axxia/Kconfig" 619 620source "arch/arm/mach-bcm/Kconfig" 621 622source "arch/arm/mach-berlin/Kconfig" 623 624source "arch/arm/mach-clps711x/Kconfig" 625 626source "arch/arm/mach-cns3xxx/Kconfig" 627 628source "arch/arm/mach-davinci/Kconfig" 629 630source "arch/arm/mach-digicolor/Kconfig" 631 632source "arch/arm/mach-dove/Kconfig" 633 634source "arch/arm/mach-ep93xx/Kconfig" 635 636source "arch/arm/mach-exynos/Kconfig" 637source "arch/arm/plat-samsung/Kconfig" 638 639source "arch/arm/mach-footbridge/Kconfig" 640 641source "arch/arm/mach-gemini/Kconfig" 642 643source "arch/arm/mach-highbank/Kconfig" 644 645source "arch/arm/mach-hisi/Kconfig" 646 647source "arch/arm/mach-imx/Kconfig" 648 649source "arch/arm/mach-integrator/Kconfig" 650 651source "arch/arm/mach-iop32x/Kconfig" 652 653source "arch/arm/mach-ixp4xx/Kconfig" 654 655source "arch/arm/mach-keystone/Kconfig" 656 657source "arch/arm/mach-lpc32xx/Kconfig" 658 659source "arch/arm/mach-mediatek/Kconfig" 660 661source "arch/arm/mach-meson/Kconfig" 662 663source "arch/arm/mach-milbeaut/Kconfig" 664 665source "arch/arm/mach-mmp/Kconfig" 666 667source "arch/arm/mach-moxart/Kconfig" 668 669source "arch/arm/mach-mv78xx0/Kconfig" 670 671source "arch/arm/mach-mvebu/Kconfig" 672 673source "arch/arm/mach-mxs/Kconfig" 674 675source "arch/arm/mach-nomadik/Kconfig" 676 677source "arch/arm/mach-npcm/Kconfig" 678 679source "arch/arm/mach-nspire/Kconfig" 680 681source "arch/arm/plat-omap/Kconfig" 682 683source "arch/arm/mach-omap1/Kconfig" 684 685source "arch/arm/mach-omap2/Kconfig" 686 687source "arch/arm/mach-orion5x/Kconfig" 688 689source "arch/arm/mach-oxnas/Kconfig" 690 691source "arch/arm/mach-picoxcell/Kconfig" 692 693source "arch/arm/mach-prima2/Kconfig" 694 695source "arch/arm/mach-pxa/Kconfig" 696source "arch/arm/plat-pxa/Kconfig" 697 698source "arch/arm/mach-qcom/Kconfig" 699 700source "arch/arm/mach-rda/Kconfig" 701 702source "arch/arm/mach-realview/Kconfig" 703 704source "arch/arm/mach-rockchip/Kconfig" 705 706source "arch/arm/mach-s3c24xx/Kconfig" 707 708source "arch/arm/mach-s3c64xx/Kconfig" 709 710source "arch/arm/mach-s5pv210/Kconfig" 711 712source "arch/arm/mach-sa1100/Kconfig" 713 714source "arch/arm/mach-shmobile/Kconfig" 715 716source "arch/arm/mach-socfpga/Kconfig" 717 718source "arch/arm/mach-spear/Kconfig" 719 720source "arch/arm/mach-sti/Kconfig" 721 722source "arch/arm/mach-stm32/Kconfig" 723 724source "arch/arm/mach-sunxi/Kconfig" 725 726source "arch/arm/mach-tango/Kconfig" 727 728source "arch/arm/mach-tegra/Kconfig" 729 730source "arch/arm/mach-u300/Kconfig" 731 732source "arch/arm/mach-uniphier/Kconfig" 733 734source "arch/arm/mach-ux500/Kconfig" 735 736source "arch/arm/mach-versatile/Kconfig" 737 738source "arch/arm/mach-vexpress/Kconfig" 739source "arch/arm/plat-versatile/Kconfig" 740 741source "arch/arm/mach-vt8500/Kconfig" 742 743source "arch/arm/mach-zx/Kconfig" 744 745source "arch/arm/mach-zynq/Kconfig" 746 747# ARMv7-M architecture 748config ARCH_EFM32 749 bool "Energy Micro efm32" 750 depends on ARM_SINGLE_ARMV7M 751 select GPIOLIB 752 help 753 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 754 processors. 755 756config ARCH_LPC18XX 757 bool "NXP LPC18xx/LPC43xx" 758 depends on ARM_SINGLE_ARMV7M 759 select ARCH_HAS_RESET_CONTROLLER 760 select ARM_AMBA 761 select CLKSRC_LPC32XX 762 select PINCTRL 763 help 764 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 765 high performance microcontrollers. 766 767config ARCH_MPS2 768 bool "ARM MPS2 platform" 769 depends on ARM_SINGLE_ARMV7M 770 select ARM_AMBA 771 select CLKSRC_MPS2 772 help 773 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 774 with a range of available cores like Cortex-M3/M4/M7. 775 776 Please, note that depends which Application Note is used memory map 777 for the platform may vary, so adjustment of RAM base might be needed. 778 779# Definitions to make life easier 780config ARCH_ACORN 781 bool 782 783config PLAT_IOP 784 bool 785 select GENERIC_CLOCKEVENTS 786 787config PLAT_ORION 788 bool 789 select CLKSRC_MMIO 790 select COMMON_CLK 791 select GENERIC_IRQ_CHIP 792 select IRQ_DOMAIN 793 794config PLAT_ORION_LEGACY 795 bool 796 select PLAT_ORION 797 798config PLAT_PXA 799 bool 800 801config PLAT_VERSATILE 802 bool 803 804source "arch/arm/mm/Kconfig" 805 806config IWMMXT 807 bool "Enable iWMMXt support" 808 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 809 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 810 help 811 Enable support for iWMMXt context switching at run time if 812 running on a CPU that supports it. 813 814if !MMU 815source "arch/arm/Kconfig-nommu" 816endif 817 818config PJ4B_ERRATA_4742 819 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 820 depends on CPU_PJ4B && MACH_ARMADA_370 821 default y 822 help 823 When coming out of either a Wait for Interrupt (WFI) or a Wait for 824 Event (WFE) IDLE states, a specific timing sensitivity exists between 825 the retiring WFI/WFE instructions and the newly issued subsequent 826 instructions. This sensitivity can result in a CPU hang scenario. 827 Workaround: 828 The software must insert either a Data Synchronization Barrier (DSB) 829 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 830 instruction 831 832config ARM_ERRATA_326103 833 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 834 depends on CPU_V6 835 help 836 Executing a SWP instruction to read-only memory does not set bit 11 837 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 838 treat the access as a read, preventing a COW from occurring and 839 causing the faulting task to livelock. 840 841config ARM_ERRATA_411920 842 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 843 depends on CPU_V6 || CPU_V6K 844 help 845 Invalidation of the Instruction Cache operation can 846 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 847 It does not affect the MPCore. This option enables the ARM Ltd. 848 recommended workaround. 849 850config ARM_ERRATA_430973 851 bool "ARM errata: Stale prediction on replaced interworking branch" 852 depends on CPU_V7 853 help 854 This option enables the workaround for the 430973 Cortex-A8 855 r1p* erratum. If a code sequence containing an ARM/Thumb 856 interworking branch is replaced with another code sequence at the 857 same virtual address, whether due to self-modifying code or virtual 858 to physical address re-mapping, Cortex-A8 does not recover from the 859 stale interworking branch prediction. This results in Cortex-A8 860 executing the new code sequence in the incorrect ARM or Thumb state. 861 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 862 and also flushes the branch target cache at every context switch. 863 Note that setting specific bits in the ACTLR register may not be 864 available in non-secure mode. 865 866config ARM_ERRATA_458693 867 bool "ARM errata: Processor deadlock when a false hazard is created" 868 depends on CPU_V7 869 depends on !ARCH_MULTIPLATFORM 870 help 871 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 872 erratum. For very specific sequences of memory operations, it is 873 possible for a hazard condition intended for a cache line to instead 874 be incorrectly associated with a different cache line. This false 875 hazard might then cause a processor deadlock. The workaround enables 876 the L1 caching of the NEON accesses and disables the PLD instruction 877 in the ACTLR register. Note that setting specific bits in the ACTLR 878 register may not be available in non-secure mode. 879 880config ARM_ERRATA_460075 881 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 882 depends on CPU_V7 883 depends on !ARCH_MULTIPLATFORM 884 help 885 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 886 erratum. Any asynchronous access to the L2 cache may encounter a 887 situation in which recent store transactions to the L2 cache are lost 888 and overwritten with stale memory contents from external memory. The 889 workaround disables the write-allocate mode for the L2 cache via the 890 ACTLR register. Note that setting specific bits in the ACTLR register 891 may not be available in non-secure mode. 892 893config ARM_ERRATA_742230 894 bool "ARM errata: DMB operation may be faulty" 895 depends on CPU_V7 && SMP 896 depends on !ARCH_MULTIPLATFORM 897 help 898 This option enables the workaround for the 742230 Cortex-A9 899 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 900 between two write operations may not ensure the correct visibility 901 ordering of the two writes. This workaround sets a specific bit in 902 the diagnostic register of the Cortex-A9 which causes the DMB 903 instruction to behave as a DSB, ensuring the correct behaviour of 904 the two writes. 905 906config ARM_ERRATA_742231 907 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 908 depends on CPU_V7 && SMP 909 depends on !ARCH_MULTIPLATFORM 910 help 911 This option enables the workaround for the 742231 Cortex-A9 912 (r2p0..r2p2) erratum. Under certain conditions, specific to the 913 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 914 accessing some data located in the same cache line, may get corrupted 915 data due to bad handling of the address hazard when the line gets 916 replaced from one of the CPUs at the same time as another CPU is 917 accessing it. This workaround sets specific bits in the diagnostic 918 register of the Cortex-A9 which reduces the linefill issuing 919 capabilities of the processor. 920 921config ARM_ERRATA_643719 922 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 923 depends on CPU_V7 && SMP 924 default y 925 help 926 This option enables the workaround for the 643719 Cortex-A9 (prior to 927 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 928 register returns zero when it should return one. The workaround 929 corrects this value, ensuring cache maintenance operations which use 930 it behave as intended and avoiding data corruption. 931 932config ARM_ERRATA_720789 933 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 934 depends on CPU_V7 935 help 936 This option enables the workaround for the 720789 Cortex-A9 (prior to 937 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 938 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 939 As a consequence of this erratum, some TLB entries which should be 940 invalidated are not, resulting in an incoherency in the system page 941 tables. The workaround changes the TLB flushing routines to invalidate 942 entries regardless of the ASID. 943 944config ARM_ERRATA_743622 945 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 946 depends on CPU_V7 947 depends on !ARCH_MULTIPLATFORM 948 help 949 This option enables the workaround for the 743622 Cortex-A9 950 (r2p*) erratum. Under very rare conditions, a faulty 951 optimisation in the Cortex-A9 Store Buffer may lead to data 952 corruption. This workaround sets a specific bit in the diagnostic 953 register of the Cortex-A9 which disables the Store Buffer 954 optimisation, preventing the defect from occurring. This has no 955 visible impact on the overall performance or power consumption of the 956 processor. 957 958config ARM_ERRATA_751472 959 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 960 depends on CPU_V7 961 depends on !ARCH_MULTIPLATFORM 962 help 963 This option enables the workaround for the 751472 Cortex-A9 (prior 964 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 965 completion of a following broadcasted operation if the second 966 operation is received by a CPU before the ICIALLUIS has completed, 967 potentially leading to corrupted entries in the cache or TLB. 968 969config ARM_ERRATA_754322 970 bool "ARM errata: possible faulty MMU translations following an ASID switch" 971 depends on CPU_V7 972 help 973 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 974 r3p*) erratum. A speculative memory access may cause a page table walk 975 which starts prior to an ASID switch but completes afterwards. This 976 can populate the micro-TLB with a stale entry which may be hit with 977 the new ASID. This workaround places two dsb instructions in the mm 978 switching code so that no page table walks can cross the ASID switch. 979 980config ARM_ERRATA_754327 981 bool "ARM errata: no automatic Store Buffer drain" 982 depends on CPU_V7 && SMP 983 help 984 This option enables the workaround for the 754327 Cortex-A9 (prior to 985 r2p0) erratum. The Store Buffer does not have any automatic draining 986 mechanism and therefore a livelock may occur if an external agent 987 continuously polls a memory location waiting to observe an update. 988 This workaround defines cpu_relax() as smp_mb(), preventing correctly 989 written polling loops from denying visibility of updates to memory. 990 991config ARM_ERRATA_364296 992 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 993 depends on CPU_V6 994 help 995 This options enables the workaround for the 364296 ARM1136 996 r0p2 erratum (possible cache data corruption with 997 hit-under-miss enabled). It sets the undocumented bit 31 in 998 the auxiliary control register and the FI bit in the control 999 register, thus disabling hit-under-miss without putting the 1000 processor into full low interrupt latency mode. ARM11MPCore 1001 is not affected. 1002 1003config ARM_ERRATA_764369 1004 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1005 depends on CPU_V7 && SMP 1006 help 1007 This option enables the workaround for erratum 764369 1008 affecting Cortex-A9 MPCore with two or more processors (all 1009 current revisions). Under certain timing circumstances, a data 1010 cache line maintenance operation by MVA targeting an Inner 1011 Shareable memory region may fail to proceed up to either the 1012 Point of Coherency or to the Point of Unification of the 1013 system. This workaround adds a DSB instruction before the 1014 relevant cache maintenance functions and sets a specific bit 1015 in the diagnostic control register of the SCU. 1016 1017config ARM_ERRATA_775420 1018 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1019 depends on CPU_V7 1020 help 1021 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1022 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1023 operation aborts with MMU exception, it might cause the processor 1024 to deadlock. This workaround puts DSB before executing ISB if 1025 an abort may occur on cache maintenance. 1026 1027config ARM_ERRATA_798181 1028 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1029 depends on CPU_V7 && SMP 1030 help 1031 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1032 adequately shooting down all use of the old entries. This 1033 option enables the Linux kernel workaround for this erratum 1034 which sends an IPI to the CPUs that are running the same ASID 1035 as the one being invalidated. 1036 1037config ARM_ERRATA_773022 1038 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1039 depends on CPU_V7 1040 help 1041 This option enables the workaround for the 773022 Cortex-A15 1042 (up to r0p4) erratum. In certain rare sequences of code, the 1043 loop buffer may deliver incorrect instructions. This 1044 workaround disables the loop buffer to avoid the erratum. 1045 1046config ARM_ERRATA_818325_852422 1047 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1048 depends on CPU_V7 1049 help 1050 This option enables the workaround for: 1051 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1052 instruction might deadlock. Fixed in r0p1. 1053 - Cortex-A12 852422: Execution of a sequence of instructions might 1054 lead to either a data corruption or a CPU deadlock. Not fixed in 1055 any Cortex-A12 cores yet. 1056 This workaround for all both errata involves setting bit[12] of the 1057 Feature Register. This bit disables an optimisation applied to a 1058 sequence of 2 instructions that use opposing condition codes. 1059 1060config ARM_ERRATA_821420 1061 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1062 depends on CPU_V7 1063 help 1064 This option enables the workaround for the 821420 Cortex-A12 1065 (all revs) erratum. In very rare timing conditions, a sequence 1066 of VMOV to Core registers instructions, for which the second 1067 one is in the shadow of a branch or abort, can lead to a 1068 deadlock when the VMOV instructions are issued out-of-order. 1069 1070config ARM_ERRATA_825619 1071 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1072 depends on CPU_V7 1073 help 1074 This option enables the workaround for the 825619 Cortex-A12 1075 (all revs) erratum. Within rare timing constraints, executing a 1076 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1077 and Device/Strongly-Ordered loads and stores might cause deadlock 1078 1079config ARM_ERRATA_857271 1080 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1081 depends on CPU_V7 1082 help 1083 This option enables the workaround for the 857271 Cortex-A12 1084 (all revs) erratum. Under very rare timing conditions, the CPU might 1085 hang. The workaround is expected to have a < 1% performance impact. 1086 1087config ARM_ERRATA_852421 1088 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1089 depends on CPU_V7 1090 help 1091 This option enables the workaround for the 852421 Cortex-A17 1092 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1093 execution of a DMB ST instruction might fail to properly order 1094 stores from GroupA and stores from GroupB. 1095 1096config ARM_ERRATA_852423 1097 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1098 depends on CPU_V7 1099 help 1100 This option enables the workaround for: 1101 - Cortex-A17 852423: Execution of a sequence of instructions might 1102 lead to either a data corruption or a CPU deadlock. Not fixed in 1103 any Cortex-A17 cores yet. 1104 This is identical to Cortex-A12 erratum 852422. It is a separate 1105 config option from the A12 erratum due to the way errata are checked 1106 for and handled. 1107 1108config ARM_ERRATA_857272 1109 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1110 depends on CPU_V7 1111 help 1112 This option enables the workaround for the 857272 Cortex-A17 erratum. 1113 This erratum is not known to be fixed in any A17 revision. 1114 This is identical to Cortex-A12 erratum 857271. It is a separate 1115 config option from the A12 erratum due to the way errata are checked 1116 for and handled. 1117 1118endmenu 1119 1120source "arch/arm/common/Kconfig" 1121 1122menu "Bus support" 1123 1124config ISA 1125 bool 1126 help 1127 Find out whether you have ISA slots on your motherboard. ISA is the 1128 name of a bus system, i.e. the way the CPU talks to the other stuff 1129 inside your box. Other bus systems are PCI, EISA, MicroChannel 1130 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1131 newer boards don't support it. If you have ISA, say Y, otherwise N. 1132 1133# Select ISA DMA controller support 1134config ISA_DMA 1135 bool 1136 select ISA_DMA_API 1137 1138# Select ISA DMA interface 1139config ISA_DMA_API 1140 bool 1141 1142config PCI_NANOENGINE 1143 bool "BSE nanoEngine PCI support" 1144 depends on SA1100_NANOENGINE 1145 help 1146 Enable PCI on the BSE nanoEngine board. 1147 1148config PCI_HOST_ITE8152 1149 bool 1150 depends on PCI && MACH_ARMCORE 1151 default y 1152 select DMABOUNCE 1153 1154config ARM_ERRATA_814220 1155 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1156 depends on CPU_V7 1157 help 1158 The v7 ARM states that all cache and branch predictor maintenance 1159 operations that do not specify an address execute, relative to 1160 each other, in program order. 1161 However, because of this erratum, an L2 set/way cache maintenance 1162 operation can overtake an L1 set/way cache maintenance operation. 1163 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1164 r0p4, r0p5. 1165 1166endmenu 1167 1168menu "Kernel Features" 1169 1170config HAVE_SMP 1171 bool 1172 help 1173 This option should be selected by machines which have an SMP- 1174 capable CPU. 1175 1176 The only effect of this option is to make the SMP-related 1177 options available to the user for configuration. 1178 1179config SMP 1180 bool "Symmetric Multi-Processing" 1181 depends on CPU_V6K || CPU_V7 1182 depends on GENERIC_CLOCKEVENTS 1183 depends on HAVE_SMP 1184 depends on MMU || ARM_MPU 1185 select IRQ_WORK 1186 help 1187 This enables support for systems with more than one CPU. If you have 1188 a system with only one CPU, say N. If you have a system with more 1189 than one CPU, say Y. 1190 1191 If you say N here, the kernel will run on uni- and multiprocessor 1192 machines, but will use only one CPU of a multiprocessor machine. If 1193 you say Y here, the kernel will run on many, but not all, 1194 uniprocessor machines. On a uniprocessor machine, the kernel 1195 will run faster if you say N here. 1196 1197 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1198 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1199 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1200 1201 If you don't know what to do here, say N. 1202 1203config SMP_ON_UP 1204 bool "Allow booting SMP kernel on uniprocessor systems" 1205 depends on SMP && !XIP_KERNEL && MMU 1206 default y 1207 help 1208 SMP kernels contain instructions which fail on non-SMP processors. 1209 Enabling this option allows the kernel to modify itself to make 1210 these instructions safe. Disabling it allows about 1K of space 1211 savings. 1212 1213 If you don't know what to do here, say Y. 1214 1215config ARM_CPU_TOPOLOGY 1216 bool "Support cpu topology definition" 1217 depends on SMP && CPU_V7 1218 default y 1219 help 1220 Support ARM cpu topology definition. The MPIDR register defines 1221 affinity between processors which is then used to describe the cpu 1222 topology of an ARM System. 1223 1224config SCHED_MC 1225 bool "Multi-core scheduler support" 1226 depends on ARM_CPU_TOPOLOGY 1227 help 1228 Multi-core scheduler support improves the CPU scheduler's decision 1229 making when dealing with multi-core CPU chips at a cost of slightly 1230 increased overhead in some places. If unsure say N here. 1231 1232config SCHED_SMT 1233 bool "SMT scheduler support" 1234 depends on ARM_CPU_TOPOLOGY 1235 help 1236 Improves the CPU scheduler's decision making when dealing with 1237 MultiThreading at a cost of slightly increased overhead in some 1238 places. If unsure say N here. 1239 1240config HAVE_ARM_SCU 1241 bool 1242 help 1243 This option enables support for the ARM snoop control unit 1244 1245config HAVE_ARM_ARCH_TIMER 1246 bool "Architected timer support" 1247 depends on CPU_V7 1248 select ARM_ARCH_TIMER 1249 select GENERIC_CLOCKEVENTS 1250 help 1251 This option enables support for the ARM architected timer 1252 1253config HAVE_ARM_TWD 1254 bool 1255 help 1256 This options enables support for the ARM timer and watchdog unit 1257 1258config MCPM 1259 bool "Multi-Cluster Power Management" 1260 depends on CPU_V7 && SMP 1261 help 1262 This option provides the common power management infrastructure 1263 for (multi-)cluster based systems, such as big.LITTLE based 1264 systems. 1265 1266config MCPM_QUAD_CLUSTER 1267 bool 1268 depends on MCPM 1269 help 1270 To avoid wasting resources unnecessarily, MCPM only supports up 1271 to 2 clusters by default. 1272 Platforms with 3 or 4 clusters that use MCPM must select this 1273 option to allow the additional clusters to be managed. 1274 1275config BIG_LITTLE 1276 bool "big.LITTLE support (Experimental)" 1277 depends on CPU_V7 && SMP 1278 select MCPM 1279 help 1280 This option enables support selections for the big.LITTLE 1281 system architecture. 1282 1283config BL_SWITCHER 1284 bool "big.LITTLE switcher support" 1285 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1286 select CPU_PM 1287 help 1288 The big.LITTLE "switcher" provides the core functionality to 1289 transparently handle transition between a cluster of A15's 1290 and a cluster of A7's in a big.LITTLE system. 1291 1292config BL_SWITCHER_DUMMY_IF 1293 tristate "Simple big.LITTLE switcher user interface" 1294 depends on BL_SWITCHER && DEBUG_KERNEL 1295 help 1296 This is a simple and dummy char dev interface to control 1297 the big.LITTLE switcher core code. It is meant for 1298 debugging purposes only. 1299 1300choice 1301 prompt "Memory split" 1302 depends on MMU 1303 default VMSPLIT_3G 1304 help 1305 Select the desired split between kernel and user memory. 1306 1307 If you are not absolutely sure what you are doing, leave this 1308 option alone! 1309 1310 config VMSPLIT_3G 1311 bool "3G/1G user/kernel split" 1312 config VMSPLIT_3G_OPT 1313 depends on !ARM_LPAE 1314 bool "3G/1G user/kernel split (for full 1G low memory)" 1315 config VMSPLIT_2G 1316 bool "2G/2G user/kernel split" 1317 config VMSPLIT_1G 1318 bool "1G/3G user/kernel split" 1319endchoice 1320 1321config PAGE_OFFSET 1322 hex 1323 default PHYS_OFFSET if !MMU 1324 default 0x40000000 if VMSPLIT_1G 1325 default 0x80000000 if VMSPLIT_2G 1326 default 0xB0000000 if VMSPLIT_3G_OPT 1327 default 0xC0000000 1328 1329config NR_CPUS 1330 int "Maximum number of CPUs (2-32)" 1331 range 2 32 1332 depends on SMP 1333 default "4" 1334 1335config HOTPLUG_CPU 1336 bool "Support for hot-pluggable CPUs" 1337 depends on SMP 1338 select GENERIC_IRQ_MIGRATION 1339 help 1340 Say Y here to experiment with turning CPUs off and on. CPUs 1341 can be controlled through /sys/devices/system/cpu. 1342 1343config ARM_PSCI 1344 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1345 depends on HAVE_ARM_SMCCC 1346 select ARM_PSCI_FW 1347 help 1348 Say Y here if you want Linux to communicate with system firmware 1349 implementing the PSCI specification for CPU-centric power 1350 management operations described in ARM document number ARM DEN 1351 0022A ("Power State Coordination Interface System Software on 1352 ARM processors"). 1353 1354# The GPIO number here must be sorted by descending number. In case of 1355# a multiplatform kernel, we just want the highest value required by the 1356# selected platforms. 1357config ARCH_NR_GPIO 1358 int 1359 default 2048 if ARCH_SOCFPGA 1360 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1361 ARCH_ZYNQ || ARCH_ASPEED 1362 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1363 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1364 default 416 if ARCH_SUNXI 1365 default 392 if ARCH_U8500 1366 default 352 if ARCH_VT8500 1367 default 288 if ARCH_ROCKCHIP 1368 default 264 if MACH_H4700 1369 default 0 1370 help 1371 Maximum number of GPIOs in the system. 1372 1373 If unsure, leave the default value. 1374 1375config HZ_FIXED 1376 int 1377 default 200 if ARCH_EBSA110 1378 default 128 if SOC_AT91RM9200 1379 default 0 1380 1381choice 1382 depends on HZ_FIXED = 0 1383 prompt "Timer frequency" 1384 1385config HZ_100 1386 bool "100 Hz" 1387 1388config HZ_200 1389 bool "200 Hz" 1390 1391config HZ_250 1392 bool "250 Hz" 1393 1394config HZ_300 1395 bool "300 Hz" 1396 1397config HZ_500 1398 bool "500 Hz" 1399 1400config HZ_1000 1401 bool "1000 Hz" 1402 1403endchoice 1404 1405config HZ 1406 int 1407 default HZ_FIXED if HZ_FIXED != 0 1408 default 100 if HZ_100 1409 default 200 if HZ_200 1410 default 250 if HZ_250 1411 default 300 if HZ_300 1412 default 500 if HZ_500 1413 default 1000 1414 1415config SCHED_HRTICK 1416 def_bool HIGH_RES_TIMERS 1417 1418config THUMB2_KERNEL 1419 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1420 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1421 default y if CPU_THUMBONLY 1422 select ARM_UNWIND 1423 help 1424 By enabling this option, the kernel will be compiled in 1425 Thumb-2 mode. 1426 1427 If unsure, say N. 1428 1429config THUMB2_AVOID_R_ARM_THM_JUMP11 1430 bool "Work around buggy Thumb-2 short branch relocations in gas" 1431 depends on THUMB2_KERNEL && MODULES 1432 default y 1433 help 1434 Various binutils versions can resolve Thumb-2 branches to 1435 locally-defined, preemptible global symbols as short-range "b.n" 1436 branch instructions. 1437 1438 This is a problem, because there's no guarantee the final 1439 destination of the symbol, or any candidate locations for a 1440 trampoline, are within range of the branch. For this reason, the 1441 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1442 relocation in modules at all, and it makes little sense to add 1443 support. 1444 1445 The symptom is that the kernel fails with an "unsupported 1446 relocation" error when loading some modules. 1447 1448 Until fixed tools are available, passing 1449 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1450 code which hits this problem, at the cost of a bit of extra runtime 1451 stack usage in some cases. 1452 1453 The problem is described in more detail at: 1454 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1455 1456 Only Thumb-2 kernels are affected. 1457 1458 Unless you are sure your tools don't have this problem, say Y. 1459 1460config ARM_PATCH_IDIV 1461 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1462 depends on CPU_32v7 && !XIP_KERNEL 1463 default y 1464 help 1465 The ARM compiler inserts calls to __aeabi_idiv() and 1466 __aeabi_uidiv() when it needs to perform division on signed 1467 and unsigned integers. Some v7 CPUs have support for the sdiv 1468 and udiv instructions that can be used to implement those 1469 functions. 1470 1471 Enabling this option allows the kernel to modify itself to 1472 replace the first two instructions of these library functions 1473 with the sdiv or udiv plus "bx lr" instructions when the CPU 1474 it is running on supports them. Typically this will be faster 1475 and less power intensive than running the original library 1476 code to do integer division. 1477 1478config AEABI 1479 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1480 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1481 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1482 help 1483 This option allows for the kernel to be compiled using the latest 1484 ARM ABI (aka EABI). This is only useful if you are using a user 1485 space environment that is also compiled with EABI. 1486 1487 Since there are major incompatibilities between the legacy ABI and 1488 EABI, especially with regard to structure member alignment, this 1489 option also changes the kernel syscall calling convention to 1490 disambiguate both ABIs and allow for backward compatibility support 1491 (selected with CONFIG_OABI_COMPAT). 1492 1493 To use this you need GCC version 4.0.0 or later. 1494 1495config OABI_COMPAT 1496 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1497 depends on AEABI && !THUMB2_KERNEL 1498 help 1499 This option preserves the old syscall interface along with the 1500 new (ARM EABI) one. It also provides a compatibility layer to 1501 intercept syscalls that have structure arguments which layout 1502 in memory differs between the legacy ABI and the new ARM EABI 1503 (only for non "thumb" binaries). This option adds a tiny 1504 overhead to all syscalls and produces a slightly larger kernel. 1505 1506 The seccomp filter system will not be available when this is 1507 selected, since there is no way yet to sensibly distinguish 1508 between calling conventions during filtering. 1509 1510 If you know you'll be using only pure EABI user space then you 1511 can say N here. If this option is not selected and you attempt 1512 to execute a legacy ABI binary then the result will be 1513 UNPREDICTABLE (in fact it can be predicted that it won't work 1514 at all). If in doubt say N. 1515 1516config ARCH_HAS_HOLES_MEMORYMODEL 1517 bool 1518 1519config ARCH_SPARSEMEM_ENABLE 1520 bool 1521 1522config ARCH_SPARSEMEM_DEFAULT 1523 def_bool ARCH_SPARSEMEM_ENABLE 1524 1525config HAVE_ARCH_PFN_VALID 1526 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1527 1528config HIGHMEM 1529 bool "High Memory Support" 1530 depends on MMU 1531 help 1532 The address space of ARM processors is only 4 Gigabytes large 1533 and it has to accommodate user address space, kernel address 1534 space as well as some memory mapped IO. That means that, if you 1535 have a large amount of physical memory and/or IO, not all of the 1536 memory can be "permanently mapped" by the kernel. The physical 1537 memory that is not permanently mapped is called "high memory". 1538 1539 Depending on the selected kernel/user memory split, minimum 1540 vmalloc space and actual amount of RAM, you may not need this 1541 option which should result in a slightly faster kernel. 1542 1543 If unsure, say n. 1544 1545config HIGHPTE 1546 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1547 depends on HIGHMEM 1548 default y 1549 help 1550 The VM uses one page of physical memory for each page table. 1551 For systems with a lot of processes, this can use a lot of 1552 precious low memory, eventually leading to low memory being 1553 consumed by page tables. Setting this option will allow 1554 user-space 2nd level page tables to reside in high memory. 1555 1556config CPU_SW_DOMAIN_PAN 1557 bool "Enable use of CPU domains to implement privileged no-access" 1558 depends on MMU && !ARM_LPAE 1559 default y 1560 help 1561 Increase kernel security by ensuring that normal kernel accesses 1562 are unable to access userspace addresses. This can help prevent 1563 use-after-free bugs becoming an exploitable privilege escalation 1564 by ensuring that magic values (such as LIST_POISON) will always 1565 fault when dereferenced. 1566 1567 CPUs with low-vector mappings use a best-efforts implementation. 1568 Their lower 1MB needs to remain accessible for the vectors, but 1569 the remainder of userspace will become appropriately inaccessible. 1570 1571config HW_PERF_EVENTS 1572 def_bool y 1573 depends on ARM_PMU 1574 1575config SYS_SUPPORTS_HUGETLBFS 1576 def_bool y 1577 depends on ARM_LPAE 1578 1579config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1580 def_bool y 1581 depends on ARM_LPAE 1582 1583config ARCH_WANT_GENERAL_HUGETLB 1584 def_bool y 1585 1586config ARM_MODULE_PLTS 1587 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1588 depends on MODULES 1589 default y 1590 help 1591 Allocate PLTs when loading modules so that jumps and calls whose 1592 targets are too far away for their relative offsets to be encoded 1593 in the instructions themselves can be bounced via veneers in the 1594 module's PLT. This allows modules to be allocated in the generic 1595 vmalloc area after the dedicated module memory area has been 1596 exhausted. The modules will use slightly more memory, but after 1597 rounding up to page size, the actual memory footprint is usually 1598 the same. 1599 1600 Disabling this is usually safe for small single-platform 1601 configurations. If unsure, say y. 1602 1603config FORCE_MAX_ZONEORDER 1604 int "Maximum zone order" 1605 default "12" if SOC_AM33XX 1606 default "9" if SA1111 || ARCH_EFM32 1607 default "11" 1608 help 1609 The kernel memory allocator divides physically contiguous memory 1610 blocks into "zones", where each zone is a power of two number of 1611 pages. This option selects the largest power of two that the kernel 1612 keeps in the memory allocator. If you need to allocate very large 1613 blocks of physically contiguous memory, then you may need to 1614 increase this value. 1615 1616 This config option is actually maximum order plus one. For example, 1617 a value of 11 means that the largest free memory block is 2^10 pages. 1618 1619config ALIGNMENT_TRAP 1620 bool 1621 depends on CPU_CP15_MMU 1622 default y if !ARCH_EBSA110 1623 select HAVE_PROC_CPU if PROC_FS 1624 help 1625 ARM processors cannot fetch/store information which is not 1626 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1627 address divisible by 4. On 32-bit ARM processors, these non-aligned 1628 fetch/store instructions will be emulated in software if you say 1629 here, which has a severe performance impact. This is necessary for 1630 correct operation of some network protocols. With an IP-only 1631 configuration it is safe to say N, otherwise say Y. 1632 1633config UACCESS_WITH_MEMCPY 1634 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1635 depends on MMU 1636 default y if CPU_FEROCEON 1637 help 1638 Implement faster copy_to_user and clear_user methods for CPU 1639 cores where a 8-word STM instruction give significantly higher 1640 memory write throughput than a sequence of individual 32bit stores. 1641 1642 A possible side effect is a slight increase in scheduling latency 1643 between threads sharing the same address space if they invoke 1644 such copy operations with large buffers. 1645 1646 However, if the CPU data cache is using a write-allocate mode, 1647 this option is unlikely to provide any performance gain. 1648 1649config SECCOMP 1650 bool 1651 prompt "Enable seccomp to safely compute untrusted bytecode" 1652 ---help--- 1653 This kernel feature is useful for number crunching applications 1654 that may need to compute untrusted bytecode during their 1655 execution. By using pipes or other transports made available to 1656 the process as file descriptors supporting the read/write 1657 syscalls, it's possible to isolate those applications in 1658 their own address space using seccomp. Once seccomp is 1659 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1660 and the task is only allowed to execute a few safe syscalls 1661 defined by each seccomp mode. 1662 1663config PARAVIRT 1664 bool "Enable paravirtualization code" 1665 help 1666 This changes the kernel so it can modify itself when it is run 1667 under a hypervisor, potentially improving performance significantly 1668 over full virtualization. 1669 1670config PARAVIRT_TIME_ACCOUNTING 1671 bool "Paravirtual steal time accounting" 1672 select PARAVIRT 1673 help 1674 Select this option to enable fine granularity task steal time 1675 accounting. Time spent executing other tasks in parallel with 1676 the current vCPU is discounted from the vCPU power. To account for 1677 that, there can be a small performance impact. 1678 1679 If in doubt, say N here. 1680 1681config XEN_DOM0 1682 def_bool y 1683 depends on XEN 1684 1685config XEN 1686 bool "Xen guest support on ARM" 1687 depends on ARM && AEABI && OF 1688 depends on CPU_V7 && !CPU_V6 1689 depends on !GENERIC_ATOMIC64 1690 depends on MMU 1691 select ARCH_DMA_ADDR_T_64BIT 1692 select ARM_PSCI 1693 select SWIOTLB 1694 select SWIOTLB_XEN 1695 select PARAVIRT 1696 help 1697 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1698 1699config STACKPROTECTOR_PER_TASK 1700 bool "Use a unique stack canary value for each task" 1701 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1702 select GCC_PLUGIN_ARM_SSP_PER_TASK 1703 default y 1704 help 1705 Due to the fact that GCC uses an ordinary symbol reference from 1706 which to load the value of the stack canary, this value can only 1707 change at reboot time on SMP systems, and all tasks running in the 1708 kernel's address space are forced to use the same canary value for 1709 the entire duration that the system is up. 1710 1711 Enable this option to switch to a different method that uses a 1712 different canary value for each task. 1713 1714endmenu 1715 1716menu "Boot options" 1717 1718config USE_OF 1719 bool "Flattened Device Tree support" 1720 select IRQ_DOMAIN 1721 select OF 1722 help 1723 Include support for flattened device tree machine descriptions. 1724 1725config ATAGS 1726 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1727 default y 1728 help 1729 This is the traditional way of passing data to the kernel at boot 1730 time. If you are solely relying on the flattened device tree (or 1731 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1732 to remove ATAGS support from your kernel binary. If unsure, 1733 leave this to y. 1734 1735config DEPRECATED_PARAM_STRUCT 1736 bool "Provide old way to pass kernel parameters" 1737 depends on ATAGS 1738 help 1739 This was deprecated in 2001 and announced to live on for 5 years. 1740 Some old boot loaders still use this way. 1741 1742# Compressed boot loader in ROM. Yes, we really want to ask about 1743# TEXT and BSS so we preserve their values in the config files. 1744config ZBOOT_ROM_TEXT 1745 hex "Compressed ROM boot loader base address" 1746 default "0" 1747 help 1748 The physical address at which the ROM-able zImage is to be 1749 placed in the target. Platforms which normally make use of 1750 ROM-able zImage formats normally set this to a suitable 1751 value in their defconfig file. 1752 1753 If ZBOOT_ROM is not enabled, this has no effect. 1754 1755config ZBOOT_ROM_BSS 1756 hex "Compressed ROM boot loader BSS address" 1757 default "0" 1758 help 1759 The base address of an area of read/write memory in the target 1760 for the ROM-able zImage which must be available while the 1761 decompressor is running. It must be large enough to hold the 1762 entire decompressed kernel plus an additional 128 KiB. 1763 Platforms which normally make use of ROM-able zImage formats 1764 normally set this to a suitable value in their defconfig file. 1765 1766 If ZBOOT_ROM is not enabled, this has no effect. 1767 1768config ZBOOT_ROM 1769 bool "Compressed boot loader in ROM/flash" 1770 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1771 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1772 help 1773 Say Y here if you intend to execute your compressed kernel image 1774 (zImage) directly from ROM or flash. If unsure, say N. 1775 1776config ARM_APPENDED_DTB 1777 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1778 depends on OF 1779 help 1780 With this option, the boot code will look for a device tree binary 1781 (DTB) appended to zImage 1782 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1783 1784 This is meant as a backward compatibility convenience for those 1785 systems with a bootloader that can't be upgraded to accommodate 1786 the documented boot protocol using a device tree. 1787 1788 Beware that there is very little in terms of protection against 1789 this option being confused by leftover garbage in memory that might 1790 look like a DTB header after a reboot if no actual DTB is appended 1791 to zImage. Do not leave this option active in a production kernel 1792 if you don't intend to always append a DTB. Proper passing of the 1793 location into r2 of a bootloader provided DTB is always preferable 1794 to this option. 1795 1796config ARM_ATAG_DTB_COMPAT 1797 bool "Supplement the appended DTB with traditional ATAG information" 1798 depends on ARM_APPENDED_DTB 1799 help 1800 Some old bootloaders can't be updated to a DTB capable one, yet 1801 they provide ATAGs with memory configuration, the ramdisk address, 1802 the kernel cmdline string, etc. Such information is dynamically 1803 provided by the bootloader and can't always be stored in a static 1804 DTB. To allow a device tree enabled kernel to be used with such 1805 bootloaders, this option allows zImage to extract the information 1806 from the ATAG list and store it at run time into the appended DTB. 1807 1808choice 1809 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1810 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1811 1812config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1813 bool "Use bootloader kernel arguments if available" 1814 help 1815 Uses the command-line options passed by the boot loader instead of 1816 the device tree bootargs property. If the boot loader doesn't provide 1817 any, the device tree bootargs property will be used. 1818 1819config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1820 bool "Extend with bootloader kernel arguments" 1821 help 1822 The command-line arguments provided by the boot loader will be 1823 appended to the the device tree bootargs property. 1824 1825endchoice 1826 1827config CMDLINE 1828 string "Default kernel command string" 1829 default "" 1830 help 1831 On some architectures (EBSA110 and CATS), there is currently no way 1832 for the boot loader to pass arguments to the kernel. For these 1833 architectures, you should supply some command-line options at build 1834 time by entering them here. As a minimum, you should specify the 1835 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1836 1837choice 1838 prompt "Kernel command line type" if CMDLINE != "" 1839 default CMDLINE_FROM_BOOTLOADER 1840 depends on ATAGS 1841 1842config CMDLINE_FROM_BOOTLOADER 1843 bool "Use bootloader kernel arguments if available" 1844 help 1845 Uses the command-line options passed by the boot loader. If 1846 the boot loader doesn't provide any, the default kernel command 1847 string provided in CMDLINE will be used. 1848 1849config CMDLINE_EXTEND 1850 bool "Extend bootloader kernel arguments" 1851 help 1852 The command-line arguments provided by the boot loader will be 1853 appended to the default kernel command string. 1854 1855config CMDLINE_FORCE 1856 bool "Always use the default kernel command string" 1857 help 1858 Always use the default kernel command string, even if the boot 1859 loader passes other arguments to the kernel. 1860 This is useful if you cannot or don't want to change the 1861 command-line options your boot loader passes to the kernel. 1862endchoice 1863 1864config XIP_KERNEL 1865 bool "Kernel Execute-In-Place from ROM" 1866 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1867 help 1868 Execute-In-Place allows the kernel to run from non-volatile storage 1869 directly addressable by the CPU, such as NOR flash. This saves RAM 1870 space since the text section of the kernel is not loaded from flash 1871 to RAM. Read-write sections, such as the data section and stack, 1872 are still copied to RAM. The XIP kernel is not compressed since 1873 it has to run directly from flash, so it will take more space to 1874 store it. The flash address used to link the kernel object files, 1875 and for storing it, is configuration dependent. Therefore, if you 1876 say Y here, you must know the proper physical address where to 1877 store the kernel image depending on your own flash memory usage. 1878 1879 Also note that the make target becomes "make xipImage" rather than 1880 "make zImage" or "make Image". The final kernel binary to put in 1881 ROM memory will be arch/arm/boot/xipImage. 1882 1883 If unsure, say N. 1884 1885config XIP_PHYS_ADDR 1886 hex "XIP Kernel Physical Location" 1887 depends on XIP_KERNEL 1888 default "0x00080000" 1889 help 1890 This is the physical address in your flash memory the kernel will 1891 be linked for and stored to. This address is dependent on your 1892 own flash usage. 1893 1894config XIP_DEFLATED_DATA 1895 bool "Store kernel .data section compressed in ROM" 1896 depends on XIP_KERNEL 1897 select ZLIB_INFLATE 1898 help 1899 Before the kernel is actually executed, its .data section has to be 1900 copied to RAM from ROM. This option allows for storing that data 1901 in compressed form and decompressed to RAM rather than merely being 1902 copied, saving some precious ROM space. A possible drawback is a 1903 slightly longer boot delay. 1904 1905config KEXEC 1906 bool "Kexec system call (EXPERIMENTAL)" 1907 depends on (!SMP || PM_SLEEP_SMP) 1908 depends on MMU 1909 select KEXEC_CORE 1910 help 1911 kexec is a system call that implements the ability to shutdown your 1912 current kernel, and to start another kernel. It is like a reboot 1913 but it is independent of the system firmware. And like a reboot 1914 you can start any kernel with it, not just Linux. 1915 1916 It is an ongoing process to be certain the hardware in a machine 1917 is properly shutdown, so do not be surprised if this code does not 1918 initially work for you. 1919 1920config ATAGS_PROC 1921 bool "Export atags in procfs" 1922 depends on ATAGS && KEXEC 1923 default y 1924 help 1925 Should the atags used to boot the kernel be exported in an "atags" 1926 file in procfs. Useful with kexec. 1927 1928config CRASH_DUMP 1929 bool "Build kdump crash kernel (EXPERIMENTAL)" 1930 help 1931 Generate crash dump after being started by kexec. This should 1932 be normally only set in special crash dump kernels which are 1933 loaded in the main kernel with kexec-tools into a specially 1934 reserved region and then later executed after a crash by 1935 kdump/kexec. The crash dump kernel must be compiled to a 1936 memory address not used by the main kernel 1937 1938 For more details see Documentation/admin-guide/kdump/kdump.rst 1939 1940config AUTO_ZRELADDR 1941 bool "Auto calculation of the decompressed kernel image address" 1942 help 1943 ZRELADDR is the physical address where the decompressed kernel 1944 image will be placed. If AUTO_ZRELADDR is selected, the address 1945 will be determined at run-time by masking the current IP with 1946 0xf8000000. This assumes the zImage being placed in the first 128MB 1947 from start of memory. 1948 1949config EFI_STUB 1950 bool 1951 1952config EFI 1953 bool "UEFI runtime support" 1954 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1955 select UCS2_STRING 1956 select EFI_PARAMS_FROM_FDT 1957 select EFI_STUB 1958 select EFI_ARMSTUB 1959 select EFI_RUNTIME_WRAPPERS 1960 ---help--- 1961 This option provides support for runtime services provided 1962 by UEFI firmware (such as non-volatile variables, realtime 1963 clock, and platform reset). A UEFI stub is also provided to 1964 allow the kernel to be booted as an EFI application. This 1965 is only useful for kernels that may run on systems that have 1966 UEFI firmware. 1967 1968config DMI 1969 bool "Enable support for SMBIOS (DMI) tables" 1970 depends on EFI 1971 default y 1972 help 1973 This enables SMBIOS/DMI feature for systems. 1974 1975 This option is only useful on systems that have UEFI firmware. 1976 However, even with this option, the resultant kernel should 1977 continue to boot on existing non-UEFI platforms. 1978 1979 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1980 i.e., the the practice of identifying the platform via DMI to 1981 decide whether certain workarounds for buggy hardware and/or 1982 firmware need to be enabled. This would require the DMI subsystem 1983 to be enabled much earlier than we do on ARM, which is non-trivial. 1984 1985endmenu 1986 1987menu "CPU Power Management" 1988 1989source "drivers/cpufreq/Kconfig" 1990 1991source "drivers/cpuidle/Kconfig" 1992 1993endmenu 1994 1995menu "Floating point emulation" 1996 1997comment "At least one emulation must be selected" 1998 1999config FPE_NWFPE 2000 bool "NWFPE math emulation" 2001 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2002 ---help--- 2003 Say Y to include the NWFPE floating point emulator in the kernel. 2004 This is necessary to run most binaries. Linux does not currently 2005 support floating point hardware so you need to say Y here even if 2006 your machine has an FPA or floating point co-processor podule. 2007 2008 You may say N here if you are going to load the Acorn FPEmulator 2009 early in the bootup. 2010 2011config FPE_NWFPE_XP 2012 bool "Support extended precision" 2013 depends on FPE_NWFPE 2014 help 2015 Say Y to include 80-bit support in the kernel floating-point 2016 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2017 Note that gcc does not generate 80-bit operations by default, 2018 so in most cases this option only enlarges the size of the 2019 floating point emulator without any good reason. 2020 2021 You almost surely want to say N here. 2022 2023config FPE_FASTFPE 2024 bool "FastFPE math emulation (EXPERIMENTAL)" 2025 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2026 ---help--- 2027 Say Y here to include the FAST floating point emulator in the kernel. 2028 This is an experimental much faster emulator which now also has full 2029 precision for the mantissa. It does not support any exceptions. 2030 It is very simple, and approximately 3-6 times faster than NWFPE. 2031 2032 It should be sufficient for most programs. It may be not suitable 2033 for scientific calculations, but you have to check this for yourself. 2034 If you do not feel you need a faster FP emulation you should better 2035 choose NWFPE. 2036 2037config VFP 2038 bool "VFP-format floating point maths" 2039 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2040 help 2041 Say Y to include VFP support code in the kernel. This is needed 2042 if your hardware includes a VFP unit. 2043 2044 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2045 release notes and additional status information. 2046 2047 Say N if your target does not have VFP hardware. 2048 2049config VFPv3 2050 bool 2051 depends on VFP 2052 default y if CPU_V7 2053 2054config NEON 2055 bool "Advanced SIMD (NEON) Extension support" 2056 depends on VFPv3 && CPU_V7 2057 help 2058 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2059 Extension. 2060 2061config KERNEL_MODE_NEON 2062 bool "Support for NEON in kernel mode" 2063 depends on NEON && AEABI 2064 help 2065 Say Y to include support for NEON in kernel mode. 2066 2067endmenu 2068 2069menu "Power management options" 2070 2071source "kernel/power/Kconfig" 2072 2073config ARCH_SUSPEND_POSSIBLE 2074 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2075 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2076 def_bool y 2077 2078config ARM_CPU_SUSPEND 2079 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2080 depends on ARCH_SUSPEND_POSSIBLE 2081 2082config ARCH_HIBERNATION_POSSIBLE 2083 bool 2084 depends on MMU 2085 default y if ARCH_SUSPEND_POSSIBLE 2086 2087endmenu 2088 2089source "drivers/firmware/Kconfig" 2090 2091if CRYPTO 2092source "arch/arm/crypto/Kconfig" 2093endif 2094 2095source "arch/arm/kvm/Kconfig" 2096