1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander 4 * 5 * Copyright (C) 2019 STMicroelectronics 6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>. 7 */ 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/mfd/stmfx.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pinctrl/pinconf.h> 14 #include <linux/pinctrl/pinmux.h> 15 16 #include "core.h" 17 #include "pinctrl-utils.h" 18 19 /* GPIOs expander */ 20 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */ 21 #define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */ 22 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */ 23 #define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */ 24 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */ 25 #define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */ 26 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */ 27 #define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */ 28 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */ 29 #define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */ 30 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */ 31 #define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */ 32 /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */ 33 #define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */ 34 /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */ 35 #define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */ 36 /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */ 37 #define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */ 38 /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/ 39 #define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */ 40 /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */ 41 #define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */ 42 43 #define NR_GPIO_REGS 3 44 #define NR_GPIOS_PER_REG 8 45 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) 46 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) 47 #define get_mask(offset) (BIT(get_shift(offset))) 48 49 /* 50 * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used. 51 * Pins availability is managed thanks to gpio-ranges property. 52 */ 53 static const struct pinctrl_pin_desc stmfx_pins[] = { 54 PINCTRL_PIN(0, "gpio0"), 55 PINCTRL_PIN(1, "gpio1"), 56 PINCTRL_PIN(2, "gpio2"), 57 PINCTRL_PIN(3, "gpio3"), 58 PINCTRL_PIN(4, "gpio4"), 59 PINCTRL_PIN(5, "gpio5"), 60 PINCTRL_PIN(6, "gpio6"), 61 PINCTRL_PIN(7, "gpio7"), 62 PINCTRL_PIN(8, "gpio8"), 63 PINCTRL_PIN(9, "gpio9"), 64 PINCTRL_PIN(10, "gpio10"), 65 PINCTRL_PIN(11, "gpio11"), 66 PINCTRL_PIN(12, "gpio12"), 67 PINCTRL_PIN(13, "gpio13"), 68 PINCTRL_PIN(14, "gpio14"), 69 PINCTRL_PIN(15, "gpio15"), 70 PINCTRL_PIN(16, "agpio0"), 71 PINCTRL_PIN(17, "agpio1"), 72 PINCTRL_PIN(18, "agpio2"), 73 PINCTRL_PIN(19, "agpio3"), 74 PINCTRL_PIN(20, "agpio4"), 75 PINCTRL_PIN(21, "agpio5"), 76 PINCTRL_PIN(22, "agpio6"), 77 PINCTRL_PIN(23, "agpio7"), 78 }; 79 80 struct stmfx_pinctrl { 81 struct device *dev; 82 struct stmfx *stmfx; 83 struct pinctrl_dev *pctl_dev; 84 struct pinctrl_desc pctl_desc; 85 struct gpio_chip gpio_chip; 86 struct irq_chip irq_chip; 87 struct mutex lock; /* IRQ bus lock */ 88 unsigned long gpio_valid_mask; 89 /* Cache of IRQ_GPI_* registers for bus_lock */ 90 u8 irq_gpi_src[NR_GPIO_REGS]; 91 u8 irq_gpi_type[NR_GPIO_REGS]; 92 u8 irq_gpi_evt[NR_GPIO_REGS]; 93 u8 irq_toggle_edge[NR_GPIO_REGS]; 94 #ifdef CONFIG_PM 95 /* Backup of GPIO_* registers for suspend/resume */ 96 u8 bkp_gpio_state[NR_GPIO_REGS]; 97 u8 bkp_gpio_dir[NR_GPIO_REGS]; 98 u8 bkp_gpio_type[NR_GPIO_REGS]; 99 u8 bkp_gpio_pupd[NR_GPIO_REGS]; 100 #endif 101 }; 102 103 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) 104 { 105 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 106 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); 107 u32 mask = get_mask(offset); 108 u32 value; 109 int ret; 110 111 ret = regmap_read(pctl->stmfx->map, reg, &value); 112 113 return ret ? ret : !!(value & mask); 114 } 115 116 static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 117 { 118 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 119 u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; 120 u32 mask = get_mask(offset); 121 122 regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), 123 mask, mask); 124 } 125 126 static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 127 { 128 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 129 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 130 u32 mask = get_mask(offset); 131 u32 val; 132 int ret; 133 134 ret = regmap_read(pctl->stmfx->map, reg, &val); 135 /* 136 * On stmfx, gpio pins direction is (0)input, (1)output. 137 */ 138 if (ret) 139 return ret; 140 141 if (val & mask) 142 return GPIO_LINE_DIRECTION_OUT; 143 144 return GPIO_LINE_DIRECTION_IN; 145 } 146 147 static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 148 { 149 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 150 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 151 u32 mask = get_mask(offset); 152 153 return regmap_write_bits(pctl->stmfx->map, reg, mask, 0); 154 } 155 156 static int stmfx_gpio_direction_output(struct gpio_chip *gc, 157 unsigned int offset, int value) 158 { 159 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 160 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 161 u32 mask = get_mask(offset); 162 163 stmfx_gpio_set(gc, offset, value); 164 165 return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); 166 } 167 168 static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl, 169 unsigned int offset) 170 { 171 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 172 u32 pupd, mask = get_mask(offset); 173 int ret; 174 175 ret = regmap_read(pctl->stmfx->map, reg, &pupd); 176 if (ret) 177 return ret; 178 179 return !!(pupd & mask); 180 } 181 182 static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl, 183 unsigned int offset, u32 pupd) 184 { 185 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 186 u32 mask = get_mask(offset); 187 188 return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0); 189 } 190 191 static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl, 192 unsigned int offset) 193 { 194 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 195 u32 type, mask = get_mask(offset); 196 int ret; 197 198 ret = regmap_read(pctl->stmfx->map, reg, &type); 199 if (ret) 200 return ret; 201 202 return !!(type & mask); 203 } 204 205 static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl, 206 unsigned int offset, u32 type) 207 { 208 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 209 u32 mask = get_mask(offset); 210 211 return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0); 212 } 213 214 static int stmfx_pinconf_get(struct pinctrl_dev *pctldev, 215 unsigned int pin, unsigned long *config) 216 { 217 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 218 u32 param = pinconf_to_config_param(*config); 219 struct pinctrl_gpio_range *range; 220 u32 arg = 0; 221 int ret, dir, type, pupd; 222 223 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 224 if (!range) 225 return -EINVAL; 226 227 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); 228 if (dir < 0) 229 return dir; 230 231 /* 232 * Currently the gpiolib IN is 1 and OUT is 0 but let's not count 233 * on it just to be on the safe side also in the future :) 234 */ 235 dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0; 236 237 type = stmfx_pinconf_get_type(pctl, pin); 238 if (type < 0) 239 return type; 240 pupd = stmfx_pinconf_get_pupd(pctl, pin); 241 if (pupd < 0) 242 return pupd; 243 244 switch (param) { 245 case PIN_CONFIG_BIAS_DISABLE: 246 if ((!dir && (!type || !pupd)) || (dir && !type)) 247 arg = 1; 248 break; 249 case PIN_CONFIG_BIAS_PULL_DOWN: 250 if (dir && type && !pupd) 251 arg = 1; 252 break; 253 case PIN_CONFIG_BIAS_PULL_UP: 254 if (type && pupd) 255 arg = 1; 256 break; 257 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 258 if ((!dir && type) || (dir && !type)) 259 arg = 1; 260 break; 261 case PIN_CONFIG_DRIVE_PUSH_PULL: 262 if ((!dir && !type) || (dir && type)) 263 arg = 1; 264 break; 265 case PIN_CONFIG_OUTPUT: 266 if (dir) 267 return -EINVAL; 268 269 ret = stmfx_gpio_get(&pctl->gpio_chip, pin); 270 if (ret < 0) 271 return ret; 272 273 arg = ret; 274 break; 275 default: 276 return -ENOTSUPP; 277 } 278 279 *config = pinconf_to_config_packed(param, arg); 280 281 return 0; 282 } 283 284 static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 285 unsigned long *configs, unsigned int num_configs) 286 { 287 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 288 struct pinctrl_gpio_range *range; 289 enum pin_config_param param; 290 u32 arg; 291 int dir, i, ret; 292 293 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 294 if (!range) { 295 dev_err(pctldev->dev, "pin %d is not available\n", pin); 296 return -EINVAL; 297 } 298 299 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); 300 if (dir < 0) 301 return dir; 302 303 for (i = 0; i < num_configs; i++) { 304 param = pinconf_to_config_param(configs[i]); 305 arg = pinconf_to_config_argument(configs[i]); 306 307 switch (param) { 308 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 309 case PIN_CONFIG_BIAS_DISABLE: 310 case PIN_CONFIG_DRIVE_PUSH_PULL: 311 ret = stmfx_pinconf_set_type(pctl, pin, 0); 312 if (ret) 313 return ret; 314 break; 315 case PIN_CONFIG_BIAS_PULL_DOWN: 316 ret = stmfx_pinconf_set_type(pctl, pin, 1); 317 if (ret) 318 return ret; 319 ret = stmfx_pinconf_set_pupd(pctl, pin, 0); 320 if (ret) 321 return ret; 322 break; 323 case PIN_CONFIG_BIAS_PULL_UP: 324 ret = stmfx_pinconf_set_type(pctl, pin, 1); 325 if (ret) 326 return ret; 327 ret = stmfx_pinconf_set_pupd(pctl, pin, 1); 328 if (ret) 329 return ret; 330 break; 331 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 332 ret = stmfx_pinconf_set_type(pctl, pin, 1); 333 if (ret) 334 return ret; 335 break; 336 case PIN_CONFIG_OUTPUT: 337 ret = stmfx_gpio_direction_output(&pctl->gpio_chip, 338 pin, arg); 339 if (ret) 340 return ret; 341 break; 342 default: 343 return -ENOTSUPP; 344 } 345 } 346 347 return 0; 348 } 349 350 static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 351 struct seq_file *s, unsigned int offset) 352 { 353 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 354 struct pinctrl_gpio_range *range; 355 int dir, type, pupd, val; 356 357 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset); 358 if (!range) 359 return; 360 361 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset); 362 if (dir < 0) 363 return; 364 type = stmfx_pinconf_get_type(pctl, offset); 365 if (type < 0) 366 return; 367 pupd = stmfx_pinconf_get_pupd(pctl, offset); 368 if (pupd < 0) 369 return; 370 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 371 if (val < 0) 372 return; 373 374 if (dir == GPIO_LINE_DIRECTION_OUT) { 375 seq_printf(s, "output %s ", val ? "high" : "low"); 376 if (type) 377 seq_printf(s, "open drain %s internal pull-up ", 378 pupd ? "with" : "without"); 379 else 380 seq_puts(s, "push pull no pull "); 381 } else { 382 seq_printf(s, "input %s ", val ? "high" : "low"); 383 if (type) 384 seq_printf(s, "with internal pull-%s ", 385 pupd ? "up" : "down"); 386 else 387 seq_printf(s, "%s ", pupd ? "floating" : "analog"); 388 } 389 } 390 391 static const struct pinconf_ops stmfx_pinconf_ops = { 392 .pin_config_get = stmfx_pinconf_get, 393 .pin_config_set = stmfx_pinconf_set, 394 .pin_config_dbg_show = stmfx_pinconf_dbg_show, 395 }; 396 397 static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 398 { 399 return 0; 400 } 401 402 static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 403 unsigned int selector) 404 { 405 return NULL; 406 } 407 408 static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 409 unsigned int selector, 410 const unsigned int **pins, 411 unsigned int *num_pins) 412 { 413 return -ENOTSUPP; 414 } 415 416 static const struct pinctrl_ops stmfx_pinctrl_ops = { 417 .get_groups_count = stmfx_pinctrl_get_groups_count, 418 .get_group_name = stmfx_pinctrl_get_group_name, 419 .get_group_pins = stmfx_pinctrl_get_group_pins, 420 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 421 .dt_free_map = pinctrl_utils_free_map, 422 }; 423 424 static void stmfx_pinctrl_irq_mask(struct irq_data *data) 425 { 426 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 427 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 428 u32 reg = get_reg(data->hwirq); 429 u32 mask = get_mask(data->hwirq); 430 431 pctl->irq_gpi_src[reg] &= ~mask; 432 } 433 434 static void stmfx_pinctrl_irq_unmask(struct irq_data *data) 435 { 436 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 437 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 438 u32 reg = get_reg(data->hwirq); 439 u32 mask = get_mask(data->hwirq); 440 441 pctl->irq_gpi_src[reg] |= mask; 442 } 443 444 static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type) 445 { 446 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 447 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 448 u32 reg = get_reg(data->hwirq); 449 u32 mask = get_mask(data->hwirq); 450 451 if (type == IRQ_TYPE_NONE) 452 return -EINVAL; 453 454 if (type & IRQ_TYPE_EDGE_BOTH) { 455 pctl->irq_gpi_evt[reg] |= mask; 456 irq_set_handler_locked(data, handle_edge_irq); 457 } else { 458 pctl->irq_gpi_evt[reg] &= ~mask; 459 irq_set_handler_locked(data, handle_level_irq); 460 } 461 462 if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH)) 463 pctl->irq_gpi_type[reg] |= mask; 464 else 465 pctl->irq_gpi_type[reg] &= ~mask; 466 467 /* 468 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current 469 * GPIO value to set the right edge trigger. But in atomic context 470 * here we can't access registers over I2C. That's why (type & 471 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock. 472 */ 473 474 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 475 pctl->irq_toggle_edge[reg] |= mask; 476 else 477 pctl->irq_toggle_edge[reg] &= mask; 478 479 return 0; 480 } 481 482 static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data) 483 { 484 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 485 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 486 487 mutex_lock(&pctl->lock); 488 } 489 490 static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data) 491 { 492 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 493 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 494 u32 reg = get_reg(data->hwirq); 495 u32 mask = get_mask(data->hwirq); 496 497 /* 498 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value 499 * (this couldn't be done in .irq_set_type because of atomic context) 500 * to set the right irq trigger type. 501 */ 502 if (pctl->irq_toggle_edge[reg] & mask) { 503 if (stmfx_gpio_get(gpio_chip, data->hwirq)) 504 pctl->irq_gpi_type[reg] &= ~mask; 505 else 506 pctl->irq_gpi_type[reg] |= mask; 507 } 508 509 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 510 pctl->irq_gpi_evt, NR_GPIO_REGS); 511 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 512 pctl->irq_gpi_type, NR_GPIO_REGS); 513 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 514 pctl->irq_gpi_src, NR_GPIO_REGS); 515 516 mutex_unlock(&pctl->lock); 517 } 518 519 static int stmfx_gpio_irq_request_resources(struct irq_data *data) 520 { 521 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 522 int ret; 523 524 ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq); 525 if (ret) 526 return ret; 527 528 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 529 } 530 531 static void stmfx_gpio_irq_release_resources(struct irq_data *data) 532 { 533 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 534 535 return gpiochip_relres_irq(gpio_chip, data->hwirq); 536 } 537 538 static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl, 539 unsigned int offset) 540 { 541 u32 reg = get_reg(offset); 542 u32 mask = get_mask(offset); 543 int val; 544 545 if (!(pctl->irq_toggle_edge[reg] & mask)) 546 return; 547 548 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 549 if (val < 0) 550 return; 551 552 if (val) { 553 pctl->irq_gpi_type[reg] &= mask; 554 regmap_write_bits(pctl->stmfx->map, 555 STMFX_REG_IRQ_GPI_TYPE + reg, 556 mask, 0); 557 558 } else { 559 pctl->irq_gpi_type[reg] |= mask; 560 regmap_write_bits(pctl->stmfx->map, 561 STMFX_REG_IRQ_GPI_TYPE + reg, 562 mask, mask); 563 } 564 } 565 566 static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) 567 { 568 struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id; 569 struct gpio_chip *gc = &pctl->gpio_chip; 570 u8 pending[NR_GPIO_REGS]; 571 u8 src[NR_GPIO_REGS] = {0, 0, 0}; 572 unsigned long n, status; 573 int ret; 574 575 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING, 576 &pending, NR_GPIO_REGS); 577 if (ret) 578 return IRQ_NONE; 579 580 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 581 src, NR_GPIO_REGS); 582 583 status = *(unsigned long *)pending; 584 for_each_set_bit(n, &status, gc->ngpio) { 585 handle_nested_irq(irq_find_mapping(gc->irq.domain, n)); 586 stmfx_pinctrl_irq_toggle_trigger(pctl, n); 587 } 588 589 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 590 pctl->irq_gpi_src, NR_GPIO_REGS); 591 592 return IRQ_HANDLED; 593 } 594 595 static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl) 596 { 597 struct pinctrl_gpio_range *gpio_range; 598 struct pinctrl_dev *pctl_dev = pctl->pctl_dev; 599 u32 func = STMFX_FUNC_GPIO; 600 601 pctl->gpio_valid_mask = GENMASK(15, 0); 602 603 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16); 604 if (gpio_range) { 605 func |= STMFX_FUNC_ALTGPIO_LOW; 606 pctl->gpio_valid_mask |= GENMASK(19, 16); 607 } 608 609 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20); 610 if (gpio_range) { 611 func |= STMFX_FUNC_ALTGPIO_HIGH; 612 pctl->gpio_valid_mask |= GENMASK(23, 20); 613 } 614 615 return stmfx_function_enable(pctl->stmfx, func); 616 } 617 618 static int stmfx_pinctrl_probe(struct platform_device *pdev) 619 { 620 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 621 struct device_node *np = pdev->dev.of_node; 622 struct stmfx_pinctrl *pctl; 623 int irq, ret; 624 625 pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL); 626 if (!pctl) 627 return -ENOMEM; 628 629 platform_set_drvdata(pdev, pctl); 630 631 pctl->dev = &pdev->dev; 632 pctl->stmfx = stmfx; 633 634 if (!of_find_property(np, "gpio-ranges", NULL)) { 635 dev_err(pctl->dev, "missing required gpio-ranges property\n"); 636 return -EINVAL; 637 } 638 639 irq = platform_get_irq(pdev, 0); 640 if (irq <= 0) 641 return -ENXIO; 642 643 mutex_init(&pctl->lock); 644 645 /* Register pin controller */ 646 pctl->pctl_desc.name = "stmfx-pinctrl"; 647 pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops; 648 pctl->pctl_desc.confops = &stmfx_pinconf_ops; 649 pctl->pctl_desc.pins = stmfx_pins; 650 pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins); 651 pctl->pctl_desc.owner = THIS_MODULE; 652 pctl->pctl_desc.link_consumers = true; 653 654 ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc, 655 pctl, &pctl->pctl_dev); 656 if (ret) { 657 dev_err(pctl->dev, "pinctrl registration failed\n"); 658 return ret; 659 } 660 661 ret = pinctrl_enable(pctl->pctl_dev); 662 if (ret) { 663 dev_err(pctl->dev, "pinctrl enable failed\n"); 664 return ret; 665 } 666 667 /* Register gpio controller */ 668 pctl->gpio_chip.label = "stmfx-gpio"; 669 pctl->gpio_chip.parent = pctl->dev; 670 pctl->gpio_chip.get_direction = stmfx_gpio_get_direction; 671 pctl->gpio_chip.direction_input = stmfx_gpio_direction_input; 672 pctl->gpio_chip.direction_output = stmfx_gpio_direction_output; 673 pctl->gpio_chip.get = stmfx_gpio_get; 674 pctl->gpio_chip.set = stmfx_gpio_set; 675 pctl->gpio_chip.set_config = gpiochip_generic_config; 676 pctl->gpio_chip.base = -1; 677 pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; 678 pctl->gpio_chip.can_sleep = true; 679 pctl->gpio_chip.of_node = np; 680 681 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 682 if (ret) { 683 dev_err(pctl->dev, "gpio_chip registration failed\n"); 684 return ret; 685 } 686 687 ret = stmfx_pinctrl_gpio_function_enable(pctl); 688 if (ret) 689 return ret; 690 691 pctl->irq_chip.name = dev_name(pctl->dev); 692 pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask; 693 pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask; 694 pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type; 695 pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock; 696 pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock; 697 pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources; 698 pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources; 699 700 ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip, 701 0, handle_bad_irq, IRQ_TYPE_NONE); 702 if (ret) { 703 dev_err(pctl->dev, "cannot add irqchip to gpiochip\n"); 704 return ret; 705 } 706 707 ret = devm_request_threaded_irq(pctl->dev, irq, NULL, 708 stmfx_pinctrl_irq_thread_fn, 709 IRQF_ONESHOT, 710 pctl->irq_chip.name, pctl); 711 if (ret) { 712 dev_err(pctl->dev, "cannot request irq%d\n", irq); 713 return ret; 714 } 715 716 gpiochip_set_nested_irqchip(&pctl->gpio_chip, &pctl->irq_chip, irq); 717 718 dev_info(pctl->dev, 719 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); 720 721 return 0; 722 } 723 724 static int stmfx_pinctrl_remove(struct platform_device *pdev) 725 { 726 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 727 728 return stmfx_function_disable(stmfx, 729 STMFX_FUNC_GPIO | 730 STMFX_FUNC_ALTGPIO_LOW | 731 STMFX_FUNC_ALTGPIO_HIGH); 732 } 733 734 #ifdef CONFIG_PM_SLEEP 735 static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl) 736 { 737 int ret; 738 739 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE, 740 &pctl->bkp_gpio_state, NR_GPIO_REGS); 741 if (ret) 742 return ret; 743 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 744 &pctl->bkp_gpio_dir, NR_GPIO_REGS); 745 if (ret) 746 return ret; 747 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 748 &pctl->bkp_gpio_type, NR_GPIO_REGS); 749 if (ret) 750 return ret; 751 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 752 &pctl->bkp_gpio_pupd, NR_GPIO_REGS); 753 if (ret) 754 return ret; 755 756 return 0; 757 } 758 759 static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl) 760 { 761 int ret; 762 763 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 764 pctl->bkp_gpio_dir, NR_GPIO_REGS); 765 if (ret) 766 return ret; 767 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 768 pctl->bkp_gpio_type, NR_GPIO_REGS); 769 if (ret) 770 return ret; 771 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 772 pctl->bkp_gpio_pupd, NR_GPIO_REGS); 773 if (ret) 774 return ret; 775 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET, 776 pctl->bkp_gpio_state, NR_GPIO_REGS); 777 if (ret) 778 return ret; 779 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 780 pctl->irq_gpi_evt, NR_GPIO_REGS); 781 if (ret) 782 return ret; 783 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 784 pctl->irq_gpi_type, NR_GPIO_REGS); 785 if (ret) 786 return ret; 787 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 788 pctl->irq_gpi_src, NR_GPIO_REGS); 789 if (ret) 790 return ret; 791 792 return 0; 793 } 794 795 static int stmfx_pinctrl_suspend(struct device *dev) 796 { 797 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 798 int ret; 799 800 ret = stmfx_pinctrl_backup_regs(pctl); 801 if (ret) { 802 dev_err(pctl->dev, "registers backup failure\n"); 803 return ret; 804 } 805 806 return 0; 807 } 808 809 static int stmfx_pinctrl_resume(struct device *dev) 810 { 811 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 812 int ret; 813 814 ret = stmfx_pinctrl_restore_regs(pctl); 815 if (ret) { 816 dev_err(pctl->dev, "registers restoration failure\n"); 817 return ret; 818 } 819 820 return 0; 821 } 822 #endif 823 824 static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops, 825 stmfx_pinctrl_suspend, stmfx_pinctrl_resume); 826 827 static const struct of_device_id stmfx_pinctrl_of_match[] = { 828 { .compatible = "st,stmfx-0300-pinctrl", }, 829 {}, 830 }; 831 MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match); 832 833 static struct platform_driver stmfx_pinctrl_driver = { 834 .driver = { 835 .name = "stmfx-pinctrl", 836 .of_match_table = stmfx_pinctrl_of_match, 837 .pm = &stmfx_pinctrl_dev_pm_ops, 838 }, 839 .probe = stmfx_pinctrl_probe, 840 .remove = stmfx_pinctrl_remove, 841 }; 842 module_platform_driver(stmfx_pinctrl_driver); 843 844 MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver"); 845 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 846 MODULE_LICENSE("GPL v2"); 847