1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Ralf Baechle 7 */ 8 #ifndef _ASM_ASMMACRO_H 9 #define _ASM_ASMMACRO_H 10 11 #include <asm/hazards.h> 12 #include <asm/asm-offsets.h> 13 #include <asm/msa.h> 14 15 #ifdef CONFIG_32BIT 16 #include <asm/asmmacro-32.h> 17 #endif 18 #ifdef CONFIG_64BIT 19 #include <asm/asmmacro-64.h> 20 #endif 21 22 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 23 #undef fp 24 25 /* 26 * Helper macros for generating raw instruction encodings. 27 */ 28 #ifdef CONFIG_CPU_MICROMIPS 29 .macro insn32_if_mm enc 30 .insn 31 .hword ((\enc) >> 16) 32 .hword ((\enc) & 0xffff) 33 .endm 34 35 .macro insn_if_mips enc 36 .endm 37 #else 38 .macro insn32_if_mm enc 39 .endm 40 41 .macro insn_if_mips enc 42 .insn 43 .word (\enc) 44 .endm 45 #endif 46 47 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 48 .macro local_irq_enable reg=t0 49 ei 50 irq_enable_hazard 51 .endm 52 53 .macro local_irq_disable reg=t0 54 di 55 irq_disable_hazard 56 .endm 57 #else 58 .macro local_irq_enable reg=t0 59 mfc0 \reg, CP0_STATUS 60 ori \reg, \reg, 1 61 mtc0 \reg, CP0_STATUS 62 irq_enable_hazard 63 .endm 64 65 .macro local_irq_disable reg=t0 66 #ifdef CONFIG_PREEMPTION 67 lw \reg, TI_PRE_COUNT($28) 68 addi \reg, \reg, 1 69 sw \reg, TI_PRE_COUNT($28) 70 #endif 71 mfc0 \reg, CP0_STATUS 72 ori \reg, \reg, 1 73 xori \reg, \reg, 1 74 mtc0 \reg, CP0_STATUS 75 irq_disable_hazard 76 #ifdef CONFIG_PREEMPTION 77 lw \reg, TI_PRE_COUNT($28) 78 addi \reg, \reg, -1 79 sw \reg, TI_PRE_COUNT($28) 80 #endif 81 .endm 82 #endif /* CONFIG_CPU_MIPSR2 */ 83 84 .macro fpu_save_16even thread tmp=t0 85 .set push 86 SET_HARDFLOAT 87 cfc1 \tmp, fcr31 88 sdc1 $f0, THREAD_FPR0(\thread) 89 sdc1 $f2, THREAD_FPR2(\thread) 90 sdc1 $f4, THREAD_FPR4(\thread) 91 sdc1 $f6, THREAD_FPR6(\thread) 92 sdc1 $f8, THREAD_FPR8(\thread) 93 sdc1 $f10, THREAD_FPR10(\thread) 94 sdc1 $f12, THREAD_FPR12(\thread) 95 sdc1 $f14, THREAD_FPR14(\thread) 96 sdc1 $f16, THREAD_FPR16(\thread) 97 sdc1 $f18, THREAD_FPR18(\thread) 98 sdc1 $f20, THREAD_FPR20(\thread) 99 sdc1 $f22, THREAD_FPR22(\thread) 100 sdc1 $f24, THREAD_FPR24(\thread) 101 sdc1 $f26, THREAD_FPR26(\thread) 102 sdc1 $f28, THREAD_FPR28(\thread) 103 sdc1 $f30, THREAD_FPR30(\thread) 104 sw \tmp, THREAD_FCR31(\thread) 105 .set pop 106 .endm 107 108 .macro fpu_save_16odd thread 109 .set push 110 .set mips64r2 111 .set fp=64 112 SET_HARDFLOAT 113 sdc1 $f1, THREAD_FPR1(\thread) 114 sdc1 $f3, THREAD_FPR3(\thread) 115 sdc1 $f5, THREAD_FPR5(\thread) 116 sdc1 $f7, THREAD_FPR7(\thread) 117 sdc1 $f9, THREAD_FPR9(\thread) 118 sdc1 $f11, THREAD_FPR11(\thread) 119 sdc1 $f13, THREAD_FPR13(\thread) 120 sdc1 $f15, THREAD_FPR15(\thread) 121 sdc1 $f17, THREAD_FPR17(\thread) 122 sdc1 $f19, THREAD_FPR19(\thread) 123 sdc1 $f21, THREAD_FPR21(\thread) 124 sdc1 $f23, THREAD_FPR23(\thread) 125 sdc1 $f25, THREAD_FPR25(\thread) 126 sdc1 $f27, THREAD_FPR27(\thread) 127 sdc1 $f29, THREAD_FPR29(\thread) 128 sdc1 $f31, THREAD_FPR31(\thread) 129 .set pop 130 .endm 131 132 .macro fpu_save_double thread status tmp 133 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 134 defined(CONFIG_CPU_MIPSR6) 135 sll \tmp, \status, 5 136 bgez \tmp, 10f 137 fpu_save_16odd \thread 138 10: 139 #endif 140 fpu_save_16even \thread \tmp 141 .endm 142 143 .macro fpu_restore_16even thread tmp=t0 144 .set push 145 SET_HARDFLOAT 146 lw \tmp, THREAD_FCR31(\thread) 147 ldc1 $f0, THREAD_FPR0(\thread) 148 ldc1 $f2, THREAD_FPR2(\thread) 149 ldc1 $f4, THREAD_FPR4(\thread) 150 ldc1 $f6, THREAD_FPR6(\thread) 151 ldc1 $f8, THREAD_FPR8(\thread) 152 ldc1 $f10, THREAD_FPR10(\thread) 153 ldc1 $f12, THREAD_FPR12(\thread) 154 ldc1 $f14, THREAD_FPR14(\thread) 155 ldc1 $f16, THREAD_FPR16(\thread) 156 ldc1 $f18, THREAD_FPR18(\thread) 157 ldc1 $f20, THREAD_FPR20(\thread) 158 ldc1 $f22, THREAD_FPR22(\thread) 159 ldc1 $f24, THREAD_FPR24(\thread) 160 ldc1 $f26, THREAD_FPR26(\thread) 161 ldc1 $f28, THREAD_FPR28(\thread) 162 ldc1 $f30, THREAD_FPR30(\thread) 163 ctc1 \tmp, fcr31 164 .set pop 165 .endm 166 167 .macro fpu_restore_16odd thread 168 .set push 169 .set mips64r2 170 .set fp=64 171 SET_HARDFLOAT 172 ldc1 $f1, THREAD_FPR1(\thread) 173 ldc1 $f3, THREAD_FPR3(\thread) 174 ldc1 $f5, THREAD_FPR5(\thread) 175 ldc1 $f7, THREAD_FPR7(\thread) 176 ldc1 $f9, THREAD_FPR9(\thread) 177 ldc1 $f11, THREAD_FPR11(\thread) 178 ldc1 $f13, THREAD_FPR13(\thread) 179 ldc1 $f15, THREAD_FPR15(\thread) 180 ldc1 $f17, THREAD_FPR17(\thread) 181 ldc1 $f19, THREAD_FPR19(\thread) 182 ldc1 $f21, THREAD_FPR21(\thread) 183 ldc1 $f23, THREAD_FPR23(\thread) 184 ldc1 $f25, THREAD_FPR25(\thread) 185 ldc1 $f27, THREAD_FPR27(\thread) 186 ldc1 $f29, THREAD_FPR29(\thread) 187 ldc1 $f31, THREAD_FPR31(\thread) 188 .set pop 189 .endm 190 191 .macro fpu_restore_double thread status tmp 192 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 193 defined(CONFIG_CPU_MIPSR6) 194 sll \tmp, \status, 5 195 bgez \tmp, 10f # 16 register mode? 196 197 fpu_restore_16odd \thread 198 10: 199 #endif 200 fpu_restore_16even \thread \tmp 201 .endm 202 203 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 204 .macro _EXT rd, rs, p, s 205 ext \rd, \rs, \p, \s 206 .endm 207 #else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */ 208 .macro _EXT rd, rs, p, s 209 srl \rd, \rs, \p 210 andi \rd, \rd, (1 << \s) - 1 211 .endm 212 #endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */ 213 214 /* 215 * Temporary until all gas have MT ASE support 216 */ 217 .macro DMT reg=0 218 .word 0x41600bc1 | (\reg << 16) 219 .endm 220 221 .macro EMT reg=0 222 .word 0x41600be1 | (\reg << 16) 223 .endm 224 225 .macro DVPE reg=0 226 .word 0x41600001 | (\reg << 16) 227 .endm 228 229 .macro EVPE reg=0 230 .word 0x41600021 | (\reg << 16) 231 .endm 232 233 .macro MFTR rt=0, rd=0, u=0, sel=0 234 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) 235 .endm 236 237 .macro MTTR rt=0, rd=0, u=0, sel=0 238 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) 239 .endm 240 241 #ifdef TOOLCHAIN_SUPPORTS_MSA 242 .macro _cfcmsa rd, cs 243 .set push 244 .set mips32r2 245 .set fp=64 246 .set msa 247 cfcmsa \rd, $\cs 248 .set pop 249 .endm 250 251 .macro _ctcmsa cd, rs 252 .set push 253 .set mips32r2 254 .set fp=64 255 .set msa 256 ctcmsa $\cd, \rs 257 .set pop 258 .endm 259 260 .macro ld_b wd, off, base 261 .set push 262 .set mips32r2 263 .set fp=64 264 .set msa 265 ld.b $w\wd, \off(\base) 266 .set pop 267 .endm 268 269 .macro ld_h wd, off, base 270 .set push 271 .set mips32r2 272 .set fp=64 273 .set msa 274 ld.h $w\wd, \off(\base) 275 .set pop 276 .endm 277 278 .macro ld_w wd, off, base 279 .set push 280 .set mips32r2 281 .set fp=64 282 .set msa 283 ld.w $w\wd, \off(\base) 284 .set pop 285 .endm 286 287 .macro ld_d wd, off, base 288 .set push 289 .set mips32r2 290 .set fp=64 291 .set msa 292 ld.d $w\wd, \off(\base) 293 .set pop 294 .endm 295 296 .macro st_b wd, off, base 297 .set push 298 .set mips32r2 299 .set fp=64 300 .set msa 301 st.b $w\wd, \off(\base) 302 .set pop 303 .endm 304 305 .macro st_h wd, off, base 306 .set push 307 .set mips32r2 308 .set fp=64 309 .set msa 310 st.h $w\wd, \off(\base) 311 .set pop 312 .endm 313 314 .macro st_w wd, off, base 315 .set push 316 .set mips32r2 317 .set fp=64 318 .set msa 319 st.w $w\wd, \off(\base) 320 .set pop 321 .endm 322 323 .macro st_d wd, off, base 324 .set push 325 .set mips32r2 326 .set fp=64 327 .set msa 328 st.d $w\wd, \off(\base) 329 .set pop 330 .endm 331 332 .macro copy_s_w ws, n 333 .set push 334 .set mips32r2 335 .set fp=64 336 .set msa 337 copy_s.w $1, $w\ws[\n] 338 .set pop 339 .endm 340 341 .macro copy_s_d ws, n 342 .set push 343 .set mips64r2 344 .set fp=64 345 .set msa 346 copy_s.d $1, $w\ws[\n] 347 .set pop 348 .endm 349 350 .macro insert_w wd, n 351 .set push 352 .set mips32r2 353 .set fp=64 354 .set msa 355 insert.w $w\wd[\n], $1 356 .set pop 357 .endm 358 359 .macro insert_d wd, n 360 .set push 361 .set mips64r2 362 .set fp=64 363 .set msa 364 insert.d $w\wd[\n], $1 365 .set pop 366 .endm 367 #else 368 369 /* 370 * Temporary until all toolchains in use include MSA support. 371 */ 372 .macro _cfcmsa rd, cs 373 .set push 374 .set noat 375 SET_HARDFLOAT 376 insn_if_mips 0x787e0059 | (\cs << 11) 377 insn32_if_mm 0x587e0056 | (\cs << 11) 378 move \rd, $1 379 .set pop 380 .endm 381 382 .macro _ctcmsa cd, rs 383 .set push 384 .set noat 385 SET_HARDFLOAT 386 move $1, \rs 387 insn_if_mips 0x783e0819 | (\cd << 6) 388 insn32_if_mm 0x583e0816 | (\cd << 6) 389 .set pop 390 .endm 391 392 .macro ld_b wd, off, base 393 .set push 394 .set noat 395 SET_HARDFLOAT 396 PTR_ADDU $1, \base, \off 397 insn_if_mips 0x78000820 | (\wd << 6) 398 insn32_if_mm 0x58000807 | (\wd << 6) 399 .set pop 400 .endm 401 402 .macro ld_h wd, off, base 403 .set push 404 .set noat 405 SET_HARDFLOAT 406 PTR_ADDU $1, \base, \off 407 insn_if_mips 0x78000821 | (\wd << 6) 408 insn32_if_mm 0x58000817 | (\wd << 6) 409 .set pop 410 .endm 411 412 .macro ld_w wd, off, base 413 .set push 414 .set noat 415 SET_HARDFLOAT 416 PTR_ADDU $1, \base, \off 417 insn_if_mips 0x78000822 | (\wd << 6) 418 insn32_if_mm 0x58000827 | (\wd << 6) 419 .set pop 420 .endm 421 422 .macro ld_d wd, off, base 423 .set push 424 .set noat 425 SET_HARDFLOAT 426 PTR_ADDU $1, \base, \off 427 insn_if_mips 0x78000823 | (\wd << 6) 428 insn32_if_mm 0x58000837 | (\wd << 6) 429 .set pop 430 .endm 431 432 .macro st_b wd, off, base 433 .set push 434 .set noat 435 SET_HARDFLOAT 436 PTR_ADDU $1, \base, \off 437 insn_if_mips 0x78000824 | (\wd << 6) 438 insn32_if_mm 0x5800080f | (\wd << 6) 439 .set pop 440 .endm 441 442 .macro st_h wd, off, base 443 .set push 444 .set noat 445 SET_HARDFLOAT 446 PTR_ADDU $1, \base, \off 447 insn_if_mips 0x78000825 | (\wd << 6) 448 insn32_if_mm 0x5800081f | (\wd << 6) 449 .set pop 450 .endm 451 452 .macro st_w wd, off, base 453 .set push 454 .set noat 455 SET_HARDFLOAT 456 PTR_ADDU $1, \base, \off 457 insn_if_mips 0x78000826 | (\wd << 6) 458 insn32_if_mm 0x5800082f | (\wd << 6) 459 .set pop 460 .endm 461 462 .macro st_d wd, off, base 463 .set push 464 .set noat 465 SET_HARDFLOAT 466 PTR_ADDU $1, \base, \off 467 insn_if_mips 0x78000827 | (\wd << 6) 468 insn32_if_mm 0x5800083f | (\wd << 6) 469 .set pop 470 .endm 471 472 .macro copy_s_w ws, n 473 .set push 474 .set noat 475 SET_HARDFLOAT 476 insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11) 477 insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11) 478 .set pop 479 .endm 480 481 .macro copy_s_d ws, n 482 .set push 483 .set noat 484 SET_HARDFLOAT 485 insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11) 486 insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11) 487 .set pop 488 .endm 489 490 .macro insert_w wd, n 491 .set push 492 .set noat 493 SET_HARDFLOAT 494 insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6) 495 insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6) 496 .set pop 497 .endm 498 499 .macro insert_d wd, n 500 .set push 501 .set noat 502 SET_HARDFLOAT 503 insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6) 504 insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6) 505 .set pop 506 .endm 507 #endif 508 509 #ifdef TOOLCHAIN_SUPPORTS_MSA 510 #define FPR_BASE_OFFS THREAD_FPR0 511 #define FPR_BASE $1 512 #else 513 #define FPR_BASE_OFFS 0 514 #define FPR_BASE \thread 515 #endif 516 517 .macro msa_save_all thread 518 .set push 519 .set noat 520 #ifdef TOOLCHAIN_SUPPORTS_MSA 521 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS 522 #endif 523 st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE 524 st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE 525 st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE 526 st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE 527 st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE 528 st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE 529 st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE 530 st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE 531 st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE 532 st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE 533 st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE 534 st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE 535 st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE 536 st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE 537 st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE 538 st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE 539 st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE 540 st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE 541 st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE 542 st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE 543 st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE 544 st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE 545 st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE 546 st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE 547 st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE 548 st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE 549 st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE 550 st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE 551 st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE 552 st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE 553 st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE 554 st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE 555 SET_HARDFLOAT 556 _cfcmsa $1, MSA_CSR 557 sw $1, THREAD_MSA_CSR(\thread) 558 .set pop 559 .endm 560 561 .macro msa_restore_all thread 562 .set push 563 .set noat 564 SET_HARDFLOAT 565 lw $1, THREAD_MSA_CSR(\thread) 566 _ctcmsa MSA_CSR, $1 567 #ifdef TOOLCHAIN_SUPPORTS_MSA 568 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS 569 #endif 570 ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE 571 ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE 572 ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE 573 ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE 574 ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE 575 ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE 576 ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE 577 ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE 578 ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE 579 ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE 580 ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE 581 ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE 582 ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE 583 ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE 584 ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE 585 ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE 586 ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE 587 ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE 588 ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE 589 ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE 590 ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE 591 ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE 592 ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE 593 ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE 594 ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE 595 ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE 596 ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE 597 ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE 598 ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE 599 ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE 600 ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE 601 ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE 602 .set pop 603 .endm 604 605 #undef FPR_BASE_OFFS 606 #undef FPR_BASE 607 608 .macro msa_init_upper wd 609 #ifdef CONFIG_64BIT 610 insert_d \wd, 1 611 #else 612 insert_w \wd, 2 613 insert_w \wd, 3 614 #endif 615 .endm 616 617 .macro msa_init_all_upper 618 .set push 619 .set noat 620 SET_HARDFLOAT 621 not $1, zero 622 msa_init_upper 0 623 msa_init_upper 1 624 msa_init_upper 2 625 msa_init_upper 3 626 msa_init_upper 4 627 msa_init_upper 5 628 msa_init_upper 6 629 msa_init_upper 7 630 msa_init_upper 8 631 msa_init_upper 9 632 msa_init_upper 10 633 msa_init_upper 11 634 msa_init_upper 12 635 msa_init_upper 13 636 msa_init_upper 14 637 msa_init_upper 15 638 msa_init_upper 16 639 msa_init_upper 17 640 msa_init_upper 18 641 msa_init_upper 19 642 msa_init_upper 20 643 msa_init_upper 21 644 msa_init_upper 22 645 msa_init_upper 23 646 msa_init_upper 24 647 msa_init_upper 25 648 msa_init_upper 26 649 msa_init_upper 27 650 msa_init_upper 28 651 msa_init_upper 29 652 msa_init_upper 30 653 msa_init_upper 31 654 .set pop 655 .endm 656 657 #endif /* _ASM_ASMMACRO_H */ 658