| b2d5025e | 18-Nov-2022 |
Sudeep Holla <sudeep.holla@arm.com> |
arm64: dts: fvp: Add information about L1 and L2 caches
Add the information about L1 and L2 caches on FVP RevC platform.
Though the cache size is configurable through the model parameters,
having de
arm64: dts: fvp: Add information about L1 and L2 caches
Add the information about L1 and L2 caches on FVP RevC platform.
Though the cache size is configurable through the model parameters,
having default values in the device tree helps to exercise and debug
any code utilising the cache information without the need of real
hardware.
Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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| 3bd7a021 | 17-Nov-2022 |
James Clark <james.clark@arm.com> |
arm64: dts: fvp: Add SPE to Foundation FVP
Add SPE DT node to FVP model. If the model doesn't support SPE (e.g.,
turned off via parameter), the driver will skip the initialisation
accordingly and th
arm64: dts: fvp: Add SPE to Foundation FVP
Add SPE DT node to FVP model. If the model doesn't support SPE (e.g.,
turned off via parameter), the driver will skip the initialisation
accordingly and thus is safe.
Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20221117102536.237515-1-james.clark@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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| 422ab8fe | 01-Aug-2022 |
Jassi Brar <jaswinder.singh@linaro.org> |
arm64: dts: juno: Add missing MHU secure-irq
The MHU secure interrupt exists physically but is missing in the DT node.
Specify the interrupt in DT node to fix a warning on Arm Juno board:
mhu@2b
arm64: dts: juno: Add missing MHU secure-irq
The MHU secure interrupt exists physically but is missing in the DT node.
Specify the interrupt in DT node to fix a warning on Arm Juno board:
mhu@2b1f0000: interrupts: [[0, 36, 4], [0, 35, 4]] is too short
Link: https://lore.kernel.org/r/20220801141005.599258-1-jassisinghbrar@gmail.com
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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| a0bf153f | 26-May-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: arm: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DT
arm64: dts: arm: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Link: https://lore.kernel.org/r/20220526204350.832361-1-krzysztof.kozlowski@linaro.org
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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| c7df8791 | 10-Jun-2022 |
Rob Herring <robh@kernel.org> |
arm64: dts: arm/juno: Drop erroneous 'mbox-name' property
The 'mbox-name' property in the Juno mailbox node is undocumented and
unused. It's the consumer side of the mailbox binding that have
'mbox-
arm64: dts: arm/juno: Drop erroneous 'mbox-name' property
The 'mbox-name' property in the Juno mailbox node is undocumented and
unused. It's the consumer side of the mailbox binding that have
'mbox-names' properties.
Link: https://lore.kernel.org/r/20220610213308.2288094-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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| b30ae563 | 30-Apr-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: juno: Drop useless 'dma-channels/requests' properties
The pl330 DMA controller provides number of DMA channels and requests
through its registers, so duplicating this information (with a
arm64: dts: juno: Drop useless 'dma-channels/requests' properties
The pl330 DMA controller provides number of DMA channels and requests
through its registers, so duplicating this information (with a chance of
mistakes) in DTS is pointless. Additionally the DTS used always wrong
property names which causes DT schema check failures - the bindings
documented 'dma-channels' and 'dma-requests' properties without leading
hash sign.
Another reason is that the number of requests also does not seem right
(should be 8).
Link: https://lore.kernel.org/r/20220430121902.59895-5-krzysztof.kozlowski@linaro.org
Reported-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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| 5393158f | 21-Apr-2022 |
Diego Sueiro <diego.sueiro@arm.com> |
arm64: dts: fvp: Add virtio-rng support
The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17,
so add the devicetree node to support it. It is disabled by default to
avoid any issues
arm64: dts: fvp: Add virtio-rng support
The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17,
so add the devicetree node to support it. It is disabled by default to
avoid any issues with models that doesn't support it.
Link: https://lore.kernel.org/r/ac3be672c636091ee1e079cadce776b1fb7e0b2e.1650543392.git.diego.sueiro@arm.com
Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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| a69d2774 | 08-Apr-2022 |
Rui Miguel Silva <rui.silva@linaro.org> |
arm64: dts: Add Arm corstone1000 platform support
Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].
The
arm64: dts: Add Arm corstone1000 platform support
Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].
These device trees contains the necessary bits to support the
Corstone 1000 FVP (Fixed Virtual Platform) [1] and the
FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host
side of this platform. [2]
0: https://developer.arm.com/documentation/102360/0000
1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
2: https://developer.arm.com/documentation/dai0550/c/
Link: https://lore.kernel.org/r/20220408131922.3864348-3-rui.silva@linaro.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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| 96bb0954 | 17-Feb-2022 |
Robin Murphy <robin.murphy@arm.com> |
arm64: dts: juno: Add separate SCMI variants
While Juno's SCP firmware initially spoke the SCPI protocol, binary
releases since 2018, and the newer open-source codebase, only speak SCMI
and thus are
arm64: dts: juno: Add separate SCMI variants
While Juno's SCP firmware initially spoke the SCPI protocol, binary
releases since 2018, and the newer open-source codebase, only speak SCMI
and thus aren't particularly compatibile with the DTs we currently have
upstream. Add a parallel set of variant DTs for boards with up-to-date
firmware, replacing the SCPI parts with their new SCMI equivalents.
Link: https://lore.kernel.org/r/f3516815104f951a05fc0f799681f77d7968f6ac.1645125063.git.robin.murphy@arm.com
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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