1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2L SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g054-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g054"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio2-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-150000000 { 50 opp-hz = /bits/ 64 <150000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-300000000 { 55 opp-hz = /bits/ 64 <300000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-600000000 { 60 opp-hz = /bits/ 64 <600000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1200000000 { 65 opp-hz = /bits/ 64 <1200000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu0>; 80 }; 81 core1 { 82 cpu = <&cpu1>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 compatible = "arm,cortex-a55"; 89 reg = <0>; 90 device_type = "cpu"; 91 #cooling-cells = <2>; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu1: cpu@100 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x100>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 L3_CA55: cache-controller-0 { 109 compatible = "cache"; 110 cache-unified; 111 cache-size = <0x40000>; 112 }; 113 }; 114 115 gpu_opp_table: opp-table-1 { 116 compatible = "operating-points-v2"; 117 118 opp-500000000 { 119 opp-hz = /bits/ 64 <500000000>; 120 opp-microvolt = <1100000>; 121 }; 122 123 opp-400000000 { 124 opp-hz = /bits/ 64 <400000000>; 125 opp-microvolt = <1100000>; 126 }; 127 128 opp-250000000 { 129 opp-hz = /bits/ 64 <250000000>; 130 opp-microvolt = <1100000>; 131 }; 132 133 opp-200000000 { 134 opp-hz = /bits/ 64 <200000000>; 135 opp-microvolt = <1100000>; 136 }; 137 138 opp-125000000 { 139 opp-hz = /bits/ 64 <125000000>; 140 opp-microvolt = <1100000>; 141 }; 142 143 opp-100000000 { 144 opp-hz = /bits/ 64 <100000000>; 145 opp-microvolt = <1100000>; 146 }; 147 148 opp-62500000 { 149 opp-hz = /bits/ 64 <62500000>; 150 opp-microvolt = <1100000>; 151 }; 152 153 opp-50000000 { 154 opp-hz = /bits/ 64 <50000000>; 155 opp-microvolt = <1100000>; 156 }; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0", "arm,psci-0.2"; 161 method = "smc"; 162 }; 163 164 soc: soc { 165 compatible = "simple-bus"; 166 interrupt-parent = <&gic>; 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges; 170 171 ssi0: ssi@10049c00 { 172 compatible = "renesas,r9a07g054-ssi", 173 "renesas,rz-ssi"; 174 reg = <0 0x10049c00 0 0x400>; 175 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 177 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 178 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 179 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 180 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, 181 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, 182 <&audio_clk1>, <&audio_clk2>; 183 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 184 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; 185 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 186 dma-names = "tx", "rx"; 187 power-domains = <&cpg>; 188 #sound-dai-cells = <0>; 189 status = "disabled"; 190 }; 191 192 ssi1: ssi@1004a000 { 193 compatible = "renesas,r9a07g054-ssi", 194 "renesas,rz-ssi"; 195 reg = <0 0x1004a000 0 0x400>; 196 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 198 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 199 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 200 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 201 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, 202 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, 203 <&audio_clk1>, <&audio_clk2>; 204 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 205 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; 206 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 207 dma-names = "tx", "rx"; 208 power-domains = <&cpg>; 209 #sound-dai-cells = <0>; 210 status = "disabled"; 211 }; 212 213 ssi2: ssi@1004a400 { 214 compatible = "renesas,r9a07g054-ssi", 215 "renesas,rz-ssi"; 216 reg = <0 0x1004a400 0 0x400>; 217 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 221 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 222 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, 223 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, 224 <&audio_clk1>, <&audio_clk2>; 225 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 226 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; 227 dmas = <&dmac 0x265f>; 228 dma-names = "rt"; 229 power-domains = <&cpg>; 230 #sound-dai-cells = <0>; 231 status = "disabled"; 232 }; 233 234 ssi3: ssi@1004a800 { 235 compatible = "renesas,r9a07g054-ssi", 236 "renesas,rz-ssi"; 237 reg = <0 0x1004a800 0 0x400>; 238 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 240 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 241 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 242 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 243 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, 244 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, 245 <&audio_clk1>, <&audio_clk2>; 246 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 247 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; 248 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 249 dma-names = "tx", "rx"; 250 power-domains = <&cpg>; 251 #sound-dai-cells = <0>; 252 status = "disabled"; 253 }; 254 255 spi0: spi@1004ac00 { 256 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 257 reg = <0 0x1004ac00 0 0x400>; 258 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 261 interrupt-names = "error", "rx", "tx"; 262 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; 263 resets = <&cpg R9A07G054_RSPI0_RST>; 264 power-domains = <&cpg>; 265 num-cs = <1>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 spi1: spi@1004b000 { 272 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 273 reg = <0 0x1004b000 0 0x400>; 274 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "error", "rx", "tx"; 278 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; 279 resets = <&cpg R9A07G054_RSPI1_RST>; 280 power-domains = <&cpg>; 281 num-cs = <1>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 status = "disabled"; 285 }; 286 287 spi2: spi@1004b400 { 288 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 289 reg = <0 0x1004b400 0 0x400>; 290 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-names = "error", "rx", "tx"; 294 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; 295 resets = <&cpg R9A07G054_RSPI2_RST>; 296 power-domains = <&cpg>; 297 num-cs = <1>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 scif0: serial@1004b800 { 304 compatible = "renesas,scif-r9a07g054", 305 "renesas,scif-r9a07g044"; 306 reg = <0 0x1004b800 0 0x400>; 307 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-names = "eri", "rxi", "txi", 314 "bri", "dri", "tei"; 315 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>; 316 clock-names = "fck"; 317 power-domains = <&cpg>; 318 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>; 319 status = "disabled"; 320 }; 321 322 scif1: serial@1004bc00 { 323 compatible = "renesas,scif-r9a07g054", 324 "renesas,scif-r9a07g044"; 325 reg = <0 0x1004bc00 0 0x400>; 326 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 332 interrupt-names = "eri", "rxi", "txi", 333 "bri", "dri", "tei"; 334 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>; 335 clock-names = "fck"; 336 power-domains = <&cpg>; 337 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>; 338 status = "disabled"; 339 }; 340 341 scif2: serial@1004c000 { 342 compatible = "renesas,scif-r9a07g054", 343 "renesas,scif-r9a07g044"; 344 reg = <0 0x1004c000 0 0x400>; 345 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 351 interrupt-names = "eri", "rxi", "txi", 352 "bri", "dri", "tei"; 353 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>; 354 clock-names = "fck"; 355 power-domains = <&cpg>; 356 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>; 357 status = "disabled"; 358 }; 359 360 scif3: serial@1004c400 { 361 compatible = "renesas,scif-r9a07g054", 362 "renesas,scif-r9a07g044"; 363 reg = <0 0x1004c400 0 0x400>; 364 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 370 interrupt-names = "eri", "rxi", "txi", 371 "bri", "dri", "tei"; 372 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>; 373 clock-names = "fck"; 374 power-domains = <&cpg>; 375 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>; 376 status = "disabled"; 377 }; 378 379 scif4: serial@1004c800 { 380 compatible = "renesas,scif-r9a07g054", 381 "renesas,scif-r9a07g044"; 382 reg = <0 0x1004c800 0 0x400>; 383 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-names = "eri", "rxi", "txi", 390 "bri", "dri", "tei"; 391 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>; 392 clock-names = "fck"; 393 power-domains = <&cpg>; 394 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>; 395 status = "disabled"; 396 }; 397 398 sci0: serial@1004d000 { 399 compatible = "renesas,r9a07g054-sci", "renesas,sci"; 400 reg = <0 0x1004d000 0 0x400>; 401 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 405 interrupt-names = "eri", "rxi", "txi", "tei"; 406 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; 407 clock-names = "fck"; 408 power-domains = <&cpg>; 409 resets = <&cpg R9A07G054_SCI0_RST>; 410 status = "disabled"; 411 }; 412 413 sci1: serial@1004d400 { 414 compatible = "renesas,r9a07g054-sci", "renesas,sci"; 415 reg = <0 0x1004d400 0 0x400>; 416 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 420 interrupt-names = "eri", "rxi", "txi", "tei"; 421 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; 422 clock-names = "fck"; 423 power-domains = <&cpg>; 424 resets = <&cpg R9A07G054_SCI1_RST>; 425 status = "disabled"; 426 }; 427 428 canfd: can@10050000 { 429 compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; 430 reg = <0 0x10050000 0 0x8000>; 431 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 439 interrupt-names = "g_err", "g_recc", 440 "ch0_err", "ch0_rec", "ch0_trx", 441 "ch1_err", "ch1_rec", "ch1_trx"; 442 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, 443 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, 444 <&can_clk>; 445 clock-names = "fck", "canfd", "can_clk"; 446 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; 447 assigned-clock-rates = <50000000>; 448 resets = <&cpg R9A07G054_CANFD_RSTP_N>, 449 <&cpg R9A07G054_CANFD_RSTC_N>; 450 reset-names = "rstp_n", "rstc_n"; 451 power-domains = <&cpg>; 452 status = "disabled"; 453 454 channel0 { 455 status = "disabled"; 456 }; 457 channel1 { 458 status = "disabled"; 459 }; 460 }; 461 462 i2c0: i2c@10058000 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 466 reg = <0 0x10058000 0 0x400>; 467 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 469 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 470 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 475 interrupt-names = "tei", "ri", "ti", "spi", "sti", 476 "naki", "ali", "tmoi"; 477 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; 478 clock-frequency = <100000>; 479 resets = <&cpg R9A07G054_I2C0_MRST>; 480 power-domains = <&cpg>; 481 status = "disabled"; 482 }; 483 484 i2c1: i2c@10058400 { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 488 reg = <0 0x10058400 0 0x400>; 489 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 491 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 492 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 497 interrupt-names = "tei", "ri", "ti", "spi", "sti", 498 "naki", "ali", "tmoi"; 499 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; 500 clock-frequency = <100000>; 501 resets = <&cpg R9A07G054_I2C1_MRST>; 502 power-domains = <&cpg>; 503 status = "disabled"; 504 }; 505 506 i2c2: i2c@10058800 { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 510 reg = <0 0x10058800 0 0x400>; 511 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 513 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 514 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-names = "tei", "ri", "ti", "spi", "sti", 520 "naki", "ali", "tmoi"; 521 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; 522 clock-frequency = <100000>; 523 resets = <&cpg R9A07G054_I2C2_MRST>; 524 power-domains = <&cpg>; 525 status = "disabled"; 526 }; 527 528 i2c3: i2c@10058c00 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 532 reg = <0 0x10058c00 0 0x400>; 533 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 541 interrupt-names = "tei", "ri", "ti", "spi", "sti", 542 "naki", "ali", "tmoi"; 543 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; 544 clock-frequency = <100000>; 545 resets = <&cpg R9A07G054_I2C3_MRST>; 546 power-domains = <&cpg>; 547 status = "disabled"; 548 }; 549 550 adc: adc@10059000 { 551 compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc"; 552 reg = <0 0x10059000 0 0x400>; 553 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 554 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>, 555 <&cpg CPG_MOD R9A07G054_ADC_PCLK>; 556 clock-names = "adclk", "pclk"; 557 resets = <&cpg R9A07G054_ADC_PRESETN>, 558 <&cpg R9A07G054_ADC_ADRST_N>; 559 reset-names = "presetn", "adrst-n"; 560 power-domains = <&cpg>; 561 status = "disabled"; 562 563 #address-cells = <1>; 564 #size-cells = <0>; 565 566 channel@0 { 567 reg = <0>; 568 }; 569 channel@1 { 570 reg = <1>; 571 }; 572 channel@2 { 573 reg = <2>; 574 }; 575 channel@3 { 576 reg = <3>; 577 }; 578 channel@4 { 579 reg = <4>; 580 }; 581 channel@5 { 582 reg = <5>; 583 }; 584 channel@6 { 585 reg = <6>; 586 }; 587 channel@7 { 588 reg = <7>; 589 }; 590 }; 591 592 tsu: thermal@10059400 { 593 compatible = "renesas,r9a07g054-tsu", 594 "renesas,rzg2l-tsu"; 595 reg = <0 0x10059400 0 0x400>; 596 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; 597 resets = <&cpg R9A07G054_TSU_PRESETN>; 598 power-domains = <&cpg>; 599 #thermal-sensor-cells = <1>; 600 }; 601 602 sbc: spi@10060000 { 603 compatible = "renesas,r9a07g054-rpc-if", 604 "renesas,rzg2l-rpc-if"; 605 reg = <0 0x10060000 0 0x10000>, 606 <0 0x20000000 0 0x10000000>, 607 <0 0x10070000 0 0x10000>; 608 reg-names = "regs", "dirmap", "wbuf"; 609 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, 611 <&cpg CPG_MOD R9A07G054_SPI_CLK>; 612 resets = <&cpg R9A07G054_SPI_RST>; 613 power-domains = <&cpg>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 status = "disabled"; 617 }; 618 619 cpg: clock-controller@11010000 { 620 compatible = "renesas,r9a07g054-cpg"; 621 reg = <0 0x11010000 0 0x10000>; 622 clocks = <&extal_clk>; 623 clock-names = "extal"; 624 #clock-cells = <2>; 625 #reset-cells = <1>; 626 #power-domain-cells = <0>; 627 }; 628 629 sysc: system-controller@11020000 { 630 compatible = "renesas,r9a07g054-sysc"; 631 reg = <0 0x11020000 0 0x10000>; 632 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-names = "lpm_int", "ca55stbydone_int", 637 "cm33stbyr_int", "ca55_deny"; 638 status = "disabled"; 639 }; 640 641 pinctrl: pinctrl@11030000 { 642 compatible = "renesas,r9a07g054-pinctrl", 643 "renesas,r9a07g044-pinctrl"; 644 reg = <0 0x11030000 0 0x10000>; 645 gpio-controller; 646 #gpio-cells = <2>; 647 gpio-ranges = <&pinctrl 0 0 392>; 648 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; 649 power-domains = <&cpg>; 650 resets = <&cpg R9A07G054_GPIO_RSTN>, 651 <&cpg R9A07G054_GPIO_PORT_RESETN>, 652 <&cpg R9A07G054_GPIO_SPARE_RESETN>; 653 }; 654 655 dmac: dma-controller@11820000 { 656 compatible = "renesas,r9a07g054-dmac", 657 "renesas,rz-dmac"; 658 reg = <0 0x11820000 0 0x10000>, 659 <0 0x11830000 0 0x10000>; 660 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 661 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 662 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 663 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 664 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 665 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 666 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 667 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 668 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 669 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 670 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 671 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 672 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 673 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 674 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 675 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 676 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 677 interrupt-names = "error", 678 "ch0", "ch1", "ch2", "ch3", 679 "ch4", "ch5", "ch6", "ch7", 680 "ch8", "ch9", "ch10", "ch11", 681 "ch12", "ch13", "ch14", "ch15"; 682 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, 683 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; 684 power-domains = <&cpg>; 685 resets = <&cpg R9A07G054_DMAC_ARESETN>, 686 <&cpg R9A07G054_DMAC_RST_ASYNC>; 687 #dma-cells = <1>; 688 dma-channels = <16>; 689 }; 690 691 gpu: gpu@11840000 { 692 compatible = "renesas,r9a07g054-mali", 693 "arm,mali-bifrost"; 694 reg = <0x0 0x11840000 0x0 0x10000>; 695 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 699 interrupt-names = "job", "mmu", "gpu", "event"; 700 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>, 701 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, 702 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; 703 clock-names = "gpu", "bus", "bus_ace"; 704 power-domains = <&cpg>; 705 resets = <&cpg R9A07G054_GPU_RESETN>, 706 <&cpg R9A07G054_GPU_AXI_RESETN>, 707 <&cpg R9A07G054_GPU_ACE_RESETN>; 708 reset-names = "rst", "axi_rst", "ace_rst"; 709 operating-points-v2 = <&gpu_opp_table>; 710 }; 711 712 gic: interrupt-controller@11900000 { 713 compatible = "arm,gic-v3"; 714 #interrupt-cells = <3>; 715 #address-cells = <0>; 716 interrupt-controller; 717 reg = <0x0 0x11900000 0 0x40000>, 718 <0x0 0x11940000 0 0x60000>; 719 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 720 }; 721 722 sdhi0: mmc@11c00000 { 723 compatible = "renesas,sdhi-r9a07g054", 724 "renesas,rcar-gen3-sdhi"; 725 reg = <0x0 0x11c00000 0 0x10000>; 726 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>, 729 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>, 730 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, 731 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; 732 clock-names = "core", "clkh", "cd", "aclk"; 733 resets = <&cpg R9A07G054_SDHI0_IXRST>; 734 power-domains = <&cpg>; 735 status = "disabled"; 736 }; 737 738 sdhi1: mmc@11c10000 { 739 compatible = "renesas,sdhi-r9a07g054", 740 "renesas,rcar-gen3-sdhi"; 741 reg = <0x0 0x11c10000 0 0x10000>; 742 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>, 745 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>, 746 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, 747 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; 748 clock-names = "core", "clkh", "cd", "aclk"; 749 resets = <&cpg R9A07G054_SDHI1_IXRST>; 750 power-domains = <&cpg>; 751 status = "disabled"; 752 }; 753 754 eth0: ethernet@11c20000 { 755 compatible = "renesas,r9a07g054-gbeth", 756 "renesas,rzg2l-gbeth"; 757 reg = <0 0x11c20000 0 0x10000>; 758 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "mux", "fil", "arp_ns"; 762 phy-mode = "rgmii"; 763 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>, 764 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>, 765 <&cpg CPG_CORE R9A07G054_CLK_HP>; 766 clock-names = "axi", "chi", "refclk"; 767 resets = <&cpg R9A07G054_ETH0_RST_HW_N>; 768 power-domains = <&cpg>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 eth1: ethernet@11c30000 { 775 compatible = "renesas,r9a07g054-gbeth", 776 "renesas,rzg2l-gbeth"; 777 reg = <0 0x11c30000 0 0x10000>; 778 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 781 interrupt-names = "mux", "fil", "arp_ns"; 782 phy-mode = "rgmii"; 783 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>, 784 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>, 785 <&cpg CPG_CORE R9A07G054_CLK_HP>; 786 clock-names = "axi", "chi", "refclk"; 787 resets = <&cpg R9A07G054_ETH1_RST_HW_N>; 788 power-domains = <&cpg>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 phyrst: usbphy-ctrl@11c40000 { 795 compatible = "renesas,r9a07g054-usbphy-ctrl", 796 "renesas,rzg2l-usbphy-ctrl"; 797 reg = <0 0x11c40000 0 0x10000>; 798 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; 799 resets = <&cpg R9A07G054_USB_PRESETN>; 800 power-domains = <&cpg>; 801 #reset-cells = <1>; 802 status = "disabled"; 803 }; 804 805 ohci0: usb@11c50000 { 806 compatible = "generic-ohci"; 807 reg = <0 0x11c50000 0 0x100>; 808 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 810 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 811 resets = <&phyrst 0>, 812 <&cpg R9A07G054_USB_U2H0_HRESETN>; 813 phys = <&usb2_phy0 1>; 814 phy-names = "usb"; 815 power-domains = <&cpg>; 816 status = "disabled"; 817 }; 818 819 ohci1: usb@11c70000 { 820 compatible = "generic-ohci"; 821 reg = <0 0x11c70000 0 0x100>; 822 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 824 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 825 resets = <&phyrst 1>, 826 <&cpg R9A07G054_USB_U2H1_HRESETN>; 827 phys = <&usb2_phy1 1>; 828 phy-names = "usb"; 829 power-domains = <&cpg>; 830 status = "disabled"; 831 }; 832 833 ehci0: usb@11c50100 { 834 compatible = "generic-ehci"; 835 reg = <0 0x11c50100 0 0x100>; 836 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 838 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 839 resets = <&phyrst 0>, 840 <&cpg R9A07G054_USB_U2H0_HRESETN>; 841 phys = <&usb2_phy0 2>; 842 phy-names = "usb"; 843 companion = <&ohci0>; 844 power-domains = <&cpg>; 845 status = "disabled"; 846 }; 847 848 ehci1: usb@11c70100 { 849 compatible = "generic-ehci"; 850 reg = <0 0x11c70100 0 0x100>; 851 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 853 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 854 resets = <&phyrst 1>, 855 <&cpg R9A07G054_USB_U2H1_HRESETN>; 856 phys = <&usb2_phy1 2>; 857 phy-names = "usb"; 858 companion = <&ohci1>; 859 power-domains = <&cpg>; 860 status = "disabled"; 861 }; 862 863 usb2_phy0: usb-phy@11c50200 { 864 compatible = "renesas,usb2-phy-r9a07g054", 865 "renesas,rzg2l-usb2-phy"; 866 reg = <0 0x11c50200 0 0x700>; 867 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 869 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 870 resets = <&phyrst 0>; 871 #phy-cells = <1>; 872 power-domains = <&cpg>; 873 status = "disabled"; 874 }; 875 876 usb2_phy1: usb-phy@11c70200 { 877 compatible = "renesas,usb2-phy-r9a07g054", 878 "renesas,rzg2l-usb2-phy"; 879 reg = <0 0x11c70200 0 0x700>; 880 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 882 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 883 resets = <&phyrst 1>; 884 #phy-cells = <1>; 885 power-domains = <&cpg>; 886 status = "disabled"; 887 }; 888 889 hsusb: usb@11c60000 { 890 compatible = "renesas,usbhs-r9a07g054", 891 "renesas,rza2-usbhs"; 892 reg = <0 0x11c60000 0 0x10000>; 893 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 894 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 898 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>; 899 resets = <&phyrst 0>, 900 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>; 901 renesas,buswait = <7>; 902 phys = <&usb2_phy0 3>; 903 phy-names = "usb"; 904 power-domains = <&cpg>; 905 status = "disabled"; 906 }; 907 908 wdt0: watchdog@12800800 { 909 compatible = "renesas,r9a07g054-wdt", 910 "renesas,rzg2l-wdt"; 911 reg = <0 0x12800800 0 0x400>; 912 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>, 913 <&cpg CPG_MOD R9A07G054_WDT0_CLK>; 914 clock-names = "pclk", "oscclk"; 915 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "wdt", "perrout"; 918 resets = <&cpg R9A07G054_WDT0_PRESETN>; 919 power-domains = <&cpg>; 920 status = "disabled"; 921 }; 922 923 wdt1: watchdog@12800c00 { 924 compatible = "renesas,r9a07g054-wdt", 925 "renesas,rzg2l-wdt"; 926 reg = <0 0x12800C00 0 0x400>; 927 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, 928 <&cpg CPG_MOD R9A07G054_WDT1_CLK>; 929 clock-names = "pclk", "oscclk"; 930 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 932 interrupt-names = "wdt", "perrout"; 933 resets = <&cpg R9A07G054_WDT1_PRESETN>; 934 power-domains = <&cpg>; 935 status = "disabled"; 936 }; 937 938 wdt2: watchdog@12800400 { 939 compatible = "renesas,r9a07g054-wdt", 940 "renesas,rzg2l-wdt"; 941 reg = <0 0x12800400 0 0x400>; 942 clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, 943 <&cpg CPG_MOD R9A07G054_WDT2_CLK>; 944 clock-names = "pclk", "oscclk"; 945 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 947 interrupt-names = "wdt", "perrout"; 948 resets = <&cpg R9A07G054_WDT2_PRESETN>; 949 power-domains = <&cpg>; 950 status = "disabled"; 951 }; 952 953 ostm0: timer@12801000 { 954 compatible = "renesas,r9a07g054-ostm", 955 "renesas,ostm"; 956 reg = <0x0 0x12801000 0x0 0x400>; 957 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 958 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; 959 resets = <&cpg R9A07G054_OSTM0_PRESETZ>; 960 power-domains = <&cpg>; 961 status = "disabled"; 962 }; 963 964 ostm1: timer@12801400 { 965 compatible = "renesas,r9a07g054-ostm", 966 "renesas,ostm"; 967 reg = <0x0 0x12801400 0x0 0x400>; 968 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 969 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; 970 resets = <&cpg R9A07G054_OSTM1_PRESETZ>; 971 power-domains = <&cpg>; 972 status = "disabled"; 973 }; 974 975 ostm2: timer@12801800 { 976 compatible = "renesas,r9a07g054-ostm", 977 "renesas,ostm"; 978 reg = <0x0 0x12801800 0x0 0x400>; 979 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 980 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>; 981 resets = <&cpg R9A07G054_OSTM2_PRESETZ>; 982 power-domains = <&cpg>; 983 status = "disabled"; 984 }; 985 }; 986 987 thermal-zones { 988 cpu-thermal { 989 polling-delay-passive = <250>; 990 polling-delay = <1000>; 991 thermal-sensors = <&tsu 0>; 992 sustainable-power = <717>; 993 994 cooling-maps { 995 map0 { 996 trip = <&target>; 997 cooling-device = <&cpu0 0 2>; 998 contribution = <1024>; 999 }; 1000 }; 1001 1002 trips { 1003 sensor_crit: sensor-crit { 1004 temperature = <125000>; 1005 hysteresis = <1000>; 1006 type = "critical"; 1007 }; 1008 1009 target: trip-point { 1010 temperature = <100000>; 1011 hysteresis = <1000>; 1012 type = "passive"; 1013 }; 1014 }; 1015 }; 1016 }; 1017 1018 timer { 1019 compatible = "arm,armv8-timer"; 1020 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1021 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1022 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1023 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1024 }; 1025}; 1026