1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <net/ip.h> 10 #include <net/tso.h> 11 #include <linux/bpf.h> 12 #include <linux/bpf_trace.h> 13 14 #include "otx2_reg.h" 15 #include "otx2_common.h" 16 #include "otx2_struct.h" 17 #include "otx2_txrx.h" 18 #include "otx2_ptp.h" 19 #include "cn10k.h" 20 21 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) 22 #define PTP_PORT 0x13F 23 /* PTPv2 header Original Timestamp starts at byte offset 34 and 24 * contains 6 byte seconds field and 4 byte nano seconds field. 25 */ 26 #define PTP_SYNC_SEC_OFFSET 34 27 28 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf, 29 struct bpf_prog *prog, 30 struct nix_cqe_rx_s *cqe, 31 struct otx2_cq_queue *cq); 32 33 static int otx2_nix_cq_op_status(struct otx2_nic *pfvf, 34 struct otx2_cq_queue *cq) 35 { 36 u64 incr = (u64)(cq->cq_idx) << 32; 37 u64 status; 38 39 status = otx2_atomic64_fetch_add(incr, pfvf->cq_op_addr); 40 41 if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) || 42 status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) { 43 dev_err(pfvf->dev, "CQ stopped due to error"); 44 return -EINVAL; 45 } 46 47 cq->cq_tail = status & 0xFFFFF; 48 cq->cq_head = (status >> 20) & 0xFFFFF; 49 if (cq->cq_tail < cq->cq_head) 50 cq->pend_cqe = (cq->cqe_cnt - cq->cq_head) + 51 cq->cq_tail; 52 else 53 cq->pend_cqe = cq->cq_tail - cq->cq_head; 54 55 return 0; 56 } 57 58 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq) 59 { 60 struct nix_cqe_hdr_s *cqe_hdr; 61 62 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head); 63 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID) 64 return NULL; 65 66 cq->cq_head++; 67 cq->cq_head &= (cq->cqe_cnt - 1); 68 69 return cqe_hdr; 70 } 71 72 static unsigned int frag_num(unsigned int i) 73 { 74 #ifdef __BIG_ENDIAN 75 return (i & ~3) + 3 - (i & 3); 76 #else 77 return i; 78 #endif 79 } 80 81 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 82 struct sk_buff *skb, int seg, int *len) 83 { 84 const skb_frag_t *frag; 85 struct page *page; 86 int offset; 87 88 /* First segment is always skb->data */ 89 if (!seg) { 90 page = virt_to_page(skb->data); 91 offset = offset_in_page(skb->data); 92 *len = skb_headlen(skb); 93 } else { 94 frag = &skb_shinfo(skb)->frags[seg - 1]; 95 page = skb_frag_page(frag); 96 offset = skb_frag_off(frag); 97 *len = skb_frag_size(frag); 98 } 99 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE); 100 } 101 102 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg) 103 { 104 int seg; 105 106 for (seg = 0; seg < sg->num_segs; seg++) { 107 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg], 108 sg->size[seg], DMA_TO_DEVICE); 109 } 110 sg->num_segs = 0; 111 } 112 113 static void otx2_xdp_snd_pkt_handler(struct otx2_nic *pfvf, 114 struct otx2_snd_queue *sq, 115 struct nix_cqe_tx_s *cqe) 116 { 117 struct nix_send_comp_s *snd_comp = &cqe->comp; 118 struct sg_list *sg; 119 struct page *page; 120 u64 pa; 121 122 sg = &sq->sg[snd_comp->sqe_id]; 123 124 pa = otx2_iova_to_phys(pfvf->iommu_domain, sg->dma_addr[0]); 125 otx2_dma_unmap_page(pfvf, sg->dma_addr[0], 126 sg->size[0], DMA_TO_DEVICE); 127 page = virt_to_page(phys_to_virt(pa)); 128 put_page(page); 129 } 130 131 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, 132 struct otx2_cq_queue *cq, 133 struct otx2_snd_queue *sq, 134 struct nix_cqe_tx_s *cqe, 135 int budget, int *tx_pkts, int *tx_bytes) 136 { 137 struct nix_send_comp_s *snd_comp = &cqe->comp; 138 struct skb_shared_hwtstamps ts; 139 struct sk_buff *skb = NULL; 140 u64 timestamp, tsns; 141 struct sg_list *sg; 142 int err; 143 144 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf)) 145 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n", 146 pfvf->netdev->name, cq->cint_idx, 147 snd_comp->status); 148 149 sg = &sq->sg[snd_comp->sqe_id]; 150 skb = (struct sk_buff *)sg->skb; 151 if (unlikely(!skb)) 152 return; 153 154 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { 155 timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id]; 156 if (timestamp != 1) { 157 timestamp = pfvf->ptp->convert_tx_ptp_tstmp(timestamp); 158 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); 159 if (!err) { 160 memset(&ts, 0, sizeof(ts)); 161 ts.hwtstamp = ns_to_ktime(tsns); 162 skb_tstamp_tx(skb, &ts); 163 } 164 } 165 } 166 167 *tx_bytes += skb->len; 168 (*tx_pkts)++; 169 otx2_dma_unmap_skb_frags(pfvf, sg); 170 napi_consume_skb(skb, budget); 171 sg->skb = (u64)NULL; 172 } 173 174 static void otx2_set_rxtstamp(struct otx2_nic *pfvf, 175 struct sk_buff *skb, void *data) 176 { 177 u64 timestamp, tsns; 178 int err; 179 180 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)) 181 return; 182 183 timestamp = pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data); 184 /* The first 8 bytes is the timestamp */ 185 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); 186 if (err) 187 return; 188 189 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns); 190 } 191 192 static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb, 193 u64 iova, int len, struct nix_rx_parse_s *parse, 194 int qidx) 195 { 196 struct page *page; 197 int off = 0; 198 void *va; 199 200 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova)); 201 202 if (likely(!skb_shinfo(skb)->nr_frags)) { 203 /* Check if data starts at some nonzero offset 204 * from the start of the buffer. For now the 205 * only possible offset is 8 bytes in the case 206 * where packet is prepended by a timestamp. 207 */ 208 if (parse->laptr) { 209 otx2_set_rxtstamp(pfvf, skb, va); 210 off = OTX2_HW_TIMESTAMP_LEN; 211 } 212 } 213 214 page = virt_to_page(va); 215 if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) { 216 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 217 va - page_address(page) + off, 218 len - off, pfvf->rbsize); 219 220 otx2_dma_unmap_page(pfvf, iova - OTX2_HEAD_ROOM, 221 pfvf->rbsize, DMA_FROM_DEVICE); 222 return true; 223 } 224 225 /* If more than MAX_SKB_FRAGS fragments are received then 226 * give back those buffer pointers to hardware for reuse. 227 */ 228 pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL); 229 230 return false; 231 } 232 233 static void otx2_set_rxhash(struct otx2_nic *pfvf, 234 struct nix_cqe_rx_s *cqe, struct sk_buff *skb) 235 { 236 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE; 237 struct otx2_rss_info *rss; 238 u32 hash = 0; 239 240 if (!(pfvf->netdev->features & NETIF_F_RXHASH)) 241 return; 242 243 rss = &pfvf->hw.rss_info; 244 if (rss->flowkey_cfg) { 245 if (rss->flowkey_cfg & 246 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6)) 247 hash_type = PKT_HASH_TYPE_L4; 248 else 249 hash_type = PKT_HASH_TYPE_L3; 250 hash = cqe->hdr.flow_tag; 251 } 252 skb_set_hash(skb, hash, hash_type); 253 } 254 255 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe, 256 int qidx) 257 { 258 struct nix_rx_sg_s *sg = &cqe->sg; 259 void *end, *start; 260 u64 *seg_addr; 261 int seg; 262 263 start = (void *)sg; 264 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 265 while (start < end) { 266 sg = (struct nix_rx_sg_s *)start; 267 seg_addr = &sg->seg_addr; 268 for (seg = 0; seg < sg->segs; seg++, seg_addr++) 269 pfvf->hw_ops->aura_freeptr(pfvf, qidx, 270 *seg_addr & ~0x07ULL); 271 start += sizeof(*sg); 272 } 273 } 274 275 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf, 276 struct nix_cqe_rx_s *cqe, int qidx) 277 { 278 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats; 279 struct nix_rx_parse_s *parse = &cqe->parse; 280 281 if (netif_msg_rx_err(pfvf)) 282 netdev_err(pfvf->netdev, 283 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n", 284 qidx, parse->errlev, parse->errcode); 285 286 if (parse->errlev == NPC_ERRLVL_RE) { 287 switch (parse->errcode) { 288 case ERRCODE_FCS: 289 case ERRCODE_FCS_RCV: 290 atomic_inc(&stats->rx_fcs_errs); 291 break; 292 case ERRCODE_UNDERSIZE: 293 atomic_inc(&stats->rx_undersize_errs); 294 break; 295 case ERRCODE_OVERSIZE: 296 atomic_inc(&stats->rx_oversize_errs); 297 break; 298 case ERRCODE_OL2_LEN_MISMATCH: 299 atomic_inc(&stats->rx_len_errs); 300 break; 301 default: 302 atomic_inc(&stats->rx_other_errs); 303 break; 304 } 305 } else if (parse->errlev == NPC_ERRLVL_NIX) { 306 switch (parse->errcode) { 307 case ERRCODE_OL3_LEN: 308 case ERRCODE_OL4_LEN: 309 case ERRCODE_IL3_LEN: 310 case ERRCODE_IL4_LEN: 311 atomic_inc(&stats->rx_len_errs); 312 break; 313 case ERRCODE_OL4_CSUM: 314 case ERRCODE_IL4_CSUM: 315 atomic_inc(&stats->rx_csum_errs); 316 break; 317 default: 318 atomic_inc(&stats->rx_other_errs); 319 break; 320 } 321 } else { 322 atomic_inc(&stats->rx_other_errs); 323 /* For now ignore all the NPC parser errors and 324 * pass the packets to stack. 325 */ 326 return false; 327 } 328 329 /* If RXALL is enabled pass on packets to stack. */ 330 if (pfvf->netdev->features & NETIF_F_RXALL) 331 return false; 332 333 /* Free buffer back to pool */ 334 if (cqe->sg.segs) 335 otx2_free_rcv_seg(pfvf, cqe, qidx); 336 return true; 337 } 338 339 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf, 340 struct napi_struct *napi, 341 struct otx2_cq_queue *cq, 342 struct nix_cqe_rx_s *cqe) 343 { 344 struct nix_rx_parse_s *parse = &cqe->parse; 345 struct nix_rx_sg_s *sg = &cqe->sg; 346 struct sk_buff *skb = NULL; 347 void *end, *start; 348 u64 *seg_addr; 349 u16 *seg_size; 350 int seg; 351 352 if (unlikely(parse->errlev || parse->errcode)) { 353 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx)) 354 return; 355 } 356 357 if (pfvf->xdp_prog) 358 if (otx2_xdp_rcv_pkt_handler(pfvf, pfvf->xdp_prog, cqe, cq)) 359 return; 360 361 skb = napi_get_frags(napi); 362 if (unlikely(!skb)) 363 return; 364 365 start = (void *)sg; 366 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 367 while (start < end) { 368 sg = (struct nix_rx_sg_s *)start; 369 seg_addr = &sg->seg_addr; 370 seg_size = (void *)sg; 371 for (seg = 0; seg < sg->segs; seg++, seg_addr++) { 372 if (otx2_skb_add_frag(pfvf, skb, *seg_addr, 373 seg_size[seg], parse, cq->cq_idx)) 374 cq->pool_ptrs++; 375 } 376 start += sizeof(*sg); 377 } 378 otx2_set_rxhash(pfvf, cqe, skb); 379 380 skb_record_rx_queue(skb, cq->cq_idx); 381 if (pfvf->netdev->features & NETIF_F_RXCSUM) 382 skb->ip_summed = CHECKSUM_UNNECESSARY; 383 384 napi_gro_frags(napi); 385 } 386 387 static int otx2_rx_napi_handler(struct otx2_nic *pfvf, 388 struct napi_struct *napi, 389 struct otx2_cq_queue *cq, int budget) 390 { 391 struct nix_cqe_rx_s *cqe; 392 int processed_cqe = 0; 393 394 if (cq->pend_cqe >= budget) 395 goto process_cqe; 396 397 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 398 return 0; 399 400 process_cqe: 401 while (likely(processed_cqe < budget) && cq->pend_cqe) { 402 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head); 403 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID || 404 !cqe->sg.seg_addr) { 405 if (!processed_cqe) 406 return 0; 407 break; 408 } 409 cq->cq_head++; 410 cq->cq_head &= (cq->cqe_cnt - 1); 411 412 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe); 413 414 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 415 cqe->sg.seg_addr = 0x00; 416 processed_cqe++; 417 cq->pend_cqe--; 418 } 419 420 /* Free CQEs to HW */ 421 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 422 ((u64)cq->cq_idx << 32) | processed_cqe); 423 424 return processed_cqe; 425 } 426 427 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq) 428 { 429 struct otx2_nic *pfvf = dev; 430 dma_addr_t bufptr; 431 432 while (cq->pool_ptrs) { 433 if (otx2_alloc_buffer(pfvf, cq, &bufptr)) 434 break; 435 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM); 436 cq->pool_ptrs--; 437 } 438 } 439 440 static int otx2_tx_napi_handler(struct otx2_nic *pfvf, 441 struct otx2_cq_queue *cq, int budget) 442 { 443 int tx_pkts = 0, tx_bytes = 0, qidx; 444 struct nix_cqe_tx_s *cqe; 445 int processed_cqe = 0; 446 447 if (cq->pend_cqe >= budget) 448 goto process_cqe; 449 450 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 451 return 0; 452 453 process_cqe: 454 while (likely(processed_cqe < budget) && cq->pend_cqe) { 455 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 456 if (unlikely(!cqe)) { 457 if (!processed_cqe) 458 return 0; 459 break; 460 } 461 if (cq->cq_type == CQ_XDP) { 462 qidx = cq->cq_idx - pfvf->hw.rx_queues; 463 otx2_xdp_snd_pkt_handler(pfvf, &pfvf->qset.sq[qidx], 464 cqe); 465 } else { 466 otx2_snd_pkt_handler(pfvf, cq, 467 &pfvf->qset.sq[cq->cint_idx], 468 cqe, budget, &tx_pkts, &tx_bytes); 469 } 470 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 471 processed_cqe++; 472 cq->pend_cqe--; 473 } 474 475 /* Free CQEs to HW */ 476 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 477 ((u64)cq->cq_idx << 32) | processed_cqe); 478 479 if (likely(tx_pkts)) { 480 struct netdev_queue *txq; 481 482 txq = netdev_get_tx_queue(pfvf->netdev, cq->cint_idx); 483 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 484 /* Check if queue was stopped earlier due to ring full */ 485 smp_mb(); 486 if (netif_tx_queue_stopped(txq) && 487 netif_carrier_ok(pfvf->netdev)) 488 netif_tx_wake_queue(txq); 489 } 490 return 0; 491 } 492 493 static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_poll *cq_poll) 494 { 495 struct dim_sample dim_sample; 496 u64 rx_frames, rx_bytes; 497 498 rx_frames = OTX2_GET_RX_STATS(RX_BCAST) + OTX2_GET_RX_STATS(RX_MCAST) + 499 OTX2_GET_RX_STATS(RX_UCAST); 500 rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 501 dim_update_sample(pfvf->napi_events, rx_frames, rx_bytes, &dim_sample); 502 net_dim(&cq_poll->dim, dim_sample); 503 } 504 505 int otx2_napi_handler(struct napi_struct *napi, int budget) 506 { 507 struct otx2_cq_queue *rx_cq = NULL; 508 struct otx2_cq_poll *cq_poll; 509 int workdone = 0, cq_idx, i; 510 struct otx2_cq_queue *cq; 511 struct otx2_qset *qset; 512 struct otx2_nic *pfvf; 513 514 cq_poll = container_of(napi, struct otx2_cq_poll, napi); 515 pfvf = (struct otx2_nic *)cq_poll->dev; 516 qset = &pfvf->qset; 517 518 for (i = 0; i < CQS_PER_CINT; i++) { 519 cq_idx = cq_poll->cq_ids[i]; 520 if (unlikely(cq_idx == CINT_INVALID_CQ)) 521 continue; 522 cq = &qset->cq[cq_idx]; 523 if (cq->cq_type == CQ_RX) { 524 rx_cq = cq; 525 workdone += otx2_rx_napi_handler(pfvf, napi, 526 cq, budget); 527 } else { 528 workdone += otx2_tx_napi_handler(pfvf, cq, budget); 529 } 530 } 531 532 if (rx_cq && rx_cq->pool_ptrs) 533 pfvf->hw_ops->refill_pool_ptrs(pfvf, rx_cq); 534 /* Clear the IRQ */ 535 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0)); 536 537 if (workdone < budget && napi_complete_done(napi, workdone)) { 538 /* If interface is going down, don't re-enable IRQ */ 539 if (pfvf->flags & OTX2_FLAG_INTF_DOWN) 540 return workdone; 541 542 /* Check for adaptive interrupt coalesce */ 543 if (workdone != 0 && 544 ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) == 545 OTX2_FLAG_ADPTV_INT_COAL_ENABLED)) { 546 /* Adjust irq coalese using net_dim */ 547 otx2_adjust_adaptive_coalese(pfvf, cq_poll); 548 /* Update irq coalescing */ 549 for (i = 0; i < pfvf->hw.cint_cnt; i++) 550 otx2_config_irq_coalescing(pfvf, i); 551 } 552 553 /* Re-enable interrupts */ 554 otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx), 555 BIT_ULL(0)); 556 } 557 return workdone; 558 } 559 560 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, 561 int size, int qidx) 562 { 563 u64 status; 564 565 /* Packet data stores should finish before SQE is flushed to HW */ 566 dma_wmb(); 567 568 do { 569 memcpy(sq->lmt_addr, sq->sqe_base, size); 570 status = otx2_lmt_flush(sq->io_addr); 571 } while (status == 0); 572 573 sq->head++; 574 sq->head &= (sq->sqe_cnt - 1); 575 } 576 577 #define MAX_SEGS_PER_SG 3 578 /* Add SQE scatter/gather subdescriptor structure */ 579 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 580 struct sk_buff *skb, int num_segs, int *offset) 581 { 582 struct nix_sqe_sg_s *sg = NULL; 583 u64 dma_addr, *iova = NULL; 584 u16 *sg_lens = NULL; 585 int seg, len; 586 587 sq->sg[sq->head].num_segs = 0; 588 589 for (seg = 0; seg < num_segs; seg++) { 590 if ((seg % MAX_SEGS_PER_SG) == 0) { 591 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 592 sg->ld_type = NIX_SEND_LDTYPE_LDD; 593 sg->subdc = NIX_SUBDC_SG; 594 sg->segs = 0; 595 sg_lens = (void *)sg; 596 iova = (void *)sg + sizeof(*sg); 597 /* Next subdc always starts at a 16byte boundary. 598 * So if sg->segs is whether 2 or 3, offset += 16bytes. 599 */ 600 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 601 *offset += sizeof(*sg) + (3 * sizeof(u64)); 602 else 603 *offset += sizeof(*sg) + sizeof(u64); 604 } 605 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 606 if (dma_mapping_error(pfvf->dev, dma_addr)) 607 return false; 608 609 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len; 610 sg->segs++; 611 *iova++ = dma_addr; 612 613 /* Save DMA mapping info for later unmapping */ 614 sq->sg[sq->head].dma_addr[seg] = dma_addr; 615 sq->sg[sq->head].size[seg] = len; 616 sq->sg[sq->head].num_segs++; 617 } 618 619 sq->sg[sq->head].skb = (u64)skb; 620 return true; 621 } 622 623 /* Add SQE extended header subdescriptor */ 624 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 625 struct sk_buff *skb, int *offset) 626 { 627 struct nix_sqe_ext_s *ext; 628 629 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset); 630 ext->subdc = NIX_SUBDC_EXT; 631 if (skb_shinfo(skb)->gso_size) { 632 ext->lso = 1; 633 ext->lso_sb = skb_tcp_all_headers(skb); 634 ext->lso_mps = skb_shinfo(skb)->gso_size; 635 636 /* Only TSOv4 and TSOv6 GSO offloads are supported */ 637 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { 638 ext->lso_format = pfvf->hw.lso_tsov4_idx; 639 640 /* HW adds payload size to 'ip_hdr->tot_len' while 641 * sending TSO segment, hence set payload length 642 * in IP header of the packet to just header length. 643 */ 644 ip_hdr(skb)->tot_len = 645 htons(ext->lso_sb - skb_network_offset(skb)); 646 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { 647 ext->lso_format = pfvf->hw.lso_tsov6_idx; 648 649 ipv6_hdr(skb)->payload_len = 650 htons(ext->lso_sb - skb_network_offset(skb)); 651 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 652 __be16 l3_proto = vlan_get_protocol(skb); 653 struct udphdr *udph = udp_hdr(skb); 654 u16 iplen; 655 656 ext->lso_sb = skb_transport_offset(skb) + 657 sizeof(struct udphdr); 658 659 /* HW adds payload size to length fields in IP and 660 * UDP headers while segmentation, hence adjust the 661 * lengths to just header sizes. 662 */ 663 iplen = htons(ext->lso_sb - skb_network_offset(skb)); 664 if (l3_proto == htons(ETH_P_IP)) { 665 ip_hdr(skb)->tot_len = iplen; 666 ext->lso_format = pfvf->hw.lso_udpv4_idx; 667 } else { 668 ipv6_hdr(skb)->payload_len = iplen; 669 ext->lso_format = pfvf->hw.lso_udpv6_idx; 670 } 671 672 udph->len = htons(sizeof(struct udphdr)); 673 } 674 } else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 675 ext->tstmp = 1; 676 } 677 678 #define OTX2_VLAN_PTR_OFFSET (ETH_HLEN - ETH_TLEN) 679 if (skb_vlan_tag_present(skb)) { 680 if (skb->vlan_proto == htons(ETH_P_8021Q)) { 681 ext->vlan1_ins_ena = 1; 682 ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET; 683 ext->vlan1_ins_tci = skb_vlan_tag_get(skb); 684 } else if (skb->vlan_proto == htons(ETH_P_8021AD)) { 685 ext->vlan0_ins_ena = 1; 686 ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET; 687 ext->vlan0_ins_tci = skb_vlan_tag_get(skb); 688 } 689 } 690 691 *offset += sizeof(*ext); 692 } 693 694 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset, 695 int alg, u64 iova, int ptp_offset, 696 u64 base_ns, int udp_csum) 697 { 698 struct nix_sqe_mem_s *mem; 699 700 mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset); 701 mem->subdc = NIX_SUBDC_MEM; 702 mem->alg = alg; 703 mem->wmem = 1; /* wait for the memory operation */ 704 mem->addr = iova; 705 706 if (ptp_offset) { 707 mem->start_offset = ptp_offset; 708 mem->udp_csum_crt = udp_csum; 709 mem->base_ns = base_ns; 710 mem->step_type = 1; 711 } 712 713 *offset += sizeof(*mem); 714 } 715 716 /* Add SQE header subdescriptor structure */ 717 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 718 struct nix_sqe_hdr_s *sqe_hdr, 719 struct sk_buff *skb, u16 qidx) 720 { 721 int proto = 0; 722 723 /* Check if SQE was framed before, if yes then no need to 724 * set these constants again and again. 725 */ 726 if (!sqe_hdr->total) { 727 /* Don't free Tx buffers to Aura */ 728 sqe_hdr->df = 1; 729 sqe_hdr->aura = sq->aura_id; 730 /* Post a CQE Tx after pkt transmission */ 731 sqe_hdr->pnc = 1; 732 sqe_hdr->sq = qidx; 733 } 734 sqe_hdr->total = skb->len; 735 /* Set SQE identifier which will be used later for freeing SKB */ 736 sqe_hdr->sqe_id = sq->head; 737 738 /* Offload TCP/UDP checksum to HW */ 739 if (skb->ip_summed == CHECKSUM_PARTIAL) { 740 sqe_hdr->ol3ptr = skb_network_offset(skb); 741 sqe_hdr->ol4ptr = skb_transport_offset(skb); 742 /* get vlan protocol Ethertype */ 743 if (eth_type_vlan(skb->protocol)) 744 skb->protocol = vlan_get_protocol(skb); 745 746 if (skb->protocol == htons(ETH_P_IP)) { 747 proto = ip_hdr(skb)->protocol; 748 /* In case of TSO, HW needs this to be explicitly set. 749 * So set this always, instead of adding a check. 750 */ 751 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM; 752 } else if (skb->protocol == htons(ETH_P_IPV6)) { 753 proto = ipv6_hdr(skb)->nexthdr; 754 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6; 755 } 756 757 if (proto == IPPROTO_TCP) 758 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM; 759 else if (proto == IPPROTO_UDP) 760 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM; 761 } 762 } 763 764 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf, 765 struct otx2_snd_queue *sq, 766 struct sk_buff *skb, int sqe, int hdr_len) 767 { 768 int num_segs = skb_shinfo(skb)->nr_frags + 1; 769 struct sg_list *sg = &sq->sg[sqe]; 770 u64 dma_addr; 771 int seg, len; 772 773 sg->num_segs = 0; 774 775 /* Get payload length at skb->data */ 776 len = skb_headlen(skb) - hdr_len; 777 778 for (seg = 0; seg < num_segs; seg++) { 779 /* Skip skb->data, if there is no payload */ 780 if (!seg && !len) 781 continue; 782 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 783 if (dma_mapping_error(pfvf->dev, dma_addr)) 784 goto unmap; 785 786 /* Save DMA mapping info for later unmapping */ 787 sg->dma_addr[sg->num_segs] = dma_addr; 788 sg->size[sg->num_segs] = len; 789 sg->num_segs++; 790 } 791 return 0; 792 unmap: 793 otx2_dma_unmap_skb_frags(pfvf, sg); 794 return -EINVAL; 795 } 796 797 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq, 798 struct sk_buff *skb, int seg, 799 u64 seg_addr, int hdr_len, int sqe) 800 { 801 struct sg_list *sg = &sq->sg[sqe]; 802 const skb_frag_t *frag; 803 int offset; 804 805 if (seg < 0) 806 return sg->dma_addr[0] + (seg_addr - (u64)skb->data); 807 808 frag = &skb_shinfo(skb)->frags[seg]; 809 offset = seg_addr - (u64)skb_frag_address(frag); 810 if (skb_headlen(skb) - hdr_len) 811 seg++; 812 return sg->dma_addr[seg] + offset; 813 } 814 815 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq, 816 struct sg_list *list, int *offset) 817 { 818 struct nix_sqe_sg_s *sg = NULL; 819 u16 *sg_lens = NULL; 820 u64 *iova = NULL; 821 int seg; 822 823 /* Add SG descriptors with buffer addresses */ 824 for (seg = 0; seg < list->num_segs; seg++) { 825 if ((seg % MAX_SEGS_PER_SG) == 0) { 826 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 827 sg->ld_type = NIX_SEND_LDTYPE_LDD; 828 sg->subdc = NIX_SUBDC_SG; 829 sg->segs = 0; 830 sg_lens = (void *)sg; 831 iova = (void *)sg + sizeof(*sg); 832 /* Next subdc always starts at a 16byte boundary. 833 * So if sg->segs is whether 2 or 3, offset += 16bytes. 834 */ 835 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 836 *offset += sizeof(*sg) + (3 * sizeof(u64)); 837 else 838 *offset += sizeof(*sg) + sizeof(u64); 839 } 840 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg]; 841 *iova++ = list->dma_addr[seg]; 842 sg->segs++; 843 } 844 } 845 846 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 847 struct sk_buff *skb, u16 qidx) 848 { 849 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx); 850 int hdr_len, tcp_data, seg_len, pkt_len, offset; 851 struct nix_sqe_hdr_s *sqe_hdr; 852 int first_sqe = sq->head; 853 struct sg_list list; 854 struct tso_t tso; 855 856 hdr_len = tso_start(skb, &tso); 857 858 /* Map SKB's fragments to DMA. 859 * It's done here to avoid mapping for every TSO segment's packet. 860 */ 861 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) { 862 dev_kfree_skb_any(skb); 863 return; 864 } 865 866 netdev_tx_sent_queue(txq, skb->len); 867 868 tcp_data = skb->len - hdr_len; 869 while (tcp_data > 0) { 870 char *hdr; 871 872 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data); 873 tcp_data -= seg_len; 874 875 /* Set SQE's SEND_HDR */ 876 memset(sq->sqe_base, 0, sq->sqe_size); 877 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 878 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 879 offset = sizeof(*sqe_hdr); 880 881 /* Add TSO segment's pkt header */ 882 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE); 883 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0); 884 list.dma_addr[0] = 885 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE); 886 list.size[0] = hdr_len; 887 list.num_segs = 1; 888 889 /* Add TSO segment's payload data fragments */ 890 pkt_len = hdr_len; 891 while (seg_len > 0) { 892 int size; 893 894 size = min_t(int, tso.size, seg_len); 895 896 list.size[list.num_segs] = size; 897 list.dma_addr[list.num_segs] = 898 otx2_tso_frag_dma_addr(sq, skb, 899 tso.next_frag_idx - 1, 900 (u64)tso.data, hdr_len, 901 first_sqe); 902 list.num_segs++; 903 pkt_len += size; 904 seg_len -= size; 905 tso_build_data(skb, &tso, size); 906 } 907 sqe_hdr->total = pkt_len; 908 otx2_sqe_tso_add_sg(sq, &list, &offset); 909 910 /* DMA mappings and skb needs to be freed only after last 911 * TSO segment is transmitted out. So set 'PNC' only for 912 * last segment. Also point last segment's sqe_id to first 913 * segment's SQE index where skb address and DMA mappings 914 * are saved. 915 */ 916 if (!tcp_data) { 917 sqe_hdr->pnc = 1; 918 sqe_hdr->sqe_id = first_sqe; 919 sq->sg[first_sqe].skb = (u64)skb; 920 } else { 921 sqe_hdr->pnc = 0; 922 } 923 924 sqe_hdr->sizem1 = (offset / 16) - 1; 925 926 /* Flush SQE to HW */ 927 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 928 } 929 } 930 931 static bool is_hw_tso_supported(struct otx2_nic *pfvf, 932 struct sk_buff *skb) 933 { 934 int payload_len, last_seg_size; 935 936 if (test_bit(HW_TSO, &pfvf->hw.cap_flag)) 937 return true; 938 939 /* On 96xx A0, HW TSO not supported */ 940 if (!is_96xx_B0(pfvf->pdev)) 941 return false; 942 943 /* HW has an issue due to which when the payload of the last LSO 944 * segment is shorter than 16 bytes, some header fields may not 945 * be correctly modified, hence don't offload such TSO segments. 946 */ 947 948 payload_len = skb->len - skb_tcp_all_headers(skb); 949 last_seg_size = payload_len % skb_shinfo(skb)->gso_size; 950 if (last_seg_size && last_seg_size < 16) 951 return false; 952 953 return true; 954 } 955 956 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb) 957 { 958 if (!skb_shinfo(skb)->gso_size) 959 return 1; 960 961 /* HW TSO */ 962 if (is_hw_tso_supported(pfvf, skb)) 963 return 1; 964 965 /* SW TSO */ 966 return skb_shinfo(skb)->gso_segs; 967 } 968 969 static bool otx2_validate_network_transport(struct sk_buff *skb) 970 { 971 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) || 972 (ipv6_hdr(skb)->nexthdr == IPPROTO_UDP)) { 973 struct udphdr *udph = udp_hdr(skb); 974 975 if (udph->source == htons(PTP_PORT) && 976 udph->dest == htons(PTP_PORT)) 977 return true; 978 } 979 980 return false; 981 } 982 983 static bool otx2_ptp_is_sync(struct sk_buff *skb, int *offset, int *udp_csum) 984 { 985 struct ethhdr *eth = (struct ethhdr *)(skb->data); 986 u16 nix_offload_hlen = 0, inner_vhlen = 0; 987 u8 *data = skb->data, *msgtype; 988 __be16 proto = eth->h_proto; 989 int network_depth = 0; 990 991 /* NIX is programmed to offload outer VLAN header 992 * in case of single vlan protocol field holds Network header ETH_IP/V6 993 * in case of stacked vlan protocol field holds Inner vlan (8100) 994 */ 995 if (skb->dev->features & NETIF_F_HW_VLAN_CTAG_TX && 996 skb->dev->features & NETIF_F_HW_VLAN_STAG_TX) { 997 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 998 /* Get vlan protocol */ 999 proto = __vlan_get_protocol(skb, eth->h_proto, NULL); 1000 /* SKB APIs like skb_transport_offset does not include 1001 * offloaded vlan header length. Need to explicitly add 1002 * the length 1003 */ 1004 nix_offload_hlen = VLAN_HLEN; 1005 inner_vhlen = VLAN_HLEN; 1006 } else if (skb->vlan_proto == htons(ETH_P_8021Q)) { 1007 nix_offload_hlen = VLAN_HLEN; 1008 } 1009 } else if (eth_type_vlan(eth->h_proto)) { 1010 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 1011 } 1012 1013 switch (ntohs(proto)) { 1014 case ETH_P_1588: 1015 if (network_depth) 1016 *offset = network_depth; 1017 else 1018 *offset = ETH_HLEN + nix_offload_hlen + 1019 inner_vhlen; 1020 break; 1021 case ETH_P_IP: 1022 case ETH_P_IPV6: 1023 if (!otx2_validate_network_transport(skb)) 1024 return false; 1025 1026 *udp_csum = 1; 1027 *offset = nix_offload_hlen + skb_transport_offset(skb) + 1028 sizeof(struct udphdr); 1029 } 1030 1031 msgtype = data + *offset; 1032 1033 /* Check PTP messageId is SYNC or not */ 1034 return (*msgtype & 0xf) == 0; 1035 } 1036 1037 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb, 1038 struct otx2_snd_queue *sq, int *offset) 1039 { 1040 struct ptpv2_tstamp *origin_tstamp; 1041 int ptp_offset = 0, udp_csum = 0; 1042 struct timespec64 ts; 1043 u64 iova; 1044 1045 if (unlikely(!skb_shinfo(skb)->gso_size && 1046 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) { 1047 if (unlikely(pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC)) { 1048 if (otx2_ptp_is_sync(skb, &ptp_offset, &udp_csum)) { 1049 origin_tstamp = (struct ptpv2_tstamp *) 1050 ((u8 *)skb->data + ptp_offset + 1051 PTP_SYNC_SEC_OFFSET); 1052 ts = ns_to_timespec64(pfvf->ptp->tstamp); 1053 origin_tstamp->seconds_msb = htons((ts.tv_sec >> 32) & 0xffff); 1054 origin_tstamp->seconds_lsb = htonl(ts.tv_sec & 0xffffffff); 1055 origin_tstamp->nanoseconds = htonl(ts.tv_nsec); 1056 /* Point to correction field in PTP packet */ 1057 ptp_offset += 8; 1058 } 1059 } else { 1060 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1061 } 1062 iova = sq->timestamps->iova + (sq->head * sizeof(u64)); 1063 otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova, 1064 ptp_offset, pfvf->ptp->base_ns, udp_csum); 1065 } else { 1066 skb_tx_timestamp(skb); 1067 } 1068 } 1069 1070 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 1071 struct sk_buff *skb, u16 qidx) 1072 { 1073 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx); 1074 struct otx2_nic *pfvf = netdev_priv(netdev); 1075 int offset, num_segs, free_sqe; 1076 struct nix_sqe_hdr_s *sqe_hdr; 1077 1078 /* Check if there is room for new SQE. 1079 * 'Num of SQBs freed to SQ's pool - SQ's Aura count' 1080 * will give free SQE count. 1081 */ 1082 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 1083 1084 if (free_sqe < sq->sqe_thresh || 1085 free_sqe < otx2_get_sqe_count(pfvf, skb)) 1086 return false; 1087 1088 num_segs = skb_shinfo(skb)->nr_frags + 1; 1089 1090 /* If SKB doesn't fit in a single SQE, linearize it. 1091 * TODO: Consider adding JUMP descriptor instead. 1092 */ 1093 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) { 1094 if (__skb_linearize(skb)) { 1095 dev_kfree_skb_any(skb); 1096 return true; 1097 } 1098 num_segs = skb_shinfo(skb)->nr_frags + 1; 1099 } 1100 1101 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) { 1102 /* Insert vlan tag before giving pkt to tso */ 1103 if (skb_vlan_tag_present(skb)) 1104 skb = __vlan_hwaccel_push_inside(skb); 1105 otx2_sq_append_tso(pfvf, sq, skb, qidx); 1106 return true; 1107 } 1108 1109 /* Set SQE's SEND_HDR. 1110 * Do not clear the first 64bit as it contains constant info. 1111 */ 1112 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 1113 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 1114 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 1115 offset = sizeof(*sqe_hdr); 1116 1117 /* Add extended header if needed */ 1118 otx2_sqe_add_ext(pfvf, sq, skb, &offset); 1119 1120 /* Add SG subdesc with data frags */ 1121 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) { 1122 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]); 1123 return false; 1124 } 1125 1126 otx2_set_txtstamp(pfvf, skb, sq, &offset); 1127 1128 sqe_hdr->sizem1 = (offset / 16) - 1; 1129 1130 netdev_tx_sent_queue(txq, skb->len); 1131 1132 /* Flush SQE to HW */ 1133 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 1134 1135 return true; 1136 } 1137 EXPORT_SYMBOL(otx2_sq_append_skb); 1138 1139 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 1140 { 1141 struct nix_cqe_rx_s *cqe; 1142 int processed_cqe = 0; 1143 u64 iova, pa; 1144 1145 if (pfvf->xdp_prog) 1146 xdp_rxq_info_unreg(&cq->xdp_rxq); 1147 1148 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 1149 return; 1150 1151 while (cq->pend_cqe) { 1152 cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq); 1153 processed_cqe++; 1154 cq->pend_cqe--; 1155 1156 if (!cqe) 1157 continue; 1158 if (cqe->sg.segs > 1) { 1159 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx); 1160 continue; 1161 } 1162 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 1163 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1164 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE); 1165 put_page(virt_to_page(phys_to_virt(pa))); 1166 } 1167 1168 /* Free CQEs to HW */ 1169 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 1170 ((u64)cq->cq_idx << 32) | processed_cqe); 1171 } 1172 1173 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 1174 { 1175 struct sk_buff *skb = NULL; 1176 struct otx2_snd_queue *sq; 1177 struct nix_cqe_tx_s *cqe; 1178 int processed_cqe = 0; 1179 struct sg_list *sg; 1180 1181 sq = &pfvf->qset.sq[cq->cint_idx]; 1182 1183 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 1184 return; 1185 1186 while (cq->pend_cqe) { 1187 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 1188 processed_cqe++; 1189 cq->pend_cqe--; 1190 1191 if (!cqe) 1192 continue; 1193 sg = &sq->sg[cqe->comp.sqe_id]; 1194 skb = (struct sk_buff *)sg->skb; 1195 if (skb) { 1196 otx2_dma_unmap_skb_frags(pfvf, sg); 1197 dev_kfree_skb_any(skb); 1198 sg->skb = (u64)NULL; 1199 } 1200 } 1201 1202 /* Free CQEs to HW */ 1203 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 1204 ((u64)cq->cq_idx << 32) | processed_cqe); 1205 } 1206 1207 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable) 1208 { 1209 struct msg_req *msg; 1210 int err; 1211 1212 mutex_lock(&pfvf->mbox.lock); 1213 if (enable) 1214 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox); 1215 else 1216 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox); 1217 1218 if (!msg) { 1219 mutex_unlock(&pfvf->mbox.lock); 1220 return -ENOMEM; 1221 } 1222 1223 err = otx2_sync_mbox_msg(&pfvf->mbox); 1224 mutex_unlock(&pfvf->mbox.lock); 1225 return err; 1226 } 1227 1228 static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, u64 dma_addr, 1229 int len, int *offset) 1230 { 1231 struct nix_sqe_sg_s *sg = NULL; 1232 u64 *iova = NULL; 1233 1234 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 1235 sg->ld_type = NIX_SEND_LDTYPE_LDD; 1236 sg->subdc = NIX_SUBDC_SG; 1237 sg->segs = 1; 1238 sg->seg1_size = len; 1239 iova = (void *)sg + sizeof(*sg); 1240 *iova = dma_addr; 1241 *offset += sizeof(*sg) + sizeof(u64); 1242 1243 sq->sg[sq->head].dma_addr[0] = dma_addr; 1244 sq->sg[sq->head].size[0] = len; 1245 sq->sg[sq->head].num_segs = 1; 1246 } 1247 1248 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx) 1249 { 1250 struct nix_sqe_hdr_s *sqe_hdr; 1251 struct otx2_snd_queue *sq; 1252 int offset, free_sqe; 1253 1254 sq = &pfvf->qset.sq[qidx]; 1255 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 1256 if (free_sqe < sq->sqe_thresh) 1257 return false; 1258 1259 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 1260 1261 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 1262 1263 if (!sqe_hdr->total) { 1264 sqe_hdr->aura = sq->aura_id; 1265 sqe_hdr->df = 1; 1266 sqe_hdr->sq = qidx; 1267 sqe_hdr->pnc = 1; 1268 } 1269 sqe_hdr->total = len; 1270 sqe_hdr->sqe_id = sq->head; 1271 1272 offset = sizeof(*sqe_hdr); 1273 1274 otx2_xdp_sqe_add_sg(sq, iova, len, &offset); 1275 sqe_hdr->sizem1 = (offset / 16) - 1; 1276 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 1277 1278 return true; 1279 } 1280 1281 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf, 1282 struct bpf_prog *prog, 1283 struct nix_cqe_rx_s *cqe, 1284 struct otx2_cq_queue *cq) 1285 { 1286 unsigned char *hard_start, *data; 1287 int qidx = cq->cq_idx; 1288 struct xdp_buff xdp; 1289 struct page *page; 1290 u64 iova, pa; 1291 u32 act; 1292 int err; 1293 1294 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 1295 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1296 page = virt_to_page(phys_to_virt(pa)); 1297 1298 xdp_init_buff(&xdp, pfvf->rbsize, &cq->xdp_rxq); 1299 1300 data = (unsigned char *)phys_to_virt(pa); 1301 hard_start = page_address(page); 1302 xdp_prepare_buff(&xdp, hard_start, data - hard_start, 1303 cqe->sg.seg_size, false); 1304 1305 act = bpf_prog_run_xdp(prog, &xdp); 1306 1307 switch (act) { 1308 case XDP_PASS: 1309 break; 1310 case XDP_TX: 1311 qidx += pfvf->hw.tx_queues; 1312 cq->pool_ptrs++; 1313 return otx2_xdp_sq_append_pkt(pfvf, iova, 1314 cqe->sg.seg_size, qidx); 1315 case XDP_REDIRECT: 1316 cq->pool_ptrs++; 1317 err = xdp_do_redirect(pfvf->netdev, &xdp, prog); 1318 1319 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, 1320 DMA_FROM_DEVICE); 1321 if (!err) 1322 return true; 1323 put_page(page); 1324 break; 1325 default: 1326 bpf_warn_invalid_xdp_action(pfvf->netdev, prog, act); 1327 break; 1328 case XDP_ABORTED: 1329 trace_xdp_exception(pfvf->netdev, prog, act); 1330 break; 1331 case XDP_DROP: 1332 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, 1333 DMA_FROM_DEVICE); 1334 put_page(page); 1335 cq->pool_ptrs++; 1336 return true; 1337 } 1338 return false; 1339 } 1340