1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * 5 * lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS 6 */ 7 8 #include <linux/module.h> 9 #include <sound/pcm.h> 10 #include <sound/soc.h> 11 #include <linux/pm_runtime.h> 12 13 #include <dt-bindings/sound/sc7180-lpass.h> 14 15 #include "lpass-lpaif-reg.h" 16 #include "lpass.h" 17 18 static struct snd_soc_dai_driver sc7280_lpass_cpu_dai_driver[] = { 19 { 20 .id = MI2S_PRIMARY, 21 .name = "Primary MI2S", 22 .playback = { 23 .stream_name = "Primary Playback", 24 .formats = SNDRV_PCM_FMTBIT_S16, 25 .rates = SNDRV_PCM_RATE_48000, 26 .rate_min = 48000, 27 .rate_max = 48000, 28 .channels_min = 2, 29 .channels_max = 2, 30 }, 31 .capture = { 32 .stream_name = "Primary Capture", 33 .formats = SNDRV_PCM_FMTBIT_S16 | 34 SNDRV_PCM_FMTBIT_S32, 35 .rates = SNDRV_PCM_RATE_48000, 36 .rate_min = 48000, 37 .rate_max = 48000, 38 .channels_min = 2, 39 .channels_max = 2, 40 }, 41 .probe = &asoc_qcom_lpass_cpu_dai_probe, 42 .ops = &asoc_qcom_lpass_cpu_dai_ops, 43 }, { 44 .id = MI2S_SECONDARY, 45 .name = "Secondary MI2S", 46 .playback = { 47 .stream_name = "Secondary MI2S Playback", 48 .formats = SNDRV_PCM_FMTBIT_S16, 49 .rates = SNDRV_PCM_RATE_48000, 50 .rate_min = 48000, 51 .rate_max = 48000, 52 .channels_min = 2, 53 .channels_max = 2, 54 }, 55 .probe = &asoc_qcom_lpass_cpu_dai_probe, 56 .ops = &asoc_qcom_lpass_cpu_dai_ops, 57 }, { 58 .id = LPASS_DP_RX, 59 .name = "Hdmi", 60 .playback = { 61 .stream_name = "DP Playback", 62 .formats = SNDRV_PCM_FMTBIT_S24, 63 .rates = SNDRV_PCM_RATE_48000, 64 .rate_min = 48000, 65 .rate_max = 48000, 66 .channels_min = 2, 67 .channels_max = 2, 68 }, 69 .ops = &asoc_qcom_lpass_hdmi_dai_ops, 70 }, { 71 .id = LPASS_CDC_DMA_RX0, 72 .name = "CDC DMA RX", 73 .playback = { 74 .stream_name = "WCD Playback", 75 .formats = SNDRV_PCM_FMTBIT_S16, 76 .rates = SNDRV_PCM_RATE_48000, 77 .rate_min = 48000, 78 .rate_max = 48000, 79 .channels_min = 2, 80 .channels_max = 2, 81 }, 82 .ops = &asoc_qcom_lpass_cdc_dma_dai_ops, 83 }, { 84 .id = LPASS_CDC_DMA_TX3, 85 .name = "CDC DMA TX", 86 .capture = { 87 .stream_name = "WCD Capture", 88 .formats = SNDRV_PCM_FMTBIT_S16, 89 .rates = SNDRV_PCM_RATE_48000, 90 .rate_min = 48000, 91 .rate_max = 48000, 92 .channels_min = 1, 93 .channels_max = 1, 94 }, 95 .ops = &asoc_qcom_lpass_cdc_dma_dai_ops, 96 }, { 97 .id = LPASS_CDC_DMA_VA_TX0, 98 .name = "CDC DMA VA", 99 .capture = { 100 .stream_name = "DMIC Capture", 101 .formats = SNDRV_PCM_FMTBIT_S16, 102 .rates = SNDRV_PCM_RATE_48000, 103 .rate_min = 48000, 104 .rate_max = 48000, 105 .channels_min = 2, 106 .channels_max = 4, 107 }, 108 .ops = &asoc_qcom_lpass_cdc_dma_dai_ops, 109 }, 110 }; 111 112 static int sc7280_lpass_alloc_dma_channel(struct lpass_data *drvdata, 113 int direction, unsigned int dai_id) 114 { 115 struct lpass_variant *v = drvdata->variant; 116 int chan = 0; 117 118 switch (dai_id) { 119 case MI2S_PRIMARY ... MI2S_QUINARY: 120 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 121 chan = find_first_zero_bit(&drvdata->dma_ch_bit_map, 122 v->rdma_channels); 123 124 if (chan >= v->rdma_channels) 125 return -EBUSY; 126 } else { 127 chan = find_next_zero_bit(&drvdata->dma_ch_bit_map, 128 v->wrdma_channel_start + 129 v->wrdma_channels, 130 v->wrdma_channel_start); 131 132 if (chan >= v->wrdma_channel_start + v->wrdma_channels) 133 return -EBUSY; 134 } 135 set_bit(chan, &drvdata->dma_ch_bit_map); 136 break; 137 case LPASS_DP_RX: 138 chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map, 139 v->hdmi_rdma_channels); 140 if (chan >= v->hdmi_rdma_channels) 141 return -EBUSY; 142 set_bit(chan, &drvdata->hdmi_dma_ch_bit_map); 143 break; 144 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: 145 chan = find_first_zero_bit(&drvdata->rxtx_dma_ch_bit_map, 146 v->rxtx_rdma_channels); 147 if (chan >= v->rxtx_rdma_channels) 148 return -EBUSY; 149 break; 150 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: 151 chan = find_next_zero_bit(&drvdata->rxtx_dma_ch_bit_map, 152 v->rxtx_wrdma_channel_start + 153 v->rxtx_wrdma_channels, 154 v->rxtx_wrdma_channel_start); 155 if (chan >= v->rxtx_wrdma_channel_start + v->rxtx_wrdma_channels) 156 return -EBUSY; 157 set_bit(chan, &drvdata->rxtx_dma_ch_bit_map); 158 break; 159 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: 160 chan = find_next_zero_bit(&drvdata->va_dma_ch_bit_map, 161 v->va_wrdma_channel_start + 162 v->va_wrdma_channels, 163 v->va_wrdma_channel_start); 164 if (chan >= v->va_wrdma_channel_start + v->va_wrdma_channels) 165 return -EBUSY; 166 set_bit(chan, &drvdata->va_dma_ch_bit_map); 167 break; 168 default: 169 break; 170 } 171 172 return chan; 173 } 174 175 static int sc7280_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id) 176 { 177 switch (dai_id) { 178 case MI2S_PRIMARY ... MI2S_QUINARY: 179 clear_bit(chan, &drvdata->dma_ch_bit_map); 180 break; 181 case LPASS_DP_RX: 182 clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map); 183 break; 184 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: 185 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: 186 clear_bit(chan, &drvdata->rxtx_dma_ch_bit_map); 187 break; 188 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: 189 clear_bit(chan, &drvdata->va_dma_ch_bit_map); 190 break; 191 default: 192 break; 193 } 194 195 return 0; 196 } 197 198 static int sc7280_lpass_init(struct platform_device *pdev) 199 { 200 struct lpass_data *drvdata = platform_get_drvdata(pdev); 201 struct lpass_variant *variant = drvdata->variant; 202 struct device *dev = &pdev->dev; 203 int ret, i; 204 205 drvdata->clks = devm_kcalloc(dev, variant->num_clks, 206 sizeof(*drvdata->clks), GFP_KERNEL); 207 if (!drvdata->clks) 208 return -ENOMEM; 209 210 drvdata->num_clks = variant->num_clks; 211 212 for (i = 0; i < drvdata->num_clks; i++) 213 drvdata->clks[i].id = variant->clk_name[i]; 214 215 ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks); 216 if (ret) { 217 dev_err(dev, "Failed to get clocks %d\n", ret); 218 return ret; 219 } 220 221 ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); 222 if (ret) { 223 dev_err(dev, "sc7280 clk_enable failed\n"); 224 return ret; 225 } 226 227 return 0; 228 } 229 230 static int sc7280_lpass_exit(struct platform_device *pdev) 231 { 232 struct lpass_data *drvdata = platform_get_drvdata(pdev); 233 234 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); 235 return 0; 236 } 237 238 static int __maybe_unused sc7280_lpass_dev_resume(struct device *dev) 239 { 240 struct lpass_data *drvdata = dev_get_drvdata(dev); 241 242 return clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); 243 } 244 245 static int __maybe_unused sc7280_lpass_dev_suspend(struct device *dev) 246 { 247 struct lpass_data *drvdata = dev_get_drvdata(dev); 248 249 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); 250 return 0; 251 } 252 253 static const struct dev_pm_ops sc7280_lpass_pm_ops = { 254 SET_SYSTEM_SLEEP_PM_OPS(sc7280_lpass_dev_suspend, sc7280_lpass_dev_resume) 255 }; 256 257 static struct lpass_variant sc7280_data = { 258 .i2sctrl_reg_base = 0x1000, 259 .i2sctrl_reg_stride = 0x1000, 260 .i2s_ports = 3, 261 .irq_reg_base = 0x9000, 262 .irq_reg_stride = 0x1000, 263 .irq_ports = 3, 264 .rdma_reg_base = 0xC000, 265 .rdma_reg_stride = 0x1000, 266 .rdma_channels = 5, 267 .rxtx_rdma_reg_base = 0xC000, 268 .rxtx_rdma_reg_stride = 0x1000, 269 .rxtx_rdma_channels = 8, 270 .hdmi_rdma_reg_base = 0x64000, 271 .hdmi_rdma_reg_stride = 0x1000, 272 .hdmi_rdma_channels = 4, 273 .dmactl_audif_start = 1, 274 .wrdma_reg_base = 0x18000, 275 .wrdma_reg_stride = 0x1000, 276 .wrdma_channel_start = 5, 277 .wrdma_channels = 4, 278 .rxtx_irq_reg_base = 0x9000, 279 .rxtx_irq_reg_stride = 0x1000, 280 .rxtx_irq_ports = 3, 281 .rxtx_wrdma_reg_base = 0x18000, 282 .rxtx_wrdma_reg_stride = 0x1000, 283 .rxtx_wrdma_channel_start = 5, 284 .rxtx_wrdma_channels = 6, 285 .va_wrdma_reg_base = 0x18000, 286 .va_wrdma_reg_stride = 0x1000, 287 .va_wrdma_channel_start = 5, 288 .va_wrdma_channels = 3, 289 .va_irq_reg_base = 0x9000, 290 .va_irq_reg_stride = 0x1000, 291 .va_irq_ports = 3, 292 293 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000), 294 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000), 295 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000), 296 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000), 297 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000), 298 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000), 299 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000), 300 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000), 301 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000), 302 303 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000), 304 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000), 305 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000), 306 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000), 307 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000), 308 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000), 309 310 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000), 311 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000), 312 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000), 313 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000), 314 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000), 315 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000), 316 317 .rxtx_rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 7, 0x1000), 318 .rxtx_rdma_fifowm = REG_FIELD_ID(0xC000, 1, 11, 7, 0x1000), 319 .rxtx_rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 7, 0x1000), 320 .rxtx_rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 7, 0x1000), 321 .rxtx_rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 7, 0x1000), 322 .rxtx_rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 7, 0x1000), 323 324 .rxtx_rdma_codec_ch = REG_FIELD_ID(0xC050, 0, 7, 7, 0x1000), 325 .rxtx_rdma_codec_intf = REG_FIELD_ID(0xC050, 16, 19, 7, 0x1000), 326 .rxtx_rdma_codec_fs_delay = REG_FIELD_ID(0xC050, 21, 24, 7, 0x1000), 327 .rxtx_rdma_codec_fs_sel = REG_FIELD_ID(0xC050, 25, 27, 7, 0x1000), 328 .rxtx_rdma_codec_pack = REG_FIELD_ID(0xC050, 29, 29, 5, 0x1000), 329 .rxtx_rdma_codec_enable = REG_FIELD_ID(0xC050, 30, 30, 7, 0x1000), 330 331 .rxtx_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000), 332 .rxtx_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000), 333 .rxtx_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000), 334 .rxtx_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000), 335 .rxtx_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000), 336 .rxtx_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000), 337 338 .rxtx_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000), 339 .rxtx_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000), 340 .rxtx_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000), 341 .rxtx_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000), 342 .rxtx_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000), 343 .rxtx_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000), 344 345 .va_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000), 346 .va_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000), 347 .va_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000), 348 .va_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000), 349 .va_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000), 350 .va_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000), 351 352 .va_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000), 353 .va_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000), 354 .va_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000), 355 .va_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000), 356 .va_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000), 357 .va_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000), 358 359 .hdmi_tx_ctl_addr = 0x1000, 360 .hdmi_legacy_addr = 0x1008, 361 .hdmi_vbit_addr = 0x610c0, 362 .hdmi_ch_lsb_addr = 0x61048, 363 .hdmi_ch_msb_addr = 0x6104c, 364 .ch_stride = 0x8, 365 .hdmi_parity_addr = 0x61034, 366 .hdmi_dmactl_addr = 0x61038, 367 .hdmi_dma_stride = 0x4, 368 .hdmi_DP_addr = 0x610c8, 369 .hdmi_sstream_addr = 0x6101c, 370 .hdmi_irq_reg_base = 0x63000, 371 .hdmi_irq_ports = 1, 372 373 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000), 374 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000), 375 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000), 376 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000), 377 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000), 378 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000), 379 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000), 380 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000), 381 382 .sstream_en = REG_FIELD(0x6101c, 0, 0), 383 .dma_sel = REG_FIELD(0x6101c, 1, 2), 384 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3), 385 .layout = REG_FIELD(0x6101c, 4, 4), 386 .layout_sp = REG_FIELD(0x6101c, 5, 8), 387 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10), 388 .dp_audio = REG_FIELD(0x6101c, 11, 11), 389 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12), 390 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13), 391 392 .mute = REG_FIELD(0x610c8, 0, 0), 393 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3), 394 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7), 395 .aif_db4 = REG_FIELD(0x610c8, 8, 15), 396 .frequency = REG_FIELD(0x610c8, 16, 21), 397 .mst_index = REG_FIELD(0x610c8, 28, 29), 398 .dptx_index = REG_FIELD(0x610c8, 30, 31), 399 400 .soft_reset = REG_FIELD(0x1000, 31, 31), 401 .force_reset = REG_FIELD(0x1000, 30, 30), 402 403 .use_hw_chs = REG_FIELD(0x61038, 0, 0), 404 .use_hw_usr = REG_FIELD(0x61038, 1, 1), 405 .hw_chs_sel = REG_FIELD(0x61038, 2, 4), 406 .hw_usr_sel = REG_FIELD(0x61038, 5, 6), 407 408 .replace_vbit = REG_FIELD(0x610c0, 0, 0), 409 .vbit_stream = REG_FIELD(0x610c0, 1, 1), 410 411 .legacy_en = REG_FIELD(0x1008, 0, 0), 412 .calc_en = REG_FIELD(0x61034, 0, 0), 413 .lsb_bits = REG_FIELD(0x61048, 0, 31), 414 .msb_bits = REG_FIELD(0x6104c, 0, 31), 415 416 .clk_name = (const char*[]) { 417 "core_cc_sysnoc_mport_core" 418 }, 419 .num_clks = 1, 420 421 .dai_driver = sc7280_lpass_cpu_dai_driver, 422 .num_dai = ARRAY_SIZE(sc7280_lpass_cpu_dai_driver), 423 .dai_osr_clk_names = (const char *[]) { 424 "audio_cc_ext_mclk0", 425 "null" 426 }, 427 .dai_bit_clk_names = (const char *[]) { 428 "core_cc_ext_if0_ibit", 429 "core_cc_ext_if1_ibit" 430 }, 431 .init = sc7280_lpass_init, 432 .exit = sc7280_lpass_exit, 433 .alloc_dma_channel = sc7280_lpass_alloc_dma_channel, 434 .free_dma_channel = sc7280_lpass_free_dma_channel, 435 }; 436 437 static const struct of_device_id sc7280_lpass_cpu_device_id[] = { 438 {.compatible = "qcom,sc7280-lpass-cpu", .data = &sc7280_data}, 439 {} 440 }; 441 MODULE_DEVICE_TABLE(of, sc7280_lpass_cpu_device_id); 442 443 static struct platform_driver sc7280_lpass_cpu_platform_driver = { 444 .driver = { 445 .name = "sc7280-lpass-cpu", 446 .of_match_table = of_match_ptr(sc7280_lpass_cpu_device_id), 447 .pm = &sc7280_lpass_pm_ops, 448 }, 449 .probe = asoc_qcom_lpass_cpu_platform_probe, 450 .remove = asoc_qcom_lpass_cpu_platform_remove, 451 .shutdown = asoc_qcom_lpass_cpu_platform_shutdown, 452 }; 453 454 module_platform_driver(sc7280_lpass_cpu_platform_driver); 455 456 MODULE_DESCRIPTION("SC7280 LPASS CPU DRIVER"); 457 MODULE_LICENSE("GPL"); 458