1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static const char *icache_policy_str[] = { 37 [ICACHE_POLICY_VPIPT] = "VPIPT", 38 [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", 39 [ICACHE_POLICY_VIPT] = "VIPT", 40 [ICACHE_POLICY_PIPT] = "PIPT", 41 }; 42 43 unsigned long __icache_flags; 44 45 static const char *const hwcap_str[] = { 46 [KERNEL_HWCAP_FP] = "fp", 47 [KERNEL_HWCAP_ASIMD] = "asimd", 48 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 49 [KERNEL_HWCAP_AES] = "aes", 50 [KERNEL_HWCAP_PMULL] = "pmull", 51 [KERNEL_HWCAP_SHA1] = "sha1", 52 [KERNEL_HWCAP_SHA2] = "sha2", 53 [KERNEL_HWCAP_CRC32] = "crc32", 54 [KERNEL_HWCAP_ATOMICS] = "atomics", 55 [KERNEL_HWCAP_FPHP] = "fphp", 56 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 57 [KERNEL_HWCAP_CPUID] = "cpuid", 58 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 59 [KERNEL_HWCAP_JSCVT] = "jscvt", 60 [KERNEL_HWCAP_FCMA] = "fcma", 61 [KERNEL_HWCAP_LRCPC] = "lrcpc", 62 [KERNEL_HWCAP_DCPOP] = "dcpop", 63 [KERNEL_HWCAP_SHA3] = "sha3", 64 [KERNEL_HWCAP_SM3] = "sm3", 65 [KERNEL_HWCAP_SM4] = "sm4", 66 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 67 [KERNEL_HWCAP_SHA512] = "sha512", 68 [KERNEL_HWCAP_SVE] = "sve", 69 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 70 [KERNEL_HWCAP_DIT] = "dit", 71 [KERNEL_HWCAP_USCAT] = "uscat", 72 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 73 [KERNEL_HWCAP_FLAGM] = "flagm", 74 [KERNEL_HWCAP_SSBS] = "ssbs", 75 [KERNEL_HWCAP_SB] = "sb", 76 [KERNEL_HWCAP_PACA] = "paca", 77 [KERNEL_HWCAP_PACG] = "pacg", 78 [KERNEL_HWCAP_DCPODP] = "dcpodp", 79 [KERNEL_HWCAP_SVE2] = "sve2", 80 [KERNEL_HWCAP_SVEAES] = "sveaes", 81 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 82 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 83 [KERNEL_HWCAP_SVESHA3] = "svesha3", 84 [KERNEL_HWCAP_SVESM4] = "svesm4", 85 [KERNEL_HWCAP_FLAGM2] = "flagm2", 86 [KERNEL_HWCAP_FRINT] = "frint", 87 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 88 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 89 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 90 [KERNEL_HWCAP_SVEBF16] = "svebf16", 91 [KERNEL_HWCAP_I8MM] = "i8mm", 92 [KERNEL_HWCAP_BF16] = "bf16", 93 [KERNEL_HWCAP_DGH] = "dgh", 94 [KERNEL_HWCAP_RNG] = "rng", 95 [KERNEL_HWCAP_BTI] = "bti", 96 [KERNEL_HWCAP_MTE] = "mte", 97 [KERNEL_HWCAP_ECV] = "ecv", 98 [KERNEL_HWCAP_AFP] = "afp", 99 [KERNEL_HWCAP_RPRES] = "rpres", 100 [KERNEL_HWCAP_MTE3] = "mte3", 101 }; 102 103 #ifdef CONFIG_COMPAT 104 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 105 static const char *const compat_hwcap_str[] = { 106 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 107 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 108 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 109 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 110 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 111 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 112 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 113 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 114 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 115 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 116 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 117 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 118 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 119 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 120 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 121 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 122 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 123 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 124 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 125 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 126 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 127 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 128 }; 129 130 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 131 static const char *const compat_hwcap2_str[] = { 132 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 133 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 134 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 135 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 136 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 137 }; 138 #endif /* CONFIG_COMPAT */ 139 140 static int c_show(struct seq_file *m, void *v) 141 { 142 int i, j; 143 bool compat = personality(current->personality) == PER_LINUX32; 144 145 for_each_online_cpu(i) { 146 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 147 u32 midr = cpuinfo->reg_midr; 148 149 /* 150 * glibc reads /proc/cpuinfo to determine the number of 151 * online processors, looking for lines beginning with 152 * "processor". Give glibc what it expects. 153 */ 154 seq_printf(m, "processor\t: %d\n", i); 155 if (compat) 156 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 157 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 158 159 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 160 loops_per_jiffy / (500000UL/HZ), 161 loops_per_jiffy / (5000UL/HZ) % 100); 162 163 /* 164 * Dump out the common processor features in a single line. 165 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 166 * rather than attempting to parse this, but there's a body of 167 * software which does already (at least for 32-bit). 168 */ 169 seq_puts(m, "Features\t:"); 170 if (compat) { 171 #ifdef CONFIG_COMPAT 172 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 173 if (compat_elf_hwcap & (1 << j)) { 174 /* 175 * Warn once if any feature should not 176 * have been present on arm64 platform. 177 */ 178 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 179 continue; 180 181 seq_printf(m, " %s", compat_hwcap_str[j]); 182 } 183 } 184 185 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 186 if (compat_elf_hwcap2 & (1 << j)) 187 seq_printf(m, " %s", compat_hwcap2_str[j]); 188 #endif /* CONFIG_COMPAT */ 189 } else { 190 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 191 if (cpu_have_feature(j)) 192 seq_printf(m, " %s", hwcap_str[j]); 193 } 194 seq_puts(m, "\n"); 195 196 seq_printf(m, "CPU implementer\t: 0x%02x\n", 197 MIDR_IMPLEMENTOR(midr)); 198 seq_printf(m, "CPU architecture: 8\n"); 199 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 200 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 201 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 202 } 203 204 return 0; 205 } 206 207 static void *c_start(struct seq_file *m, loff_t *pos) 208 { 209 return *pos < 1 ? (void *)1 : NULL; 210 } 211 212 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 213 { 214 ++*pos; 215 return NULL; 216 } 217 218 static void c_stop(struct seq_file *m, void *v) 219 { 220 } 221 222 const struct seq_operations cpuinfo_op = { 223 .start = c_start, 224 .next = c_next, 225 .stop = c_stop, 226 .show = c_show 227 }; 228 229 230 static struct kobj_type cpuregs_kobj_type = { 231 .sysfs_ops = &kobj_sysfs_ops, 232 }; 233 234 /* 235 * The ARM ARM uses the phrase "32-bit register" to describe a register 236 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 237 * no statement is made as to whether the upper 32 bits will or will not 238 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 239 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 240 * 241 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 242 * registers, we expose them both as 64 bit values to cater for possible 243 * future expansion without an ABI break. 244 */ 245 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 246 #define CPUREGS_ATTR_RO(_name, _field) \ 247 static ssize_t _name##_show(struct kobject *kobj, \ 248 struct kobj_attribute *attr, char *buf) \ 249 { \ 250 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 251 \ 252 if (info->reg_midr) \ 253 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 254 else \ 255 return 0; \ 256 } \ 257 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 258 259 CPUREGS_ATTR_RO(midr_el1, midr); 260 CPUREGS_ATTR_RO(revidr_el1, revidr); 261 262 static struct attribute *cpuregs_id_attrs[] = { 263 &cpuregs_attr_midr_el1.attr, 264 &cpuregs_attr_revidr_el1.attr, 265 NULL 266 }; 267 268 static const struct attribute_group cpuregs_attr_group = { 269 .attrs = cpuregs_id_attrs, 270 .name = "identification" 271 }; 272 273 static int cpuid_cpu_online(unsigned int cpu) 274 { 275 int rc; 276 struct device *dev; 277 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 278 279 dev = get_cpu_device(cpu); 280 if (!dev) { 281 rc = -ENODEV; 282 goto out; 283 } 284 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 285 if (rc) 286 goto out; 287 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 288 if (rc) 289 kobject_del(&info->kobj); 290 out: 291 return rc; 292 } 293 294 static int cpuid_cpu_offline(unsigned int cpu) 295 { 296 struct device *dev; 297 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 298 299 dev = get_cpu_device(cpu); 300 if (!dev) 301 return -ENODEV; 302 if (info->kobj.parent) { 303 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 304 kobject_del(&info->kobj); 305 } 306 307 return 0; 308 } 309 310 static int __init cpuinfo_regs_init(void) 311 { 312 int cpu, ret; 313 314 for_each_possible_cpu(cpu) { 315 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 316 317 kobject_init(&info->kobj, &cpuregs_kobj_type); 318 } 319 320 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 321 cpuid_cpu_online, cpuid_cpu_offline); 322 if (ret < 0) { 323 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 324 return ret; 325 } 326 return 0; 327 } 328 device_initcall(cpuinfo_regs_init); 329 330 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 331 { 332 unsigned int cpu = smp_processor_id(); 333 u32 l1ip = CTR_L1IP(info->reg_ctr); 334 335 switch (l1ip) { 336 case ICACHE_POLICY_PIPT: 337 break; 338 case ICACHE_POLICY_VPIPT: 339 set_bit(ICACHEF_VPIPT, &__icache_flags); 340 break; 341 case ICACHE_POLICY_RESERVED: 342 case ICACHE_POLICY_VIPT: 343 /* Assume aliasing */ 344 set_bit(ICACHEF_ALIASING, &__icache_flags); 345 break; 346 } 347 348 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); 349 } 350 351 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 352 { 353 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 354 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 355 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 356 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 357 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 358 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 359 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 360 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 361 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 362 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 363 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 364 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 365 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 366 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 367 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 368 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 369 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 370 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 371 372 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 373 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 374 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 375 } 376 377 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 378 { 379 info->reg_cntfrq = arch_timer_get_cntfrq(); 380 /* 381 * Use the effective value of the CTR_EL0 than the raw value 382 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 383 * with the CLIDR_EL1 fields to avoid triggering false warnings 384 * when there is a mismatch across the CPUs. Keep track of the 385 * effective value of the CTR_EL0 in our internal records for 386 * accurate sanity check and feature enablement. 387 */ 388 info->reg_ctr = read_cpuid_effective_cachetype(); 389 info->reg_dczid = read_cpuid(DCZID_EL0); 390 info->reg_midr = read_cpuid_id(); 391 info->reg_revidr = read_cpuid(REVIDR_EL1); 392 393 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 394 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 395 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 396 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 397 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 398 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 399 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 400 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 401 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 402 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 403 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 404 405 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 406 info->reg_gmid = read_cpuid(GMID_EL1); 407 408 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 409 __cpuinfo_store_cpu_32bit(&info->aarch32); 410 411 if (IS_ENABLED(CONFIG_ARM64_SVE) && 412 id_aa64pfr0_sve(info->reg_id_aa64pfr0)) 413 info->reg_zcr = read_zcr_features(); 414 415 cpuinfo_detect_icache_policy(info); 416 } 417 418 void cpuinfo_store_cpu(void) 419 { 420 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 421 __cpuinfo_store_cpu(info); 422 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 423 } 424 425 void __init cpuinfo_store_boot_cpu(void) 426 { 427 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 428 __cpuinfo_store_cpu(info); 429 430 boot_cpu_data = *info; 431 init_cpu_features(&boot_cpu_data); 432 } 433