1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (chip->info->ops->port_set_pause) { 453 err = chip->info->ops->port_set_pause(chip, port, pause); 454 if (err) 455 goto restore_link; 456 } 457 458 err = mv88e6xxx_port_config_interface(chip, port, mode); 459 restore_link: 460 if (chip->info->ops->port_set_link(chip, port, link)) 461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 462 463 return err; 464 } 465 466 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 467 { 468 struct mv88e6xxx_chip *chip = ds->priv; 469 470 return port < chip->info->num_internal_phys; 471 } 472 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 474 { 475 u16 reg; 476 int err; 477 478 /* The 88e6250 family does not have the PHY detect bit. Instead, 479 * report whether the port is internal. 480 */ 481 if (chip->info->family == MV88E6XXX_FAMILY_6250) 482 return port < chip->info->num_internal_phys; 483 484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 485 if (err) { 486 dev_err(chip->dev, 487 "p%d: %s: failed to read port status\n", 488 port, __func__); 489 return err; 490 } 491 492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 493 } 494 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 496 struct phylink_link_state *state) 497 { 498 struct mv88e6xxx_chip *chip = ds->priv; 499 int lane; 500 int err; 501 502 mv88e6xxx_reg_lock(chip); 503 lane = mv88e6xxx_serdes_get_lane(chip, port); 504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 506 state); 507 else 508 err = -EOPNOTSUPP; 509 mv88e6xxx_reg_unlock(chip); 510 511 return err; 512 } 513 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 515 unsigned int mode, 516 phy_interface_t interface, 517 const unsigned long *advertise) 518 { 519 const struct mv88e6xxx_ops *ops = chip->info->ops; 520 int lane; 521 522 if (ops->serdes_pcs_config) { 523 lane = mv88e6xxx_serdes_get_lane(chip, port); 524 if (lane >= 0) 525 return ops->serdes_pcs_config(chip, port, lane, mode, 526 interface, advertise); 527 } 528 529 return 0; 530 } 531 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 533 { 534 struct mv88e6xxx_chip *chip = ds->priv; 535 const struct mv88e6xxx_ops *ops; 536 int err = 0; 537 int lane; 538 539 ops = chip->info->ops; 540 541 if (ops->serdes_pcs_an_restart) { 542 mv88e6xxx_reg_lock(chip); 543 lane = mv88e6xxx_serdes_get_lane(chip, port); 544 if (lane >= 0) 545 err = ops->serdes_pcs_an_restart(chip, port, lane); 546 mv88e6xxx_reg_unlock(chip); 547 548 if (err) 549 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 550 } 551 } 552 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 554 unsigned int mode, 555 int speed, int duplex) 556 { 557 const struct mv88e6xxx_ops *ops = chip->info->ops; 558 int lane; 559 560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 561 lane = mv88e6xxx_serdes_get_lane(chip, port); 562 if (lane >= 0) 563 return ops->serdes_pcs_link_up(chip, port, lane, 564 speed, duplex); 565 } 566 567 return 0; 568 } 569 570 static const u8 mv88e6185_phy_interface_modes[] = { 571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 578 }; 579 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582 { 583 u8 cmode = chip->ports[port].cmode; 584 585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 586 587 if (mv88e6xxx_phy_is_internal(chip->ds, port)) { 588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 589 } else { 590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 591 mv88e6185_phy_interface_modes[cmode]) 592 __set_bit(mv88e6185_phy_interface_modes[cmode], 593 config->supported_interfaces); 594 595 config->mac_capabilities |= MAC_1000FD; 596 } 597 } 598 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 600 struct phylink_config *config) 601 { 602 u8 cmode = chip->ports[port].cmode; 603 604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 605 mv88e6185_phy_interface_modes[cmode]) 606 __set_bit(mv88e6185_phy_interface_modes[cmode], 607 config->supported_interfaces); 608 609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 610 MAC_1000FD; 611 } 612 613 static const u8 mv88e6xxx_phy_interface_modes[] = { 614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_MII, 615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_RMII, 618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 622 /* higher interface modes are not needed here, since ports supporting 623 * them are writable, and so the supported interfaces are filled in the 624 * corresponding .phylink_set_interfaces() implementation below 625 */ 626 }; 627 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 629 { 630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 631 mv88e6xxx_phy_interface_modes[cmode]) 632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 634 phy_interface_set_rgmii(supported); 635 } 636 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 638 struct phylink_config *config) 639 { 640 unsigned long *supported = config->supported_interfaces; 641 642 /* Translate the default cmode */ 643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 644 645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 646 } 647 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 649 { 650 u16 reg, val; 651 int err; 652 653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 654 if (err) 655 return err; 656 657 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 659 return 0xf; 660 661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 663 if (err) 664 return err; 665 666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 667 if (err) 668 return err; 669 670 /* Restore PHY_DETECT value */ 671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 672 if (err) 673 return err; 674 675 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 676 } 677 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 679 struct phylink_config *config) 680 { 681 unsigned long *supported = config->supported_interfaces; 682 int err, cmode; 683 684 /* Translate the default cmode */ 685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 686 687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 688 MAC_1000FD; 689 690 /* Port 4 supports automedia if the serdes is associated with it. */ 691 if (port == 4) { 692 mv88e6xxx_reg_lock(chip); 693 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 694 if (err < 0) 695 dev_err(chip->dev, "p%d: failed to read scratch\n", 696 port); 697 if (err <= 0) 698 goto unlock; 699 700 cmode = mv88e6352_get_port4_serdes_cmode(chip); 701 if (cmode < 0) 702 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 703 port); 704 else 705 mv88e6xxx_translate_cmode(cmode, supported); 706 unlock: 707 mv88e6xxx_reg_unlock(chip); 708 } 709 } 710 711 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 712 struct phylink_config *config) 713 { 714 unsigned long *supported = config->supported_interfaces; 715 716 /* Translate the default cmode */ 717 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 718 719 /* No ethtool bits for 200Mbps */ 720 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 721 MAC_1000FD; 722 723 /* The C_Mode field is programmable on port 5 */ 724 if (port == 5) { 725 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 726 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 727 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 728 729 config->mac_capabilities |= MAC_2500FD; 730 } 731 } 732 733 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 734 struct phylink_config *config) 735 { 736 unsigned long *supported = config->supported_interfaces; 737 738 /* Translate the default cmode */ 739 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 740 741 /* No ethtool bits for 200Mbps */ 742 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 743 MAC_1000FD; 744 745 /* The C_Mode field is programmable on ports 9 and 10 */ 746 if (port == 9 || port == 10) { 747 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 748 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 749 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 750 751 config->mac_capabilities |= MAC_2500FD; 752 } 753 } 754 755 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 756 struct phylink_config *config) 757 { 758 unsigned long *supported = config->supported_interfaces; 759 760 mv88e6390_phylink_get_caps(chip, port, config); 761 762 /* For the 6x90X, ports 2-7 can be in automedia mode. 763 * (Note that 6x90 doesn't support RXAUI nor XAUI). 764 * 765 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 766 * configured for 1000BASE-X, SGMII or 2500BASE-X. 767 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 768 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 769 * 770 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 771 * configured for 1000BASE-X, SGMII or 2500BASE-X. 772 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 773 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 774 * 775 * For now, be permissive (as the old code was) and allow 1000BASE-X 776 * on ports 2..7. 777 */ 778 if (port >= 2 && port <= 7) 779 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 780 781 /* The C_Mode field can also be programmed for 10G speeds */ 782 if (port == 9 || port == 10) { 783 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 784 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 785 786 config->mac_capabilities |= MAC_10000FD; 787 } 788 } 789 790 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 791 struct phylink_config *config) 792 { 793 unsigned long *supported = config->supported_interfaces; 794 bool is_6191x = 795 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 796 797 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 798 799 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 800 MAC_1000FD; 801 802 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 803 if (port == 0 || port == 9 || port == 10) { 804 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 805 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 806 807 /* 6191X supports >1G modes only on port 10 */ 808 if (!is_6191x || port == 10) { 809 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 810 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 811 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 812 /* FIXME: USXGMII is not supported yet */ 813 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */ 814 815 config->mac_capabilities |= MAC_2500FD | MAC_5000FD | 816 MAC_10000FD; 817 } 818 } 819 820 if (port == 0) { 821 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 822 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 823 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 824 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 825 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 826 } 827 } 828 829 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 830 struct phylink_config *config) 831 { 832 struct mv88e6xxx_chip *chip = ds->priv; 833 834 chip->info->ops->phylink_get_caps(chip, port, config); 835 836 /* Internal ports need GMII for PHYLIB */ 837 if (mv88e6xxx_phy_is_internal(ds, port)) 838 __set_bit(PHY_INTERFACE_MODE_GMII, 839 config->supported_interfaces); 840 } 841 842 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 843 unsigned int mode, 844 const struct phylink_link_state *state) 845 { 846 struct mv88e6xxx_chip *chip = ds->priv; 847 struct mv88e6xxx_port *p; 848 int err = 0; 849 850 p = &chip->ports[port]; 851 852 mv88e6xxx_reg_lock(chip); 853 854 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 855 /* In inband mode, the link may come up at any time while the 856 * link is not forced down. Force the link down while we 857 * reconfigure the interface mode. 858 */ 859 if (mode == MLO_AN_INBAND && 860 p->interface != state->interface && 861 chip->info->ops->port_set_link) 862 chip->info->ops->port_set_link(chip, port, 863 LINK_FORCED_DOWN); 864 865 err = mv88e6xxx_port_config_interface(chip, port, 866 state->interface); 867 if (err && err != -EOPNOTSUPP) 868 goto err_unlock; 869 870 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 871 state->interface, 872 state->advertising); 873 /* FIXME: we should restart negotiation if something changed - 874 * which is something we get if we convert to using phylinks 875 * PCS operations. 876 */ 877 if (err > 0) 878 err = 0; 879 } 880 881 /* Undo the forced down state above after completing configuration 882 * irrespective of its state on entry, which allows the link to come 883 * up in the in-band case where there is no separate SERDES. Also 884 * ensure that the link can come up if the PPU is in use and we are 885 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 886 */ 887 if (chip->info->ops->port_set_link && 888 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 889 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 890 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 891 892 p->interface = state->interface; 893 894 err_unlock: 895 mv88e6xxx_reg_unlock(chip); 896 897 if (err && err != -EOPNOTSUPP) 898 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 899 } 900 901 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 902 unsigned int mode, 903 phy_interface_t interface) 904 { 905 struct mv88e6xxx_chip *chip = ds->priv; 906 const struct mv88e6xxx_ops *ops; 907 int err = 0; 908 909 ops = chip->info->ops; 910 911 mv88e6xxx_reg_lock(chip); 912 /* Force the link down if we know the port may not be automatically 913 * updated by the switch or if we are using fixed-link mode. 914 */ 915 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 916 mode == MLO_AN_FIXED) && ops->port_sync_link) 917 err = ops->port_sync_link(chip, port, mode, false); 918 919 if (!err && ops->port_set_speed_duplex) 920 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 921 DUPLEX_UNFORCED); 922 mv88e6xxx_reg_unlock(chip); 923 924 if (err) 925 dev_err(chip->dev, 926 "p%d: failed to force MAC link down\n", port); 927 } 928 929 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 930 unsigned int mode, phy_interface_t interface, 931 struct phy_device *phydev, 932 int speed, int duplex, 933 bool tx_pause, bool rx_pause) 934 { 935 struct mv88e6xxx_chip *chip = ds->priv; 936 const struct mv88e6xxx_ops *ops; 937 int err = 0; 938 939 ops = chip->info->ops; 940 941 mv88e6xxx_reg_lock(chip); 942 /* Configure and force the link up if we know that the port may not 943 * automatically updated by the switch or if we are using fixed-link 944 * mode. 945 */ 946 if (!mv88e6xxx_port_ppu_updates(chip, port) || 947 mode == MLO_AN_FIXED) { 948 /* FIXME: for an automedia port, should we force the link 949 * down here - what if the link comes up due to "other" media 950 * while we're bringing the port up, how is the exclusivity 951 * handled in the Marvell hardware? E.g. port 2 on 88E6390 952 * shared between internal PHY and Serdes. 953 */ 954 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 955 duplex); 956 if (err) 957 goto error; 958 959 if (ops->port_set_speed_duplex) { 960 err = ops->port_set_speed_duplex(chip, port, 961 speed, duplex); 962 if (err && err != -EOPNOTSUPP) 963 goto error; 964 } 965 966 if (ops->port_sync_link) 967 err = ops->port_sync_link(chip, port, mode, true); 968 } 969 error: 970 mv88e6xxx_reg_unlock(chip); 971 972 if (err && err != -EOPNOTSUPP) 973 dev_err(ds->dev, 974 "p%d: failed to configure MAC link up\n", port); 975 } 976 977 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 978 { 979 if (!chip->info->ops->stats_snapshot) 980 return -EOPNOTSUPP; 981 982 return chip->info->ops->stats_snapshot(chip, port); 983 } 984 985 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 986 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 987 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 988 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 989 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 990 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 991 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 992 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 993 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 994 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 995 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 996 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 997 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 998 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 999 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1000 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1001 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1002 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1003 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1004 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1005 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1006 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1007 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1008 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1009 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1010 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1011 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1012 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1013 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1014 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1015 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1016 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1017 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1018 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1019 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1020 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1021 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1022 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1023 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1024 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1025 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1026 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1027 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1028 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1029 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1030 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1031 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1032 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1033 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1034 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1035 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1036 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1037 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1038 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1039 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1040 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1041 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1042 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1043 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1044 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1045 }; 1046 1047 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1048 struct mv88e6xxx_hw_stat *s, 1049 int port, u16 bank1_select, 1050 u16 histogram) 1051 { 1052 u32 low; 1053 u32 high = 0; 1054 u16 reg = 0; 1055 int err; 1056 u64 value; 1057 1058 switch (s->type) { 1059 case STATS_TYPE_PORT: 1060 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1061 if (err) 1062 return U64_MAX; 1063 1064 low = reg; 1065 if (s->size == 4) { 1066 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1067 if (err) 1068 return U64_MAX; 1069 low |= ((u32)reg) << 16; 1070 } 1071 break; 1072 case STATS_TYPE_BANK1: 1073 reg = bank1_select; 1074 fallthrough; 1075 case STATS_TYPE_BANK0: 1076 reg |= s->reg | histogram; 1077 mv88e6xxx_g1_stats_read(chip, reg, &low); 1078 if (s->size == 8) 1079 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1080 break; 1081 default: 1082 return U64_MAX; 1083 } 1084 value = (((u64)high) << 32) | low; 1085 return value; 1086 } 1087 1088 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1089 uint8_t *data, int types) 1090 { 1091 struct mv88e6xxx_hw_stat *stat; 1092 int i, j; 1093 1094 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1095 stat = &mv88e6xxx_hw_stats[i]; 1096 if (stat->type & types) { 1097 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1098 ETH_GSTRING_LEN); 1099 j++; 1100 } 1101 } 1102 1103 return j; 1104 } 1105 1106 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1107 uint8_t *data) 1108 { 1109 return mv88e6xxx_stats_get_strings(chip, data, 1110 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1111 } 1112 1113 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1114 uint8_t *data) 1115 { 1116 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1117 } 1118 1119 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1120 uint8_t *data) 1121 { 1122 return mv88e6xxx_stats_get_strings(chip, data, 1123 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1124 } 1125 1126 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1127 "atu_member_violation", 1128 "atu_miss_violation", 1129 "atu_full_violation", 1130 "vtu_member_violation", 1131 "vtu_miss_violation", 1132 }; 1133 1134 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1135 { 1136 unsigned int i; 1137 1138 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1139 strscpy(data + i * ETH_GSTRING_LEN, 1140 mv88e6xxx_atu_vtu_stats_strings[i], 1141 ETH_GSTRING_LEN); 1142 } 1143 1144 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1145 u32 stringset, uint8_t *data) 1146 { 1147 struct mv88e6xxx_chip *chip = ds->priv; 1148 int count = 0; 1149 1150 if (stringset != ETH_SS_STATS) 1151 return; 1152 1153 mv88e6xxx_reg_lock(chip); 1154 1155 if (chip->info->ops->stats_get_strings) 1156 count = chip->info->ops->stats_get_strings(chip, data); 1157 1158 if (chip->info->ops->serdes_get_strings) { 1159 data += count * ETH_GSTRING_LEN; 1160 count = chip->info->ops->serdes_get_strings(chip, port, data); 1161 } 1162 1163 data += count * ETH_GSTRING_LEN; 1164 mv88e6xxx_atu_vtu_get_strings(data); 1165 1166 mv88e6xxx_reg_unlock(chip); 1167 } 1168 1169 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1170 int types) 1171 { 1172 struct mv88e6xxx_hw_stat *stat; 1173 int i, j; 1174 1175 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1176 stat = &mv88e6xxx_hw_stats[i]; 1177 if (stat->type & types) 1178 j++; 1179 } 1180 return j; 1181 } 1182 1183 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1184 { 1185 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1186 STATS_TYPE_PORT); 1187 } 1188 1189 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1190 { 1191 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1192 } 1193 1194 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1195 { 1196 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1197 STATS_TYPE_BANK1); 1198 } 1199 1200 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1201 { 1202 struct mv88e6xxx_chip *chip = ds->priv; 1203 int serdes_count = 0; 1204 int count = 0; 1205 1206 if (sset != ETH_SS_STATS) 1207 return 0; 1208 1209 mv88e6xxx_reg_lock(chip); 1210 if (chip->info->ops->stats_get_sset_count) 1211 count = chip->info->ops->stats_get_sset_count(chip); 1212 if (count < 0) 1213 goto out; 1214 1215 if (chip->info->ops->serdes_get_sset_count) 1216 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1217 port); 1218 if (serdes_count < 0) { 1219 count = serdes_count; 1220 goto out; 1221 } 1222 count += serdes_count; 1223 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1224 1225 out: 1226 mv88e6xxx_reg_unlock(chip); 1227 1228 return count; 1229 } 1230 1231 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1232 uint64_t *data, int types, 1233 u16 bank1_select, u16 histogram) 1234 { 1235 struct mv88e6xxx_hw_stat *stat; 1236 int i, j; 1237 1238 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1239 stat = &mv88e6xxx_hw_stats[i]; 1240 if (stat->type & types) { 1241 mv88e6xxx_reg_lock(chip); 1242 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1243 bank1_select, 1244 histogram); 1245 mv88e6xxx_reg_unlock(chip); 1246 1247 j++; 1248 } 1249 } 1250 return j; 1251 } 1252 1253 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1254 uint64_t *data) 1255 { 1256 return mv88e6xxx_stats_get_stats(chip, port, data, 1257 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1258 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1259 } 1260 1261 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1262 uint64_t *data) 1263 { 1264 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1265 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1266 } 1267 1268 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1269 uint64_t *data) 1270 { 1271 return mv88e6xxx_stats_get_stats(chip, port, data, 1272 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1273 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1274 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1275 } 1276 1277 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1278 uint64_t *data) 1279 { 1280 return mv88e6xxx_stats_get_stats(chip, port, data, 1281 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1282 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1283 0); 1284 } 1285 1286 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1287 uint64_t *data) 1288 { 1289 *data++ = chip->ports[port].atu_member_violation; 1290 *data++ = chip->ports[port].atu_miss_violation; 1291 *data++ = chip->ports[port].atu_full_violation; 1292 *data++ = chip->ports[port].vtu_member_violation; 1293 *data++ = chip->ports[port].vtu_miss_violation; 1294 } 1295 1296 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1297 uint64_t *data) 1298 { 1299 int count = 0; 1300 1301 if (chip->info->ops->stats_get_stats) 1302 count = chip->info->ops->stats_get_stats(chip, port, data); 1303 1304 mv88e6xxx_reg_lock(chip); 1305 if (chip->info->ops->serdes_get_stats) { 1306 data += count; 1307 count = chip->info->ops->serdes_get_stats(chip, port, data); 1308 } 1309 data += count; 1310 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1311 mv88e6xxx_reg_unlock(chip); 1312 } 1313 1314 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1315 uint64_t *data) 1316 { 1317 struct mv88e6xxx_chip *chip = ds->priv; 1318 int ret; 1319 1320 mv88e6xxx_reg_lock(chip); 1321 1322 ret = mv88e6xxx_stats_snapshot(chip, port); 1323 mv88e6xxx_reg_unlock(chip); 1324 1325 if (ret < 0) 1326 return; 1327 1328 mv88e6xxx_get_stats(chip, port, data); 1329 1330 } 1331 1332 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1333 { 1334 struct mv88e6xxx_chip *chip = ds->priv; 1335 int len; 1336 1337 len = 32 * sizeof(u16); 1338 if (chip->info->ops->serdes_get_regs_len) 1339 len += chip->info->ops->serdes_get_regs_len(chip, port); 1340 1341 return len; 1342 } 1343 1344 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1345 struct ethtool_regs *regs, void *_p) 1346 { 1347 struct mv88e6xxx_chip *chip = ds->priv; 1348 int err; 1349 u16 reg; 1350 u16 *p = _p; 1351 int i; 1352 1353 regs->version = chip->info->prod_num; 1354 1355 memset(p, 0xff, 32 * sizeof(u16)); 1356 1357 mv88e6xxx_reg_lock(chip); 1358 1359 for (i = 0; i < 32; i++) { 1360 1361 err = mv88e6xxx_port_read(chip, port, i, ®); 1362 if (!err) 1363 p[i] = reg; 1364 } 1365 1366 if (chip->info->ops->serdes_get_regs) 1367 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1368 1369 mv88e6xxx_reg_unlock(chip); 1370 } 1371 1372 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1373 struct ethtool_eee *e) 1374 { 1375 /* Nothing to do on the port's MAC */ 1376 return 0; 1377 } 1378 1379 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1380 struct ethtool_eee *e) 1381 { 1382 /* Nothing to do on the port's MAC */ 1383 return 0; 1384 } 1385 1386 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1387 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1388 { 1389 struct dsa_switch *ds = chip->ds; 1390 struct dsa_switch_tree *dst = ds->dst; 1391 struct dsa_port *dp, *other_dp; 1392 bool found = false; 1393 u16 pvlan; 1394 1395 /* dev is a physical switch */ 1396 if (dev <= dst->last_switch) { 1397 list_for_each_entry(dp, &dst->ports, list) { 1398 if (dp->ds->index == dev && dp->index == port) { 1399 /* dp might be a DSA link or a user port, so it 1400 * might or might not have a bridge. 1401 * Use the "found" variable for both cases. 1402 */ 1403 found = true; 1404 break; 1405 } 1406 } 1407 /* dev is a virtual bridge */ 1408 } else { 1409 list_for_each_entry(dp, &dst->ports, list) { 1410 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1411 1412 if (!bridge_num) 1413 continue; 1414 1415 if (bridge_num + dst->last_switch != dev) 1416 continue; 1417 1418 found = true; 1419 break; 1420 } 1421 } 1422 1423 /* Prevent frames from unknown switch or virtual bridge */ 1424 if (!found) 1425 return 0; 1426 1427 /* Frames from DSA links and CPU ports can egress any local port */ 1428 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1429 return mv88e6xxx_port_mask(chip); 1430 1431 pvlan = 0; 1432 1433 /* Frames from standalone user ports can only egress on the 1434 * upstream port. 1435 */ 1436 if (!dsa_port_bridge_dev_get(dp)) 1437 return BIT(dsa_switch_upstream_port(ds)); 1438 1439 /* Frames from bridged user ports can egress any local DSA 1440 * links and CPU ports, as well as any local member of their 1441 * bridge group. 1442 */ 1443 dsa_switch_for_each_port(other_dp, ds) 1444 if (other_dp->type == DSA_PORT_TYPE_CPU || 1445 other_dp->type == DSA_PORT_TYPE_DSA || 1446 dsa_port_bridge_same(dp, other_dp)) 1447 pvlan |= BIT(other_dp->index); 1448 1449 return pvlan; 1450 } 1451 1452 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1453 { 1454 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1455 1456 /* prevent frames from going back out of the port they came in on */ 1457 output_ports &= ~BIT(port); 1458 1459 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1460 } 1461 1462 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1463 u8 state) 1464 { 1465 struct mv88e6xxx_chip *chip = ds->priv; 1466 int err; 1467 1468 mv88e6xxx_reg_lock(chip); 1469 err = mv88e6xxx_port_set_state(chip, port, state); 1470 mv88e6xxx_reg_unlock(chip); 1471 1472 if (err) 1473 dev_err(ds->dev, "p%d: failed to update state\n", port); 1474 } 1475 1476 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1477 { 1478 int err; 1479 1480 if (chip->info->ops->ieee_pri_map) { 1481 err = chip->info->ops->ieee_pri_map(chip); 1482 if (err) 1483 return err; 1484 } 1485 1486 if (chip->info->ops->ip_pri_map) { 1487 err = chip->info->ops->ip_pri_map(chip); 1488 if (err) 1489 return err; 1490 } 1491 1492 return 0; 1493 } 1494 1495 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1496 { 1497 struct dsa_switch *ds = chip->ds; 1498 int target, port; 1499 int err; 1500 1501 if (!chip->info->global2_addr) 1502 return 0; 1503 1504 /* Initialize the routing port to the 32 possible target devices */ 1505 for (target = 0; target < 32; target++) { 1506 port = dsa_routing_port(ds, target); 1507 if (port == ds->num_ports) 1508 port = 0x1f; 1509 1510 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1511 if (err) 1512 return err; 1513 } 1514 1515 if (chip->info->ops->set_cascade_port) { 1516 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1517 err = chip->info->ops->set_cascade_port(chip, port); 1518 if (err) 1519 return err; 1520 } 1521 1522 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1523 if (err) 1524 return err; 1525 1526 return 0; 1527 } 1528 1529 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1530 { 1531 /* Clear all trunk masks and mapping */ 1532 if (chip->info->global2_addr) 1533 return mv88e6xxx_g2_trunk_clear(chip); 1534 1535 return 0; 1536 } 1537 1538 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1539 { 1540 if (chip->info->ops->rmu_disable) 1541 return chip->info->ops->rmu_disable(chip); 1542 1543 return 0; 1544 } 1545 1546 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1547 { 1548 if (chip->info->ops->pot_clear) 1549 return chip->info->ops->pot_clear(chip); 1550 1551 return 0; 1552 } 1553 1554 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1555 { 1556 if (chip->info->ops->mgmt_rsvd2cpu) 1557 return chip->info->ops->mgmt_rsvd2cpu(chip); 1558 1559 return 0; 1560 } 1561 1562 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1563 { 1564 int err; 1565 1566 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1567 if (err) 1568 return err; 1569 1570 /* The chips that have a "learn2all" bit in Global1, ATU 1571 * Control are precisely those whose port registers have a 1572 * Message Port bit in Port Control 1 and hence implement 1573 * ->port_setup_message_port. 1574 */ 1575 if (chip->info->ops->port_setup_message_port) { 1576 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1577 if (err) 1578 return err; 1579 } 1580 1581 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1582 } 1583 1584 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1585 { 1586 int port; 1587 int err; 1588 1589 if (!chip->info->ops->irl_init_all) 1590 return 0; 1591 1592 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1593 /* Disable ingress rate limiting by resetting all per port 1594 * ingress rate limit resources to their initial state. 1595 */ 1596 err = chip->info->ops->irl_init_all(chip, port); 1597 if (err) 1598 return err; 1599 } 1600 1601 return 0; 1602 } 1603 1604 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1605 { 1606 if (chip->info->ops->set_switch_mac) { 1607 u8 addr[ETH_ALEN]; 1608 1609 eth_random_addr(addr); 1610 1611 return chip->info->ops->set_switch_mac(chip, addr); 1612 } 1613 1614 return 0; 1615 } 1616 1617 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1618 { 1619 struct dsa_switch_tree *dst = chip->ds->dst; 1620 struct dsa_switch *ds; 1621 struct dsa_port *dp; 1622 u16 pvlan = 0; 1623 1624 if (!mv88e6xxx_has_pvt(chip)) 1625 return 0; 1626 1627 /* Skip the local source device, which uses in-chip port VLAN */ 1628 if (dev != chip->ds->index) { 1629 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1630 1631 ds = dsa_switch_find(dst->index, dev); 1632 dp = ds ? dsa_to_port(ds, port) : NULL; 1633 if (dp && dp->lag) { 1634 /* As the PVT is used to limit flooding of 1635 * FORWARD frames, which use the LAG ID as the 1636 * source port, we must translate dev/port to 1637 * the special "LAG device" in the PVT, using 1638 * the LAG ID (one-based) as the port number 1639 * (zero-based). 1640 */ 1641 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1642 port = dsa_port_lag_id_get(dp) - 1; 1643 } 1644 } 1645 1646 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1647 } 1648 1649 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1650 { 1651 int dev, port; 1652 int err; 1653 1654 if (!mv88e6xxx_has_pvt(chip)) 1655 return 0; 1656 1657 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1658 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1659 */ 1660 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1661 if (err) 1662 return err; 1663 1664 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1665 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1666 err = mv88e6xxx_pvt_map(chip, dev, port); 1667 if (err) 1668 return err; 1669 } 1670 } 1671 1672 return 0; 1673 } 1674 1675 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1676 u16 fid) 1677 { 1678 if (dsa_to_port(chip->ds, port)->lag) 1679 /* Hardware is incapable of fast-aging a LAG through a 1680 * regular ATU move operation. Until we have something 1681 * more fancy in place this is a no-op. 1682 */ 1683 return -EOPNOTSUPP; 1684 1685 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1686 } 1687 1688 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1689 { 1690 struct mv88e6xxx_chip *chip = ds->priv; 1691 int err; 1692 1693 mv88e6xxx_reg_lock(chip); 1694 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1695 mv88e6xxx_reg_unlock(chip); 1696 1697 if (err) 1698 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1699 port, err); 1700 } 1701 1702 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1703 { 1704 if (!mv88e6xxx_max_vid(chip)) 1705 return 0; 1706 1707 return mv88e6xxx_g1_vtu_flush(chip); 1708 } 1709 1710 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1711 struct mv88e6xxx_vtu_entry *entry) 1712 { 1713 int err; 1714 1715 if (!chip->info->ops->vtu_getnext) 1716 return -EOPNOTSUPP; 1717 1718 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1719 entry->valid = false; 1720 1721 err = chip->info->ops->vtu_getnext(chip, entry); 1722 1723 if (entry->vid != vid) 1724 entry->valid = false; 1725 1726 return err; 1727 } 1728 1729 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1730 int (*cb)(struct mv88e6xxx_chip *chip, 1731 const struct mv88e6xxx_vtu_entry *entry, 1732 void *priv), 1733 void *priv) 1734 { 1735 struct mv88e6xxx_vtu_entry entry = { 1736 .vid = mv88e6xxx_max_vid(chip), 1737 .valid = false, 1738 }; 1739 int err; 1740 1741 if (!chip->info->ops->vtu_getnext) 1742 return -EOPNOTSUPP; 1743 1744 do { 1745 err = chip->info->ops->vtu_getnext(chip, &entry); 1746 if (err) 1747 return err; 1748 1749 if (!entry.valid) 1750 break; 1751 1752 err = cb(chip, &entry, priv); 1753 if (err) 1754 return err; 1755 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1756 1757 return 0; 1758 } 1759 1760 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1761 struct mv88e6xxx_vtu_entry *entry) 1762 { 1763 if (!chip->info->ops->vtu_loadpurge) 1764 return -EOPNOTSUPP; 1765 1766 return chip->info->ops->vtu_loadpurge(chip, entry); 1767 } 1768 1769 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1770 const struct mv88e6xxx_vtu_entry *entry, 1771 void *_fid_bitmap) 1772 { 1773 unsigned long *fid_bitmap = _fid_bitmap; 1774 1775 set_bit(entry->fid, fid_bitmap); 1776 return 0; 1777 } 1778 1779 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1780 { 1781 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1782 1783 /* Every FID has an associated VID, so walking the VTU 1784 * will discover the full set of FIDs in use. 1785 */ 1786 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1787 } 1788 1789 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1790 { 1791 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1792 int err; 1793 1794 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1795 if (err) 1796 return err; 1797 1798 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1799 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1800 return -ENOSPC; 1801 1802 /* Clear the database */ 1803 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1804 } 1805 1806 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1807 struct mv88e6xxx_stu_entry *entry) 1808 { 1809 if (!chip->info->ops->stu_loadpurge) 1810 return -EOPNOTSUPP; 1811 1812 return chip->info->ops->stu_loadpurge(chip, entry); 1813 } 1814 1815 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1816 { 1817 struct mv88e6xxx_stu_entry stu = { 1818 .valid = true, 1819 .sid = 0 1820 }; 1821 1822 if (!mv88e6xxx_has_stu(chip)) 1823 return 0; 1824 1825 /* Make sure that SID 0 is always valid. This is used by VTU 1826 * entries that do not make use of the STU, e.g. when creating 1827 * a VLAN upper on a port that is also part of a VLAN 1828 * filtering bridge. 1829 */ 1830 return mv88e6xxx_stu_loadpurge(chip, &stu); 1831 } 1832 1833 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1834 { 1835 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1836 struct mv88e6xxx_mst *mst; 1837 1838 __set_bit(0, busy); 1839 1840 list_for_each_entry(mst, &chip->msts, node) 1841 __set_bit(mst->stu.sid, busy); 1842 1843 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1844 1845 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1846 } 1847 1848 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1849 { 1850 struct mv88e6xxx_mst *mst, *tmp; 1851 int err; 1852 1853 if (!sid) 1854 return 0; 1855 1856 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1857 if (mst->stu.sid != sid) 1858 continue; 1859 1860 if (!refcount_dec_and_test(&mst->refcnt)) 1861 return 0; 1862 1863 mst->stu.valid = false; 1864 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1865 if (err) { 1866 refcount_set(&mst->refcnt, 1); 1867 return err; 1868 } 1869 1870 list_del(&mst->node); 1871 kfree(mst); 1872 return 0; 1873 } 1874 1875 return -ENOENT; 1876 } 1877 1878 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1879 u16 msti, u8 *sid) 1880 { 1881 struct mv88e6xxx_mst *mst; 1882 int err, i; 1883 1884 if (!mv88e6xxx_has_stu(chip)) { 1885 err = -EOPNOTSUPP; 1886 goto err; 1887 } 1888 1889 if (!msti) { 1890 *sid = 0; 1891 return 0; 1892 } 1893 1894 list_for_each_entry(mst, &chip->msts, node) { 1895 if (mst->br == br && mst->msti == msti) { 1896 refcount_inc(&mst->refcnt); 1897 *sid = mst->stu.sid; 1898 return 0; 1899 } 1900 } 1901 1902 err = mv88e6xxx_sid_get(chip, sid); 1903 if (err) 1904 goto err; 1905 1906 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1907 if (!mst) { 1908 err = -ENOMEM; 1909 goto err; 1910 } 1911 1912 INIT_LIST_HEAD(&mst->node); 1913 refcount_set(&mst->refcnt, 1); 1914 mst->br = br; 1915 mst->msti = msti; 1916 mst->stu.valid = true; 1917 mst->stu.sid = *sid; 1918 1919 /* The bridge starts out all ports in the disabled state. But 1920 * a STU state of disabled means to go by the port-global 1921 * state. So we set all user port's initial state to blocking, 1922 * to match the bridge's behavior. 1923 */ 1924 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1925 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1926 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1927 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1928 1929 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1930 if (err) 1931 goto err_free; 1932 1933 list_add_tail(&mst->node, &chip->msts); 1934 return 0; 1935 1936 err_free: 1937 kfree(mst); 1938 err: 1939 return err; 1940 } 1941 1942 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1943 const struct switchdev_mst_state *st) 1944 { 1945 struct dsa_port *dp = dsa_to_port(ds, port); 1946 struct mv88e6xxx_chip *chip = ds->priv; 1947 struct mv88e6xxx_mst *mst; 1948 u8 state; 1949 int err; 1950 1951 if (!mv88e6xxx_has_stu(chip)) 1952 return -EOPNOTSUPP; 1953 1954 switch (st->state) { 1955 case BR_STATE_DISABLED: 1956 case BR_STATE_BLOCKING: 1957 case BR_STATE_LISTENING: 1958 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1959 break; 1960 case BR_STATE_LEARNING: 1961 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1962 break; 1963 case BR_STATE_FORWARDING: 1964 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1965 break; 1966 default: 1967 return -EINVAL; 1968 } 1969 1970 list_for_each_entry(mst, &chip->msts, node) { 1971 if (mst->br == dsa_port_bridge_dev_get(dp) && 1972 mst->msti == st->msti) { 1973 if (mst->stu.state[port] == state) 1974 return 0; 1975 1976 mst->stu.state[port] = state; 1977 mv88e6xxx_reg_lock(chip); 1978 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1979 mv88e6xxx_reg_unlock(chip); 1980 return err; 1981 } 1982 } 1983 1984 return -ENOENT; 1985 } 1986 1987 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1988 u16 vid) 1989 { 1990 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1991 struct mv88e6xxx_chip *chip = ds->priv; 1992 struct mv88e6xxx_vtu_entry vlan; 1993 int err; 1994 1995 /* DSA and CPU ports have to be members of multiple vlans */ 1996 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1997 return 0; 1998 1999 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2000 if (err) 2001 return err; 2002 2003 if (!vlan.valid) 2004 return 0; 2005 2006 dsa_switch_for_each_user_port(other_dp, ds) { 2007 struct net_device *other_br; 2008 2009 if (vlan.member[other_dp->index] == 2010 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2011 continue; 2012 2013 if (dsa_port_bridge_same(dp, other_dp)) 2014 break; /* same bridge, check next VLAN */ 2015 2016 other_br = dsa_port_bridge_dev_get(other_dp); 2017 if (!other_br) 2018 continue; 2019 2020 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2021 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2022 return -EOPNOTSUPP; 2023 } 2024 2025 return 0; 2026 } 2027 2028 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2029 { 2030 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2031 struct net_device *br = dsa_port_bridge_dev_get(dp); 2032 struct mv88e6xxx_port *p = &chip->ports[port]; 2033 u16 pvid = MV88E6XXX_VID_STANDALONE; 2034 bool drop_untagged = false; 2035 int err; 2036 2037 if (br) { 2038 if (br_vlan_enabled(br)) { 2039 pvid = p->bridge_pvid.vid; 2040 drop_untagged = !p->bridge_pvid.valid; 2041 } else { 2042 pvid = MV88E6XXX_VID_BRIDGED; 2043 } 2044 } 2045 2046 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2047 if (err) 2048 return err; 2049 2050 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2051 } 2052 2053 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2054 bool vlan_filtering, 2055 struct netlink_ext_ack *extack) 2056 { 2057 struct mv88e6xxx_chip *chip = ds->priv; 2058 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2059 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2060 int err; 2061 2062 if (!mv88e6xxx_max_vid(chip)) 2063 return -EOPNOTSUPP; 2064 2065 mv88e6xxx_reg_lock(chip); 2066 2067 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2068 if (err) 2069 goto unlock; 2070 2071 err = mv88e6xxx_port_commit_pvid(chip, port); 2072 if (err) 2073 goto unlock; 2074 2075 unlock: 2076 mv88e6xxx_reg_unlock(chip); 2077 2078 return err; 2079 } 2080 2081 static int 2082 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2083 const struct switchdev_obj_port_vlan *vlan) 2084 { 2085 struct mv88e6xxx_chip *chip = ds->priv; 2086 int err; 2087 2088 if (!mv88e6xxx_max_vid(chip)) 2089 return -EOPNOTSUPP; 2090 2091 /* If the requested port doesn't belong to the same bridge as the VLAN 2092 * members, do not support it (yet) and fallback to software VLAN. 2093 */ 2094 mv88e6xxx_reg_lock(chip); 2095 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2096 mv88e6xxx_reg_unlock(chip); 2097 2098 return err; 2099 } 2100 2101 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2102 const unsigned char *addr, u16 vid, 2103 u8 state) 2104 { 2105 struct mv88e6xxx_atu_entry entry; 2106 struct mv88e6xxx_vtu_entry vlan; 2107 u16 fid; 2108 int err; 2109 2110 /* Ports have two private address databases: one for when the port is 2111 * standalone and one for when the port is under a bridge and the 2112 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2113 * address database to remain 100% empty, so we never load an ATU entry 2114 * into a standalone port's database. Therefore, translate the null 2115 * VLAN ID into the port's database used for VLAN-unaware bridging. 2116 */ 2117 if (vid == 0) { 2118 fid = MV88E6XXX_FID_BRIDGED; 2119 } else { 2120 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2121 if (err) 2122 return err; 2123 2124 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2125 if (!vlan.valid) 2126 return -EOPNOTSUPP; 2127 2128 fid = vlan.fid; 2129 } 2130 2131 entry.state = 0; 2132 ether_addr_copy(entry.mac, addr); 2133 eth_addr_dec(entry.mac); 2134 2135 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2136 if (err) 2137 return err; 2138 2139 /* Initialize a fresh ATU entry if it isn't found */ 2140 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2141 memset(&entry, 0, sizeof(entry)); 2142 ether_addr_copy(entry.mac, addr); 2143 } 2144 2145 /* Purge the ATU entry only if no port is using it anymore */ 2146 if (!state) { 2147 entry.portvec &= ~BIT(port); 2148 if (!entry.portvec) 2149 entry.state = 0; 2150 } else { 2151 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2152 entry.portvec = BIT(port); 2153 else 2154 entry.portvec |= BIT(port); 2155 2156 entry.state = state; 2157 } 2158 2159 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2160 } 2161 2162 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2163 const struct mv88e6xxx_policy *policy) 2164 { 2165 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2166 enum mv88e6xxx_policy_action action = policy->action; 2167 const u8 *addr = policy->addr; 2168 u16 vid = policy->vid; 2169 u8 state; 2170 int err; 2171 int id; 2172 2173 if (!chip->info->ops->port_set_policy) 2174 return -EOPNOTSUPP; 2175 2176 switch (mapping) { 2177 case MV88E6XXX_POLICY_MAPPING_DA: 2178 case MV88E6XXX_POLICY_MAPPING_SA: 2179 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2180 state = 0; /* Dissociate the port and address */ 2181 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2182 is_multicast_ether_addr(addr)) 2183 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2184 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2185 is_unicast_ether_addr(addr)) 2186 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2187 else 2188 return -EOPNOTSUPP; 2189 2190 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2191 state); 2192 if (err) 2193 return err; 2194 break; 2195 default: 2196 return -EOPNOTSUPP; 2197 } 2198 2199 /* Skip the port's policy clearing if the mapping is still in use */ 2200 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2201 idr_for_each_entry(&chip->policies, policy, id) 2202 if (policy->port == port && 2203 policy->mapping == mapping && 2204 policy->action != action) 2205 return 0; 2206 2207 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2208 } 2209 2210 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2211 struct ethtool_rx_flow_spec *fs) 2212 { 2213 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2214 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2215 enum mv88e6xxx_policy_mapping mapping; 2216 enum mv88e6xxx_policy_action action; 2217 struct mv88e6xxx_policy *policy; 2218 u16 vid = 0; 2219 u8 *addr; 2220 int err; 2221 int id; 2222 2223 if (fs->location != RX_CLS_LOC_ANY) 2224 return -EINVAL; 2225 2226 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2227 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2228 else 2229 return -EOPNOTSUPP; 2230 2231 switch (fs->flow_type & ~FLOW_EXT) { 2232 case ETHER_FLOW: 2233 if (!is_zero_ether_addr(mac_mask->h_dest) && 2234 is_zero_ether_addr(mac_mask->h_source)) { 2235 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2236 addr = mac_entry->h_dest; 2237 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2238 !is_zero_ether_addr(mac_mask->h_source)) { 2239 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2240 addr = mac_entry->h_source; 2241 } else { 2242 /* Cannot support DA and SA mapping in the same rule */ 2243 return -EOPNOTSUPP; 2244 } 2245 break; 2246 default: 2247 return -EOPNOTSUPP; 2248 } 2249 2250 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2251 if (fs->m_ext.vlan_tci != htons(0xffff)) 2252 return -EOPNOTSUPP; 2253 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2254 } 2255 2256 idr_for_each_entry(&chip->policies, policy, id) { 2257 if (policy->port == port && policy->mapping == mapping && 2258 policy->action == action && policy->vid == vid && 2259 ether_addr_equal(policy->addr, addr)) 2260 return -EEXIST; 2261 } 2262 2263 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2264 if (!policy) 2265 return -ENOMEM; 2266 2267 fs->location = 0; 2268 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2269 GFP_KERNEL); 2270 if (err) { 2271 devm_kfree(chip->dev, policy); 2272 return err; 2273 } 2274 2275 memcpy(&policy->fs, fs, sizeof(*fs)); 2276 ether_addr_copy(policy->addr, addr); 2277 policy->mapping = mapping; 2278 policy->action = action; 2279 policy->port = port; 2280 policy->vid = vid; 2281 2282 err = mv88e6xxx_policy_apply(chip, port, policy); 2283 if (err) { 2284 idr_remove(&chip->policies, fs->location); 2285 devm_kfree(chip->dev, policy); 2286 return err; 2287 } 2288 2289 return 0; 2290 } 2291 2292 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2293 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2294 { 2295 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2296 struct mv88e6xxx_chip *chip = ds->priv; 2297 struct mv88e6xxx_policy *policy; 2298 int err; 2299 int id; 2300 2301 mv88e6xxx_reg_lock(chip); 2302 2303 switch (rxnfc->cmd) { 2304 case ETHTOOL_GRXCLSRLCNT: 2305 rxnfc->data = 0; 2306 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2307 rxnfc->rule_cnt = 0; 2308 idr_for_each_entry(&chip->policies, policy, id) 2309 if (policy->port == port) 2310 rxnfc->rule_cnt++; 2311 err = 0; 2312 break; 2313 case ETHTOOL_GRXCLSRULE: 2314 err = -ENOENT; 2315 policy = idr_find(&chip->policies, fs->location); 2316 if (policy) { 2317 memcpy(fs, &policy->fs, sizeof(*fs)); 2318 err = 0; 2319 } 2320 break; 2321 case ETHTOOL_GRXCLSRLALL: 2322 rxnfc->data = 0; 2323 rxnfc->rule_cnt = 0; 2324 idr_for_each_entry(&chip->policies, policy, id) 2325 if (policy->port == port) 2326 rule_locs[rxnfc->rule_cnt++] = id; 2327 err = 0; 2328 break; 2329 default: 2330 err = -EOPNOTSUPP; 2331 break; 2332 } 2333 2334 mv88e6xxx_reg_unlock(chip); 2335 2336 return err; 2337 } 2338 2339 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2340 struct ethtool_rxnfc *rxnfc) 2341 { 2342 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2343 struct mv88e6xxx_chip *chip = ds->priv; 2344 struct mv88e6xxx_policy *policy; 2345 int err; 2346 2347 mv88e6xxx_reg_lock(chip); 2348 2349 switch (rxnfc->cmd) { 2350 case ETHTOOL_SRXCLSRLINS: 2351 err = mv88e6xxx_policy_insert(chip, port, fs); 2352 break; 2353 case ETHTOOL_SRXCLSRLDEL: 2354 err = -ENOENT; 2355 policy = idr_remove(&chip->policies, fs->location); 2356 if (policy) { 2357 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2358 err = mv88e6xxx_policy_apply(chip, port, policy); 2359 devm_kfree(chip->dev, policy); 2360 } 2361 break; 2362 default: 2363 err = -EOPNOTSUPP; 2364 break; 2365 } 2366 2367 mv88e6xxx_reg_unlock(chip); 2368 2369 return err; 2370 } 2371 2372 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2373 u16 vid) 2374 { 2375 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2376 u8 broadcast[ETH_ALEN]; 2377 2378 eth_broadcast_addr(broadcast); 2379 2380 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2381 } 2382 2383 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2384 { 2385 int port; 2386 int err; 2387 2388 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2389 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2390 struct net_device *brport; 2391 2392 if (dsa_is_unused_port(chip->ds, port)) 2393 continue; 2394 2395 brport = dsa_port_to_bridge_port(dp); 2396 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2397 /* Skip bridged user ports where broadcast 2398 * flooding is disabled. 2399 */ 2400 continue; 2401 2402 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2403 if (err) 2404 return err; 2405 } 2406 2407 return 0; 2408 } 2409 2410 struct mv88e6xxx_port_broadcast_sync_ctx { 2411 int port; 2412 bool flood; 2413 }; 2414 2415 static int 2416 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2417 const struct mv88e6xxx_vtu_entry *vlan, 2418 void *_ctx) 2419 { 2420 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2421 u8 broadcast[ETH_ALEN]; 2422 u8 state; 2423 2424 if (ctx->flood) 2425 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2426 else 2427 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2428 2429 eth_broadcast_addr(broadcast); 2430 2431 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2432 vlan->vid, state); 2433 } 2434 2435 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2436 bool flood) 2437 { 2438 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2439 .port = port, 2440 .flood = flood, 2441 }; 2442 struct mv88e6xxx_vtu_entry vid0 = { 2443 .vid = 0, 2444 }; 2445 int err; 2446 2447 /* Update the port's private database... */ 2448 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2449 if (err) 2450 return err; 2451 2452 /* ...and the database for all VLANs. */ 2453 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2454 &ctx); 2455 } 2456 2457 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2458 u16 vid, u8 member, bool warn) 2459 { 2460 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2461 struct mv88e6xxx_vtu_entry vlan; 2462 int i, err; 2463 2464 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2465 if (err) 2466 return err; 2467 2468 if (!vlan.valid) { 2469 memset(&vlan, 0, sizeof(vlan)); 2470 2471 if (vid == MV88E6XXX_VID_STANDALONE) 2472 vlan.policy = true; 2473 2474 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2475 if (err) 2476 return err; 2477 2478 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2479 if (i == port) 2480 vlan.member[i] = member; 2481 else 2482 vlan.member[i] = non_member; 2483 2484 vlan.vid = vid; 2485 vlan.valid = true; 2486 2487 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2488 if (err) 2489 return err; 2490 2491 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2492 if (err) 2493 return err; 2494 } else if (vlan.member[port] != member) { 2495 vlan.member[port] = member; 2496 2497 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2498 if (err) 2499 return err; 2500 } else if (warn) { 2501 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2502 port, vid); 2503 } 2504 2505 return 0; 2506 } 2507 2508 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2509 const struct switchdev_obj_port_vlan *vlan, 2510 struct netlink_ext_ack *extack) 2511 { 2512 struct mv88e6xxx_chip *chip = ds->priv; 2513 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2514 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2515 struct mv88e6xxx_port *p = &chip->ports[port]; 2516 bool warn; 2517 u8 member; 2518 int err; 2519 2520 if (!vlan->vid) 2521 return 0; 2522 2523 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2524 if (err) 2525 return err; 2526 2527 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2528 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2529 else if (untagged) 2530 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2531 else 2532 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2533 2534 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2535 * and then the CPU port. Do not warn for duplicates for the CPU port. 2536 */ 2537 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2538 2539 mv88e6xxx_reg_lock(chip); 2540 2541 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2542 if (err) { 2543 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2544 vlan->vid, untagged ? 'u' : 't'); 2545 goto out; 2546 } 2547 2548 if (pvid) { 2549 p->bridge_pvid.vid = vlan->vid; 2550 p->bridge_pvid.valid = true; 2551 2552 err = mv88e6xxx_port_commit_pvid(chip, port); 2553 if (err) 2554 goto out; 2555 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2556 /* The old pvid was reinstalled as a non-pvid VLAN */ 2557 p->bridge_pvid.valid = false; 2558 2559 err = mv88e6xxx_port_commit_pvid(chip, port); 2560 if (err) 2561 goto out; 2562 } 2563 2564 out: 2565 mv88e6xxx_reg_unlock(chip); 2566 2567 return err; 2568 } 2569 2570 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2571 int port, u16 vid) 2572 { 2573 struct mv88e6xxx_vtu_entry vlan; 2574 int i, err; 2575 2576 if (!vid) 2577 return 0; 2578 2579 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2580 if (err) 2581 return err; 2582 2583 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2584 * tell switchdev that this VLAN is likely handled in software. 2585 */ 2586 if (!vlan.valid || 2587 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2588 return -EOPNOTSUPP; 2589 2590 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2591 2592 /* keep the VLAN unless all ports are excluded */ 2593 vlan.valid = false; 2594 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2595 if (vlan.member[i] != 2596 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2597 vlan.valid = true; 2598 break; 2599 } 2600 } 2601 2602 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2603 if (err) 2604 return err; 2605 2606 if (!vlan.valid) { 2607 err = mv88e6xxx_mst_put(chip, vlan.sid); 2608 if (err) 2609 return err; 2610 } 2611 2612 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2613 } 2614 2615 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2616 const struct switchdev_obj_port_vlan *vlan) 2617 { 2618 struct mv88e6xxx_chip *chip = ds->priv; 2619 struct mv88e6xxx_port *p = &chip->ports[port]; 2620 int err = 0; 2621 u16 pvid; 2622 2623 if (!mv88e6xxx_max_vid(chip)) 2624 return -EOPNOTSUPP; 2625 2626 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2627 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2628 * switchdev workqueue to ensure that all FDB entries are deleted 2629 * before we remove the VLAN. 2630 */ 2631 dsa_flush_workqueue(); 2632 2633 mv88e6xxx_reg_lock(chip); 2634 2635 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2636 if (err) 2637 goto unlock; 2638 2639 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2640 if (err) 2641 goto unlock; 2642 2643 if (vlan->vid == pvid) { 2644 p->bridge_pvid.valid = false; 2645 2646 err = mv88e6xxx_port_commit_pvid(chip, port); 2647 if (err) 2648 goto unlock; 2649 } 2650 2651 unlock: 2652 mv88e6xxx_reg_unlock(chip); 2653 2654 return err; 2655 } 2656 2657 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2658 { 2659 struct mv88e6xxx_chip *chip = ds->priv; 2660 struct mv88e6xxx_vtu_entry vlan; 2661 int err; 2662 2663 mv88e6xxx_reg_lock(chip); 2664 2665 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2666 if (err) 2667 goto unlock; 2668 2669 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2670 2671 unlock: 2672 mv88e6xxx_reg_unlock(chip); 2673 2674 return err; 2675 } 2676 2677 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2678 struct dsa_bridge bridge, 2679 const struct switchdev_vlan_msti *msti) 2680 { 2681 struct mv88e6xxx_chip *chip = ds->priv; 2682 struct mv88e6xxx_vtu_entry vlan; 2683 u8 old_sid, new_sid; 2684 int err; 2685 2686 if (!mv88e6xxx_has_stu(chip)) 2687 return -EOPNOTSUPP; 2688 2689 mv88e6xxx_reg_lock(chip); 2690 2691 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2692 if (err) 2693 goto unlock; 2694 2695 if (!vlan.valid) { 2696 err = -EINVAL; 2697 goto unlock; 2698 } 2699 2700 old_sid = vlan.sid; 2701 2702 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2703 if (err) 2704 goto unlock; 2705 2706 if (new_sid != old_sid) { 2707 vlan.sid = new_sid; 2708 2709 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2710 if (err) { 2711 mv88e6xxx_mst_put(chip, new_sid); 2712 goto unlock; 2713 } 2714 } 2715 2716 err = mv88e6xxx_mst_put(chip, old_sid); 2717 2718 unlock: 2719 mv88e6xxx_reg_unlock(chip); 2720 return err; 2721 } 2722 2723 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2724 const unsigned char *addr, u16 vid, 2725 struct dsa_db db) 2726 { 2727 struct mv88e6xxx_chip *chip = ds->priv; 2728 int err; 2729 2730 mv88e6xxx_reg_lock(chip); 2731 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2732 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2733 mv88e6xxx_reg_unlock(chip); 2734 2735 return err; 2736 } 2737 2738 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2739 const unsigned char *addr, u16 vid, 2740 struct dsa_db db) 2741 { 2742 struct mv88e6xxx_chip *chip = ds->priv; 2743 int err; 2744 2745 mv88e6xxx_reg_lock(chip); 2746 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2747 mv88e6xxx_reg_unlock(chip); 2748 2749 return err; 2750 } 2751 2752 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2753 u16 fid, u16 vid, int port, 2754 dsa_fdb_dump_cb_t *cb, void *data) 2755 { 2756 struct mv88e6xxx_atu_entry addr; 2757 bool is_static; 2758 int err; 2759 2760 addr.state = 0; 2761 eth_broadcast_addr(addr.mac); 2762 2763 do { 2764 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2765 if (err) 2766 return err; 2767 2768 if (!addr.state) 2769 break; 2770 2771 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2772 continue; 2773 2774 if (!is_unicast_ether_addr(addr.mac)) 2775 continue; 2776 2777 is_static = (addr.state == 2778 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2779 err = cb(addr.mac, vid, is_static, data); 2780 if (err) 2781 return err; 2782 } while (!is_broadcast_ether_addr(addr.mac)); 2783 2784 return err; 2785 } 2786 2787 struct mv88e6xxx_port_db_dump_vlan_ctx { 2788 int port; 2789 dsa_fdb_dump_cb_t *cb; 2790 void *data; 2791 }; 2792 2793 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2794 const struct mv88e6xxx_vtu_entry *entry, 2795 void *_data) 2796 { 2797 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2798 2799 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2800 ctx->port, ctx->cb, ctx->data); 2801 } 2802 2803 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2804 dsa_fdb_dump_cb_t *cb, void *data) 2805 { 2806 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2807 .port = port, 2808 .cb = cb, 2809 .data = data, 2810 }; 2811 u16 fid; 2812 int err; 2813 2814 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2815 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2816 if (err) 2817 return err; 2818 2819 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2820 if (err) 2821 return err; 2822 2823 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2824 } 2825 2826 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2827 dsa_fdb_dump_cb_t *cb, void *data) 2828 { 2829 struct mv88e6xxx_chip *chip = ds->priv; 2830 int err; 2831 2832 mv88e6xxx_reg_lock(chip); 2833 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2834 mv88e6xxx_reg_unlock(chip); 2835 2836 return err; 2837 } 2838 2839 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2840 struct dsa_bridge bridge) 2841 { 2842 struct dsa_switch *ds = chip->ds; 2843 struct dsa_switch_tree *dst = ds->dst; 2844 struct dsa_port *dp; 2845 int err; 2846 2847 list_for_each_entry(dp, &dst->ports, list) { 2848 if (dsa_port_offloads_bridge(dp, &bridge)) { 2849 if (dp->ds == ds) { 2850 /* This is a local bridge group member, 2851 * remap its Port VLAN Map. 2852 */ 2853 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2854 if (err) 2855 return err; 2856 } else { 2857 /* This is an external bridge group member, 2858 * remap its cross-chip Port VLAN Table entry. 2859 */ 2860 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2861 dp->index); 2862 if (err) 2863 return err; 2864 } 2865 } 2866 } 2867 2868 return 0; 2869 } 2870 2871 /* Treat the software bridge as a virtual single-port switch behind the 2872 * CPU and map in the PVT. First dst->last_switch elements are taken by 2873 * physical switches, so start from beyond that range. 2874 */ 2875 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2876 unsigned int bridge_num) 2877 { 2878 u8 dev = bridge_num + ds->dst->last_switch; 2879 struct mv88e6xxx_chip *chip = ds->priv; 2880 2881 return mv88e6xxx_pvt_map(chip, dev, 0); 2882 } 2883 2884 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2885 struct dsa_bridge bridge, 2886 bool *tx_fwd_offload, 2887 struct netlink_ext_ack *extack) 2888 { 2889 struct mv88e6xxx_chip *chip = ds->priv; 2890 int err; 2891 2892 mv88e6xxx_reg_lock(chip); 2893 2894 err = mv88e6xxx_bridge_map(chip, bridge); 2895 if (err) 2896 goto unlock; 2897 2898 err = mv88e6xxx_port_set_map_da(chip, port, true); 2899 if (err) 2900 goto unlock; 2901 2902 err = mv88e6xxx_port_commit_pvid(chip, port); 2903 if (err) 2904 goto unlock; 2905 2906 if (mv88e6xxx_has_pvt(chip)) { 2907 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2908 if (err) 2909 goto unlock; 2910 2911 *tx_fwd_offload = true; 2912 } 2913 2914 unlock: 2915 mv88e6xxx_reg_unlock(chip); 2916 2917 return err; 2918 } 2919 2920 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2921 struct dsa_bridge bridge) 2922 { 2923 struct mv88e6xxx_chip *chip = ds->priv; 2924 int err; 2925 2926 mv88e6xxx_reg_lock(chip); 2927 2928 if (bridge.tx_fwd_offload && 2929 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2930 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2931 2932 if (mv88e6xxx_bridge_map(chip, bridge) || 2933 mv88e6xxx_port_vlan_map(chip, port)) 2934 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2935 2936 err = mv88e6xxx_port_set_map_da(chip, port, false); 2937 if (err) 2938 dev_err(ds->dev, 2939 "port %d failed to restore map-DA: %pe\n", 2940 port, ERR_PTR(err)); 2941 2942 err = mv88e6xxx_port_commit_pvid(chip, port); 2943 if (err) 2944 dev_err(ds->dev, 2945 "port %d failed to restore standalone pvid: %pe\n", 2946 port, ERR_PTR(err)); 2947 2948 mv88e6xxx_reg_unlock(chip); 2949 } 2950 2951 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2952 int tree_index, int sw_index, 2953 int port, struct dsa_bridge bridge, 2954 struct netlink_ext_ack *extack) 2955 { 2956 struct mv88e6xxx_chip *chip = ds->priv; 2957 int err; 2958 2959 if (tree_index != ds->dst->index) 2960 return 0; 2961 2962 mv88e6xxx_reg_lock(chip); 2963 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2964 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2965 mv88e6xxx_reg_unlock(chip); 2966 2967 return err; 2968 } 2969 2970 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2971 int tree_index, int sw_index, 2972 int port, struct dsa_bridge bridge) 2973 { 2974 struct mv88e6xxx_chip *chip = ds->priv; 2975 2976 if (tree_index != ds->dst->index) 2977 return; 2978 2979 mv88e6xxx_reg_lock(chip); 2980 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2981 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2982 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2983 mv88e6xxx_reg_unlock(chip); 2984 } 2985 2986 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2987 { 2988 if (chip->info->ops->reset) 2989 return chip->info->ops->reset(chip); 2990 2991 return 0; 2992 } 2993 2994 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2995 { 2996 struct gpio_desc *gpiod = chip->reset; 2997 2998 /* If there is a GPIO connected to the reset pin, toggle it */ 2999 if (gpiod) { 3000 gpiod_set_value_cansleep(gpiod, 1); 3001 usleep_range(10000, 20000); 3002 gpiod_set_value_cansleep(gpiod, 0); 3003 usleep_range(10000, 20000); 3004 3005 mv88e6xxx_g1_wait_eeprom_done(chip); 3006 } 3007 } 3008 3009 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3010 { 3011 int i, err; 3012 3013 /* Set all ports to the Disabled state */ 3014 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3015 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3016 if (err) 3017 return err; 3018 } 3019 3020 /* Wait for transmit queues to drain, 3021 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3022 */ 3023 usleep_range(2000, 4000); 3024 3025 return 0; 3026 } 3027 3028 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3029 { 3030 int err; 3031 3032 err = mv88e6xxx_disable_ports(chip); 3033 if (err) 3034 return err; 3035 3036 mv88e6xxx_hardware_reset(chip); 3037 3038 return mv88e6xxx_software_reset(chip); 3039 } 3040 3041 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3042 enum mv88e6xxx_frame_mode frame, 3043 enum mv88e6xxx_egress_mode egress, u16 etype) 3044 { 3045 int err; 3046 3047 if (!chip->info->ops->port_set_frame_mode) 3048 return -EOPNOTSUPP; 3049 3050 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3051 if (err) 3052 return err; 3053 3054 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3055 if (err) 3056 return err; 3057 3058 if (chip->info->ops->port_set_ether_type) 3059 return chip->info->ops->port_set_ether_type(chip, port, etype); 3060 3061 return 0; 3062 } 3063 3064 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3065 { 3066 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3067 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3068 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3069 } 3070 3071 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3072 { 3073 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3074 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3075 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3076 } 3077 3078 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3079 { 3080 return mv88e6xxx_set_port_mode(chip, port, 3081 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3082 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3083 ETH_P_EDSA); 3084 } 3085 3086 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3087 { 3088 if (dsa_is_dsa_port(chip->ds, port)) 3089 return mv88e6xxx_set_port_mode_dsa(chip, port); 3090 3091 if (dsa_is_user_port(chip->ds, port)) 3092 return mv88e6xxx_set_port_mode_normal(chip, port); 3093 3094 /* Setup CPU port mode depending on its supported tag format */ 3095 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3096 return mv88e6xxx_set_port_mode_dsa(chip, port); 3097 3098 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3099 return mv88e6xxx_set_port_mode_edsa(chip, port); 3100 3101 return -EINVAL; 3102 } 3103 3104 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3105 { 3106 bool message = dsa_is_dsa_port(chip->ds, port); 3107 3108 return mv88e6xxx_port_set_message_port(chip, port, message); 3109 } 3110 3111 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3112 { 3113 int err; 3114 3115 if (chip->info->ops->port_set_ucast_flood) { 3116 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3117 if (err) 3118 return err; 3119 } 3120 if (chip->info->ops->port_set_mcast_flood) { 3121 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3122 if (err) 3123 return err; 3124 } 3125 3126 return 0; 3127 } 3128 3129 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3130 { 3131 struct mv88e6xxx_port *mvp = dev_id; 3132 struct mv88e6xxx_chip *chip = mvp->chip; 3133 irqreturn_t ret = IRQ_NONE; 3134 int port = mvp->port; 3135 int lane; 3136 3137 mv88e6xxx_reg_lock(chip); 3138 lane = mv88e6xxx_serdes_get_lane(chip, port); 3139 if (lane >= 0) 3140 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3141 mv88e6xxx_reg_unlock(chip); 3142 3143 return ret; 3144 } 3145 3146 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3147 int lane) 3148 { 3149 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3150 unsigned int irq; 3151 int err; 3152 3153 /* Nothing to request if this SERDES port has no IRQ */ 3154 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3155 if (!irq) 3156 return 0; 3157 3158 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3159 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3160 3161 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3162 mv88e6xxx_reg_unlock(chip); 3163 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3164 IRQF_ONESHOT, dev_id->serdes_irq_name, 3165 dev_id); 3166 mv88e6xxx_reg_lock(chip); 3167 if (err) 3168 return err; 3169 3170 dev_id->serdes_irq = irq; 3171 3172 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3173 } 3174 3175 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3176 int lane) 3177 { 3178 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3179 unsigned int irq = dev_id->serdes_irq; 3180 int err; 3181 3182 /* Nothing to free if no IRQ has been requested */ 3183 if (!irq) 3184 return 0; 3185 3186 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3187 3188 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3189 mv88e6xxx_reg_unlock(chip); 3190 free_irq(irq, dev_id); 3191 mv88e6xxx_reg_lock(chip); 3192 3193 dev_id->serdes_irq = 0; 3194 3195 return err; 3196 } 3197 3198 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3199 bool on) 3200 { 3201 int lane; 3202 int err; 3203 3204 lane = mv88e6xxx_serdes_get_lane(chip, port); 3205 if (lane < 0) 3206 return 0; 3207 3208 if (on) { 3209 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3210 if (err) 3211 return err; 3212 3213 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3214 } else { 3215 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3216 if (err) 3217 return err; 3218 3219 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3220 } 3221 3222 return err; 3223 } 3224 3225 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3226 enum mv88e6xxx_egress_direction direction, 3227 int port) 3228 { 3229 int err; 3230 3231 if (!chip->info->ops->set_egress_port) 3232 return -EOPNOTSUPP; 3233 3234 err = chip->info->ops->set_egress_port(chip, direction, port); 3235 if (err) 3236 return err; 3237 3238 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3239 chip->ingress_dest_port = port; 3240 else 3241 chip->egress_dest_port = port; 3242 3243 return 0; 3244 } 3245 3246 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3247 { 3248 struct dsa_switch *ds = chip->ds; 3249 int upstream_port; 3250 int err; 3251 3252 upstream_port = dsa_upstream_port(ds, port); 3253 if (chip->info->ops->port_set_upstream_port) { 3254 err = chip->info->ops->port_set_upstream_port(chip, port, 3255 upstream_port); 3256 if (err) 3257 return err; 3258 } 3259 3260 if (port == upstream_port) { 3261 if (chip->info->ops->set_cpu_port) { 3262 err = chip->info->ops->set_cpu_port(chip, 3263 upstream_port); 3264 if (err) 3265 return err; 3266 } 3267 3268 err = mv88e6xxx_set_egress_port(chip, 3269 MV88E6XXX_EGRESS_DIR_INGRESS, 3270 upstream_port); 3271 if (err && err != -EOPNOTSUPP) 3272 return err; 3273 3274 err = mv88e6xxx_set_egress_port(chip, 3275 MV88E6XXX_EGRESS_DIR_EGRESS, 3276 upstream_port); 3277 if (err && err != -EOPNOTSUPP) 3278 return err; 3279 } 3280 3281 return 0; 3282 } 3283 3284 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3285 { 3286 struct device_node *phy_handle = NULL; 3287 struct dsa_switch *ds = chip->ds; 3288 phy_interface_t mode; 3289 struct dsa_port *dp; 3290 int tx_amp, speed; 3291 int err; 3292 u16 reg; 3293 3294 chip->ports[port].chip = chip; 3295 chip->ports[port].port = port; 3296 3297 dp = dsa_to_port(ds, port); 3298 3299 /* MAC Forcing register: don't force link, speed, duplex or flow control 3300 * state to any particular values on physical ports, but force the CPU 3301 * port and all DSA ports to their maximum bandwidth and full duplex. 3302 */ 3303 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 3304 struct phylink_config pl_config = {}; 3305 unsigned long caps; 3306 3307 mv88e6xxx_get_caps(ds, port, &pl_config); 3308 3309 caps = pl_config.mac_capabilities; 3310 3311 if (chip->info->ops->port_max_speed_mode) 3312 mode = chip->info->ops->port_max_speed_mode(port); 3313 else 3314 mode = PHY_INTERFACE_MODE_NA; 3315 3316 if (caps & MAC_10000FD) 3317 speed = SPEED_10000; 3318 else if (caps & MAC_5000FD) 3319 speed = SPEED_5000; 3320 else if (caps & MAC_2500FD) 3321 speed = SPEED_2500; 3322 else if (caps & MAC_1000) 3323 speed = SPEED_1000; 3324 else if (caps & MAC_100) 3325 speed = SPEED_100; 3326 else 3327 speed = SPEED_10; 3328 3329 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3330 speed, DUPLEX_FULL, 3331 PAUSE_OFF, mode); 3332 } else { 3333 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3334 SPEED_UNFORCED, DUPLEX_UNFORCED, 3335 PAUSE_ON, 3336 PHY_INTERFACE_MODE_NA); 3337 } 3338 if (err) 3339 return err; 3340 3341 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3342 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3343 * tunneling, determine priority by looking at 802.1p and IP 3344 * priority fields (IP prio has precedence), and set STP state 3345 * to Forwarding. 3346 * 3347 * If this is the CPU link, use DSA or EDSA tagging depending 3348 * on which tagging mode was configured. 3349 * 3350 * If this is a link to another switch, use DSA tagging mode. 3351 * 3352 * If this is the upstream port for this switch, enable 3353 * forwarding of unknown unicasts and multicasts. 3354 */ 3355 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 3356 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3357 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3358 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3359 if (err) 3360 return err; 3361 3362 err = mv88e6xxx_setup_port_mode(chip, port); 3363 if (err) 3364 return err; 3365 3366 err = mv88e6xxx_setup_egress_floods(chip, port); 3367 if (err) 3368 return err; 3369 3370 /* Port Control 2: don't force a good FCS, set the MTU size to 3371 * 10222 bytes, disable 802.1q tags checking, don't discard 3372 * tagged or untagged frames on this port, skip destination 3373 * address lookup on user ports, disable ARP mirroring and don't 3374 * send a copy of all transmitted/received frames on this port 3375 * to the CPU. 3376 */ 3377 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3378 if (err) 3379 return err; 3380 3381 err = mv88e6xxx_setup_upstream_port(chip, port); 3382 if (err) 3383 return err; 3384 3385 /* On chips that support it, set all downstream DSA ports' 3386 * VLAN policy to TRAP. In combination with loading 3387 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3388 * provides a better isolation barrier between standalone 3389 * ports, as the ATU is bypassed on any intermediate switches 3390 * between the incoming port and the CPU. 3391 */ 3392 if (dsa_is_downstream_port(ds, port) && 3393 chip->info->ops->port_set_policy) { 3394 err = chip->info->ops->port_set_policy(chip, port, 3395 MV88E6XXX_POLICY_MAPPING_VTU, 3396 MV88E6XXX_POLICY_ACTION_TRAP); 3397 if (err) 3398 return err; 3399 } 3400 3401 /* User ports start out in standalone mode and 802.1Q is 3402 * therefore disabled. On DSA ports, all valid VIDs are always 3403 * loaded in the VTU - therefore, enable 802.1Q in order to take 3404 * advantage of VLAN policy on chips that supports it. 3405 */ 3406 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3407 dsa_is_user_port(ds, port) ? 3408 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3409 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3410 if (err) 3411 return err; 3412 3413 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3414 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3415 * the first free FID. This will be used as the private PVID for 3416 * unbridged ports. Shared (DSA and CPU) ports must also be 3417 * members of this VID, in order to trap all frames assigned to 3418 * it to the CPU. 3419 */ 3420 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3421 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3422 false); 3423 if (err) 3424 return err; 3425 3426 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3427 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3428 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3429 * as the private PVID on ports under a VLAN-unaware bridge. 3430 * Shared (DSA and CPU) ports must also be members of it, to translate 3431 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3432 * relying on their port default FID. 3433 */ 3434 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3435 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3436 false); 3437 if (err) 3438 return err; 3439 3440 if (chip->info->ops->port_set_jumbo_size) { 3441 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3442 if (err) 3443 return err; 3444 } 3445 3446 /* Port Association Vector: disable automatic address learning 3447 * on all user ports since they start out in standalone 3448 * mode. When joining a bridge, learning will be configured to 3449 * match the bridge port settings. Enable learning on all 3450 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3451 * learning process. 3452 * 3453 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3454 * and RefreshLocked. I.e. setup standard automatic learning. 3455 */ 3456 if (dsa_is_user_port(ds, port)) 3457 reg = 0; 3458 else 3459 reg = 1 << port; 3460 3461 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3462 reg); 3463 if (err) 3464 return err; 3465 3466 /* Egress rate control 2: disable egress rate control. */ 3467 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3468 0x0000); 3469 if (err) 3470 return err; 3471 3472 if (chip->info->ops->port_pause_limit) { 3473 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3474 if (err) 3475 return err; 3476 } 3477 3478 if (chip->info->ops->port_disable_learn_limit) { 3479 err = chip->info->ops->port_disable_learn_limit(chip, port); 3480 if (err) 3481 return err; 3482 } 3483 3484 if (chip->info->ops->port_disable_pri_override) { 3485 err = chip->info->ops->port_disable_pri_override(chip, port); 3486 if (err) 3487 return err; 3488 } 3489 3490 if (chip->info->ops->port_tag_remap) { 3491 err = chip->info->ops->port_tag_remap(chip, port); 3492 if (err) 3493 return err; 3494 } 3495 3496 if (chip->info->ops->port_egress_rate_limiting) { 3497 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3498 if (err) 3499 return err; 3500 } 3501 3502 if (chip->info->ops->port_setup_message_port) { 3503 err = chip->info->ops->port_setup_message_port(chip, port); 3504 if (err) 3505 return err; 3506 } 3507 3508 if (chip->info->ops->serdes_set_tx_amplitude) { 3509 if (dp) 3510 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3511 3512 if (phy_handle && !of_property_read_u32(phy_handle, 3513 "tx-p2p-microvolt", 3514 &tx_amp)) 3515 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3516 port, tx_amp); 3517 if (phy_handle) { 3518 of_node_put(phy_handle); 3519 if (err) 3520 return err; 3521 } 3522 } 3523 3524 /* Port based VLAN map: give each port the same default address 3525 * database, and allow bidirectional communication between the 3526 * CPU and DSA port(s), and the other ports. 3527 */ 3528 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3529 if (err) 3530 return err; 3531 3532 err = mv88e6xxx_port_vlan_map(chip, port); 3533 if (err) 3534 return err; 3535 3536 /* Default VLAN ID and priority: don't set a default VLAN 3537 * ID, and set the default packet priority to zero. 3538 */ 3539 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3540 } 3541 3542 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3543 { 3544 struct mv88e6xxx_chip *chip = ds->priv; 3545 3546 if (chip->info->ops->port_set_jumbo_size) 3547 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3548 else if (chip->info->ops->set_max_frame_size) 3549 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3550 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3551 } 3552 3553 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3554 { 3555 struct mv88e6xxx_chip *chip = ds->priv; 3556 int ret = 0; 3557 3558 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3559 new_mtu += EDSA_HLEN; 3560 3561 mv88e6xxx_reg_lock(chip); 3562 if (chip->info->ops->port_set_jumbo_size) 3563 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3564 else if (chip->info->ops->set_max_frame_size) 3565 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3566 else 3567 if (new_mtu > 1522) 3568 ret = -EINVAL; 3569 mv88e6xxx_reg_unlock(chip); 3570 3571 return ret; 3572 } 3573 3574 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3575 struct phy_device *phydev) 3576 { 3577 struct mv88e6xxx_chip *chip = ds->priv; 3578 int err; 3579 3580 mv88e6xxx_reg_lock(chip); 3581 err = mv88e6xxx_serdes_power(chip, port, true); 3582 mv88e6xxx_reg_unlock(chip); 3583 3584 return err; 3585 } 3586 3587 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3588 { 3589 struct mv88e6xxx_chip *chip = ds->priv; 3590 3591 mv88e6xxx_reg_lock(chip); 3592 if (mv88e6xxx_serdes_power(chip, port, false)) 3593 dev_err(chip->dev, "failed to power off SERDES\n"); 3594 mv88e6xxx_reg_unlock(chip); 3595 } 3596 3597 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3598 unsigned int ageing_time) 3599 { 3600 struct mv88e6xxx_chip *chip = ds->priv; 3601 int err; 3602 3603 mv88e6xxx_reg_lock(chip); 3604 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3605 mv88e6xxx_reg_unlock(chip); 3606 3607 return err; 3608 } 3609 3610 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3611 { 3612 int err; 3613 3614 /* Initialize the statistics unit */ 3615 if (chip->info->ops->stats_set_histogram) { 3616 err = chip->info->ops->stats_set_histogram(chip); 3617 if (err) 3618 return err; 3619 } 3620 3621 return mv88e6xxx_g1_stats_clear(chip); 3622 } 3623 3624 /* Check if the errata has already been applied. */ 3625 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3626 { 3627 int port; 3628 int err; 3629 u16 val; 3630 3631 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3632 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3633 if (err) { 3634 dev_err(chip->dev, 3635 "Error reading hidden register: %d\n", err); 3636 return false; 3637 } 3638 if (val != 0x01c0) 3639 return false; 3640 } 3641 3642 return true; 3643 } 3644 3645 /* The 6390 copper ports have an errata which require poking magic 3646 * values into undocumented hidden registers and then performing a 3647 * software reset. 3648 */ 3649 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3650 { 3651 int port; 3652 int err; 3653 3654 if (mv88e6390_setup_errata_applied(chip)) 3655 return 0; 3656 3657 /* Set the ports into blocking mode */ 3658 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3659 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3660 if (err) 3661 return err; 3662 } 3663 3664 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3665 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3666 if (err) 3667 return err; 3668 } 3669 3670 return mv88e6xxx_software_reset(chip); 3671 } 3672 3673 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3674 { 3675 mv88e6xxx_teardown_devlink_params(ds); 3676 dsa_devlink_resources_unregister(ds); 3677 mv88e6xxx_teardown_devlink_regions_global(ds); 3678 } 3679 3680 static int mv88e6xxx_setup(struct dsa_switch *ds) 3681 { 3682 struct mv88e6xxx_chip *chip = ds->priv; 3683 u8 cmode; 3684 int err; 3685 int i; 3686 3687 chip->ds = ds; 3688 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3689 3690 /* Since virtual bridges are mapped in the PVT, the number we support 3691 * depends on the physical switch topology. We need to let DSA figure 3692 * that out and therefore we cannot set this at dsa_register_switch() 3693 * time. 3694 */ 3695 if (mv88e6xxx_has_pvt(chip)) 3696 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3697 ds->dst->last_switch - 1; 3698 3699 mv88e6xxx_reg_lock(chip); 3700 3701 if (chip->info->ops->setup_errata) { 3702 err = chip->info->ops->setup_errata(chip); 3703 if (err) 3704 goto unlock; 3705 } 3706 3707 /* Cache the cmode of each port. */ 3708 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3709 if (chip->info->ops->port_get_cmode) { 3710 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3711 if (err) 3712 goto unlock; 3713 3714 chip->ports[i].cmode = cmode; 3715 } 3716 } 3717 3718 err = mv88e6xxx_vtu_setup(chip); 3719 if (err) 3720 goto unlock; 3721 3722 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3723 * VTU, thereby also flushing the STU). 3724 */ 3725 err = mv88e6xxx_stu_setup(chip); 3726 if (err) 3727 goto unlock; 3728 3729 /* Setup Switch Port Registers */ 3730 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3731 if (dsa_is_unused_port(ds, i)) 3732 continue; 3733 3734 /* Prevent the use of an invalid port. */ 3735 if (mv88e6xxx_is_invalid_port(chip, i)) { 3736 dev_err(chip->dev, "port %d is invalid\n", i); 3737 err = -EINVAL; 3738 goto unlock; 3739 } 3740 3741 err = mv88e6xxx_setup_port(chip, i); 3742 if (err) 3743 goto unlock; 3744 } 3745 3746 err = mv88e6xxx_irl_setup(chip); 3747 if (err) 3748 goto unlock; 3749 3750 err = mv88e6xxx_mac_setup(chip); 3751 if (err) 3752 goto unlock; 3753 3754 err = mv88e6xxx_phy_setup(chip); 3755 if (err) 3756 goto unlock; 3757 3758 err = mv88e6xxx_pvt_setup(chip); 3759 if (err) 3760 goto unlock; 3761 3762 err = mv88e6xxx_atu_setup(chip); 3763 if (err) 3764 goto unlock; 3765 3766 err = mv88e6xxx_broadcast_setup(chip, 0); 3767 if (err) 3768 goto unlock; 3769 3770 err = mv88e6xxx_pot_setup(chip); 3771 if (err) 3772 goto unlock; 3773 3774 err = mv88e6xxx_rmu_setup(chip); 3775 if (err) 3776 goto unlock; 3777 3778 err = mv88e6xxx_rsvd2cpu_setup(chip); 3779 if (err) 3780 goto unlock; 3781 3782 err = mv88e6xxx_trunk_setup(chip); 3783 if (err) 3784 goto unlock; 3785 3786 err = mv88e6xxx_devmap_setup(chip); 3787 if (err) 3788 goto unlock; 3789 3790 err = mv88e6xxx_pri_setup(chip); 3791 if (err) 3792 goto unlock; 3793 3794 /* Setup PTP Hardware Clock and timestamping */ 3795 if (chip->info->ptp_support) { 3796 err = mv88e6xxx_ptp_setup(chip); 3797 if (err) 3798 goto unlock; 3799 3800 err = mv88e6xxx_hwtstamp_setup(chip); 3801 if (err) 3802 goto unlock; 3803 } 3804 3805 err = mv88e6xxx_stats_setup(chip); 3806 if (err) 3807 goto unlock; 3808 3809 unlock: 3810 mv88e6xxx_reg_unlock(chip); 3811 3812 if (err) 3813 return err; 3814 3815 /* Have to be called without holding the register lock, since 3816 * they take the devlink lock, and we later take the locks in 3817 * the reverse order when getting/setting parameters or 3818 * resource occupancy. 3819 */ 3820 err = mv88e6xxx_setup_devlink_resources(ds); 3821 if (err) 3822 return err; 3823 3824 err = mv88e6xxx_setup_devlink_params(ds); 3825 if (err) 3826 goto out_resources; 3827 3828 err = mv88e6xxx_setup_devlink_regions_global(ds); 3829 if (err) 3830 goto out_params; 3831 3832 return 0; 3833 3834 out_params: 3835 mv88e6xxx_teardown_devlink_params(ds); 3836 out_resources: 3837 dsa_devlink_resources_unregister(ds); 3838 3839 return err; 3840 } 3841 3842 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3843 { 3844 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3845 } 3846 3847 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3848 { 3849 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3850 } 3851 3852 /* prod_id for switch families which do not have a PHY model number */ 3853 static const u16 family_prod_id_table[] = { 3854 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3855 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3856 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3857 }; 3858 3859 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3860 { 3861 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3862 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3863 u16 prod_id; 3864 u16 val; 3865 int err; 3866 3867 if (!chip->info->ops->phy_read) 3868 return -EOPNOTSUPP; 3869 3870 mv88e6xxx_reg_lock(chip); 3871 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3872 mv88e6xxx_reg_unlock(chip); 3873 3874 /* Some internal PHYs don't have a model number. */ 3875 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3876 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3877 prod_id = family_prod_id_table[chip->info->family]; 3878 if (prod_id) 3879 val |= prod_id >> 4; 3880 } 3881 3882 return err ? err : val; 3883 } 3884 3885 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3886 { 3887 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3888 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3889 int err; 3890 3891 if (!chip->info->ops->phy_write) 3892 return -EOPNOTSUPP; 3893 3894 mv88e6xxx_reg_lock(chip); 3895 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3896 mv88e6xxx_reg_unlock(chip); 3897 3898 return err; 3899 } 3900 3901 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3902 struct device_node *np, 3903 bool external) 3904 { 3905 static int index; 3906 struct mv88e6xxx_mdio_bus *mdio_bus; 3907 struct mii_bus *bus; 3908 int err; 3909 3910 if (external) { 3911 mv88e6xxx_reg_lock(chip); 3912 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3913 mv88e6xxx_reg_unlock(chip); 3914 3915 if (err) 3916 return err; 3917 } 3918 3919 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3920 if (!bus) 3921 return -ENOMEM; 3922 3923 mdio_bus = bus->priv; 3924 mdio_bus->bus = bus; 3925 mdio_bus->chip = chip; 3926 INIT_LIST_HEAD(&mdio_bus->list); 3927 mdio_bus->external = external; 3928 3929 if (np) { 3930 bus->name = np->full_name; 3931 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3932 } else { 3933 bus->name = "mv88e6xxx SMI"; 3934 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3935 } 3936 3937 bus->read = mv88e6xxx_mdio_read; 3938 bus->write = mv88e6xxx_mdio_write; 3939 bus->parent = chip->dev; 3940 3941 if (!external) { 3942 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3943 if (err) 3944 goto out; 3945 } 3946 3947 err = of_mdiobus_register(bus, np); 3948 if (err) { 3949 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3950 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3951 goto out; 3952 } 3953 3954 if (external) 3955 list_add_tail(&mdio_bus->list, &chip->mdios); 3956 else 3957 list_add(&mdio_bus->list, &chip->mdios); 3958 3959 return 0; 3960 3961 out: 3962 mdiobus_free(bus); 3963 return err; 3964 } 3965 3966 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3967 3968 { 3969 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3970 struct mii_bus *bus; 3971 3972 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3973 bus = mdio_bus->bus; 3974 3975 if (!mdio_bus->external) 3976 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3977 3978 mdiobus_unregister(bus); 3979 mdiobus_free(bus); 3980 } 3981 } 3982 3983 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3984 struct device_node *np) 3985 { 3986 struct device_node *child; 3987 int err; 3988 3989 /* Always register one mdio bus for the internal/default mdio 3990 * bus. This maybe represented in the device tree, but is 3991 * optional. 3992 */ 3993 child = of_get_child_by_name(np, "mdio"); 3994 err = mv88e6xxx_mdio_register(chip, child, false); 3995 of_node_put(child); 3996 if (err) 3997 return err; 3998 3999 /* Walk the device tree, and see if there are any other nodes 4000 * which say they are compatible with the external mdio 4001 * bus. 4002 */ 4003 for_each_available_child_of_node(np, child) { 4004 if (of_device_is_compatible( 4005 child, "marvell,mv88e6xxx-mdio-external")) { 4006 err = mv88e6xxx_mdio_register(chip, child, true); 4007 if (err) { 4008 mv88e6xxx_mdios_unregister(chip); 4009 of_node_put(child); 4010 return err; 4011 } 4012 } 4013 } 4014 4015 return 0; 4016 } 4017 4018 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4019 { 4020 struct mv88e6xxx_chip *chip = ds->priv; 4021 4022 return chip->eeprom_len; 4023 } 4024 4025 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4026 struct ethtool_eeprom *eeprom, u8 *data) 4027 { 4028 struct mv88e6xxx_chip *chip = ds->priv; 4029 int err; 4030 4031 if (!chip->info->ops->get_eeprom) 4032 return -EOPNOTSUPP; 4033 4034 mv88e6xxx_reg_lock(chip); 4035 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4036 mv88e6xxx_reg_unlock(chip); 4037 4038 if (err) 4039 return err; 4040 4041 eeprom->magic = 0xc3ec4951; 4042 4043 return 0; 4044 } 4045 4046 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4047 struct ethtool_eeprom *eeprom, u8 *data) 4048 { 4049 struct mv88e6xxx_chip *chip = ds->priv; 4050 int err; 4051 4052 if (!chip->info->ops->set_eeprom) 4053 return -EOPNOTSUPP; 4054 4055 if (eeprom->magic != 0xc3ec4951) 4056 return -EINVAL; 4057 4058 mv88e6xxx_reg_lock(chip); 4059 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4060 mv88e6xxx_reg_unlock(chip); 4061 4062 return err; 4063 } 4064 4065 static const struct mv88e6xxx_ops mv88e6085_ops = { 4066 /* MV88E6XXX_FAMILY_6097 */ 4067 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4068 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4069 .irl_init_all = mv88e6352_g2_irl_init_all, 4070 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4071 .phy_read = mv88e6185_phy_ppu_read, 4072 .phy_write = mv88e6185_phy_ppu_write, 4073 .port_set_link = mv88e6xxx_port_set_link, 4074 .port_sync_link = mv88e6xxx_port_sync_link, 4075 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4076 .port_tag_remap = mv88e6095_port_tag_remap, 4077 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4078 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4079 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4080 .port_set_ether_type = mv88e6351_port_set_ether_type, 4081 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4082 .port_pause_limit = mv88e6097_port_pause_limit, 4083 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4084 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4085 .port_get_cmode = mv88e6185_port_get_cmode, 4086 .port_setup_message_port = mv88e6xxx_setup_message_port, 4087 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4088 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4089 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4090 .stats_get_strings = mv88e6095_stats_get_strings, 4091 .stats_get_stats = mv88e6095_stats_get_stats, 4092 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4093 .set_egress_port = mv88e6095_g1_set_egress_port, 4094 .watchdog_ops = &mv88e6097_watchdog_ops, 4095 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4096 .pot_clear = mv88e6xxx_g2_pot_clear, 4097 .ppu_enable = mv88e6185_g1_ppu_enable, 4098 .ppu_disable = mv88e6185_g1_ppu_disable, 4099 .reset = mv88e6185_g1_reset, 4100 .rmu_disable = mv88e6085_g1_rmu_disable, 4101 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4102 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4103 .stu_getnext = mv88e6352_g1_stu_getnext, 4104 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4105 .phylink_get_caps = mv88e6185_phylink_get_caps, 4106 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4107 }; 4108 4109 static const struct mv88e6xxx_ops mv88e6095_ops = { 4110 /* MV88E6XXX_FAMILY_6095 */ 4111 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4112 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4113 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4114 .phy_read = mv88e6185_phy_ppu_read, 4115 .phy_write = mv88e6185_phy_ppu_write, 4116 .port_set_link = mv88e6xxx_port_set_link, 4117 .port_sync_link = mv88e6185_port_sync_link, 4118 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4119 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4120 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4121 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4122 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4123 .port_get_cmode = mv88e6185_port_get_cmode, 4124 .port_setup_message_port = mv88e6xxx_setup_message_port, 4125 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4126 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4127 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4128 .stats_get_strings = mv88e6095_stats_get_strings, 4129 .stats_get_stats = mv88e6095_stats_get_stats, 4130 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4131 .serdes_power = mv88e6185_serdes_power, 4132 .serdes_get_lane = mv88e6185_serdes_get_lane, 4133 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4134 .ppu_enable = mv88e6185_g1_ppu_enable, 4135 .ppu_disable = mv88e6185_g1_ppu_disable, 4136 .reset = mv88e6185_g1_reset, 4137 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4138 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4139 .phylink_get_caps = mv88e6095_phylink_get_caps, 4140 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4141 }; 4142 4143 static const struct mv88e6xxx_ops mv88e6097_ops = { 4144 /* MV88E6XXX_FAMILY_6097 */ 4145 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4146 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4147 .irl_init_all = mv88e6352_g2_irl_init_all, 4148 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4149 .phy_read = mv88e6xxx_g2_smi_phy_read, 4150 .phy_write = mv88e6xxx_g2_smi_phy_write, 4151 .port_set_link = mv88e6xxx_port_set_link, 4152 .port_sync_link = mv88e6185_port_sync_link, 4153 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4154 .port_tag_remap = mv88e6095_port_tag_remap, 4155 .port_set_policy = mv88e6352_port_set_policy, 4156 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4157 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4158 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4159 .port_set_ether_type = mv88e6351_port_set_ether_type, 4160 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4161 .port_pause_limit = mv88e6097_port_pause_limit, 4162 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4163 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4164 .port_get_cmode = mv88e6185_port_get_cmode, 4165 .port_setup_message_port = mv88e6xxx_setup_message_port, 4166 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4167 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4168 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4169 .stats_get_strings = mv88e6095_stats_get_strings, 4170 .stats_get_stats = mv88e6095_stats_get_stats, 4171 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4172 .set_egress_port = mv88e6095_g1_set_egress_port, 4173 .watchdog_ops = &mv88e6097_watchdog_ops, 4174 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4175 .serdes_power = mv88e6185_serdes_power, 4176 .serdes_get_lane = mv88e6185_serdes_get_lane, 4177 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4178 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4179 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4180 .serdes_irq_status = mv88e6097_serdes_irq_status, 4181 .pot_clear = mv88e6xxx_g2_pot_clear, 4182 .reset = mv88e6352_g1_reset, 4183 .rmu_disable = mv88e6085_g1_rmu_disable, 4184 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4185 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4186 .phylink_get_caps = mv88e6095_phylink_get_caps, 4187 .stu_getnext = mv88e6352_g1_stu_getnext, 4188 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4189 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4190 }; 4191 4192 static const struct mv88e6xxx_ops mv88e6123_ops = { 4193 /* MV88E6XXX_FAMILY_6165 */ 4194 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4195 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4196 .irl_init_all = mv88e6352_g2_irl_init_all, 4197 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4198 .phy_read = mv88e6xxx_g2_smi_phy_read, 4199 .phy_write = mv88e6xxx_g2_smi_phy_write, 4200 .port_set_link = mv88e6xxx_port_set_link, 4201 .port_sync_link = mv88e6xxx_port_sync_link, 4202 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4203 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4204 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4205 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4206 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4207 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4208 .port_get_cmode = mv88e6185_port_get_cmode, 4209 .port_setup_message_port = mv88e6xxx_setup_message_port, 4210 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4211 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4212 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4213 .stats_get_strings = mv88e6095_stats_get_strings, 4214 .stats_get_stats = mv88e6095_stats_get_stats, 4215 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4216 .set_egress_port = mv88e6095_g1_set_egress_port, 4217 .watchdog_ops = &mv88e6097_watchdog_ops, 4218 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4219 .pot_clear = mv88e6xxx_g2_pot_clear, 4220 .reset = mv88e6352_g1_reset, 4221 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4222 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4223 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4224 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4225 .stu_getnext = mv88e6352_g1_stu_getnext, 4226 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4227 .phylink_get_caps = mv88e6185_phylink_get_caps, 4228 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4229 }; 4230 4231 static const struct mv88e6xxx_ops mv88e6131_ops = { 4232 /* MV88E6XXX_FAMILY_6185 */ 4233 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4234 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4235 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4236 .phy_read = mv88e6185_phy_ppu_read, 4237 .phy_write = mv88e6185_phy_ppu_write, 4238 .port_set_link = mv88e6xxx_port_set_link, 4239 .port_sync_link = mv88e6xxx_port_sync_link, 4240 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4241 .port_tag_remap = mv88e6095_port_tag_remap, 4242 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4243 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4244 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4245 .port_set_ether_type = mv88e6351_port_set_ether_type, 4246 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4247 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4248 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4249 .port_pause_limit = mv88e6097_port_pause_limit, 4250 .port_set_pause = mv88e6185_port_set_pause, 4251 .port_get_cmode = mv88e6185_port_get_cmode, 4252 .port_setup_message_port = mv88e6xxx_setup_message_port, 4253 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4254 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4255 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4256 .stats_get_strings = mv88e6095_stats_get_strings, 4257 .stats_get_stats = mv88e6095_stats_get_stats, 4258 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4259 .set_egress_port = mv88e6095_g1_set_egress_port, 4260 .watchdog_ops = &mv88e6097_watchdog_ops, 4261 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4262 .ppu_enable = mv88e6185_g1_ppu_enable, 4263 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4264 .ppu_disable = mv88e6185_g1_ppu_disable, 4265 .reset = mv88e6185_g1_reset, 4266 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4267 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4268 .phylink_get_caps = mv88e6185_phylink_get_caps, 4269 }; 4270 4271 static const struct mv88e6xxx_ops mv88e6141_ops = { 4272 /* MV88E6XXX_FAMILY_6341 */ 4273 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4274 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4275 .irl_init_all = mv88e6352_g2_irl_init_all, 4276 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4277 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4278 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4279 .phy_read = mv88e6xxx_g2_smi_phy_read, 4280 .phy_write = mv88e6xxx_g2_smi_phy_write, 4281 .port_set_link = mv88e6xxx_port_set_link, 4282 .port_sync_link = mv88e6xxx_port_sync_link, 4283 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4284 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4285 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4286 .port_tag_remap = mv88e6095_port_tag_remap, 4287 .port_set_policy = mv88e6352_port_set_policy, 4288 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4289 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4290 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4291 .port_set_ether_type = mv88e6351_port_set_ether_type, 4292 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4293 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4294 .port_pause_limit = mv88e6097_port_pause_limit, 4295 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4296 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4297 .port_get_cmode = mv88e6352_port_get_cmode, 4298 .port_set_cmode = mv88e6341_port_set_cmode, 4299 .port_setup_message_port = mv88e6xxx_setup_message_port, 4300 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4301 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4302 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4303 .stats_get_strings = mv88e6320_stats_get_strings, 4304 .stats_get_stats = mv88e6390_stats_get_stats, 4305 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4306 .set_egress_port = mv88e6390_g1_set_egress_port, 4307 .watchdog_ops = &mv88e6390_watchdog_ops, 4308 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4309 .pot_clear = mv88e6xxx_g2_pot_clear, 4310 .reset = mv88e6352_g1_reset, 4311 .rmu_disable = mv88e6390_g1_rmu_disable, 4312 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4313 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4314 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4315 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4316 .stu_getnext = mv88e6352_g1_stu_getnext, 4317 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4318 .serdes_power = mv88e6390_serdes_power, 4319 .serdes_get_lane = mv88e6341_serdes_get_lane, 4320 /* Check status register pause & lpa register */ 4321 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4322 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4323 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4324 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4325 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4326 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4327 .serdes_irq_status = mv88e6390_serdes_irq_status, 4328 .gpio_ops = &mv88e6352_gpio_ops, 4329 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4330 .serdes_get_strings = mv88e6390_serdes_get_strings, 4331 .serdes_get_stats = mv88e6390_serdes_get_stats, 4332 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4333 .serdes_get_regs = mv88e6390_serdes_get_regs, 4334 .phylink_get_caps = mv88e6341_phylink_get_caps, 4335 }; 4336 4337 static const struct mv88e6xxx_ops mv88e6161_ops = { 4338 /* MV88E6XXX_FAMILY_6165 */ 4339 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4340 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4341 .irl_init_all = mv88e6352_g2_irl_init_all, 4342 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4343 .phy_read = mv88e6xxx_g2_smi_phy_read, 4344 .phy_write = mv88e6xxx_g2_smi_phy_write, 4345 .port_set_link = mv88e6xxx_port_set_link, 4346 .port_sync_link = mv88e6xxx_port_sync_link, 4347 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4348 .port_tag_remap = mv88e6095_port_tag_remap, 4349 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4350 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4351 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4352 .port_set_ether_type = mv88e6351_port_set_ether_type, 4353 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4354 .port_pause_limit = mv88e6097_port_pause_limit, 4355 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4356 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4357 .port_get_cmode = mv88e6185_port_get_cmode, 4358 .port_setup_message_port = mv88e6xxx_setup_message_port, 4359 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4360 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4361 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4362 .stats_get_strings = mv88e6095_stats_get_strings, 4363 .stats_get_stats = mv88e6095_stats_get_stats, 4364 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4365 .set_egress_port = mv88e6095_g1_set_egress_port, 4366 .watchdog_ops = &mv88e6097_watchdog_ops, 4367 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4368 .pot_clear = mv88e6xxx_g2_pot_clear, 4369 .reset = mv88e6352_g1_reset, 4370 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4371 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4372 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4373 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4374 .stu_getnext = mv88e6352_g1_stu_getnext, 4375 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4376 .avb_ops = &mv88e6165_avb_ops, 4377 .ptp_ops = &mv88e6165_ptp_ops, 4378 .phylink_get_caps = mv88e6185_phylink_get_caps, 4379 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4380 }; 4381 4382 static const struct mv88e6xxx_ops mv88e6165_ops = { 4383 /* MV88E6XXX_FAMILY_6165 */ 4384 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4385 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4386 .irl_init_all = mv88e6352_g2_irl_init_all, 4387 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4388 .phy_read = mv88e6165_phy_read, 4389 .phy_write = mv88e6165_phy_write, 4390 .port_set_link = mv88e6xxx_port_set_link, 4391 .port_sync_link = mv88e6xxx_port_sync_link, 4392 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4393 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4394 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4395 .port_get_cmode = mv88e6185_port_get_cmode, 4396 .port_setup_message_port = mv88e6xxx_setup_message_port, 4397 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4398 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4399 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4400 .stats_get_strings = mv88e6095_stats_get_strings, 4401 .stats_get_stats = mv88e6095_stats_get_stats, 4402 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4403 .set_egress_port = mv88e6095_g1_set_egress_port, 4404 .watchdog_ops = &mv88e6097_watchdog_ops, 4405 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4406 .pot_clear = mv88e6xxx_g2_pot_clear, 4407 .reset = mv88e6352_g1_reset, 4408 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4409 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4410 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4411 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4412 .stu_getnext = mv88e6352_g1_stu_getnext, 4413 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4414 .avb_ops = &mv88e6165_avb_ops, 4415 .ptp_ops = &mv88e6165_ptp_ops, 4416 .phylink_get_caps = mv88e6185_phylink_get_caps, 4417 }; 4418 4419 static const struct mv88e6xxx_ops mv88e6171_ops = { 4420 /* MV88E6XXX_FAMILY_6351 */ 4421 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4422 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4423 .irl_init_all = mv88e6352_g2_irl_init_all, 4424 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4425 .phy_read = mv88e6xxx_g2_smi_phy_read, 4426 .phy_write = mv88e6xxx_g2_smi_phy_write, 4427 .port_set_link = mv88e6xxx_port_set_link, 4428 .port_sync_link = mv88e6xxx_port_sync_link, 4429 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4430 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4431 .port_tag_remap = mv88e6095_port_tag_remap, 4432 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4433 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4434 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4435 .port_set_ether_type = mv88e6351_port_set_ether_type, 4436 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4437 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4438 .port_pause_limit = mv88e6097_port_pause_limit, 4439 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4440 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4441 .port_get_cmode = mv88e6352_port_get_cmode, 4442 .port_setup_message_port = mv88e6xxx_setup_message_port, 4443 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4444 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4445 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4446 .stats_get_strings = mv88e6095_stats_get_strings, 4447 .stats_get_stats = mv88e6095_stats_get_stats, 4448 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4449 .set_egress_port = mv88e6095_g1_set_egress_port, 4450 .watchdog_ops = &mv88e6097_watchdog_ops, 4451 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4452 .pot_clear = mv88e6xxx_g2_pot_clear, 4453 .reset = mv88e6352_g1_reset, 4454 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4455 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4456 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4457 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4458 .stu_getnext = mv88e6352_g1_stu_getnext, 4459 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4460 .phylink_get_caps = mv88e6185_phylink_get_caps, 4461 }; 4462 4463 static const struct mv88e6xxx_ops mv88e6172_ops = { 4464 /* MV88E6XXX_FAMILY_6352 */ 4465 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4466 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4467 .irl_init_all = mv88e6352_g2_irl_init_all, 4468 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4469 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4471 .phy_read = mv88e6xxx_g2_smi_phy_read, 4472 .phy_write = mv88e6xxx_g2_smi_phy_write, 4473 .port_set_link = mv88e6xxx_port_set_link, 4474 .port_sync_link = mv88e6xxx_port_sync_link, 4475 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4476 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4477 .port_tag_remap = mv88e6095_port_tag_remap, 4478 .port_set_policy = mv88e6352_port_set_policy, 4479 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4480 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4481 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4482 .port_set_ether_type = mv88e6351_port_set_ether_type, 4483 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4484 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4485 .port_pause_limit = mv88e6097_port_pause_limit, 4486 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4487 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4488 .port_get_cmode = mv88e6352_port_get_cmode, 4489 .port_setup_message_port = mv88e6xxx_setup_message_port, 4490 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4491 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4492 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4493 .stats_get_strings = mv88e6095_stats_get_strings, 4494 .stats_get_stats = mv88e6095_stats_get_stats, 4495 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4496 .set_egress_port = mv88e6095_g1_set_egress_port, 4497 .watchdog_ops = &mv88e6097_watchdog_ops, 4498 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4499 .pot_clear = mv88e6xxx_g2_pot_clear, 4500 .reset = mv88e6352_g1_reset, 4501 .rmu_disable = mv88e6352_g1_rmu_disable, 4502 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4503 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4504 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4505 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4506 .stu_getnext = mv88e6352_g1_stu_getnext, 4507 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4508 .serdes_get_lane = mv88e6352_serdes_get_lane, 4509 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4510 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4511 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4512 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4513 .serdes_power = mv88e6352_serdes_power, 4514 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4515 .serdes_get_regs = mv88e6352_serdes_get_regs, 4516 .gpio_ops = &mv88e6352_gpio_ops, 4517 .phylink_get_caps = mv88e6352_phylink_get_caps, 4518 }; 4519 4520 static const struct mv88e6xxx_ops mv88e6175_ops = { 4521 /* MV88E6XXX_FAMILY_6351 */ 4522 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4523 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4524 .irl_init_all = mv88e6352_g2_irl_init_all, 4525 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4526 .phy_read = mv88e6xxx_g2_smi_phy_read, 4527 .phy_write = mv88e6xxx_g2_smi_phy_write, 4528 .port_set_link = mv88e6xxx_port_set_link, 4529 .port_sync_link = mv88e6xxx_port_sync_link, 4530 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4531 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4532 .port_tag_remap = mv88e6095_port_tag_remap, 4533 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4534 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4535 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4536 .port_set_ether_type = mv88e6351_port_set_ether_type, 4537 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4538 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4539 .port_pause_limit = mv88e6097_port_pause_limit, 4540 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4541 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4542 .port_get_cmode = mv88e6352_port_get_cmode, 4543 .port_setup_message_port = mv88e6xxx_setup_message_port, 4544 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4545 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4546 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4547 .stats_get_strings = mv88e6095_stats_get_strings, 4548 .stats_get_stats = mv88e6095_stats_get_stats, 4549 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4550 .set_egress_port = mv88e6095_g1_set_egress_port, 4551 .watchdog_ops = &mv88e6097_watchdog_ops, 4552 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4553 .pot_clear = mv88e6xxx_g2_pot_clear, 4554 .reset = mv88e6352_g1_reset, 4555 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4556 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4557 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4558 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4559 .stu_getnext = mv88e6352_g1_stu_getnext, 4560 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4561 .phylink_get_caps = mv88e6185_phylink_get_caps, 4562 }; 4563 4564 static const struct mv88e6xxx_ops mv88e6176_ops = { 4565 /* MV88E6XXX_FAMILY_6352 */ 4566 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4567 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4568 .irl_init_all = mv88e6352_g2_irl_init_all, 4569 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4570 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4571 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4572 .phy_read = mv88e6xxx_g2_smi_phy_read, 4573 .phy_write = mv88e6xxx_g2_smi_phy_write, 4574 .port_set_link = mv88e6xxx_port_set_link, 4575 .port_sync_link = mv88e6xxx_port_sync_link, 4576 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4577 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4578 .port_tag_remap = mv88e6095_port_tag_remap, 4579 .port_set_policy = mv88e6352_port_set_policy, 4580 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4581 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4582 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4583 .port_set_ether_type = mv88e6351_port_set_ether_type, 4584 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4585 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4586 .port_pause_limit = mv88e6097_port_pause_limit, 4587 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4588 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4589 .port_get_cmode = mv88e6352_port_get_cmode, 4590 .port_setup_message_port = mv88e6xxx_setup_message_port, 4591 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4592 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4593 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4594 .stats_get_strings = mv88e6095_stats_get_strings, 4595 .stats_get_stats = mv88e6095_stats_get_stats, 4596 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4597 .set_egress_port = mv88e6095_g1_set_egress_port, 4598 .watchdog_ops = &mv88e6097_watchdog_ops, 4599 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4600 .pot_clear = mv88e6xxx_g2_pot_clear, 4601 .reset = mv88e6352_g1_reset, 4602 .rmu_disable = mv88e6352_g1_rmu_disable, 4603 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4604 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4605 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4606 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4607 .stu_getnext = mv88e6352_g1_stu_getnext, 4608 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4609 .serdes_get_lane = mv88e6352_serdes_get_lane, 4610 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4611 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4612 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4613 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4614 .serdes_power = mv88e6352_serdes_power, 4615 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4616 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4617 .serdes_irq_status = mv88e6352_serdes_irq_status, 4618 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4619 .serdes_get_regs = mv88e6352_serdes_get_regs, 4620 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4621 .gpio_ops = &mv88e6352_gpio_ops, 4622 .phylink_get_caps = mv88e6352_phylink_get_caps, 4623 }; 4624 4625 static const struct mv88e6xxx_ops mv88e6185_ops = { 4626 /* MV88E6XXX_FAMILY_6185 */ 4627 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4628 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4629 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4630 .phy_read = mv88e6185_phy_ppu_read, 4631 .phy_write = mv88e6185_phy_ppu_write, 4632 .port_set_link = mv88e6xxx_port_set_link, 4633 .port_sync_link = mv88e6185_port_sync_link, 4634 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4635 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4636 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4637 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4638 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4639 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4640 .port_set_pause = mv88e6185_port_set_pause, 4641 .port_get_cmode = mv88e6185_port_get_cmode, 4642 .port_setup_message_port = mv88e6xxx_setup_message_port, 4643 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4644 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4645 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4646 .stats_get_strings = mv88e6095_stats_get_strings, 4647 .stats_get_stats = mv88e6095_stats_get_stats, 4648 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4649 .set_egress_port = mv88e6095_g1_set_egress_port, 4650 .watchdog_ops = &mv88e6097_watchdog_ops, 4651 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4652 .serdes_power = mv88e6185_serdes_power, 4653 .serdes_get_lane = mv88e6185_serdes_get_lane, 4654 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4655 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4656 .ppu_enable = mv88e6185_g1_ppu_enable, 4657 .ppu_disable = mv88e6185_g1_ppu_disable, 4658 .reset = mv88e6185_g1_reset, 4659 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4660 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4661 .phylink_get_caps = mv88e6185_phylink_get_caps, 4662 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4663 }; 4664 4665 static const struct mv88e6xxx_ops mv88e6190_ops = { 4666 /* MV88E6XXX_FAMILY_6390 */ 4667 .setup_errata = mv88e6390_setup_errata, 4668 .irl_init_all = mv88e6390_g2_irl_init_all, 4669 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4670 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4671 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4672 .phy_read = mv88e6xxx_g2_smi_phy_read, 4673 .phy_write = mv88e6xxx_g2_smi_phy_write, 4674 .port_set_link = mv88e6xxx_port_set_link, 4675 .port_sync_link = mv88e6xxx_port_sync_link, 4676 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4677 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4678 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4679 .port_tag_remap = mv88e6390_port_tag_remap, 4680 .port_set_policy = mv88e6352_port_set_policy, 4681 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4682 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4683 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4684 .port_set_ether_type = mv88e6351_port_set_ether_type, 4685 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4686 .port_pause_limit = mv88e6390_port_pause_limit, 4687 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4688 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4689 .port_get_cmode = mv88e6352_port_get_cmode, 4690 .port_set_cmode = mv88e6390_port_set_cmode, 4691 .port_setup_message_port = mv88e6xxx_setup_message_port, 4692 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4693 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4694 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4695 .stats_get_strings = mv88e6320_stats_get_strings, 4696 .stats_get_stats = mv88e6390_stats_get_stats, 4697 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4698 .set_egress_port = mv88e6390_g1_set_egress_port, 4699 .watchdog_ops = &mv88e6390_watchdog_ops, 4700 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4701 .pot_clear = mv88e6xxx_g2_pot_clear, 4702 .reset = mv88e6352_g1_reset, 4703 .rmu_disable = mv88e6390_g1_rmu_disable, 4704 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4705 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4706 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4707 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4708 .stu_getnext = mv88e6390_g1_stu_getnext, 4709 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4710 .serdes_power = mv88e6390_serdes_power, 4711 .serdes_get_lane = mv88e6390_serdes_get_lane, 4712 /* Check status register pause & lpa register */ 4713 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4714 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4715 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4716 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4717 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4718 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4719 .serdes_irq_status = mv88e6390_serdes_irq_status, 4720 .serdes_get_strings = mv88e6390_serdes_get_strings, 4721 .serdes_get_stats = mv88e6390_serdes_get_stats, 4722 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4723 .serdes_get_regs = mv88e6390_serdes_get_regs, 4724 .gpio_ops = &mv88e6352_gpio_ops, 4725 .phylink_get_caps = mv88e6390_phylink_get_caps, 4726 }; 4727 4728 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4729 /* MV88E6XXX_FAMILY_6390 */ 4730 .setup_errata = mv88e6390_setup_errata, 4731 .irl_init_all = mv88e6390_g2_irl_init_all, 4732 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4733 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4734 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4735 .phy_read = mv88e6xxx_g2_smi_phy_read, 4736 .phy_write = mv88e6xxx_g2_smi_phy_write, 4737 .port_set_link = mv88e6xxx_port_set_link, 4738 .port_sync_link = mv88e6xxx_port_sync_link, 4739 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4740 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4741 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4742 .port_tag_remap = mv88e6390_port_tag_remap, 4743 .port_set_policy = mv88e6352_port_set_policy, 4744 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4745 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4746 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4747 .port_set_ether_type = mv88e6351_port_set_ether_type, 4748 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4749 .port_pause_limit = mv88e6390_port_pause_limit, 4750 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4751 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4752 .port_get_cmode = mv88e6352_port_get_cmode, 4753 .port_set_cmode = mv88e6390x_port_set_cmode, 4754 .port_setup_message_port = mv88e6xxx_setup_message_port, 4755 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4756 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4757 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4758 .stats_get_strings = mv88e6320_stats_get_strings, 4759 .stats_get_stats = mv88e6390_stats_get_stats, 4760 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4761 .set_egress_port = mv88e6390_g1_set_egress_port, 4762 .watchdog_ops = &mv88e6390_watchdog_ops, 4763 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4764 .pot_clear = mv88e6xxx_g2_pot_clear, 4765 .reset = mv88e6352_g1_reset, 4766 .rmu_disable = mv88e6390_g1_rmu_disable, 4767 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4768 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4769 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4770 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4771 .stu_getnext = mv88e6390_g1_stu_getnext, 4772 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4773 .serdes_power = mv88e6390_serdes_power, 4774 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4775 /* Check status register pause & lpa register */ 4776 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4777 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4778 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4779 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4780 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4781 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4782 .serdes_irq_status = mv88e6390_serdes_irq_status, 4783 .serdes_get_strings = mv88e6390_serdes_get_strings, 4784 .serdes_get_stats = mv88e6390_serdes_get_stats, 4785 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4786 .serdes_get_regs = mv88e6390_serdes_get_regs, 4787 .gpio_ops = &mv88e6352_gpio_ops, 4788 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4789 }; 4790 4791 static const struct mv88e6xxx_ops mv88e6191_ops = { 4792 /* MV88E6XXX_FAMILY_6390 */ 4793 .setup_errata = mv88e6390_setup_errata, 4794 .irl_init_all = mv88e6390_g2_irl_init_all, 4795 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4796 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4797 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4798 .phy_read = mv88e6xxx_g2_smi_phy_read, 4799 .phy_write = mv88e6xxx_g2_smi_phy_write, 4800 .port_set_link = mv88e6xxx_port_set_link, 4801 .port_sync_link = mv88e6xxx_port_sync_link, 4802 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4803 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4804 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4805 .port_tag_remap = mv88e6390_port_tag_remap, 4806 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4807 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4808 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4809 .port_set_ether_type = mv88e6351_port_set_ether_type, 4810 .port_pause_limit = mv88e6390_port_pause_limit, 4811 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4812 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4813 .port_get_cmode = mv88e6352_port_get_cmode, 4814 .port_set_cmode = mv88e6390_port_set_cmode, 4815 .port_setup_message_port = mv88e6xxx_setup_message_port, 4816 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4817 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4818 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4819 .stats_get_strings = mv88e6320_stats_get_strings, 4820 .stats_get_stats = mv88e6390_stats_get_stats, 4821 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4822 .set_egress_port = mv88e6390_g1_set_egress_port, 4823 .watchdog_ops = &mv88e6390_watchdog_ops, 4824 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4825 .pot_clear = mv88e6xxx_g2_pot_clear, 4826 .reset = mv88e6352_g1_reset, 4827 .rmu_disable = mv88e6390_g1_rmu_disable, 4828 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4829 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4830 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4831 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4832 .stu_getnext = mv88e6390_g1_stu_getnext, 4833 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4834 .serdes_power = mv88e6390_serdes_power, 4835 .serdes_get_lane = mv88e6390_serdes_get_lane, 4836 /* Check status register pause & lpa register */ 4837 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4838 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4839 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4840 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4841 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4842 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4843 .serdes_irq_status = mv88e6390_serdes_irq_status, 4844 .serdes_get_strings = mv88e6390_serdes_get_strings, 4845 .serdes_get_stats = mv88e6390_serdes_get_stats, 4846 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4847 .serdes_get_regs = mv88e6390_serdes_get_regs, 4848 .avb_ops = &mv88e6390_avb_ops, 4849 .ptp_ops = &mv88e6352_ptp_ops, 4850 .phylink_get_caps = mv88e6390_phylink_get_caps, 4851 }; 4852 4853 static const struct mv88e6xxx_ops mv88e6240_ops = { 4854 /* MV88E6XXX_FAMILY_6352 */ 4855 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4856 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4857 .irl_init_all = mv88e6352_g2_irl_init_all, 4858 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4859 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4860 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4861 .phy_read = mv88e6xxx_g2_smi_phy_read, 4862 .phy_write = mv88e6xxx_g2_smi_phy_write, 4863 .port_set_link = mv88e6xxx_port_set_link, 4864 .port_sync_link = mv88e6xxx_port_sync_link, 4865 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4866 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4867 .port_tag_remap = mv88e6095_port_tag_remap, 4868 .port_set_policy = mv88e6352_port_set_policy, 4869 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4870 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4871 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4872 .port_set_ether_type = mv88e6351_port_set_ether_type, 4873 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4874 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4875 .port_pause_limit = mv88e6097_port_pause_limit, 4876 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4877 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4878 .port_get_cmode = mv88e6352_port_get_cmode, 4879 .port_setup_message_port = mv88e6xxx_setup_message_port, 4880 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4881 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4882 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4883 .stats_get_strings = mv88e6095_stats_get_strings, 4884 .stats_get_stats = mv88e6095_stats_get_stats, 4885 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4886 .set_egress_port = mv88e6095_g1_set_egress_port, 4887 .watchdog_ops = &mv88e6097_watchdog_ops, 4888 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4889 .pot_clear = mv88e6xxx_g2_pot_clear, 4890 .reset = mv88e6352_g1_reset, 4891 .rmu_disable = mv88e6352_g1_rmu_disable, 4892 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4893 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4894 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4895 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4896 .stu_getnext = mv88e6352_g1_stu_getnext, 4897 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4898 .serdes_get_lane = mv88e6352_serdes_get_lane, 4899 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4900 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4901 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4902 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4903 .serdes_power = mv88e6352_serdes_power, 4904 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4905 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4906 .serdes_irq_status = mv88e6352_serdes_irq_status, 4907 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4908 .serdes_get_regs = mv88e6352_serdes_get_regs, 4909 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4910 .gpio_ops = &mv88e6352_gpio_ops, 4911 .avb_ops = &mv88e6352_avb_ops, 4912 .ptp_ops = &mv88e6352_ptp_ops, 4913 .phylink_get_caps = mv88e6352_phylink_get_caps, 4914 }; 4915 4916 static const struct mv88e6xxx_ops mv88e6250_ops = { 4917 /* MV88E6XXX_FAMILY_6250 */ 4918 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4919 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4920 .irl_init_all = mv88e6352_g2_irl_init_all, 4921 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4922 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4923 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4924 .phy_read = mv88e6xxx_g2_smi_phy_read, 4925 .phy_write = mv88e6xxx_g2_smi_phy_write, 4926 .port_set_link = mv88e6xxx_port_set_link, 4927 .port_sync_link = mv88e6xxx_port_sync_link, 4928 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4929 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4930 .port_tag_remap = mv88e6095_port_tag_remap, 4931 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4932 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4933 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4934 .port_set_ether_type = mv88e6351_port_set_ether_type, 4935 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4936 .port_pause_limit = mv88e6097_port_pause_limit, 4937 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4938 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4939 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4940 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4941 .stats_get_strings = mv88e6250_stats_get_strings, 4942 .stats_get_stats = mv88e6250_stats_get_stats, 4943 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4944 .set_egress_port = mv88e6095_g1_set_egress_port, 4945 .watchdog_ops = &mv88e6250_watchdog_ops, 4946 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4947 .pot_clear = mv88e6xxx_g2_pot_clear, 4948 .reset = mv88e6250_g1_reset, 4949 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4950 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4951 .avb_ops = &mv88e6352_avb_ops, 4952 .ptp_ops = &mv88e6250_ptp_ops, 4953 .phylink_get_caps = mv88e6250_phylink_get_caps, 4954 }; 4955 4956 static const struct mv88e6xxx_ops mv88e6290_ops = { 4957 /* MV88E6XXX_FAMILY_6390 */ 4958 .setup_errata = mv88e6390_setup_errata, 4959 .irl_init_all = mv88e6390_g2_irl_init_all, 4960 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4961 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4962 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4963 .phy_read = mv88e6xxx_g2_smi_phy_read, 4964 .phy_write = mv88e6xxx_g2_smi_phy_write, 4965 .port_set_link = mv88e6xxx_port_set_link, 4966 .port_sync_link = mv88e6xxx_port_sync_link, 4967 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4968 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4969 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4970 .port_tag_remap = mv88e6390_port_tag_remap, 4971 .port_set_policy = mv88e6352_port_set_policy, 4972 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4973 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4974 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4975 .port_set_ether_type = mv88e6351_port_set_ether_type, 4976 .port_pause_limit = mv88e6390_port_pause_limit, 4977 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4978 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4979 .port_get_cmode = mv88e6352_port_get_cmode, 4980 .port_set_cmode = mv88e6390_port_set_cmode, 4981 .port_setup_message_port = mv88e6xxx_setup_message_port, 4982 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4983 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4984 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4985 .stats_get_strings = mv88e6320_stats_get_strings, 4986 .stats_get_stats = mv88e6390_stats_get_stats, 4987 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4988 .set_egress_port = mv88e6390_g1_set_egress_port, 4989 .watchdog_ops = &mv88e6390_watchdog_ops, 4990 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4991 .pot_clear = mv88e6xxx_g2_pot_clear, 4992 .reset = mv88e6352_g1_reset, 4993 .rmu_disable = mv88e6390_g1_rmu_disable, 4994 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4995 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4996 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4997 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4998 .stu_getnext = mv88e6390_g1_stu_getnext, 4999 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5000 .serdes_power = mv88e6390_serdes_power, 5001 .serdes_get_lane = mv88e6390_serdes_get_lane, 5002 /* Check status register pause & lpa register */ 5003 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5004 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5005 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5006 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5007 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5008 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5009 .serdes_irq_status = mv88e6390_serdes_irq_status, 5010 .serdes_get_strings = mv88e6390_serdes_get_strings, 5011 .serdes_get_stats = mv88e6390_serdes_get_stats, 5012 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5013 .serdes_get_regs = mv88e6390_serdes_get_regs, 5014 .gpio_ops = &mv88e6352_gpio_ops, 5015 .avb_ops = &mv88e6390_avb_ops, 5016 .ptp_ops = &mv88e6352_ptp_ops, 5017 .phylink_get_caps = mv88e6390_phylink_get_caps, 5018 }; 5019 5020 static const struct mv88e6xxx_ops mv88e6320_ops = { 5021 /* MV88E6XXX_FAMILY_6320 */ 5022 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5023 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5024 .irl_init_all = mv88e6352_g2_irl_init_all, 5025 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5026 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5027 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5028 .phy_read = mv88e6xxx_g2_smi_phy_read, 5029 .phy_write = mv88e6xxx_g2_smi_phy_write, 5030 .port_set_link = mv88e6xxx_port_set_link, 5031 .port_sync_link = mv88e6xxx_port_sync_link, 5032 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5033 .port_tag_remap = mv88e6095_port_tag_remap, 5034 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5035 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5036 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5037 .port_set_ether_type = mv88e6351_port_set_ether_type, 5038 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5039 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5040 .port_pause_limit = mv88e6097_port_pause_limit, 5041 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5042 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5043 .port_get_cmode = mv88e6352_port_get_cmode, 5044 .port_setup_message_port = mv88e6xxx_setup_message_port, 5045 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5046 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5047 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5048 .stats_get_strings = mv88e6320_stats_get_strings, 5049 .stats_get_stats = mv88e6320_stats_get_stats, 5050 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5051 .set_egress_port = mv88e6095_g1_set_egress_port, 5052 .watchdog_ops = &mv88e6390_watchdog_ops, 5053 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5054 .pot_clear = mv88e6xxx_g2_pot_clear, 5055 .reset = mv88e6352_g1_reset, 5056 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5057 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5058 .gpio_ops = &mv88e6352_gpio_ops, 5059 .avb_ops = &mv88e6352_avb_ops, 5060 .ptp_ops = &mv88e6352_ptp_ops, 5061 .phylink_get_caps = mv88e6185_phylink_get_caps, 5062 }; 5063 5064 static const struct mv88e6xxx_ops mv88e6321_ops = { 5065 /* MV88E6XXX_FAMILY_6320 */ 5066 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5067 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5068 .irl_init_all = mv88e6352_g2_irl_init_all, 5069 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5070 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5071 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5072 .phy_read = mv88e6xxx_g2_smi_phy_read, 5073 .phy_write = mv88e6xxx_g2_smi_phy_write, 5074 .port_set_link = mv88e6xxx_port_set_link, 5075 .port_sync_link = mv88e6xxx_port_sync_link, 5076 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5077 .port_tag_remap = mv88e6095_port_tag_remap, 5078 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5079 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5080 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5081 .port_set_ether_type = mv88e6351_port_set_ether_type, 5082 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5083 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5084 .port_pause_limit = mv88e6097_port_pause_limit, 5085 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5086 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5087 .port_get_cmode = mv88e6352_port_get_cmode, 5088 .port_setup_message_port = mv88e6xxx_setup_message_port, 5089 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5090 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5091 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5092 .stats_get_strings = mv88e6320_stats_get_strings, 5093 .stats_get_stats = mv88e6320_stats_get_stats, 5094 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5095 .set_egress_port = mv88e6095_g1_set_egress_port, 5096 .watchdog_ops = &mv88e6390_watchdog_ops, 5097 .reset = mv88e6352_g1_reset, 5098 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5099 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5100 .gpio_ops = &mv88e6352_gpio_ops, 5101 .avb_ops = &mv88e6352_avb_ops, 5102 .ptp_ops = &mv88e6352_ptp_ops, 5103 .phylink_get_caps = mv88e6185_phylink_get_caps, 5104 }; 5105 5106 static const struct mv88e6xxx_ops mv88e6341_ops = { 5107 /* MV88E6XXX_FAMILY_6341 */ 5108 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5109 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5110 .irl_init_all = mv88e6352_g2_irl_init_all, 5111 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5112 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5113 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5114 .phy_read = mv88e6xxx_g2_smi_phy_read, 5115 .phy_write = mv88e6xxx_g2_smi_phy_write, 5116 .port_set_link = mv88e6xxx_port_set_link, 5117 .port_sync_link = mv88e6xxx_port_sync_link, 5118 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5119 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5120 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5121 .port_tag_remap = mv88e6095_port_tag_remap, 5122 .port_set_policy = mv88e6352_port_set_policy, 5123 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5124 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5125 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5126 .port_set_ether_type = mv88e6351_port_set_ether_type, 5127 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5128 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5129 .port_pause_limit = mv88e6097_port_pause_limit, 5130 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5131 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5132 .port_get_cmode = mv88e6352_port_get_cmode, 5133 .port_set_cmode = mv88e6341_port_set_cmode, 5134 .port_setup_message_port = mv88e6xxx_setup_message_port, 5135 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5136 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5137 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5138 .stats_get_strings = mv88e6320_stats_get_strings, 5139 .stats_get_stats = mv88e6390_stats_get_stats, 5140 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5141 .set_egress_port = mv88e6390_g1_set_egress_port, 5142 .watchdog_ops = &mv88e6390_watchdog_ops, 5143 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5144 .pot_clear = mv88e6xxx_g2_pot_clear, 5145 .reset = mv88e6352_g1_reset, 5146 .rmu_disable = mv88e6390_g1_rmu_disable, 5147 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5148 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5149 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5150 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5151 .stu_getnext = mv88e6352_g1_stu_getnext, 5152 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5153 .serdes_power = mv88e6390_serdes_power, 5154 .serdes_get_lane = mv88e6341_serdes_get_lane, 5155 /* Check status register pause & lpa register */ 5156 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5157 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5158 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5159 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5160 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5161 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5162 .serdes_irq_status = mv88e6390_serdes_irq_status, 5163 .gpio_ops = &mv88e6352_gpio_ops, 5164 .avb_ops = &mv88e6390_avb_ops, 5165 .ptp_ops = &mv88e6352_ptp_ops, 5166 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5167 .serdes_get_strings = mv88e6390_serdes_get_strings, 5168 .serdes_get_stats = mv88e6390_serdes_get_stats, 5169 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5170 .serdes_get_regs = mv88e6390_serdes_get_regs, 5171 .phylink_get_caps = mv88e6341_phylink_get_caps, 5172 }; 5173 5174 static const struct mv88e6xxx_ops mv88e6350_ops = { 5175 /* MV88E6XXX_FAMILY_6351 */ 5176 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5177 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5178 .irl_init_all = mv88e6352_g2_irl_init_all, 5179 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5180 .phy_read = mv88e6xxx_g2_smi_phy_read, 5181 .phy_write = mv88e6xxx_g2_smi_phy_write, 5182 .port_set_link = mv88e6xxx_port_set_link, 5183 .port_sync_link = mv88e6xxx_port_sync_link, 5184 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5185 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5186 .port_tag_remap = mv88e6095_port_tag_remap, 5187 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5188 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5189 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5190 .port_set_ether_type = mv88e6351_port_set_ether_type, 5191 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5192 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5193 .port_pause_limit = mv88e6097_port_pause_limit, 5194 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5195 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5196 .port_get_cmode = mv88e6352_port_get_cmode, 5197 .port_setup_message_port = mv88e6xxx_setup_message_port, 5198 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5199 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5200 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5201 .stats_get_strings = mv88e6095_stats_get_strings, 5202 .stats_get_stats = mv88e6095_stats_get_stats, 5203 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5204 .set_egress_port = mv88e6095_g1_set_egress_port, 5205 .watchdog_ops = &mv88e6097_watchdog_ops, 5206 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5207 .pot_clear = mv88e6xxx_g2_pot_clear, 5208 .reset = mv88e6352_g1_reset, 5209 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5210 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5211 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5212 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5213 .stu_getnext = mv88e6352_g1_stu_getnext, 5214 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5215 .phylink_get_caps = mv88e6185_phylink_get_caps, 5216 }; 5217 5218 static const struct mv88e6xxx_ops mv88e6351_ops = { 5219 /* MV88E6XXX_FAMILY_6351 */ 5220 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5221 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5222 .irl_init_all = mv88e6352_g2_irl_init_all, 5223 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5224 .phy_read = mv88e6xxx_g2_smi_phy_read, 5225 .phy_write = mv88e6xxx_g2_smi_phy_write, 5226 .port_set_link = mv88e6xxx_port_set_link, 5227 .port_sync_link = mv88e6xxx_port_sync_link, 5228 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5229 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5230 .port_tag_remap = mv88e6095_port_tag_remap, 5231 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5232 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5233 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5234 .port_set_ether_type = mv88e6351_port_set_ether_type, 5235 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5236 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5237 .port_pause_limit = mv88e6097_port_pause_limit, 5238 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5239 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5240 .port_get_cmode = mv88e6352_port_get_cmode, 5241 .port_setup_message_port = mv88e6xxx_setup_message_port, 5242 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5243 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5244 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5245 .stats_get_strings = mv88e6095_stats_get_strings, 5246 .stats_get_stats = mv88e6095_stats_get_stats, 5247 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5248 .set_egress_port = mv88e6095_g1_set_egress_port, 5249 .watchdog_ops = &mv88e6097_watchdog_ops, 5250 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5251 .pot_clear = mv88e6xxx_g2_pot_clear, 5252 .reset = mv88e6352_g1_reset, 5253 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5254 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5255 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5256 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5257 .stu_getnext = mv88e6352_g1_stu_getnext, 5258 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5259 .avb_ops = &mv88e6352_avb_ops, 5260 .ptp_ops = &mv88e6352_ptp_ops, 5261 .phylink_get_caps = mv88e6185_phylink_get_caps, 5262 }; 5263 5264 static const struct mv88e6xxx_ops mv88e6352_ops = { 5265 /* MV88E6XXX_FAMILY_6352 */ 5266 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5267 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5268 .irl_init_all = mv88e6352_g2_irl_init_all, 5269 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5270 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5271 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5272 .phy_read = mv88e6xxx_g2_smi_phy_read, 5273 .phy_write = mv88e6xxx_g2_smi_phy_write, 5274 .port_set_link = mv88e6xxx_port_set_link, 5275 .port_sync_link = mv88e6xxx_port_sync_link, 5276 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5277 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5278 .port_tag_remap = mv88e6095_port_tag_remap, 5279 .port_set_policy = mv88e6352_port_set_policy, 5280 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5281 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5282 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5283 .port_set_ether_type = mv88e6351_port_set_ether_type, 5284 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5285 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5286 .port_pause_limit = mv88e6097_port_pause_limit, 5287 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5288 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5289 .port_get_cmode = mv88e6352_port_get_cmode, 5290 .port_setup_message_port = mv88e6xxx_setup_message_port, 5291 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5292 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5293 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5294 .stats_get_strings = mv88e6095_stats_get_strings, 5295 .stats_get_stats = mv88e6095_stats_get_stats, 5296 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5297 .set_egress_port = mv88e6095_g1_set_egress_port, 5298 .watchdog_ops = &mv88e6097_watchdog_ops, 5299 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5300 .pot_clear = mv88e6xxx_g2_pot_clear, 5301 .reset = mv88e6352_g1_reset, 5302 .rmu_disable = mv88e6352_g1_rmu_disable, 5303 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5304 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5305 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5306 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5307 .stu_getnext = mv88e6352_g1_stu_getnext, 5308 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5309 .serdes_get_lane = mv88e6352_serdes_get_lane, 5310 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5311 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5312 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5313 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5314 .serdes_power = mv88e6352_serdes_power, 5315 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5316 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5317 .serdes_irq_status = mv88e6352_serdes_irq_status, 5318 .gpio_ops = &mv88e6352_gpio_ops, 5319 .avb_ops = &mv88e6352_avb_ops, 5320 .ptp_ops = &mv88e6352_ptp_ops, 5321 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5322 .serdes_get_strings = mv88e6352_serdes_get_strings, 5323 .serdes_get_stats = mv88e6352_serdes_get_stats, 5324 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5325 .serdes_get_regs = mv88e6352_serdes_get_regs, 5326 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5327 .phylink_get_caps = mv88e6352_phylink_get_caps, 5328 }; 5329 5330 static const struct mv88e6xxx_ops mv88e6390_ops = { 5331 /* MV88E6XXX_FAMILY_6390 */ 5332 .setup_errata = mv88e6390_setup_errata, 5333 .irl_init_all = mv88e6390_g2_irl_init_all, 5334 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5335 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5336 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5337 .phy_read = mv88e6xxx_g2_smi_phy_read, 5338 .phy_write = mv88e6xxx_g2_smi_phy_write, 5339 .port_set_link = mv88e6xxx_port_set_link, 5340 .port_sync_link = mv88e6xxx_port_sync_link, 5341 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5342 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5343 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5344 .port_tag_remap = mv88e6390_port_tag_remap, 5345 .port_set_policy = mv88e6352_port_set_policy, 5346 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5347 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5348 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5349 .port_set_ether_type = mv88e6351_port_set_ether_type, 5350 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5351 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5352 .port_pause_limit = mv88e6390_port_pause_limit, 5353 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5354 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5355 .port_get_cmode = mv88e6352_port_get_cmode, 5356 .port_set_cmode = mv88e6390_port_set_cmode, 5357 .port_setup_message_port = mv88e6xxx_setup_message_port, 5358 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5359 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5360 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5361 .stats_get_strings = mv88e6320_stats_get_strings, 5362 .stats_get_stats = mv88e6390_stats_get_stats, 5363 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5364 .set_egress_port = mv88e6390_g1_set_egress_port, 5365 .watchdog_ops = &mv88e6390_watchdog_ops, 5366 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5367 .pot_clear = mv88e6xxx_g2_pot_clear, 5368 .reset = mv88e6352_g1_reset, 5369 .rmu_disable = mv88e6390_g1_rmu_disable, 5370 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5371 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5372 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5373 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5374 .stu_getnext = mv88e6390_g1_stu_getnext, 5375 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5376 .serdes_power = mv88e6390_serdes_power, 5377 .serdes_get_lane = mv88e6390_serdes_get_lane, 5378 /* Check status register pause & lpa register */ 5379 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5380 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5381 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5382 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5383 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5384 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5385 .serdes_irq_status = mv88e6390_serdes_irq_status, 5386 .gpio_ops = &mv88e6352_gpio_ops, 5387 .avb_ops = &mv88e6390_avb_ops, 5388 .ptp_ops = &mv88e6352_ptp_ops, 5389 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5390 .serdes_get_strings = mv88e6390_serdes_get_strings, 5391 .serdes_get_stats = mv88e6390_serdes_get_stats, 5392 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5393 .serdes_get_regs = mv88e6390_serdes_get_regs, 5394 .phylink_get_caps = mv88e6390_phylink_get_caps, 5395 }; 5396 5397 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5398 /* MV88E6XXX_FAMILY_6390 */ 5399 .setup_errata = mv88e6390_setup_errata, 5400 .irl_init_all = mv88e6390_g2_irl_init_all, 5401 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5402 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5403 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5404 .phy_read = mv88e6xxx_g2_smi_phy_read, 5405 .phy_write = mv88e6xxx_g2_smi_phy_write, 5406 .port_set_link = mv88e6xxx_port_set_link, 5407 .port_sync_link = mv88e6xxx_port_sync_link, 5408 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5409 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5410 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5411 .port_tag_remap = mv88e6390_port_tag_remap, 5412 .port_set_policy = mv88e6352_port_set_policy, 5413 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5414 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5415 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5416 .port_set_ether_type = mv88e6351_port_set_ether_type, 5417 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5418 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5419 .port_pause_limit = mv88e6390_port_pause_limit, 5420 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5421 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5422 .port_get_cmode = mv88e6352_port_get_cmode, 5423 .port_set_cmode = mv88e6390x_port_set_cmode, 5424 .port_setup_message_port = mv88e6xxx_setup_message_port, 5425 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5426 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5427 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5428 .stats_get_strings = mv88e6320_stats_get_strings, 5429 .stats_get_stats = mv88e6390_stats_get_stats, 5430 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5431 .set_egress_port = mv88e6390_g1_set_egress_port, 5432 .watchdog_ops = &mv88e6390_watchdog_ops, 5433 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5434 .pot_clear = mv88e6xxx_g2_pot_clear, 5435 .reset = mv88e6352_g1_reset, 5436 .rmu_disable = mv88e6390_g1_rmu_disable, 5437 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5438 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5439 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5440 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5441 .stu_getnext = mv88e6390_g1_stu_getnext, 5442 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5443 .serdes_power = mv88e6390_serdes_power, 5444 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5445 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5446 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5447 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5448 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5449 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5450 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5451 .serdes_irq_status = mv88e6390_serdes_irq_status, 5452 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5453 .serdes_get_strings = mv88e6390_serdes_get_strings, 5454 .serdes_get_stats = mv88e6390_serdes_get_stats, 5455 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5456 .serdes_get_regs = mv88e6390_serdes_get_regs, 5457 .gpio_ops = &mv88e6352_gpio_ops, 5458 .avb_ops = &mv88e6390_avb_ops, 5459 .ptp_ops = &mv88e6352_ptp_ops, 5460 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5461 }; 5462 5463 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5464 /* MV88E6XXX_FAMILY_6393 */ 5465 .setup_errata = mv88e6393x_serdes_setup_errata, 5466 .irl_init_all = mv88e6390_g2_irl_init_all, 5467 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5468 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5469 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5470 .phy_read = mv88e6xxx_g2_smi_phy_read, 5471 .phy_write = mv88e6xxx_g2_smi_phy_write, 5472 .port_set_link = mv88e6xxx_port_set_link, 5473 .port_sync_link = mv88e6xxx_port_sync_link, 5474 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5475 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5476 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5477 .port_tag_remap = mv88e6390_port_tag_remap, 5478 .port_set_policy = mv88e6393x_port_set_policy, 5479 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5480 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5481 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5482 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5483 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5484 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5485 .port_pause_limit = mv88e6390_port_pause_limit, 5486 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5487 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5488 .port_get_cmode = mv88e6352_port_get_cmode, 5489 .port_set_cmode = mv88e6393x_port_set_cmode, 5490 .port_setup_message_port = mv88e6xxx_setup_message_port, 5491 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5492 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5493 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5494 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5495 .stats_get_strings = mv88e6320_stats_get_strings, 5496 .stats_get_stats = mv88e6390_stats_get_stats, 5497 /* .set_cpu_port is missing because this family does not support a global 5498 * CPU port, only per port CPU port which is set via 5499 * .port_set_upstream_port method. 5500 */ 5501 .set_egress_port = mv88e6393x_set_egress_port, 5502 .watchdog_ops = &mv88e6390_watchdog_ops, 5503 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5504 .pot_clear = mv88e6xxx_g2_pot_clear, 5505 .reset = mv88e6352_g1_reset, 5506 .rmu_disable = mv88e6390_g1_rmu_disable, 5507 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5508 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5509 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5510 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5511 .stu_getnext = mv88e6390_g1_stu_getnext, 5512 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5513 .serdes_power = mv88e6393x_serdes_power, 5514 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5515 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5516 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5517 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5518 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5519 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5520 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5521 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5522 /* TODO: serdes stats */ 5523 .gpio_ops = &mv88e6352_gpio_ops, 5524 .avb_ops = &mv88e6390_avb_ops, 5525 .ptp_ops = &mv88e6352_ptp_ops, 5526 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5527 }; 5528 5529 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5530 [MV88E6085] = { 5531 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5532 .family = MV88E6XXX_FAMILY_6097, 5533 .name = "Marvell 88E6085", 5534 .num_databases = 4096, 5535 .num_macs = 8192, 5536 .num_ports = 10, 5537 .num_internal_phys = 5, 5538 .max_vid = 4095, 5539 .max_sid = 63, 5540 .port_base_addr = 0x10, 5541 .phy_base_addr = 0x0, 5542 .global1_addr = 0x1b, 5543 .global2_addr = 0x1c, 5544 .age_time_coeff = 15000, 5545 .g1_irqs = 8, 5546 .g2_irqs = 10, 5547 .atu_move_port_mask = 0xf, 5548 .pvt = true, 5549 .multi_chip = true, 5550 .ops = &mv88e6085_ops, 5551 }, 5552 5553 [MV88E6095] = { 5554 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5555 .family = MV88E6XXX_FAMILY_6095, 5556 .name = "Marvell 88E6095/88E6095F", 5557 .num_databases = 256, 5558 .num_macs = 8192, 5559 .num_ports = 11, 5560 .num_internal_phys = 0, 5561 .max_vid = 4095, 5562 .port_base_addr = 0x10, 5563 .phy_base_addr = 0x0, 5564 .global1_addr = 0x1b, 5565 .global2_addr = 0x1c, 5566 .age_time_coeff = 15000, 5567 .g1_irqs = 8, 5568 .atu_move_port_mask = 0xf, 5569 .multi_chip = true, 5570 .ops = &mv88e6095_ops, 5571 }, 5572 5573 [MV88E6097] = { 5574 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5575 .family = MV88E6XXX_FAMILY_6097, 5576 .name = "Marvell 88E6097/88E6097F", 5577 .num_databases = 4096, 5578 .num_macs = 8192, 5579 .num_ports = 11, 5580 .num_internal_phys = 8, 5581 .max_vid = 4095, 5582 .max_sid = 63, 5583 .port_base_addr = 0x10, 5584 .phy_base_addr = 0x0, 5585 .global1_addr = 0x1b, 5586 .global2_addr = 0x1c, 5587 .age_time_coeff = 15000, 5588 .g1_irqs = 8, 5589 .g2_irqs = 10, 5590 .atu_move_port_mask = 0xf, 5591 .pvt = true, 5592 .multi_chip = true, 5593 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5594 .ops = &mv88e6097_ops, 5595 }, 5596 5597 [MV88E6123] = { 5598 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5599 .family = MV88E6XXX_FAMILY_6165, 5600 .name = "Marvell 88E6123", 5601 .num_databases = 4096, 5602 .num_macs = 1024, 5603 .num_ports = 3, 5604 .num_internal_phys = 5, 5605 .max_vid = 4095, 5606 .max_sid = 63, 5607 .port_base_addr = 0x10, 5608 .phy_base_addr = 0x0, 5609 .global1_addr = 0x1b, 5610 .global2_addr = 0x1c, 5611 .age_time_coeff = 15000, 5612 .g1_irqs = 9, 5613 .g2_irqs = 10, 5614 .atu_move_port_mask = 0xf, 5615 .pvt = true, 5616 .multi_chip = true, 5617 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5618 .ops = &mv88e6123_ops, 5619 }, 5620 5621 [MV88E6131] = { 5622 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5623 .family = MV88E6XXX_FAMILY_6185, 5624 .name = "Marvell 88E6131", 5625 .num_databases = 256, 5626 .num_macs = 8192, 5627 .num_ports = 8, 5628 .num_internal_phys = 0, 5629 .max_vid = 4095, 5630 .port_base_addr = 0x10, 5631 .phy_base_addr = 0x0, 5632 .global1_addr = 0x1b, 5633 .global2_addr = 0x1c, 5634 .age_time_coeff = 15000, 5635 .g1_irqs = 9, 5636 .atu_move_port_mask = 0xf, 5637 .multi_chip = true, 5638 .ops = &mv88e6131_ops, 5639 }, 5640 5641 [MV88E6141] = { 5642 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5643 .family = MV88E6XXX_FAMILY_6341, 5644 .name = "Marvell 88E6141", 5645 .num_databases = 4096, 5646 .num_macs = 2048, 5647 .num_ports = 6, 5648 .num_internal_phys = 5, 5649 .num_gpio = 11, 5650 .max_vid = 4095, 5651 .max_sid = 63, 5652 .port_base_addr = 0x10, 5653 .phy_base_addr = 0x10, 5654 .global1_addr = 0x1b, 5655 .global2_addr = 0x1c, 5656 .age_time_coeff = 3750, 5657 .atu_move_port_mask = 0x1f, 5658 .g1_irqs = 9, 5659 .g2_irqs = 10, 5660 .pvt = true, 5661 .multi_chip = true, 5662 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5663 .ops = &mv88e6141_ops, 5664 }, 5665 5666 [MV88E6161] = { 5667 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5668 .family = MV88E6XXX_FAMILY_6165, 5669 .name = "Marvell 88E6161", 5670 .num_databases = 4096, 5671 .num_macs = 1024, 5672 .num_ports = 6, 5673 .num_internal_phys = 5, 5674 .max_vid = 4095, 5675 .max_sid = 63, 5676 .port_base_addr = 0x10, 5677 .phy_base_addr = 0x0, 5678 .global1_addr = 0x1b, 5679 .global2_addr = 0x1c, 5680 .age_time_coeff = 15000, 5681 .g1_irqs = 9, 5682 .g2_irqs = 10, 5683 .atu_move_port_mask = 0xf, 5684 .pvt = true, 5685 .multi_chip = true, 5686 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5687 .ptp_support = true, 5688 .ops = &mv88e6161_ops, 5689 }, 5690 5691 [MV88E6165] = { 5692 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5693 .family = MV88E6XXX_FAMILY_6165, 5694 .name = "Marvell 88E6165", 5695 .num_databases = 4096, 5696 .num_macs = 8192, 5697 .num_ports = 6, 5698 .num_internal_phys = 0, 5699 .max_vid = 4095, 5700 .max_sid = 63, 5701 .port_base_addr = 0x10, 5702 .phy_base_addr = 0x0, 5703 .global1_addr = 0x1b, 5704 .global2_addr = 0x1c, 5705 .age_time_coeff = 15000, 5706 .g1_irqs = 9, 5707 .g2_irqs = 10, 5708 .atu_move_port_mask = 0xf, 5709 .pvt = true, 5710 .multi_chip = true, 5711 .ptp_support = true, 5712 .ops = &mv88e6165_ops, 5713 }, 5714 5715 [MV88E6171] = { 5716 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5717 .family = MV88E6XXX_FAMILY_6351, 5718 .name = "Marvell 88E6171", 5719 .num_databases = 4096, 5720 .num_macs = 8192, 5721 .num_ports = 7, 5722 .num_internal_phys = 5, 5723 .max_vid = 4095, 5724 .max_sid = 63, 5725 .port_base_addr = 0x10, 5726 .phy_base_addr = 0x0, 5727 .global1_addr = 0x1b, 5728 .global2_addr = 0x1c, 5729 .age_time_coeff = 15000, 5730 .g1_irqs = 9, 5731 .g2_irqs = 10, 5732 .atu_move_port_mask = 0xf, 5733 .pvt = true, 5734 .multi_chip = true, 5735 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5736 .ops = &mv88e6171_ops, 5737 }, 5738 5739 [MV88E6172] = { 5740 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5741 .family = MV88E6XXX_FAMILY_6352, 5742 .name = "Marvell 88E6172", 5743 .num_databases = 4096, 5744 .num_macs = 8192, 5745 .num_ports = 7, 5746 .num_internal_phys = 5, 5747 .num_gpio = 15, 5748 .max_vid = 4095, 5749 .max_sid = 63, 5750 .port_base_addr = 0x10, 5751 .phy_base_addr = 0x0, 5752 .global1_addr = 0x1b, 5753 .global2_addr = 0x1c, 5754 .age_time_coeff = 15000, 5755 .g1_irqs = 9, 5756 .g2_irqs = 10, 5757 .atu_move_port_mask = 0xf, 5758 .pvt = true, 5759 .multi_chip = true, 5760 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5761 .ops = &mv88e6172_ops, 5762 }, 5763 5764 [MV88E6175] = { 5765 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5766 .family = MV88E6XXX_FAMILY_6351, 5767 .name = "Marvell 88E6175", 5768 .num_databases = 4096, 5769 .num_macs = 8192, 5770 .num_ports = 7, 5771 .num_internal_phys = 5, 5772 .max_vid = 4095, 5773 .max_sid = 63, 5774 .port_base_addr = 0x10, 5775 .phy_base_addr = 0x0, 5776 .global1_addr = 0x1b, 5777 .global2_addr = 0x1c, 5778 .age_time_coeff = 15000, 5779 .g1_irqs = 9, 5780 .g2_irqs = 10, 5781 .atu_move_port_mask = 0xf, 5782 .pvt = true, 5783 .multi_chip = true, 5784 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5785 .ops = &mv88e6175_ops, 5786 }, 5787 5788 [MV88E6176] = { 5789 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5790 .family = MV88E6XXX_FAMILY_6352, 5791 .name = "Marvell 88E6176", 5792 .num_databases = 4096, 5793 .num_macs = 8192, 5794 .num_ports = 7, 5795 .num_internal_phys = 5, 5796 .num_gpio = 15, 5797 .max_vid = 4095, 5798 .max_sid = 63, 5799 .port_base_addr = 0x10, 5800 .phy_base_addr = 0x0, 5801 .global1_addr = 0x1b, 5802 .global2_addr = 0x1c, 5803 .age_time_coeff = 15000, 5804 .g1_irqs = 9, 5805 .g2_irqs = 10, 5806 .atu_move_port_mask = 0xf, 5807 .pvt = true, 5808 .multi_chip = true, 5809 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5810 .ops = &mv88e6176_ops, 5811 }, 5812 5813 [MV88E6185] = { 5814 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5815 .family = MV88E6XXX_FAMILY_6185, 5816 .name = "Marvell 88E6185", 5817 .num_databases = 256, 5818 .num_macs = 8192, 5819 .num_ports = 10, 5820 .num_internal_phys = 0, 5821 .max_vid = 4095, 5822 .port_base_addr = 0x10, 5823 .phy_base_addr = 0x0, 5824 .global1_addr = 0x1b, 5825 .global2_addr = 0x1c, 5826 .age_time_coeff = 15000, 5827 .g1_irqs = 8, 5828 .atu_move_port_mask = 0xf, 5829 .multi_chip = true, 5830 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5831 .ops = &mv88e6185_ops, 5832 }, 5833 5834 [MV88E6190] = { 5835 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5836 .family = MV88E6XXX_FAMILY_6390, 5837 .name = "Marvell 88E6190", 5838 .num_databases = 4096, 5839 .num_macs = 16384, 5840 .num_ports = 11, /* 10 + Z80 */ 5841 .num_internal_phys = 9, 5842 .num_gpio = 16, 5843 .max_vid = 8191, 5844 .max_sid = 63, 5845 .port_base_addr = 0x0, 5846 .phy_base_addr = 0x0, 5847 .global1_addr = 0x1b, 5848 .global2_addr = 0x1c, 5849 .age_time_coeff = 3750, 5850 .g1_irqs = 9, 5851 .g2_irqs = 14, 5852 .pvt = true, 5853 .multi_chip = true, 5854 .atu_move_port_mask = 0x1f, 5855 .ops = &mv88e6190_ops, 5856 }, 5857 5858 [MV88E6190X] = { 5859 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5860 .family = MV88E6XXX_FAMILY_6390, 5861 .name = "Marvell 88E6190X", 5862 .num_databases = 4096, 5863 .num_macs = 16384, 5864 .num_ports = 11, /* 10 + Z80 */ 5865 .num_internal_phys = 9, 5866 .num_gpio = 16, 5867 .max_vid = 8191, 5868 .max_sid = 63, 5869 .port_base_addr = 0x0, 5870 .phy_base_addr = 0x0, 5871 .global1_addr = 0x1b, 5872 .global2_addr = 0x1c, 5873 .age_time_coeff = 3750, 5874 .g1_irqs = 9, 5875 .g2_irqs = 14, 5876 .atu_move_port_mask = 0x1f, 5877 .pvt = true, 5878 .multi_chip = true, 5879 .ops = &mv88e6190x_ops, 5880 }, 5881 5882 [MV88E6191] = { 5883 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5884 .family = MV88E6XXX_FAMILY_6390, 5885 .name = "Marvell 88E6191", 5886 .num_databases = 4096, 5887 .num_macs = 16384, 5888 .num_ports = 11, /* 10 + Z80 */ 5889 .num_internal_phys = 9, 5890 .max_vid = 8191, 5891 .max_sid = 63, 5892 .port_base_addr = 0x0, 5893 .phy_base_addr = 0x0, 5894 .global1_addr = 0x1b, 5895 .global2_addr = 0x1c, 5896 .age_time_coeff = 3750, 5897 .g1_irqs = 9, 5898 .g2_irqs = 14, 5899 .atu_move_port_mask = 0x1f, 5900 .pvt = true, 5901 .multi_chip = true, 5902 .ptp_support = true, 5903 .ops = &mv88e6191_ops, 5904 }, 5905 5906 [MV88E6191X] = { 5907 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5908 .family = MV88E6XXX_FAMILY_6393, 5909 .name = "Marvell 88E6191X", 5910 .num_databases = 4096, 5911 .num_ports = 11, /* 10 + Z80 */ 5912 .num_internal_phys = 9, 5913 .max_vid = 8191, 5914 .max_sid = 63, 5915 .port_base_addr = 0x0, 5916 .phy_base_addr = 0x0, 5917 .global1_addr = 0x1b, 5918 .global2_addr = 0x1c, 5919 .age_time_coeff = 3750, 5920 .g1_irqs = 10, 5921 .g2_irqs = 14, 5922 .atu_move_port_mask = 0x1f, 5923 .pvt = true, 5924 .multi_chip = true, 5925 .ptp_support = true, 5926 .ops = &mv88e6393x_ops, 5927 }, 5928 5929 [MV88E6193X] = { 5930 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5931 .family = MV88E6XXX_FAMILY_6393, 5932 .name = "Marvell 88E6193X", 5933 .num_databases = 4096, 5934 .num_ports = 11, /* 10 + Z80 */ 5935 .num_internal_phys = 9, 5936 .max_vid = 8191, 5937 .max_sid = 63, 5938 .port_base_addr = 0x0, 5939 .phy_base_addr = 0x0, 5940 .global1_addr = 0x1b, 5941 .global2_addr = 0x1c, 5942 .age_time_coeff = 3750, 5943 .g1_irqs = 10, 5944 .g2_irqs = 14, 5945 .atu_move_port_mask = 0x1f, 5946 .pvt = true, 5947 .multi_chip = true, 5948 .ptp_support = true, 5949 .ops = &mv88e6393x_ops, 5950 }, 5951 5952 [MV88E6220] = { 5953 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5954 .family = MV88E6XXX_FAMILY_6250, 5955 .name = "Marvell 88E6220", 5956 .num_databases = 64, 5957 5958 /* Ports 2-4 are not routed to pins 5959 * => usable ports 0, 1, 5, 6 5960 */ 5961 .num_ports = 7, 5962 .num_internal_phys = 2, 5963 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5964 .max_vid = 4095, 5965 .port_base_addr = 0x08, 5966 .phy_base_addr = 0x00, 5967 .global1_addr = 0x0f, 5968 .global2_addr = 0x07, 5969 .age_time_coeff = 15000, 5970 .g1_irqs = 9, 5971 .g2_irqs = 10, 5972 .atu_move_port_mask = 0xf, 5973 .dual_chip = true, 5974 .ptp_support = true, 5975 .ops = &mv88e6250_ops, 5976 }, 5977 5978 [MV88E6240] = { 5979 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5980 .family = MV88E6XXX_FAMILY_6352, 5981 .name = "Marvell 88E6240", 5982 .num_databases = 4096, 5983 .num_macs = 8192, 5984 .num_ports = 7, 5985 .num_internal_phys = 5, 5986 .num_gpio = 15, 5987 .max_vid = 4095, 5988 .max_sid = 63, 5989 .port_base_addr = 0x10, 5990 .phy_base_addr = 0x0, 5991 .global1_addr = 0x1b, 5992 .global2_addr = 0x1c, 5993 .age_time_coeff = 15000, 5994 .g1_irqs = 9, 5995 .g2_irqs = 10, 5996 .atu_move_port_mask = 0xf, 5997 .pvt = true, 5998 .multi_chip = true, 5999 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6000 .ptp_support = true, 6001 .ops = &mv88e6240_ops, 6002 }, 6003 6004 [MV88E6250] = { 6005 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6006 .family = MV88E6XXX_FAMILY_6250, 6007 .name = "Marvell 88E6250", 6008 .num_databases = 64, 6009 .num_ports = 7, 6010 .num_internal_phys = 5, 6011 .max_vid = 4095, 6012 .port_base_addr = 0x08, 6013 .phy_base_addr = 0x00, 6014 .global1_addr = 0x0f, 6015 .global2_addr = 0x07, 6016 .age_time_coeff = 15000, 6017 .g1_irqs = 9, 6018 .g2_irqs = 10, 6019 .atu_move_port_mask = 0xf, 6020 .dual_chip = true, 6021 .ptp_support = true, 6022 .ops = &mv88e6250_ops, 6023 }, 6024 6025 [MV88E6290] = { 6026 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6027 .family = MV88E6XXX_FAMILY_6390, 6028 .name = "Marvell 88E6290", 6029 .num_databases = 4096, 6030 .num_ports = 11, /* 10 + Z80 */ 6031 .num_internal_phys = 9, 6032 .num_gpio = 16, 6033 .max_vid = 8191, 6034 .max_sid = 63, 6035 .port_base_addr = 0x0, 6036 .phy_base_addr = 0x0, 6037 .global1_addr = 0x1b, 6038 .global2_addr = 0x1c, 6039 .age_time_coeff = 3750, 6040 .g1_irqs = 9, 6041 .g2_irqs = 14, 6042 .atu_move_port_mask = 0x1f, 6043 .pvt = true, 6044 .multi_chip = true, 6045 .ptp_support = true, 6046 .ops = &mv88e6290_ops, 6047 }, 6048 6049 [MV88E6320] = { 6050 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6051 .family = MV88E6XXX_FAMILY_6320, 6052 .name = "Marvell 88E6320", 6053 .num_databases = 4096, 6054 .num_macs = 8192, 6055 .num_ports = 7, 6056 .num_internal_phys = 5, 6057 .num_gpio = 15, 6058 .max_vid = 4095, 6059 .port_base_addr = 0x10, 6060 .phy_base_addr = 0x0, 6061 .global1_addr = 0x1b, 6062 .global2_addr = 0x1c, 6063 .age_time_coeff = 15000, 6064 .g1_irqs = 8, 6065 .g2_irqs = 10, 6066 .atu_move_port_mask = 0xf, 6067 .pvt = true, 6068 .multi_chip = true, 6069 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6070 .ptp_support = true, 6071 .ops = &mv88e6320_ops, 6072 }, 6073 6074 [MV88E6321] = { 6075 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6076 .family = MV88E6XXX_FAMILY_6320, 6077 .name = "Marvell 88E6321", 6078 .num_databases = 4096, 6079 .num_macs = 8192, 6080 .num_ports = 7, 6081 .num_internal_phys = 5, 6082 .num_gpio = 15, 6083 .max_vid = 4095, 6084 .port_base_addr = 0x10, 6085 .phy_base_addr = 0x0, 6086 .global1_addr = 0x1b, 6087 .global2_addr = 0x1c, 6088 .age_time_coeff = 15000, 6089 .g1_irqs = 8, 6090 .g2_irqs = 10, 6091 .atu_move_port_mask = 0xf, 6092 .multi_chip = true, 6093 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6094 .ptp_support = true, 6095 .ops = &mv88e6321_ops, 6096 }, 6097 6098 [MV88E6341] = { 6099 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6100 .family = MV88E6XXX_FAMILY_6341, 6101 .name = "Marvell 88E6341", 6102 .num_databases = 4096, 6103 .num_macs = 2048, 6104 .num_internal_phys = 5, 6105 .num_ports = 6, 6106 .num_gpio = 11, 6107 .max_vid = 4095, 6108 .max_sid = 63, 6109 .port_base_addr = 0x10, 6110 .phy_base_addr = 0x10, 6111 .global1_addr = 0x1b, 6112 .global2_addr = 0x1c, 6113 .age_time_coeff = 3750, 6114 .atu_move_port_mask = 0x1f, 6115 .g1_irqs = 9, 6116 .g2_irqs = 10, 6117 .pvt = true, 6118 .multi_chip = true, 6119 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6120 .ptp_support = true, 6121 .ops = &mv88e6341_ops, 6122 }, 6123 6124 [MV88E6350] = { 6125 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6126 .family = MV88E6XXX_FAMILY_6351, 6127 .name = "Marvell 88E6350", 6128 .num_databases = 4096, 6129 .num_macs = 8192, 6130 .num_ports = 7, 6131 .num_internal_phys = 5, 6132 .max_vid = 4095, 6133 .max_sid = 63, 6134 .port_base_addr = 0x10, 6135 .phy_base_addr = 0x0, 6136 .global1_addr = 0x1b, 6137 .global2_addr = 0x1c, 6138 .age_time_coeff = 15000, 6139 .g1_irqs = 9, 6140 .g2_irqs = 10, 6141 .atu_move_port_mask = 0xf, 6142 .pvt = true, 6143 .multi_chip = true, 6144 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6145 .ops = &mv88e6350_ops, 6146 }, 6147 6148 [MV88E6351] = { 6149 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6150 .family = MV88E6XXX_FAMILY_6351, 6151 .name = "Marvell 88E6351", 6152 .num_databases = 4096, 6153 .num_macs = 8192, 6154 .num_ports = 7, 6155 .num_internal_phys = 5, 6156 .max_vid = 4095, 6157 .max_sid = 63, 6158 .port_base_addr = 0x10, 6159 .phy_base_addr = 0x0, 6160 .global1_addr = 0x1b, 6161 .global2_addr = 0x1c, 6162 .age_time_coeff = 15000, 6163 .g1_irqs = 9, 6164 .g2_irqs = 10, 6165 .atu_move_port_mask = 0xf, 6166 .pvt = true, 6167 .multi_chip = true, 6168 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6169 .ops = &mv88e6351_ops, 6170 }, 6171 6172 [MV88E6352] = { 6173 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6174 .family = MV88E6XXX_FAMILY_6352, 6175 .name = "Marvell 88E6352", 6176 .num_databases = 4096, 6177 .num_macs = 8192, 6178 .num_ports = 7, 6179 .num_internal_phys = 5, 6180 .num_gpio = 15, 6181 .max_vid = 4095, 6182 .max_sid = 63, 6183 .port_base_addr = 0x10, 6184 .phy_base_addr = 0x0, 6185 .global1_addr = 0x1b, 6186 .global2_addr = 0x1c, 6187 .age_time_coeff = 15000, 6188 .g1_irqs = 9, 6189 .g2_irqs = 10, 6190 .atu_move_port_mask = 0xf, 6191 .pvt = true, 6192 .multi_chip = true, 6193 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6194 .ptp_support = true, 6195 .ops = &mv88e6352_ops, 6196 }, 6197 [MV88E6390] = { 6198 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6199 .family = MV88E6XXX_FAMILY_6390, 6200 .name = "Marvell 88E6390", 6201 .num_databases = 4096, 6202 .num_macs = 16384, 6203 .num_ports = 11, /* 10 + Z80 */ 6204 .num_internal_phys = 9, 6205 .num_gpio = 16, 6206 .max_vid = 8191, 6207 .max_sid = 63, 6208 .port_base_addr = 0x0, 6209 .phy_base_addr = 0x0, 6210 .global1_addr = 0x1b, 6211 .global2_addr = 0x1c, 6212 .age_time_coeff = 3750, 6213 .g1_irqs = 9, 6214 .g2_irqs = 14, 6215 .atu_move_port_mask = 0x1f, 6216 .pvt = true, 6217 .multi_chip = true, 6218 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6219 .ptp_support = true, 6220 .ops = &mv88e6390_ops, 6221 }, 6222 [MV88E6390X] = { 6223 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6224 .family = MV88E6XXX_FAMILY_6390, 6225 .name = "Marvell 88E6390X", 6226 .num_databases = 4096, 6227 .num_macs = 16384, 6228 .num_ports = 11, /* 10 + Z80 */ 6229 .num_internal_phys = 9, 6230 .num_gpio = 16, 6231 .max_vid = 8191, 6232 .max_sid = 63, 6233 .port_base_addr = 0x0, 6234 .phy_base_addr = 0x0, 6235 .global1_addr = 0x1b, 6236 .global2_addr = 0x1c, 6237 .age_time_coeff = 3750, 6238 .g1_irqs = 9, 6239 .g2_irqs = 14, 6240 .atu_move_port_mask = 0x1f, 6241 .pvt = true, 6242 .multi_chip = true, 6243 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6244 .ptp_support = true, 6245 .ops = &mv88e6390x_ops, 6246 }, 6247 6248 [MV88E6393X] = { 6249 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6250 .family = MV88E6XXX_FAMILY_6393, 6251 .name = "Marvell 88E6393X", 6252 .num_databases = 4096, 6253 .num_ports = 11, /* 10 + Z80 */ 6254 .num_internal_phys = 9, 6255 .max_vid = 8191, 6256 .max_sid = 63, 6257 .port_base_addr = 0x0, 6258 .phy_base_addr = 0x0, 6259 .global1_addr = 0x1b, 6260 .global2_addr = 0x1c, 6261 .age_time_coeff = 3750, 6262 .g1_irqs = 10, 6263 .g2_irqs = 14, 6264 .atu_move_port_mask = 0x1f, 6265 .pvt = true, 6266 .multi_chip = true, 6267 .ptp_support = true, 6268 .ops = &mv88e6393x_ops, 6269 }, 6270 }; 6271 6272 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6273 { 6274 int i; 6275 6276 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6277 if (mv88e6xxx_table[i].prod_num == prod_num) 6278 return &mv88e6xxx_table[i]; 6279 6280 return NULL; 6281 } 6282 6283 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6284 { 6285 const struct mv88e6xxx_info *info; 6286 unsigned int prod_num, rev; 6287 u16 id; 6288 int err; 6289 6290 mv88e6xxx_reg_lock(chip); 6291 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6292 mv88e6xxx_reg_unlock(chip); 6293 if (err) 6294 return err; 6295 6296 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6297 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6298 6299 info = mv88e6xxx_lookup_info(prod_num); 6300 if (!info) 6301 return -ENODEV; 6302 6303 /* Update the compatible info with the probed one */ 6304 chip->info = info; 6305 6306 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6307 chip->info->prod_num, chip->info->name, rev); 6308 6309 return 0; 6310 } 6311 6312 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6313 struct mdio_device *mdiodev) 6314 { 6315 int err; 6316 6317 /* dual_chip takes precedence over single/multi-chip modes */ 6318 if (chip->info->dual_chip) 6319 return -EINVAL; 6320 6321 /* If the mdio addr is 16 indicating the first port address of a switch 6322 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6323 * configured in single chip addressing mode. Setup the smi access as 6324 * single chip addressing mode and attempt to detect the model of the 6325 * switch, if this fails the device is not configured in single chip 6326 * addressing mode. 6327 */ 6328 if (mdiodev->addr != 16) 6329 return -EINVAL; 6330 6331 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6332 if (err) 6333 return err; 6334 6335 return mv88e6xxx_detect(chip); 6336 } 6337 6338 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6339 { 6340 struct mv88e6xxx_chip *chip; 6341 6342 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6343 if (!chip) 6344 return NULL; 6345 6346 chip->dev = dev; 6347 6348 mutex_init(&chip->reg_lock); 6349 INIT_LIST_HEAD(&chip->mdios); 6350 idr_init(&chip->policies); 6351 INIT_LIST_HEAD(&chip->msts); 6352 6353 return chip; 6354 } 6355 6356 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6357 int port, 6358 enum dsa_tag_protocol m) 6359 { 6360 struct mv88e6xxx_chip *chip = ds->priv; 6361 6362 return chip->tag_protocol; 6363 } 6364 6365 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6366 enum dsa_tag_protocol proto) 6367 { 6368 struct mv88e6xxx_chip *chip = ds->priv; 6369 enum dsa_tag_protocol old_protocol; 6370 struct dsa_port *cpu_dp; 6371 int err; 6372 6373 switch (proto) { 6374 case DSA_TAG_PROTO_EDSA: 6375 switch (chip->info->edsa_support) { 6376 case MV88E6XXX_EDSA_UNSUPPORTED: 6377 return -EPROTONOSUPPORT; 6378 case MV88E6XXX_EDSA_UNDOCUMENTED: 6379 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6380 fallthrough; 6381 case MV88E6XXX_EDSA_SUPPORTED: 6382 break; 6383 } 6384 break; 6385 case DSA_TAG_PROTO_DSA: 6386 break; 6387 default: 6388 return -EPROTONOSUPPORT; 6389 } 6390 6391 old_protocol = chip->tag_protocol; 6392 chip->tag_protocol = proto; 6393 6394 mv88e6xxx_reg_lock(chip); 6395 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6396 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6397 if (err) { 6398 mv88e6xxx_reg_unlock(chip); 6399 goto unwind; 6400 } 6401 } 6402 mv88e6xxx_reg_unlock(chip); 6403 6404 return 0; 6405 6406 unwind: 6407 chip->tag_protocol = old_protocol; 6408 6409 mv88e6xxx_reg_lock(chip); 6410 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6411 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6412 mv88e6xxx_reg_unlock(chip); 6413 6414 return err; 6415 } 6416 6417 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6418 const struct switchdev_obj_port_mdb *mdb, 6419 struct dsa_db db) 6420 { 6421 struct mv88e6xxx_chip *chip = ds->priv; 6422 int err; 6423 6424 mv88e6xxx_reg_lock(chip); 6425 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6426 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6427 mv88e6xxx_reg_unlock(chip); 6428 6429 return err; 6430 } 6431 6432 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6433 const struct switchdev_obj_port_mdb *mdb, 6434 struct dsa_db db) 6435 { 6436 struct mv88e6xxx_chip *chip = ds->priv; 6437 int err; 6438 6439 mv88e6xxx_reg_lock(chip); 6440 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6441 mv88e6xxx_reg_unlock(chip); 6442 6443 return err; 6444 } 6445 6446 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6447 struct dsa_mall_mirror_tc_entry *mirror, 6448 bool ingress, 6449 struct netlink_ext_ack *extack) 6450 { 6451 enum mv88e6xxx_egress_direction direction = ingress ? 6452 MV88E6XXX_EGRESS_DIR_INGRESS : 6453 MV88E6XXX_EGRESS_DIR_EGRESS; 6454 struct mv88e6xxx_chip *chip = ds->priv; 6455 bool other_mirrors = false; 6456 int i; 6457 int err; 6458 6459 mutex_lock(&chip->reg_lock); 6460 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6461 mirror->to_local_port) { 6462 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6463 other_mirrors |= ingress ? 6464 chip->ports[i].mirror_ingress : 6465 chip->ports[i].mirror_egress; 6466 6467 /* Can't change egress port when other mirror is active */ 6468 if (other_mirrors) { 6469 err = -EBUSY; 6470 goto out; 6471 } 6472 6473 err = mv88e6xxx_set_egress_port(chip, direction, 6474 mirror->to_local_port); 6475 if (err) 6476 goto out; 6477 } 6478 6479 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6480 out: 6481 mutex_unlock(&chip->reg_lock); 6482 6483 return err; 6484 } 6485 6486 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6487 struct dsa_mall_mirror_tc_entry *mirror) 6488 { 6489 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6490 MV88E6XXX_EGRESS_DIR_INGRESS : 6491 MV88E6XXX_EGRESS_DIR_EGRESS; 6492 struct mv88e6xxx_chip *chip = ds->priv; 6493 bool other_mirrors = false; 6494 int i; 6495 6496 mutex_lock(&chip->reg_lock); 6497 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6498 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6499 6500 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6501 other_mirrors |= mirror->ingress ? 6502 chip->ports[i].mirror_ingress : 6503 chip->ports[i].mirror_egress; 6504 6505 /* Reset egress port when no other mirror is active */ 6506 if (!other_mirrors) { 6507 if (mv88e6xxx_set_egress_port(chip, direction, 6508 dsa_upstream_port(ds, port))) 6509 dev_err(ds->dev, "failed to set egress port\n"); 6510 } 6511 6512 mutex_unlock(&chip->reg_lock); 6513 } 6514 6515 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6516 struct switchdev_brport_flags flags, 6517 struct netlink_ext_ack *extack) 6518 { 6519 struct mv88e6xxx_chip *chip = ds->priv; 6520 const struct mv88e6xxx_ops *ops; 6521 6522 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6523 BR_BCAST_FLOOD | BR_PORT_LOCKED)) 6524 return -EINVAL; 6525 6526 ops = chip->info->ops; 6527 6528 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6529 return -EINVAL; 6530 6531 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6532 return -EINVAL; 6533 6534 return 0; 6535 } 6536 6537 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6538 struct switchdev_brport_flags flags, 6539 struct netlink_ext_ack *extack) 6540 { 6541 struct mv88e6xxx_chip *chip = ds->priv; 6542 int err = -EOPNOTSUPP; 6543 6544 mv88e6xxx_reg_lock(chip); 6545 6546 if (flags.mask & BR_LEARNING) { 6547 bool learning = !!(flags.val & BR_LEARNING); 6548 u16 pav = learning ? (1 << port) : 0; 6549 6550 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6551 if (err) 6552 goto out; 6553 } 6554 6555 if (flags.mask & BR_FLOOD) { 6556 bool unicast = !!(flags.val & BR_FLOOD); 6557 6558 err = chip->info->ops->port_set_ucast_flood(chip, port, 6559 unicast); 6560 if (err) 6561 goto out; 6562 } 6563 6564 if (flags.mask & BR_MCAST_FLOOD) { 6565 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6566 6567 err = chip->info->ops->port_set_mcast_flood(chip, port, 6568 multicast); 6569 if (err) 6570 goto out; 6571 } 6572 6573 if (flags.mask & BR_BCAST_FLOOD) { 6574 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6575 6576 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6577 if (err) 6578 goto out; 6579 } 6580 6581 if (flags.mask & BR_PORT_LOCKED) { 6582 bool locked = !!(flags.val & BR_PORT_LOCKED); 6583 6584 err = mv88e6xxx_port_set_lock(chip, port, locked); 6585 if (err) 6586 goto out; 6587 } 6588 out: 6589 mv88e6xxx_reg_unlock(chip); 6590 6591 return err; 6592 } 6593 6594 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6595 struct dsa_lag lag, 6596 struct netdev_lag_upper_info *info, 6597 struct netlink_ext_ack *extack) 6598 { 6599 struct mv88e6xxx_chip *chip = ds->priv; 6600 struct dsa_port *dp; 6601 int members = 0; 6602 6603 if (!mv88e6xxx_has_lag(chip)) { 6604 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6605 return false; 6606 } 6607 6608 if (!lag.id) 6609 return false; 6610 6611 dsa_lag_foreach_port(dp, ds->dst, &lag) 6612 /* Includes the port joining the LAG */ 6613 members++; 6614 6615 if (members > 8) { 6616 NL_SET_ERR_MSG_MOD(extack, 6617 "Cannot offload more than 8 LAG ports"); 6618 return false; 6619 } 6620 6621 /* We could potentially relax this to include active 6622 * backup in the future. 6623 */ 6624 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6625 NL_SET_ERR_MSG_MOD(extack, 6626 "Can only offload LAG using hash TX type"); 6627 return false; 6628 } 6629 6630 /* Ideally we would also validate that the hash type matches 6631 * the hardware. Alas, this is always set to unknown on team 6632 * interfaces. 6633 */ 6634 return true; 6635 } 6636 6637 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6638 { 6639 struct mv88e6xxx_chip *chip = ds->priv; 6640 struct dsa_port *dp; 6641 u16 map = 0; 6642 int id; 6643 6644 /* DSA LAG IDs are one-based, hardware is zero-based */ 6645 id = lag.id - 1; 6646 6647 /* Build the map of all ports to distribute flows destined for 6648 * this LAG. This can be either a local user port, or a DSA 6649 * port if the LAG port is on a remote chip. 6650 */ 6651 dsa_lag_foreach_port(dp, ds->dst, &lag) 6652 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6653 6654 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6655 } 6656 6657 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6658 /* Row number corresponds to the number of active members in a 6659 * LAG. Each column states which of the eight hash buckets are 6660 * mapped to the column:th port in the LAG. 6661 * 6662 * Example: In a LAG with three active ports, the second port 6663 * ([2][1]) would be selected for traffic mapped to buckets 6664 * 3,4,5 (0x38). 6665 */ 6666 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6667 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6668 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6669 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6670 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6671 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6672 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6673 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6674 }; 6675 6676 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6677 int num_tx, int nth) 6678 { 6679 u8 active = 0; 6680 int i; 6681 6682 num_tx = num_tx <= 8 ? num_tx : 8; 6683 if (nth < num_tx) 6684 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6685 6686 for (i = 0; i < 8; i++) { 6687 if (BIT(i) & active) 6688 mask[i] |= BIT(port); 6689 } 6690 } 6691 6692 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6693 { 6694 struct mv88e6xxx_chip *chip = ds->priv; 6695 unsigned int id, num_tx; 6696 struct dsa_port *dp; 6697 struct dsa_lag *lag; 6698 int i, err, nth; 6699 u16 mask[8]; 6700 u16 ivec; 6701 6702 /* Assume no port is a member of any LAG. */ 6703 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6704 6705 /* Disable all masks for ports that _are_ members of a LAG. */ 6706 dsa_switch_for_each_port(dp, ds) { 6707 if (!dp->lag) 6708 continue; 6709 6710 ivec &= ~BIT(dp->index); 6711 } 6712 6713 for (i = 0; i < 8; i++) 6714 mask[i] = ivec; 6715 6716 /* Enable the correct subset of masks for all LAG ports that 6717 * are in the Tx set. 6718 */ 6719 dsa_lags_foreach_id(id, ds->dst) { 6720 lag = dsa_lag_by_id(ds->dst, id); 6721 if (!lag) 6722 continue; 6723 6724 num_tx = 0; 6725 dsa_lag_foreach_port(dp, ds->dst, lag) { 6726 if (dp->lag_tx_enabled) 6727 num_tx++; 6728 } 6729 6730 if (!num_tx) 6731 continue; 6732 6733 nth = 0; 6734 dsa_lag_foreach_port(dp, ds->dst, lag) { 6735 if (!dp->lag_tx_enabled) 6736 continue; 6737 6738 if (dp->ds == ds) 6739 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6740 num_tx, nth); 6741 6742 nth++; 6743 } 6744 } 6745 6746 for (i = 0; i < 8; i++) { 6747 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6748 if (err) 6749 return err; 6750 } 6751 6752 return 0; 6753 } 6754 6755 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6756 struct dsa_lag lag) 6757 { 6758 int err; 6759 6760 err = mv88e6xxx_lag_sync_masks(ds); 6761 6762 if (!err) 6763 err = mv88e6xxx_lag_sync_map(ds, lag); 6764 6765 return err; 6766 } 6767 6768 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6769 { 6770 struct mv88e6xxx_chip *chip = ds->priv; 6771 int err; 6772 6773 mv88e6xxx_reg_lock(chip); 6774 err = mv88e6xxx_lag_sync_masks(ds); 6775 mv88e6xxx_reg_unlock(chip); 6776 return err; 6777 } 6778 6779 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6780 struct dsa_lag lag, 6781 struct netdev_lag_upper_info *info, 6782 struct netlink_ext_ack *extack) 6783 { 6784 struct mv88e6xxx_chip *chip = ds->priv; 6785 int err, id; 6786 6787 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6788 return -EOPNOTSUPP; 6789 6790 /* DSA LAG IDs are one-based */ 6791 id = lag.id - 1; 6792 6793 mv88e6xxx_reg_lock(chip); 6794 6795 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6796 if (err) 6797 goto err_unlock; 6798 6799 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6800 if (err) 6801 goto err_clear_trunk; 6802 6803 mv88e6xxx_reg_unlock(chip); 6804 return 0; 6805 6806 err_clear_trunk: 6807 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6808 err_unlock: 6809 mv88e6xxx_reg_unlock(chip); 6810 return err; 6811 } 6812 6813 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6814 struct dsa_lag lag) 6815 { 6816 struct mv88e6xxx_chip *chip = ds->priv; 6817 int err_sync, err_trunk; 6818 6819 mv88e6xxx_reg_lock(chip); 6820 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6821 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6822 mv88e6xxx_reg_unlock(chip); 6823 return err_sync ? : err_trunk; 6824 } 6825 6826 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6827 int port) 6828 { 6829 struct mv88e6xxx_chip *chip = ds->priv; 6830 int err; 6831 6832 mv88e6xxx_reg_lock(chip); 6833 err = mv88e6xxx_lag_sync_masks(ds); 6834 mv88e6xxx_reg_unlock(chip); 6835 return err; 6836 } 6837 6838 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6839 int port, struct dsa_lag lag, 6840 struct netdev_lag_upper_info *info, 6841 struct netlink_ext_ack *extack) 6842 { 6843 struct mv88e6xxx_chip *chip = ds->priv; 6844 int err; 6845 6846 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6847 return -EOPNOTSUPP; 6848 6849 mv88e6xxx_reg_lock(chip); 6850 6851 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6852 if (err) 6853 goto unlock; 6854 6855 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6856 6857 unlock: 6858 mv88e6xxx_reg_unlock(chip); 6859 return err; 6860 } 6861 6862 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6863 int port, struct dsa_lag lag) 6864 { 6865 struct mv88e6xxx_chip *chip = ds->priv; 6866 int err_sync, err_pvt; 6867 6868 mv88e6xxx_reg_lock(chip); 6869 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6870 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6871 mv88e6xxx_reg_unlock(chip); 6872 return err_sync ? : err_pvt; 6873 } 6874 6875 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6876 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6877 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6878 .setup = mv88e6xxx_setup, 6879 .teardown = mv88e6xxx_teardown, 6880 .port_setup = mv88e6xxx_port_setup, 6881 .port_teardown = mv88e6xxx_port_teardown, 6882 .phylink_get_caps = mv88e6xxx_get_caps, 6883 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6884 .phylink_mac_config = mv88e6xxx_mac_config, 6885 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6886 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6887 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6888 .get_strings = mv88e6xxx_get_strings, 6889 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6890 .get_sset_count = mv88e6xxx_get_sset_count, 6891 .port_enable = mv88e6xxx_port_enable, 6892 .port_disable = mv88e6xxx_port_disable, 6893 .port_max_mtu = mv88e6xxx_get_max_mtu, 6894 .port_change_mtu = mv88e6xxx_change_mtu, 6895 .get_mac_eee = mv88e6xxx_get_mac_eee, 6896 .set_mac_eee = mv88e6xxx_set_mac_eee, 6897 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6898 .get_eeprom = mv88e6xxx_get_eeprom, 6899 .set_eeprom = mv88e6xxx_set_eeprom, 6900 .get_regs_len = mv88e6xxx_get_regs_len, 6901 .get_regs = mv88e6xxx_get_regs, 6902 .get_rxnfc = mv88e6xxx_get_rxnfc, 6903 .set_rxnfc = mv88e6xxx_set_rxnfc, 6904 .set_ageing_time = mv88e6xxx_set_ageing_time, 6905 .port_bridge_join = mv88e6xxx_port_bridge_join, 6906 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6907 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6908 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6909 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6910 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 6911 .port_fast_age = mv88e6xxx_port_fast_age, 6912 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 6913 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6914 .port_vlan_add = mv88e6xxx_port_vlan_add, 6915 .port_vlan_del = mv88e6xxx_port_vlan_del, 6916 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 6917 .port_fdb_add = mv88e6xxx_port_fdb_add, 6918 .port_fdb_del = mv88e6xxx_port_fdb_del, 6919 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6920 .port_mdb_add = mv88e6xxx_port_mdb_add, 6921 .port_mdb_del = mv88e6xxx_port_mdb_del, 6922 .port_mirror_add = mv88e6xxx_port_mirror_add, 6923 .port_mirror_del = mv88e6xxx_port_mirror_del, 6924 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6925 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6926 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6927 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6928 .port_txtstamp = mv88e6xxx_port_txtstamp, 6929 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6930 .get_ts_info = mv88e6xxx_get_ts_info, 6931 .devlink_param_get = mv88e6xxx_devlink_param_get, 6932 .devlink_param_set = mv88e6xxx_devlink_param_set, 6933 .devlink_info_get = mv88e6xxx_devlink_info_get, 6934 .port_lag_change = mv88e6xxx_port_lag_change, 6935 .port_lag_join = mv88e6xxx_port_lag_join, 6936 .port_lag_leave = mv88e6xxx_port_lag_leave, 6937 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6938 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6939 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6940 }; 6941 6942 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6943 { 6944 struct device *dev = chip->dev; 6945 struct dsa_switch *ds; 6946 6947 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6948 if (!ds) 6949 return -ENOMEM; 6950 6951 ds->dev = dev; 6952 ds->num_ports = mv88e6xxx_num_ports(chip); 6953 ds->priv = chip; 6954 ds->dev = dev; 6955 ds->ops = &mv88e6xxx_switch_ops; 6956 ds->ageing_time_min = chip->info->age_time_coeff; 6957 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6958 6959 /* Some chips support up to 32, but that requires enabling the 6960 * 5-bit port mode, which we do not support. 640k^W16 ought to 6961 * be enough for anyone. 6962 */ 6963 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6964 6965 dev_set_drvdata(dev, ds); 6966 6967 return dsa_register_switch(ds); 6968 } 6969 6970 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6971 { 6972 dsa_unregister_switch(chip->ds); 6973 } 6974 6975 static const void *pdata_device_get_match_data(struct device *dev) 6976 { 6977 const struct of_device_id *matches = dev->driver->of_match_table; 6978 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6979 6980 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6981 matches++) { 6982 if (!strcmp(pdata->compatible, matches->compatible)) 6983 return matches->data; 6984 } 6985 return NULL; 6986 } 6987 6988 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6989 * would be lost after a power cycle so prevent it to be suspended. 6990 */ 6991 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6992 { 6993 return -EOPNOTSUPP; 6994 } 6995 6996 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6997 { 6998 return 0; 6999 } 7000 7001 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7002 7003 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7004 { 7005 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7006 const struct mv88e6xxx_info *compat_info = NULL; 7007 struct device *dev = &mdiodev->dev; 7008 struct device_node *np = dev->of_node; 7009 struct mv88e6xxx_chip *chip; 7010 int port; 7011 int err; 7012 7013 if (!np && !pdata) 7014 return -EINVAL; 7015 7016 if (np) 7017 compat_info = of_device_get_match_data(dev); 7018 7019 if (pdata) { 7020 compat_info = pdata_device_get_match_data(dev); 7021 7022 if (!pdata->netdev) 7023 return -EINVAL; 7024 7025 for (port = 0; port < DSA_MAX_PORTS; port++) { 7026 if (!(pdata->enabled_ports & (1 << port))) 7027 continue; 7028 if (strcmp(pdata->cd.port_names[port], "cpu")) 7029 continue; 7030 pdata->cd.netdev[port] = &pdata->netdev->dev; 7031 break; 7032 } 7033 } 7034 7035 if (!compat_info) 7036 return -EINVAL; 7037 7038 chip = mv88e6xxx_alloc_chip(dev); 7039 if (!chip) { 7040 err = -ENOMEM; 7041 goto out; 7042 } 7043 7044 chip->info = compat_info; 7045 7046 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7047 if (IS_ERR(chip->reset)) { 7048 err = PTR_ERR(chip->reset); 7049 goto out; 7050 } 7051 if (chip->reset) 7052 usleep_range(1000, 2000); 7053 7054 /* Detect if the device is configured in single chip addressing mode, 7055 * otherwise continue with address specific smi init/detection. 7056 */ 7057 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7058 if (err) { 7059 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7060 if (err) 7061 goto out; 7062 7063 err = mv88e6xxx_detect(chip); 7064 if (err) 7065 goto out; 7066 } 7067 7068 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7069 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7070 else 7071 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7072 7073 mv88e6xxx_phy_init(chip); 7074 7075 if (chip->info->ops->get_eeprom) { 7076 if (np) 7077 of_property_read_u32(np, "eeprom-length", 7078 &chip->eeprom_len); 7079 else 7080 chip->eeprom_len = pdata->eeprom_len; 7081 } 7082 7083 mv88e6xxx_reg_lock(chip); 7084 err = mv88e6xxx_switch_reset(chip); 7085 mv88e6xxx_reg_unlock(chip); 7086 if (err) 7087 goto out; 7088 7089 if (np) { 7090 chip->irq = of_irq_get(np, 0); 7091 if (chip->irq == -EPROBE_DEFER) { 7092 err = chip->irq; 7093 goto out; 7094 } 7095 } 7096 7097 if (pdata) 7098 chip->irq = pdata->irq; 7099 7100 /* Has to be performed before the MDIO bus is created, because 7101 * the PHYs will link their interrupts to these interrupt 7102 * controllers 7103 */ 7104 mv88e6xxx_reg_lock(chip); 7105 if (chip->irq > 0) 7106 err = mv88e6xxx_g1_irq_setup(chip); 7107 else 7108 err = mv88e6xxx_irq_poll_setup(chip); 7109 mv88e6xxx_reg_unlock(chip); 7110 7111 if (err) 7112 goto out; 7113 7114 if (chip->info->g2_irqs > 0) { 7115 err = mv88e6xxx_g2_irq_setup(chip); 7116 if (err) 7117 goto out_g1_irq; 7118 } 7119 7120 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7121 if (err) 7122 goto out_g2_irq; 7123 7124 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7125 if (err) 7126 goto out_g1_atu_prob_irq; 7127 7128 err = mv88e6xxx_mdios_register(chip, np); 7129 if (err) 7130 goto out_g1_vtu_prob_irq; 7131 7132 err = mv88e6xxx_register_switch(chip); 7133 if (err) 7134 goto out_mdio; 7135 7136 return 0; 7137 7138 out_mdio: 7139 mv88e6xxx_mdios_unregister(chip); 7140 out_g1_vtu_prob_irq: 7141 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7142 out_g1_atu_prob_irq: 7143 mv88e6xxx_g1_atu_prob_irq_free(chip); 7144 out_g2_irq: 7145 if (chip->info->g2_irqs > 0) 7146 mv88e6xxx_g2_irq_free(chip); 7147 out_g1_irq: 7148 if (chip->irq > 0) 7149 mv88e6xxx_g1_irq_free(chip); 7150 else 7151 mv88e6xxx_irq_poll_free(chip); 7152 out: 7153 if (pdata) 7154 dev_put(pdata->netdev); 7155 7156 return err; 7157 } 7158 7159 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7160 { 7161 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7162 struct mv88e6xxx_chip *chip; 7163 7164 if (!ds) 7165 return; 7166 7167 chip = ds->priv; 7168 7169 if (chip->info->ptp_support) { 7170 mv88e6xxx_hwtstamp_free(chip); 7171 mv88e6xxx_ptp_free(chip); 7172 } 7173 7174 mv88e6xxx_phy_destroy(chip); 7175 mv88e6xxx_unregister_switch(chip); 7176 mv88e6xxx_mdios_unregister(chip); 7177 7178 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7179 mv88e6xxx_g1_atu_prob_irq_free(chip); 7180 7181 if (chip->info->g2_irqs > 0) 7182 mv88e6xxx_g2_irq_free(chip); 7183 7184 if (chip->irq > 0) 7185 mv88e6xxx_g1_irq_free(chip); 7186 else 7187 mv88e6xxx_irq_poll_free(chip); 7188 } 7189 7190 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7191 { 7192 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7193 7194 if (!ds) 7195 return; 7196 7197 dsa_switch_shutdown(ds); 7198 7199 dev_set_drvdata(&mdiodev->dev, NULL); 7200 } 7201 7202 static const struct of_device_id mv88e6xxx_of_match[] = { 7203 { 7204 .compatible = "marvell,mv88e6085", 7205 .data = &mv88e6xxx_table[MV88E6085], 7206 }, 7207 { 7208 .compatible = "marvell,mv88e6190", 7209 .data = &mv88e6xxx_table[MV88E6190], 7210 }, 7211 { 7212 .compatible = "marvell,mv88e6250", 7213 .data = &mv88e6xxx_table[MV88E6250], 7214 }, 7215 { /* sentinel */ }, 7216 }; 7217 7218 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7219 7220 static struct mdio_driver mv88e6xxx_driver = { 7221 .probe = mv88e6xxx_probe, 7222 .remove = mv88e6xxx_remove, 7223 .shutdown = mv88e6xxx_shutdown, 7224 .mdiodrv.driver = { 7225 .name = "mv88e6085", 7226 .of_match_table = mv88e6xxx_of_match, 7227 .pm = &mv88e6xxx_pm_ops, 7228 }, 7229 }; 7230 7231 mdio_module_driver(mv88e6xxx_driver); 7232 7233 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7234 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7235 MODULE_LICENSE("GPL"); 7236