xref: /openbmc/linux/drivers/i2c/busses/i2c-s3c2410.c (revision 724ba675)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3  *
4  * Copyright (C) 2004,2005,2009 Simtec Electronics
5  *	Ben Dooks <ben@simtec.co.uk>
6  *
7  * S3C2410 I2C Controller
8 */
9 
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/clk.h>
23 #include <linux/cpufreq.h>
24 #include <linux/slab.h>
25 #include <linux/io.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/mfd/syscon.h>
31 #include <linux/regmap.h>
32 
33 #include <asm/irq.h>
34 
35 #include <linux/platform_data/i2c-s3c2410.h>
36 
37 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
38 
39 #define S3C2410_IICCON			0x00
40 #define S3C2410_IICSTAT			0x04
41 #define S3C2410_IICADD			0x08
42 #define S3C2410_IICDS			0x0C
43 #define S3C2440_IICLC			0x10
44 
45 #define S3C2410_IICCON_ACKEN		(1 << 7)
46 #define S3C2410_IICCON_TXDIV_16		(0 << 6)
47 #define S3C2410_IICCON_TXDIV_512	(1 << 6)
48 #define S3C2410_IICCON_IRQEN		(1 << 5)
49 #define S3C2410_IICCON_IRQPEND		(1 << 4)
50 #define S3C2410_IICCON_SCALE(x)		((x) & 0xf)
51 #define S3C2410_IICCON_SCALEMASK	(0xf)
52 
53 #define S3C2410_IICSTAT_MASTER_RX	(2 << 6)
54 #define S3C2410_IICSTAT_MASTER_TX	(3 << 6)
55 #define S3C2410_IICSTAT_SLAVE_RX	(0 << 6)
56 #define S3C2410_IICSTAT_SLAVE_TX	(1 << 6)
57 #define S3C2410_IICSTAT_MODEMASK	(3 << 6)
58 
59 #define S3C2410_IICSTAT_START		(1 << 5)
60 #define S3C2410_IICSTAT_BUSBUSY		(1 << 5)
61 #define S3C2410_IICSTAT_TXRXEN		(1 << 4)
62 #define S3C2410_IICSTAT_ARBITR		(1 << 3)
63 #define S3C2410_IICSTAT_ASSLAVE		(1 << 2)
64 #define S3C2410_IICSTAT_ADDR0		(1 << 1)
65 #define S3C2410_IICSTAT_LASTBIT		(1 << 0)
66 
67 #define S3C2410_IICLC_SDA_DELAY0	(0 << 0)
68 #define S3C2410_IICLC_SDA_DELAY5	(1 << 0)
69 #define S3C2410_IICLC_SDA_DELAY10	(2 << 0)
70 #define S3C2410_IICLC_SDA_DELAY15	(3 << 0)
71 #define S3C2410_IICLC_SDA_DELAY_MASK	(3 << 0)
72 
73 #define S3C2410_IICLC_FILTER_ON		(1 << 2)
74 
75 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
76 #define QUIRK_S3C2440		(1 << 0)
77 #define QUIRK_HDMIPHY		(1 << 1)
78 #define QUIRK_NO_GPIO		(1 << 2)
79 #define QUIRK_POLL		(1 << 3)
80 
81 /* Max time to wait for bus to become idle after a xfer (in us) */
82 #define S3C2410_IDLE_TIMEOUT	5000
83 
84 /* Exynos5 Sysreg offset */
85 #define EXYNOS5_SYS_I2C_CFG	0x0234
86 
87 /* i2c controller state */
88 enum s3c24xx_i2c_state {
89 	STATE_IDLE,
90 	STATE_START,
91 	STATE_READ,
92 	STATE_WRITE,
93 	STATE_STOP
94 };
95 
96 struct s3c24xx_i2c {
97 	wait_queue_head_t	wait;
98 	kernel_ulong_t		quirks;
99 
100 	struct i2c_msg		*msg;
101 	unsigned int		msg_num;
102 	unsigned int		msg_idx;
103 	unsigned int		msg_ptr;
104 
105 	unsigned int		tx_setup;
106 	unsigned int		irq;
107 
108 	enum s3c24xx_i2c_state	state;
109 	unsigned long		clkrate;
110 
111 	void __iomem		*regs;
112 	struct clk		*clk;
113 	struct device		*dev;
114 	struct i2c_adapter	adap;
115 
116 	struct s3c2410_platform_i2c	*pdata;
117 	struct gpio_desc	*gpios[2];
118 	struct pinctrl          *pctrl;
119 	struct regmap		*sysreg;
120 	unsigned int		sys_i2c_cfg;
121 };
122 
123 static const struct platform_device_id s3c24xx_driver_ids[] = {
124 	{
125 		.name		= "s3c2410-i2c",
126 		.driver_data	= 0,
127 	}, {
128 		.name		= "s3c2440-i2c",
129 		.driver_data	= QUIRK_S3C2440,
130 	}, {
131 		.name		= "s3c2440-hdmiphy-i2c",
132 		.driver_data	= QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
133 	}, { },
134 };
135 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
136 
137 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
138 
139 #ifdef CONFIG_OF
140 static const struct of_device_id s3c24xx_i2c_match[] = {
141 	{ .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
142 	{ .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
143 	{ .compatible = "samsung,s3c2440-hdmiphy-i2c",
144 	  .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
145 	{ .compatible = "samsung,exynos5-sata-phy-i2c",
146 	  .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
147 	{},
148 };
149 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
150 #endif
151 
152 /*
153  * Get controller type either from device tree or platform device variant.
154  */
155 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
156 {
157 	if (pdev->dev.of_node)
158 		return (kernel_ulong_t)of_device_get_match_data(&pdev->dev);
159 
160 	return platform_get_device_id(pdev)->driver_data;
161 }
162 
163 /*
164  * Complete the message and wake up the caller, using the given return code,
165  * or zero to mean ok.
166  */
167 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
168 {
169 	dev_dbg(i2c->dev, "master_complete %d\n", ret);
170 
171 	i2c->msg_ptr = 0;
172 	i2c->msg = NULL;
173 	i2c->msg_idx++;
174 	i2c->msg_num = 0;
175 	if (ret)
176 		i2c->msg_idx = ret;
177 
178 	if (!(i2c->quirks & QUIRK_POLL))
179 		wake_up(&i2c->wait);
180 }
181 
182 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
183 {
184 	unsigned long tmp;
185 
186 	tmp = readl(i2c->regs + S3C2410_IICCON);
187 	writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
188 }
189 
190 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
191 {
192 	unsigned long tmp;
193 
194 	tmp = readl(i2c->regs + S3C2410_IICCON);
195 	writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
196 }
197 
198 /* irq enable/disable functions */
199 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
200 {
201 	unsigned long tmp;
202 
203 	tmp = readl(i2c->regs + S3C2410_IICCON);
204 	writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
205 }
206 
207 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
208 {
209 	unsigned long tmp;
210 
211 	tmp = readl(i2c->regs + S3C2410_IICCON);
212 	writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
213 }
214 
215 static bool is_ack(struct s3c24xx_i2c *i2c)
216 {
217 	int tries;
218 
219 	for (tries = 50; tries; --tries) {
220 		if (readl(i2c->regs + S3C2410_IICCON)
221 			& S3C2410_IICCON_IRQPEND) {
222 			if (!(readl(i2c->regs + S3C2410_IICSTAT)
223 				& S3C2410_IICSTAT_LASTBIT))
224 				return true;
225 		}
226 		usleep_range(1000, 2000);
227 	}
228 	dev_err(i2c->dev, "ack was not received\n");
229 	return false;
230 }
231 
232 /*
233  * put the start of a message onto the bus
234  */
235 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
236 				      struct i2c_msg *msg)
237 {
238 	unsigned int addr = (msg->addr & 0x7f) << 1;
239 	unsigned long stat;
240 	unsigned long iiccon;
241 
242 	stat = 0;
243 	stat |=  S3C2410_IICSTAT_TXRXEN;
244 
245 	if (msg->flags & I2C_M_RD) {
246 		stat |= S3C2410_IICSTAT_MASTER_RX;
247 		addr |= 1;
248 	} else
249 		stat |= S3C2410_IICSTAT_MASTER_TX;
250 
251 	if (msg->flags & I2C_M_REV_DIR_ADDR)
252 		addr ^= 1;
253 
254 	/* todo - check for whether ack wanted or not */
255 	s3c24xx_i2c_enable_ack(i2c);
256 
257 	iiccon = readl(i2c->regs + S3C2410_IICCON);
258 	writel(stat, i2c->regs + S3C2410_IICSTAT);
259 
260 	dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
261 	writeb(addr, i2c->regs + S3C2410_IICDS);
262 
263 	/*
264 	 * delay here to ensure the data byte has gotten onto the bus
265 	 * before the transaction is started
266 	 */
267 	ndelay(i2c->tx_setup);
268 
269 	dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
270 	writel(iiccon, i2c->regs + S3C2410_IICCON);
271 
272 	stat |= S3C2410_IICSTAT_START;
273 	writel(stat, i2c->regs + S3C2410_IICSTAT);
274 
275 	if (i2c->quirks & QUIRK_POLL) {
276 		while ((i2c->msg_num != 0) && is_ack(i2c)) {
277 			i2c_s3c_irq_nextbyte(i2c, stat);
278 			stat = readl(i2c->regs + S3C2410_IICSTAT);
279 
280 			if (stat & S3C2410_IICSTAT_ARBITR)
281 				dev_err(i2c->dev, "deal with arbitration loss\n");
282 		}
283 	}
284 }
285 
286 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
287 {
288 	unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
289 
290 	dev_dbg(i2c->dev, "STOP\n");
291 
292 	/*
293 	 * The datasheet says that the STOP sequence should be:
294 	 *  1) I2CSTAT.5 = 0	- Clear BUSY (or 'generate STOP')
295 	 *  2) I2CCON.4 = 0	- Clear IRQPEND
296 	 *  3) Wait until the stop condition takes effect.
297 	 *  4*) I2CSTAT.4 = 0	- Clear TXRXEN
298 	 *
299 	 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
300 	 *
301 	 * However, after much experimentation, it appears that:
302 	 * a) normal buses automatically clear BUSY and transition from
303 	 *    Master->Slave when they complete generating a STOP condition.
304 	 *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
305 	 *    after starting the STOP generation here.
306 	 * b) HDMIPHY bus does neither, so there is no way to do step 3.
307 	 *    There is no indication when this bus has finished generating
308 	 *    STOP.
309 	 *
310 	 * In fact, we have found that as soon as the IRQPEND bit is cleared in
311 	 * step 2, the HDMIPHY bus generates the STOP condition, and then
312 	 * immediately starts transferring another data byte, even though the
313 	 * bus is supposedly stopped.  This is presumably because the bus is
314 	 * still in "Master" mode, and its BUSY bit is still set.
315 	 *
316 	 * To avoid these extra post-STOP transactions on HDMI phy devices, we
317 	 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
318 	 * instead of first generating a proper STOP condition.  This should
319 	 * float SDA & SCK terminating the transfer.  Subsequent transfers
320 	 *  start with a proper START condition, and proceed normally.
321 	 *
322 	 * The HDMIPHY bus is an internal bus that always has exactly two
323 	 * devices, the host as Master and the HDMIPHY device as the slave.
324 	 * Skipping the STOP condition has been tested on this bus and works.
325 	 */
326 	if (i2c->quirks & QUIRK_HDMIPHY) {
327 		/* Stop driving the I2C pins */
328 		iicstat &= ~S3C2410_IICSTAT_TXRXEN;
329 	} else {
330 		/* stop the transfer */
331 		iicstat &= ~S3C2410_IICSTAT_START;
332 	}
333 	writel(iicstat, i2c->regs + S3C2410_IICSTAT);
334 
335 	i2c->state = STATE_STOP;
336 
337 	s3c24xx_i2c_master_complete(i2c, ret);
338 	s3c24xx_i2c_disable_irq(i2c);
339 }
340 
341 /*
342  * helper functions to determine the current state in the set of
343  * messages we are sending
344  */
345 
346 /*
347  * returns TRUE if the current message is the last in the set
348  */
349 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
350 {
351 	return i2c->msg_idx >= (i2c->msg_num - 1);
352 }
353 
354 /*
355  * returns TRUE if we this is the last byte in the current message
356  */
357 static inline int is_msglast(struct s3c24xx_i2c *i2c)
358 {
359 	/*
360 	 * msg->len is always 1 for the first byte of smbus block read.
361 	 * Actual length will be read from slave. More bytes will be
362 	 * read according to the length then.
363 	 */
364 	if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
365 		return 0;
366 
367 	return i2c->msg_ptr == i2c->msg->len-1;
368 }
369 
370 /*
371  * returns TRUE if we reached the end of the current message
372  */
373 static inline int is_msgend(struct s3c24xx_i2c *i2c)
374 {
375 	return i2c->msg_ptr >= i2c->msg->len;
376 }
377 
378 /*
379  * process an interrupt and work out what to do
380  */
381 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
382 {
383 	unsigned long tmp;
384 	unsigned char byte;
385 	int ret = 0;
386 
387 	switch (i2c->state) {
388 
389 	case STATE_IDLE:
390 		dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
391 		goto out;
392 
393 	case STATE_STOP:
394 		dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
395 		s3c24xx_i2c_disable_irq(i2c);
396 		goto out_ack;
397 
398 	case STATE_START:
399 		/*
400 		 * last thing we did was send a start condition on the
401 		 * bus, or started a new i2c message
402 		 */
403 		if (iicstat & S3C2410_IICSTAT_LASTBIT &&
404 		    !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
405 			/* ack was not received... */
406 			dev_dbg(i2c->dev, "ack was not received\n");
407 			s3c24xx_i2c_stop(i2c, -ENXIO);
408 			goto out_ack;
409 		}
410 
411 		if (i2c->msg->flags & I2C_M_RD)
412 			i2c->state = STATE_READ;
413 		else
414 			i2c->state = STATE_WRITE;
415 
416 		/*
417 		 * Terminate the transfer if there is nothing to do
418 		 * as this is used by the i2c probe to find devices.
419 		 */
420 		if (is_lastmsg(i2c) && i2c->msg->len == 0) {
421 			s3c24xx_i2c_stop(i2c, 0);
422 			goto out_ack;
423 		}
424 
425 		if (i2c->state == STATE_READ)
426 			goto prepare_read;
427 
428 		/*
429 		 * fall through to the write state, as we will need to
430 		 * send a byte as well
431 		 */
432 		fallthrough;
433 	case STATE_WRITE:
434 		/*
435 		 * we are writing data to the device... check for the
436 		 * end of the message, and if so, work out what to do
437 		 */
438 		if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
439 			if (iicstat & S3C2410_IICSTAT_LASTBIT) {
440 				dev_dbg(i2c->dev, "WRITE: No Ack\n");
441 
442 				s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
443 				goto out_ack;
444 			}
445 		}
446 
447  retry_write:
448 
449 		if (!is_msgend(i2c)) {
450 			byte = i2c->msg->buf[i2c->msg_ptr++];
451 			writeb(byte, i2c->regs + S3C2410_IICDS);
452 
453 			/*
454 			 * delay after writing the byte to allow the
455 			 * data setup time on the bus, as writing the
456 			 * data to the register causes the first bit
457 			 * to appear on SDA, and SCL will change as
458 			 * soon as the interrupt is acknowledged
459 			 */
460 			ndelay(i2c->tx_setup);
461 
462 		} else if (!is_lastmsg(i2c)) {
463 			/* we need to go to the next i2c message */
464 
465 			dev_dbg(i2c->dev, "WRITE: Next Message\n");
466 
467 			i2c->msg_ptr = 0;
468 			i2c->msg_idx++;
469 			i2c->msg++;
470 
471 			/* check to see if we need to do another message */
472 			if (i2c->msg->flags & I2C_M_NOSTART) {
473 
474 				if (i2c->msg->flags & I2C_M_RD) {
475 					/*
476 					 * cannot do this, the controller
477 					 * forces us to send a new START
478 					 * when we change direction
479 					 */
480 					dev_dbg(i2c->dev,
481 						"missing START before write->read\n");
482 					s3c24xx_i2c_stop(i2c, -EINVAL);
483 					break;
484 				}
485 
486 				goto retry_write;
487 			} else {
488 				/* send the new start */
489 				s3c24xx_i2c_message_start(i2c, i2c->msg);
490 				i2c->state = STATE_START;
491 			}
492 
493 		} else {
494 			/* send stop */
495 			s3c24xx_i2c_stop(i2c, 0);
496 		}
497 		break;
498 
499 	case STATE_READ:
500 		/*
501 		 * we have a byte of data in the data register, do
502 		 * something with it, and then work out whether we are
503 		 * going to do any more read/write
504 		 */
505 		byte = readb(i2c->regs + S3C2410_IICDS);
506 		i2c->msg->buf[i2c->msg_ptr++] = byte;
507 
508 		/* Add actual length to read for smbus block read */
509 		if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
510 			i2c->msg->len += byte;
511  prepare_read:
512 		if (is_msglast(i2c)) {
513 			/* last byte of buffer */
514 
515 			if (is_lastmsg(i2c))
516 				s3c24xx_i2c_disable_ack(i2c);
517 
518 		} else if (is_msgend(i2c)) {
519 			/*
520 			 * ok, we've read the entire buffer, see if there
521 			 * is anything else we need to do
522 			 */
523 			if (is_lastmsg(i2c)) {
524 				/* last message, send stop and complete */
525 				dev_dbg(i2c->dev, "READ: Send Stop\n");
526 
527 				s3c24xx_i2c_stop(i2c, 0);
528 			} else {
529 				/* go to the next transfer */
530 				dev_dbg(i2c->dev, "READ: Next Transfer\n");
531 
532 				i2c->msg_ptr = 0;
533 				i2c->msg_idx++;
534 				i2c->msg++;
535 			}
536 		}
537 
538 		break;
539 	}
540 
541 	/* acknowlegde the IRQ and get back on with the work */
542 
543  out_ack:
544 	tmp = readl(i2c->regs + S3C2410_IICCON);
545 	tmp &= ~S3C2410_IICCON_IRQPEND;
546 	writel(tmp, i2c->regs + S3C2410_IICCON);
547  out:
548 	return ret;
549 }
550 
551 /*
552  * top level IRQ servicing routine
553  */
554 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
555 {
556 	struct s3c24xx_i2c *i2c = dev_id;
557 	unsigned long status;
558 	unsigned long tmp;
559 
560 	status = readl(i2c->regs + S3C2410_IICSTAT);
561 
562 	if (status & S3C2410_IICSTAT_ARBITR) {
563 		/* deal with arbitration loss */
564 		dev_err(i2c->dev, "deal with arbitration loss\n");
565 	}
566 
567 	if (i2c->state == STATE_IDLE) {
568 		dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
569 
570 		tmp = readl(i2c->regs + S3C2410_IICCON);
571 		tmp &= ~S3C2410_IICCON_IRQPEND;
572 		writel(tmp, i2c->regs +  S3C2410_IICCON);
573 		goto out;
574 	}
575 
576 	/*
577 	 * pretty much this leaves us with the fact that we've
578 	 * transmitted or received whatever byte we last sent
579 	 */
580 	i2c_s3c_irq_nextbyte(i2c, status);
581 
582  out:
583 	return IRQ_HANDLED;
584 }
585 
586 /*
587  * Disable the bus so that we won't get any interrupts from now on, or try
588  * to drive any lines. This is the default state when we don't have
589  * anything to send/receive.
590  *
591  * If there is an event on the bus, or we have a pre-existing event at
592  * kernel boot time, we may not notice the event and the I2C controller
593  * will lock the bus with the I2C clock line low indefinitely.
594  */
595 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
596 {
597 	unsigned long tmp;
598 
599 	/* Stop driving the I2C pins */
600 	tmp = readl(i2c->regs + S3C2410_IICSTAT);
601 	tmp &= ~S3C2410_IICSTAT_TXRXEN;
602 	writel(tmp, i2c->regs + S3C2410_IICSTAT);
603 
604 	/* We don't expect any interrupts now, and don't want send acks */
605 	tmp = readl(i2c->regs + S3C2410_IICCON);
606 	tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
607 		S3C2410_IICCON_ACKEN);
608 	writel(tmp, i2c->regs + S3C2410_IICCON);
609 }
610 
611 
612 /*
613  * get the i2c bus for a master transaction
614  */
615 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
616 {
617 	unsigned long iicstat;
618 	int timeout = 400;
619 
620 	while (timeout-- > 0) {
621 		iicstat = readl(i2c->regs + S3C2410_IICSTAT);
622 
623 		if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
624 			return 0;
625 
626 		msleep(1);
627 	}
628 
629 	return -ETIMEDOUT;
630 }
631 
632 /*
633  * wait for the i2c bus to become idle.
634  */
635 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
636 {
637 	unsigned long iicstat;
638 	ktime_t start, now;
639 	unsigned long delay;
640 	int spins;
641 
642 	/* ensure the stop has been through the bus */
643 
644 	dev_dbg(i2c->dev, "waiting for bus idle\n");
645 
646 	start = now = ktime_get();
647 
648 	/*
649 	 * Most of the time, the bus is already idle within a few usec of the
650 	 * end of a transaction.  However, really slow i2c devices can stretch
651 	 * the clock, delaying STOP generation.
652 	 *
653 	 * On slower SoCs this typically happens within a very small number of
654 	 * instructions so busy wait briefly to avoid scheduling overhead.
655 	 */
656 	spins = 3;
657 	iicstat = readl(i2c->regs + S3C2410_IICSTAT);
658 	while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
659 		cpu_relax();
660 		iicstat = readl(i2c->regs + S3C2410_IICSTAT);
661 	}
662 
663 	/*
664 	 * If we do get an appreciable delay as a compromise between idle
665 	 * detection latency for the normal, fast case, and system load in the
666 	 * slow device case, use an exponential back off in the polling loop,
667 	 * up to 1/10th of the total timeout, then continue to poll at a
668 	 * constant rate up to the timeout.
669 	 */
670 	delay = 1;
671 	while ((iicstat & S3C2410_IICSTAT_START) &&
672 	       ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
673 		usleep_range(delay, 2 * delay);
674 		if (delay < S3C2410_IDLE_TIMEOUT / 10)
675 			delay <<= 1;
676 		now = ktime_get();
677 		iicstat = readl(i2c->regs + S3C2410_IICSTAT);
678 	}
679 
680 	if (iicstat & S3C2410_IICSTAT_START)
681 		dev_warn(i2c->dev, "timeout waiting for bus idle\n");
682 }
683 
684 /*
685  * this starts an i2c transfer
686  */
687 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
688 			      struct i2c_msg *msgs, int num)
689 {
690 	unsigned long timeout;
691 	int ret;
692 
693 	ret = s3c24xx_i2c_set_master(i2c);
694 	if (ret != 0) {
695 		dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
696 		ret = -EAGAIN;
697 		goto out;
698 	}
699 
700 	i2c->msg     = msgs;
701 	i2c->msg_num = num;
702 	i2c->msg_ptr = 0;
703 	i2c->msg_idx = 0;
704 	i2c->state   = STATE_START;
705 
706 	s3c24xx_i2c_enable_irq(i2c);
707 	s3c24xx_i2c_message_start(i2c, msgs);
708 
709 	if (i2c->quirks & QUIRK_POLL) {
710 		ret = i2c->msg_idx;
711 
712 		if (ret != num)
713 			dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
714 
715 		goto out;
716 	}
717 
718 	timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
719 
720 	ret = i2c->msg_idx;
721 
722 	/*
723 	 * Having these next two as dev_err() makes life very
724 	 * noisy when doing an i2cdetect
725 	 */
726 	if (timeout == 0)
727 		dev_dbg(i2c->dev, "timeout\n");
728 	else if (ret != num)
729 		dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
730 
731 	/* For QUIRK_HDMIPHY, bus is already disabled */
732 	if (i2c->quirks & QUIRK_HDMIPHY)
733 		goto out;
734 
735 	s3c24xx_i2c_wait_idle(i2c);
736 
737 	s3c24xx_i2c_disable_bus(i2c);
738 
739  out:
740 	i2c->state = STATE_IDLE;
741 
742 	return ret;
743 }
744 
745 /*
746  * first port of call from the i2c bus code when an message needs
747  * transferring across the i2c bus.
748  */
749 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
750 			struct i2c_msg *msgs, int num)
751 {
752 	struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
753 	int retry;
754 	int ret;
755 
756 	ret = clk_enable(i2c->clk);
757 	if (ret)
758 		return ret;
759 
760 	for (retry = 0; retry < adap->retries; retry++) {
761 
762 		ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
763 
764 		if (ret != -EAGAIN) {
765 			clk_disable(i2c->clk);
766 			return ret;
767 		}
768 
769 		dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
770 
771 		udelay(100);
772 	}
773 
774 	clk_disable(i2c->clk);
775 	return -EREMOTEIO;
776 }
777 
778 /* declare our i2c functionality */
779 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
780 {
781 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART |
782 		I2C_FUNC_PROTOCOL_MANGLING;
783 }
784 
785 /* i2c bus registration info */
786 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
787 	.master_xfer		= s3c24xx_i2c_xfer,
788 	.functionality		= s3c24xx_i2c_func,
789 };
790 
791 /*
792  * return the divisor settings for a given frequency
793  */
794 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
795 				   unsigned int *div1, unsigned int *divs)
796 {
797 	unsigned int calc_divs = clkin / wanted;
798 	unsigned int calc_div1;
799 
800 	if (calc_divs > (16*16))
801 		calc_div1 = 512;
802 	else
803 		calc_div1 = 16;
804 
805 	calc_divs += calc_div1-1;
806 	calc_divs /= calc_div1;
807 
808 	if (calc_divs == 0)
809 		calc_divs = 1;
810 	if (calc_divs > 17)
811 		calc_divs = 17;
812 
813 	*divs = calc_divs;
814 	*div1 = calc_div1;
815 
816 	return clkin / (calc_divs * calc_div1);
817 }
818 
819 /*
820  * work out a divisor for the user requested frequency setting,
821  * either by the requested frequency, or scanning the acceptable
822  * range of frequencies until something is found
823  */
824 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
825 {
826 	struct s3c2410_platform_i2c *pdata = i2c->pdata;
827 	unsigned long clkin = clk_get_rate(i2c->clk);
828 	unsigned int divs, div1;
829 	unsigned long target_frequency;
830 	u32 iiccon;
831 	int freq;
832 
833 	i2c->clkrate = clkin;
834 	clkin /= 1000;	/* clkin now in KHz */
835 
836 	dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
837 
838 	target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ;
839 
840 	target_frequency /= 1000; /* Target frequency now in KHz */
841 
842 	freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
843 
844 	if (freq > target_frequency) {
845 		dev_err(i2c->dev,
846 			"Unable to achieve desired frequency %luKHz."	\
847 			" Lowest achievable %dKHz\n", target_frequency, freq);
848 		return -EINVAL;
849 	}
850 
851 	*got = freq;
852 
853 	iiccon = readl(i2c->regs + S3C2410_IICCON);
854 	iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
855 	iiccon |= (divs-1);
856 
857 	if (div1 == 512)
858 		iiccon |= S3C2410_IICCON_TXDIV_512;
859 
860 	if (i2c->quirks & QUIRK_POLL)
861 		iiccon |= S3C2410_IICCON_SCALE(2);
862 
863 	writel(iiccon, i2c->regs + S3C2410_IICCON);
864 
865 	if (i2c->quirks & QUIRK_S3C2440) {
866 		unsigned long sda_delay;
867 
868 		if (pdata->sda_delay) {
869 			sda_delay = clkin * pdata->sda_delay;
870 			sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
871 			sda_delay = DIV_ROUND_UP(sda_delay, 5);
872 			if (sda_delay > 3)
873 				sda_delay = 3;
874 			sda_delay |= S3C2410_IICLC_FILTER_ON;
875 		} else
876 			sda_delay = 0;
877 
878 		dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
879 		writel(sda_delay, i2c->regs + S3C2440_IICLC);
880 	}
881 
882 	return 0;
883 }
884 
885 #ifdef CONFIG_OF
886 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
887 {
888 	int i;
889 
890 	if (i2c->quirks & QUIRK_NO_GPIO)
891 		return 0;
892 
893 	for (i = 0; i < 2; i++) {
894 		i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,
895 						     i, GPIOD_ASIS);
896 		if (IS_ERR(i2c->gpios[i])) {
897 			dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);
898 			return -EINVAL;
899 		}
900 	}
901 	return 0;
902 }
903 
904 #else
905 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
906 {
907 	return 0;
908 }
909 #endif
910 
911 /*
912  * initialise the controller, set the IO lines and frequency
913  */
914 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
915 {
916 	struct s3c2410_platform_i2c *pdata;
917 	unsigned int freq;
918 
919 	/* get the plafrom data */
920 
921 	pdata = i2c->pdata;
922 
923 	/* write slave address */
924 
925 	writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
926 
927 	dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
928 
929 	writel(0, i2c->regs + S3C2410_IICCON);
930 	writel(0, i2c->regs + S3C2410_IICSTAT);
931 
932 	/* we need to work out the divisors for the clock... */
933 
934 	if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
935 		dev_err(i2c->dev, "cannot meet bus frequency required\n");
936 		return -EINVAL;
937 	}
938 
939 	/* todo - check that the i2c lines aren't being dragged anywhere */
940 
941 	dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
942 	dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
943 		readl(i2c->regs + S3C2410_IICCON));
944 
945 	return 0;
946 }
947 
948 #ifdef CONFIG_OF
949 /*
950  * Parse the device tree node and retreive the platform data.
951  */
952 static void
953 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
954 {
955 	struct s3c2410_platform_i2c *pdata = i2c->pdata;
956 	int id;
957 
958 	if (!np)
959 		return;
960 
961 	pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
962 	of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
963 	of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
964 	of_property_read_u32(np, "samsung,i2c-max-bus-freq",
965 				(u32 *)&pdata->frequency);
966 	/*
967 	 * Exynos5's legacy i2c controller and new high speed i2c
968 	 * controller have muxed interrupt sources. By default the
969 	 * interrupts for 4-channel HS-I2C controller are enabled.
970 	 * If nodes for first four channels of legacy i2c controller
971 	 * are available then re-configure the interrupts via the
972 	 * system register.
973 	 */
974 	id = of_alias_get_id(np, "i2c");
975 	i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
976 			"samsung,sysreg-phandle");
977 	if (IS_ERR(i2c->sysreg))
978 		return;
979 
980 	regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
981 }
982 #else
983 static void
984 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
985 #endif
986 
987 static int s3c24xx_i2c_probe(struct platform_device *pdev)
988 {
989 	struct s3c24xx_i2c *i2c;
990 	struct s3c2410_platform_i2c *pdata = NULL;
991 	struct resource *res;
992 	int ret;
993 
994 	if (!pdev->dev.of_node) {
995 		pdata = dev_get_platdata(&pdev->dev);
996 		if (!pdata) {
997 			dev_err(&pdev->dev, "no platform data\n");
998 			return -EINVAL;
999 		}
1000 	}
1001 
1002 	i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1003 	if (!i2c)
1004 		return -ENOMEM;
1005 
1006 	i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1007 	if (!i2c->pdata)
1008 		return -ENOMEM;
1009 
1010 	i2c->quirks = s3c24xx_get_device_quirks(pdev);
1011 	i2c->sysreg = ERR_PTR(-ENOENT);
1012 	if (pdata)
1013 		memcpy(i2c->pdata, pdata, sizeof(*pdata));
1014 	else
1015 		s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1016 
1017 	strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1018 	i2c->adap.owner = THIS_MODULE;
1019 	i2c->adap.algo = &s3c24xx_i2c_algorithm;
1020 	i2c->adap.retries = 2;
1021 	i2c->adap.class = I2C_CLASS_DEPRECATED;
1022 	i2c->tx_setup = 50;
1023 
1024 	init_waitqueue_head(&i2c->wait);
1025 
1026 	/* find the clock and enable it */
1027 	i2c->dev = &pdev->dev;
1028 	i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1029 	if (IS_ERR(i2c->clk)) {
1030 		dev_err(&pdev->dev, "cannot get clock\n");
1031 		return -ENOENT;
1032 	}
1033 
1034 	dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1035 
1036 	/* map the registers */
1037 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1038 	i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1039 
1040 	if (IS_ERR(i2c->regs))
1041 		return PTR_ERR(i2c->regs);
1042 
1043 	dev_dbg(&pdev->dev, "registers %p (%p)\n",
1044 		i2c->regs, res);
1045 
1046 	/* setup info block for the i2c core */
1047 	i2c->adap.algo_data = i2c;
1048 	i2c->adap.dev.parent = &pdev->dev;
1049 	i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1050 
1051 	/* inititalise the i2c gpio lines */
1052 	if (i2c->pdata->cfg_gpio)
1053 		i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1054 	else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1055 		return -EINVAL;
1056 
1057 	/* initialise the i2c controller */
1058 	ret = clk_prepare_enable(i2c->clk);
1059 	if (ret) {
1060 		dev_err(&pdev->dev, "I2C clock enable failed\n");
1061 		return ret;
1062 	}
1063 
1064 	ret = s3c24xx_i2c_init(i2c);
1065 	clk_disable(i2c->clk);
1066 	if (ret != 0) {
1067 		dev_err(&pdev->dev, "I2C controller init failed\n");
1068 		clk_unprepare(i2c->clk);
1069 		return ret;
1070 	}
1071 
1072 	/*
1073 	 * find the IRQ for this unit (note, this relies on the init call to
1074 	 * ensure no current IRQs pending
1075 	 */
1076 	if (!(i2c->quirks & QUIRK_POLL)) {
1077 		i2c->irq = ret = platform_get_irq(pdev, 0);
1078 		if (ret < 0) {
1079 			dev_err(&pdev->dev, "cannot find IRQ\n");
1080 			clk_unprepare(i2c->clk);
1081 			return ret;
1082 		}
1083 
1084 		ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1085 				       0, dev_name(&pdev->dev), i2c);
1086 		if (ret != 0) {
1087 			dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1088 			clk_unprepare(i2c->clk);
1089 			return ret;
1090 		}
1091 	}
1092 
1093 	/*
1094 	 * Note, previous versions of the driver used i2c_add_adapter()
1095 	 * to add the bus at any number. We now pass the bus number via
1096 	 * the platform data, so if unset it will now default to always
1097 	 * being bus 0.
1098 	 */
1099 	i2c->adap.nr = i2c->pdata->bus_num;
1100 	i2c->adap.dev.of_node = pdev->dev.of_node;
1101 
1102 	platform_set_drvdata(pdev, i2c);
1103 
1104 	pm_runtime_enable(&pdev->dev);
1105 
1106 	ret = i2c_add_numbered_adapter(&i2c->adap);
1107 	if (ret < 0) {
1108 		pm_runtime_disable(&pdev->dev);
1109 		clk_unprepare(i2c->clk);
1110 		return ret;
1111 	}
1112 
1113 	dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1114 	return 0;
1115 }
1116 
1117 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1118 {
1119 	struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1120 
1121 	clk_unprepare(i2c->clk);
1122 
1123 	pm_runtime_disable(&pdev->dev);
1124 
1125 	i2c_del_adapter(&i2c->adap);
1126 
1127 	return 0;
1128 }
1129 
1130 #ifdef CONFIG_PM_SLEEP
1131 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1132 {
1133 	struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1134 
1135 	i2c_mark_adapter_suspended(&i2c->adap);
1136 
1137 	if (!IS_ERR(i2c->sysreg))
1138 		regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1139 
1140 	return 0;
1141 }
1142 
1143 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1144 {
1145 	struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1146 	int ret;
1147 
1148 	if (!IS_ERR(i2c->sysreg))
1149 		regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1150 
1151 	ret = clk_enable(i2c->clk);
1152 	if (ret)
1153 		return ret;
1154 	s3c24xx_i2c_init(i2c);
1155 	clk_disable(i2c->clk);
1156 	i2c_mark_adapter_resumed(&i2c->adap);
1157 
1158 	return 0;
1159 }
1160 #endif
1161 
1162 #ifdef CONFIG_PM
1163 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1164 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1165 				      s3c24xx_i2c_resume_noirq)
1166 };
1167 
1168 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1169 #else
1170 #define S3C24XX_DEV_PM_OPS NULL
1171 #endif
1172 
1173 static struct platform_driver s3c24xx_i2c_driver = {
1174 	.probe		= s3c24xx_i2c_probe,
1175 	.remove		= s3c24xx_i2c_remove,
1176 	.id_table	= s3c24xx_driver_ids,
1177 	.driver		= {
1178 		.name	= "s3c-i2c",
1179 		.pm	= S3C24XX_DEV_PM_OPS,
1180 		.of_match_table = of_match_ptr(s3c24xx_i2c_match),
1181 	},
1182 };
1183 
1184 static int __init i2c_adap_s3c_init(void)
1185 {
1186 	return platform_driver_register(&s3c24xx_i2c_driver);
1187 }
1188 subsys_initcall(i2c_adap_s3c_init);
1189 
1190 static void __exit i2c_adap_s3c_exit(void)
1191 {
1192 	platform_driver_unregister(&s3c24xx_i2c_driver);
1193 }
1194 module_exit(i2c_adap_s3c_exit);
1195 
1196 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1197 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1198 MODULE_LICENSE("GPL");
1199