1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 4 * Copyright (C) 2020 Western Digital Corporation or its affiliates. 5 */ 6#include <dt-bindings/clock/k210-clk.h> 7#include <dt-bindings/pinctrl/k210-fpioa.h> 8#include <dt-bindings/reset/k210-rst.h> 9 10/ { 11 /* 12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 13 * wide, and the upper half of all addresses is ignored. 14 */ 15 #address-cells = <1>; 16 #size-cells = <1>; 17 compatible = "canaan,kendryte-k210"; 18 19 aliases { 20 serial0 = &uarths0; 21 serial1 = &uart1; 22 serial2 = &uart2; 23 serial3 = &uart3; 24 }; 25 26 /* 27 * The K210 has an sv39 MMU following the privileged specification v1.9. 28 * Since this is a non-ratified draft specification, the kernel does not 29 * support it and the K210 support enabled only for the !MMU case. 30 * Be consistent with this by setting the CPUs MMU type to "none". 31 */ 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 timebase-frequency = <7800000>; 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "canaan,k210", "riscv"; 39 reg = <0>; 40 riscv,isa = "rv64imafdc"; 41 mmu-type = "riscv,none"; 42 i-cache-block-size = <64>; 43 i-cache-size = <0x8000>; 44 d-cache-block-size = <64>; 45 d-cache-size = <0x8000>; 46 cpu0_intc: interrupt-controller { 47 #interrupt-cells = <1>; 48 interrupt-controller; 49 compatible = "riscv,cpu-intc"; 50 }; 51 }; 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "canaan,k210", "riscv"; 55 reg = <1>; 56 riscv,isa = "rv64imafdc"; 57 mmu-type = "riscv,none"; 58 i-cache-block-size = <64>; 59 i-cache-size = <0x8000>; 60 d-cache-block-size = <64>; 61 d-cache-size = <0x8000>; 62 cpu1_intc: interrupt-controller { 63 #interrupt-cells = <1>; 64 interrupt-controller; 65 compatible = "riscv,cpu-intc"; 66 }; 67 }; 68 }; 69 70 sram: memory@80000000 { 71 device_type = "memory"; 72 compatible = "canaan,k210-sram"; 73 reg = <0x80000000 0x400000>, 74 <0x80400000 0x200000>, 75 <0x80600000 0x200000>; 76 reg-names = "sram0", "sram1", "aisram"; 77 clocks = <&sysclk K210_CLK_SRAM0>, 78 <&sysclk K210_CLK_SRAM1>, 79 <&sysclk K210_CLK_AI>; 80 clock-names = "sram0", "sram1", "aisram"; 81 }; 82 83 clocks { 84 in0: oscillator { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <26000000>; 88 }; 89 }; 90 91 soc { 92 #address-cells = <1>; 93 #size-cells = <1>; 94 compatible = "simple-bus"; 95 ranges; 96 interrupt-parent = <&plic0>; 97 98 rom0: nvmem@1000 { 99 reg = <0x1000 0x1000>; 100 read-only; 101 }; 102 103 clint0: timer@2000000 { 104 compatible = "canaan,k210-clint", "sifive,clint0"; 105 reg = <0x2000000 0xC000>; 106 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 107 <&cpu1_intc 3>, <&cpu1_intc 7>; 108 }; 109 110 plic0: interrupt-controller@c000000 { 111 #interrupt-cells = <1>; 112 #address-cells = <0>; 113 compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; 114 reg = <0xC000000 0x4000000>; 115 interrupt-controller; 116 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 117 <&cpu1_intc 11>, <&cpu1_intc 9>; 118 riscv,ndev = <65>; 119 }; 120 121 uarths0: serial@38000000 { 122 compatible = "canaan,k210-uarths", "sifive,uart0"; 123 reg = <0x38000000 0x1000>; 124 interrupts = <33>; 125 clocks = <&sysclk K210_CLK_CPU>; 126 }; 127 128 gpio0: gpio-controller@38001000 { 129 #interrupt-cells = <2>; 130 #gpio-cells = <2>; 131 compatible = "canaan,k210-gpiohs", "sifive,gpio0"; 132 reg = <0x38001000 0x1000>; 133 interrupt-controller; 134 interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, 135 <41>, <42>, <43>, <44>, <45>, <46>, <47>, 136 <48>, <49>, <50>, <51>, <52>, <53>, <54>, 137 <55>, <56>, <57>, <58>, <59>, <60>, <61>, 138 <62>, <63>, <64>, <65>; 139 gpio-controller; 140 ngpios = <32>; 141 }; 142 143 dmac0: dma-controller@50000000 { 144 compatible = "snps,axi-dma-1.01a"; 145 reg = <0x50000000 0x1000>; 146 interrupts = <27>, <28>, <29>, <30>, <31>, <32>; 147 #dma-cells = <1>; 148 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; 149 clock-names = "core-clk", "cfgr-clk"; 150 resets = <&sysrst K210_RST_DMA>; 151 dma-channels = <6>; 152 snps,dma-masters = <2>; 153 snps,priority = <0 1 2 3 4 5>; 154 snps,data-width = <5>; 155 snps,block-size = <0x200000 0x200000 0x200000 156 0x200000 0x200000 0x200000>; 157 snps,axi-max-burst-len = <256>; 158 }; 159 160 apb0: bus@50200000 { 161 #address-cells = <1>; 162 #size-cells = <1>; 163 compatible = "simple-pm-bus"; 164 ranges; 165 clocks = <&sysclk K210_CLK_APB0>; 166 167 gpio1: gpio@50200000 { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "snps,dw-apb-gpio"; 171 reg = <0x50200000 0x80>; 172 clocks = <&sysclk K210_CLK_APB0>, 173 <&sysclk K210_CLK_GPIO>; 174 clock-names = "bus", "db"; 175 resets = <&sysrst K210_RST_GPIO>; 176 177 gpio1_0: gpio-port@0 { 178 #gpio-cells = <2>; 179 #interrupt-cells = <2>; 180 compatible = "snps,dw-apb-gpio-port"; 181 reg = <0>; 182 interrupt-controller; 183 interrupts = <23>; 184 gpio-controller; 185 ngpios = <8>; 186 }; 187 }; 188 189 uart1: serial@50210000 { 190 compatible = "snps,dw-apb-uart"; 191 reg = <0x50210000 0x100>; 192 interrupts = <11>; 193 clocks = <&sysclk K210_CLK_UART1>, 194 <&sysclk K210_CLK_APB0>; 195 clock-names = "baudclk", "apb_pclk"; 196 resets = <&sysrst K210_RST_UART1>; 197 reg-io-width = <4>; 198 reg-shift = <2>; 199 dcd-override; 200 dsr-override; 201 cts-override; 202 ri-override; 203 }; 204 205 uart2: serial@50220000 { 206 compatible = "snps,dw-apb-uart"; 207 reg = <0x50220000 0x100>; 208 interrupts = <12>; 209 clocks = <&sysclk K210_CLK_UART2>, 210 <&sysclk K210_CLK_APB0>; 211 clock-names = "baudclk", "apb_pclk"; 212 resets = <&sysrst K210_RST_UART2>; 213 reg-io-width = <4>; 214 reg-shift = <2>; 215 dcd-override; 216 dsr-override; 217 cts-override; 218 ri-override; 219 }; 220 221 uart3: serial@50230000 { 222 compatible = "snps,dw-apb-uart"; 223 reg = <0x50230000 0x100>; 224 interrupts = <13>; 225 clocks = <&sysclk K210_CLK_UART3>, 226 <&sysclk K210_CLK_APB0>; 227 clock-names = "baudclk", "apb_pclk"; 228 resets = <&sysrst K210_RST_UART3>; 229 reg-io-width = <4>; 230 reg-shift = <2>; 231 dcd-override; 232 dsr-override; 233 cts-override; 234 ri-override; 235 }; 236 237 spi2: spi@50240000 { 238 compatible = "canaan,k210-spi"; 239 spi-slave; 240 reg = <0x50240000 0x100>; 241 #address-cells = <0>; 242 #size-cells = <0>; 243 interrupts = <3>; 244 clocks = <&sysclk K210_CLK_SPI2>, 245 <&sysclk K210_CLK_APB0>; 246 clock-names = "ssi_clk", "pclk"; 247 resets = <&sysrst K210_RST_SPI2>; 248 spi-max-frequency = <25000000>; 249 }; 250 251 i2s0: i2s@50250000 { 252 compatible = "snps,designware-i2s"; 253 reg = <0x50250000 0x200>; 254 interrupts = <5>; 255 clocks = <&sysclk K210_CLK_I2S0>; 256 clock-names = "i2sclk"; 257 resets = <&sysrst K210_RST_I2S0>; 258 }; 259 260 i2s1: i2s@50260000 { 261 compatible = "snps,designware-i2s"; 262 reg = <0x50260000 0x200>; 263 interrupts = <6>; 264 clocks = <&sysclk K210_CLK_I2S1>; 265 clock-names = "i2sclk"; 266 resets = <&sysrst K210_RST_I2S1>; 267 }; 268 269 i2s2: i2s@50270000 { 270 compatible = "snps,designware-i2s"; 271 reg = <0x50270000 0x200>; 272 interrupts = <7>; 273 clocks = <&sysclk K210_CLK_I2S2>; 274 clock-names = "i2sclk"; 275 resets = <&sysrst K210_RST_I2S2>; 276 }; 277 278 i2c0: i2c@50280000 { 279 compatible = "snps,designware-i2c"; 280 reg = <0x50280000 0x100>; 281 interrupts = <8>; 282 clocks = <&sysclk K210_CLK_I2C0>, 283 <&sysclk K210_CLK_APB0>; 284 clock-names = "ref", "pclk"; 285 resets = <&sysrst K210_RST_I2C0>; 286 }; 287 288 i2c1: i2c@50290000 { 289 compatible = "snps,designware-i2c"; 290 reg = <0x50290000 0x100>; 291 interrupts = <9>; 292 clocks = <&sysclk K210_CLK_I2C1>, 293 <&sysclk K210_CLK_APB0>; 294 clock-names = "ref", "pclk"; 295 resets = <&sysrst K210_RST_I2C1>; 296 }; 297 298 i2c2: i2c@502a0000 { 299 compatible = "snps,designware-i2c"; 300 reg = <0x502A0000 0x100>; 301 interrupts = <10>; 302 clocks = <&sysclk K210_CLK_I2C2>, 303 <&sysclk K210_CLK_APB0>; 304 clock-names = "ref", "pclk"; 305 resets = <&sysrst K210_RST_I2C2>; 306 }; 307 308 fpioa: pinmux@502b0000 { 309 compatible = "canaan,k210-fpioa"; 310 reg = <0x502B0000 0x100>; 311 clocks = <&sysclk K210_CLK_FPIOA>, 312 <&sysclk K210_CLK_APB0>; 313 clock-names = "ref", "pclk"; 314 resets = <&sysrst K210_RST_FPIOA>; 315 canaan,k210-sysctl-power = <&sysctl 108>; 316 }; 317 318 timer0: timer@502d0000 { 319 compatible = "snps,dw-apb-timer"; 320 reg = <0x502D0000 0x100>; 321 interrupts = <14>, <15>; 322 clocks = <&sysclk K210_CLK_TIMER0>, 323 <&sysclk K210_CLK_APB0>; 324 clock-names = "timer", "pclk"; 325 resets = <&sysrst K210_RST_TIMER0>; 326 }; 327 328 timer1: timer@502e0000 { 329 compatible = "snps,dw-apb-timer"; 330 reg = <0x502E0000 0x100>; 331 interrupts = <16>, <17>; 332 clocks = <&sysclk K210_CLK_TIMER1>, 333 <&sysclk K210_CLK_APB0>; 334 clock-names = "timer", "pclk"; 335 resets = <&sysrst K210_RST_TIMER1>; 336 }; 337 338 timer2: timer@502f0000 { 339 compatible = "snps,dw-apb-timer"; 340 reg = <0x502F0000 0x100>; 341 interrupts = <18>, <19>; 342 clocks = <&sysclk K210_CLK_TIMER2>, 343 <&sysclk K210_CLK_APB0>; 344 clock-names = "timer", "pclk"; 345 resets = <&sysrst K210_RST_TIMER2>; 346 }; 347 }; 348 349 apb1: bus@50400000 { 350 #address-cells = <1>; 351 #size-cells = <1>; 352 compatible = "simple-pm-bus"; 353 ranges; 354 clocks = <&sysclk K210_CLK_APB1>; 355 356 wdt0: watchdog@50400000 { 357 compatible = "snps,dw-wdt"; 358 reg = <0x50400000 0x100>; 359 interrupts = <21>; 360 clocks = <&sysclk K210_CLK_WDT0>, 361 <&sysclk K210_CLK_APB1>; 362 clock-names = "tclk", "pclk"; 363 resets = <&sysrst K210_RST_WDT0>; 364 }; 365 366 wdt1: watchdog@50410000 { 367 compatible = "snps,dw-wdt"; 368 reg = <0x50410000 0x100>; 369 interrupts = <22>; 370 clocks = <&sysclk K210_CLK_WDT1>, 371 <&sysclk K210_CLK_APB1>; 372 clock-names = "tclk", "pclk"; 373 resets = <&sysrst K210_RST_WDT1>; 374 }; 375 376 sysctl: syscon@50440000 { 377 compatible = "canaan,k210-sysctl", 378 "syscon", "simple-mfd"; 379 reg = <0x50440000 0x100>; 380 clocks = <&sysclk K210_CLK_APB1>; 381 clock-names = "pclk"; 382 383 sysclk: clock-controller { 384 #clock-cells = <1>; 385 compatible = "canaan,k210-clk"; 386 clocks = <&in0>; 387 }; 388 389 sysrst: reset-controller { 390 compatible = "canaan,k210-rst"; 391 #reset-cells = <1>; 392 }; 393 394 reboot: syscon-reboot { 395 compatible = "syscon-reboot"; 396 regmap = <&sysctl>; 397 offset = <48>; 398 mask = <1>; 399 value = <1>; 400 }; 401 }; 402 }; 403 404 apb2: bus@52000000 { 405 #address-cells = <1>; 406 #size-cells = <1>; 407 compatible = "simple-pm-bus"; 408 ranges; 409 clocks = <&sysclk K210_CLK_APB2>; 410 411 spi0: spi@52000000 { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 compatible = "canaan,k210-spi"; 415 reg = <0x52000000 0x100>; 416 interrupts = <1>; 417 clocks = <&sysclk K210_CLK_SPI0>, 418 <&sysclk K210_CLK_APB2>; 419 clock-names = "ssi_clk", "pclk"; 420 resets = <&sysrst K210_RST_SPI0>; 421 reset-names = "spi"; 422 spi-max-frequency = <25000000>; 423 num-cs = <4>; 424 reg-io-width = <4>; 425 }; 426 427 spi1: spi@53000000 { 428 #address-cells = <1>; 429 #size-cells = <0>; 430 compatible = "canaan,k210-spi"; 431 reg = <0x53000000 0x100>; 432 interrupts = <2>; 433 clocks = <&sysclk K210_CLK_SPI1>, 434 <&sysclk K210_CLK_APB2>; 435 clock-names = "ssi_clk", "pclk"; 436 resets = <&sysrst K210_RST_SPI1>; 437 reset-names = "spi"; 438 spi-max-frequency = <25000000>; 439 num-cs = <4>; 440 reg-io-width = <4>; 441 }; 442 443 spi3: spi@54000000 { 444 #address-cells = <1>; 445 #size-cells = <0>; 446 compatible = "snps,dwc-ssi-1.01a"; 447 reg = <0x54000000 0x200>; 448 interrupts = <4>; 449 clocks = <&sysclk K210_CLK_SPI3>, 450 <&sysclk K210_CLK_APB2>; 451 clock-names = "ssi_clk", "pclk"; 452 resets = <&sysrst K210_RST_SPI3>; 453 reset-names = "spi"; 454 /* Could possibly go up to 200 MHz */ 455 spi-max-frequency = <100000000>; 456 num-cs = <4>; 457 reg-io-width = <4>; 458 }; 459 }; 460 }; 461}; 462