1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11#include "imx93-pinfunc.h" 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 mmc0 = &usdhc1; 20 mmc1 = &usdhc2; 21 mmc2 = &usdhc3; 22 serial0 = &lpuart1; 23 serial1 = &lpuart2; 24 serial2 = &lpuart3; 25 serial3 = &lpuart4; 26 serial4 = &lpuart5; 27 serial5 = &lpuart6; 28 serial6 = &lpuart7; 29 serial7 = &lpuart8; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 A55_0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a55"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 #cooling-cells = <2>; 42 }; 43 44 A55_1: cpu@100 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a55"; 47 reg = <0x100>; 48 enable-method = "psci"; 49 #cooling-cells = <2>; 50 }; 51 52 }; 53 54 osc_32k: clock-osc-32k { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <32768>; 58 clock-output-names = "osc_32k"; 59 }; 60 61 osc_24m: clock-osc-24m { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <24000000>; 65 clock-output-names = "osc_24m"; 66 }; 67 68 clk_ext1: clock-ext1 { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <133000000>; 72 clock-output-names = "clk_ext1"; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0"; 77 method = "smc"; 78 }; 79 80 timer { 81 compatible = "arm,armv8-timer"; 82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 83 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 84 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 85 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 86 clock-frequency = <24000000>; 87 arm,no-tick-in-suspend; 88 interrupt-parent = <&gic>; 89 }; 90 91 gic: interrupt-controller@48000000 { 92 compatible = "arm,gic-v3"; 93 reg = <0 0x48000000 0 0x10000>, 94 <0 0x48040000 0 0xc0000>; 95 #interrupt-cells = <3>; 96 interrupt-controller; 97 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 98 interrupt-parent = <&gic>; 99 }; 100 101 soc@0 { 102 compatible = "simple-bus"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 ranges = <0x0 0x0 0x0 0x80000000>, 106 <0x28000000 0x0 0x28000000 0x10000000>; 107 108 aips1: bus@44000000 { 109 compatible = "fsl,aips-bus", "simple-bus"; 110 reg = <0x44000000 0x800000>; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 ranges; 114 115 mu1: mailbox@44230000 { 116 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 117 reg = <0x44230000 0x10000>; 118 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 119 #mbox-cells = <2>; 120 status = "disabled"; 121 }; 122 123 system_counter: timer@44290000 { 124 compatible = "nxp,sysctr-timer"; 125 reg = <0x44290000 0x30000>; 126 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&osc_24m>; 128 clock-names = "per"; 129 }; 130 131 lpuart1: serial@44380000 { 132 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 133 reg = <0x44380000 0x1000>; 134 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 136 clock-names = "ipg"; 137 status = "disabled"; 138 }; 139 140 lpuart2: serial@44390000 { 141 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 142 reg = <0x44390000 0x1000>; 143 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 145 clock-names = "ipg"; 146 status = "disabled"; 147 }; 148 149 iomuxc: pinctrl@443c0000 { 150 compatible = "fsl,imx93-iomuxc"; 151 reg = <0x443c0000 0x10000>; 152 status = "okay"; 153 }; 154 155 clk: clock-controller@44450000 { 156 compatible = "fsl,imx93-ccm"; 157 reg = <0x44450000 0x10000>; 158 #clock-cells = <1>; 159 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 160 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 161 status = "okay"; 162 }; 163 164 anatop: anatop@44480000 { 165 compatible = "fsl,imx93-anatop", "syscon"; 166 reg = <0x44480000 0x10000>; 167 }; 168 }; 169 170 aips2: bus@42000000 { 171 compatible = "fsl,aips-bus", "simple-bus"; 172 reg = <0x42000000 0x800000>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges; 176 177 mu2: mailbox@42440000 { 178 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 179 reg = <0x42440000 0x10000>; 180 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 181 #mbox-cells = <2>; 182 status = "disabled"; 183 }; 184 185 lpuart3: serial@42570000 { 186 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 187 reg = <0x42570000 0x1000>; 188 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 190 clock-names = "ipg"; 191 status = "disabled"; 192 }; 193 194 lpuart4: serial@42580000 { 195 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 196 reg = <0x42580000 0x1000>; 197 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 199 clock-names = "ipg"; 200 status = "disabled"; 201 }; 202 203 lpuart5: serial@42590000 { 204 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 205 reg = <0x42590000 0x1000>; 206 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 208 clock-names = "ipg"; 209 status = "disabled"; 210 }; 211 212 lpuart6: serial@425a0000 { 213 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 214 reg = <0x425a0000 0x1000>; 215 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 217 clock-names = "ipg"; 218 status = "disabled"; 219 }; 220 221 lpuart7: serial@42690000 { 222 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 223 reg = <0x42690000 0x1000>; 224 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 226 clock-names = "ipg"; 227 status = "disabled"; 228 }; 229 230 lpuart8: serial@426a0000 { 231 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 232 reg = <0x426a0000 0x1000>; 233 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 235 clock-names = "ipg"; 236 status = "disabled"; 237 }; 238 }; 239 240 aips3: bus@42800000 { 241 compatible = "fsl,aips-bus", "simple-bus"; 242 reg = <0x42800000 0x800000>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 ranges; 246 247 usdhc1: mmc@42850000 { 248 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 249 reg = <0x42850000 0x10000>; 250 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&clk IMX93_CLK_DUMMY>, 252 <&clk IMX93_CLK_DUMMY>, 253 <&clk IMX93_CLK_USDHC1_GATE>; 254 clock-names = "ipg", "ahb", "per"; 255 bus-width = <8>; 256 fsl,tuning-start-tap = <20>; 257 fsl,tuning-step= <2>; 258 status = "disabled"; 259 }; 260 261 usdhc2: mmc@42860000 { 262 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 263 reg = <0x42860000 0x10000>; 264 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&clk IMX93_CLK_DUMMY>, 266 <&clk IMX93_CLK_DUMMY>, 267 <&clk IMX93_CLK_USDHC2_GATE>; 268 clock-names = "ipg", "ahb", "per"; 269 bus-width = <4>; 270 fsl,tuning-start-tap = <20>; 271 fsl,tuning-step= <2>; 272 status = "disabled"; 273 }; 274 275 usdhc3: mmc@428b0000 { 276 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 277 reg = <0x428b0000 0x10000>; 278 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&clk IMX93_CLK_DUMMY>, 280 <&clk IMX93_CLK_DUMMY>, 281 <&clk IMX93_CLK_USDHC3_GATE>; 282 clock-names = "ipg", "ahb", "per"; 283 bus-width = <4>; 284 fsl,tuning-start-tap = <20>; 285 fsl,tuning-step= <2>; 286 status = "disabled"; 287 }; 288 }; 289 290 gpio2: gpio@43810080 { 291 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 292 reg = <0x43810080 0x1000>, <0x43810040 0x40>; 293 gpio-controller; 294 #gpio-cells = <2>; 295 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 gpio-ranges = <&iomuxc 0 32 32>; 299 }; 300 301 gpio3: gpio@43820080 { 302 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 303 reg = <0x43820080 0x1000>, <0x43820040 0x40>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-controller; 308 #interrupt-cells = <2>; 309 gpio-ranges = <&iomuxc 0 64 32>; 310 }; 311 312 gpio4: gpio@43830080 { 313 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 314 reg = <0x43830080 0x1000>, <0x43830040 0x40>; 315 gpio-controller; 316 #gpio-cells = <2>; 317 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 gpio-ranges = <&iomuxc 0 96 32>; 321 }; 322 323 gpio1: gpio@47400080 { 324 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 325 reg = <0x47400080 0x1000>, <0x47400040 0x40>; 326 gpio-controller; 327 #gpio-cells = <2>; 328 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 329 interrupt-controller; 330 #interrupt-cells = <2>; 331 gpio-ranges = <&iomuxc 0 0 32>; 332 }; 333 }; 334}; 335