1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_tm.h" 24 #include "hclge_err.h" 25 #include "hnae3.h" 26 #include "hclge_devlink.h" 27 #include "hclge_comm_cmd.h" 28 29 #define HCLGE_NAME "hclge" 30 31 #define HCLGE_BUF_SIZE_UNIT 256U 32 #define HCLGE_BUF_MUL_BY 2 33 #define HCLGE_BUF_DIV_BY 2 34 #define NEED_RESERVE_TC_NUM 2 35 #define BUF_MAX_PERCENT 100 36 #define BUF_RESERVE_PERCENT 90 37 38 #define HCLGE_RESET_MAX_FAIL_CNT 5 39 #define HCLGE_RESET_SYNC_TIME 100 40 #define HCLGE_PF_RESET_SYNC_TIME 20 41 #define HCLGE_PF_RESET_SYNC_CNT 1500 42 43 /* Get DFX BD number offset */ 44 #define HCLGE_DFX_BIOS_BD_OFFSET 1 45 #define HCLGE_DFX_SSU_0_BD_OFFSET 2 46 #define HCLGE_DFX_SSU_1_BD_OFFSET 3 47 #define HCLGE_DFX_IGU_BD_OFFSET 4 48 #define HCLGE_DFX_RPU_0_BD_OFFSET 5 49 #define HCLGE_DFX_RPU_1_BD_OFFSET 6 50 #define HCLGE_DFX_NCSI_BD_OFFSET 7 51 #define HCLGE_DFX_RTC_BD_OFFSET 8 52 #define HCLGE_DFX_PPP_BD_OFFSET 9 53 #define HCLGE_DFX_RCB_BD_OFFSET 10 54 #define HCLGE_DFX_TQP_BD_OFFSET 11 55 #define HCLGE_DFX_SSU_2_BD_OFFSET 12 56 57 #define HCLGE_LINK_STATUS_MS 10 58 59 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 60 static int hclge_init_vlan_config(struct hclge_dev *hdev); 61 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 62 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 63 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 64 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 65 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 66 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 67 unsigned long *addr); 68 static int hclge_set_default_loopback(struct hclge_dev *hdev); 69 70 static void hclge_sync_mac_table(struct hclge_dev *hdev); 71 static void hclge_restore_hw_table(struct hclge_dev *hdev); 72 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 73 static void hclge_sync_fd_table(struct hclge_dev *hdev); 74 75 static struct hnae3_ae_algo ae_algo; 76 77 static struct workqueue_struct *hclge_wq; 78 79 static const struct pci_device_id ae_algo_pci_tbl[] = { 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 88 /* required last entry */ 89 {0, } 90 }; 91 92 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 93 94 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 95 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 96 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 97 HCLGE_COMM_NIC_CSQ_TAIL_REG, 98 HCLGE_COMM_NIC_CSQ_HEAD_REG, 99 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 100 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 101 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 102 HCLGE_COMM_NIC_CRQ_TAIL_REG, 103 HCLGE_COMM_NIC_CRQ_HEAD_REG, 104 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 105 HCLGE_COMM_CMDQ_INTR_STS_REG, 106 HCLGE_COMM_CMDQ_INTR_EN_REG, 107 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 108 109 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE, 110 HCLGE_PF_OTHER_INT_REG, 111 HCLGE_MISC_RESET_STS_REG, 112 HCLGE_MISC_VECTOR_INT_STS, 113 HCLGE_GLOBAL_RESET_REG, 114 HCLGE_FUN_RST_ING, 115 HCLGE_GRO_EN_REG}; 116 117 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG, 118 HCLGE_RING_RX_ADDR_H_REG, 119 HCLGE_RING_RX_BD_NUM_REG, 120 HCLGE_RING_RX_BD_LENGTH_REG, 121 HCLGE_RING_RX_MERGE_EN_REG, 122 HCLGE_RING_RX_TAIL_REG, 123 HCLGE_RING_RX_HEAD_REG, 124 HCLGE_RING_RX_FBD_NUM_REG, 125 HCLGE_RING_RX_OFFSET_REG, 126 HCLGE_RING_RX_FBD_OFFSET_REG, 127 HCLGE_RING_RX_STASH_REG, 128 HCLGE_RING_RX_BD_ERR_REG, 129 HCLGE_RING_TX_ADDR_L_REG, 130 HCLGE_RING_TX_ADDR_H_REG, 131 HCLGE_RING_TX_BD_NUM_REG, 132 HCLGE_RING_TX_PRIORITY_REG, 133 HCLGE_RING_TX_TC_REG, 134 HCLGE_RING_TX_MERGE_EN_REG, 135 HCLGE_RING_TX_TAIL_REG, 136 HCLGE_RING_TX_HEAD_REG, 137 HCLGE_RING_TX_FBD_NUM_REG, 138 HCLGE_RING_TX_OFFSET_REG, 139 HCLGE_RING_TX_EBD_NUM_REG, 140 HCLGE_RING_TX_EBD_OFFSET_REG, 141 HCLGE_RING_TX_BD_ERR_REG, 142 HCLGE_RING_EN_REG}; 143 144 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG, 145 HCLGE_TQP_INTR_GL0_REG, 146 HCLGE_TQP_INTR_GL1_REG, 147 HCLGE_TQP_INTR_GL2_REG, 148 HCLGE_TQP_INTR_RL_REG}; 149 150 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 151 "App Loopback test", 152 "Serdes serial Loopback test", 153 "Serdes parallel Loopback test", 154 "Phy Loopback test" 155 }; 156 157 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 158 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 160 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 162 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 164 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 166 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 168 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 170 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 172 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 174 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 176 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 178 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 180 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 182 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 184 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 186 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 188 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 190 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 192 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 194 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 196 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 198 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 200 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 202 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 204 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 206 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 208 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 210 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 212 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 214 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 216 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 218 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 220 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 222 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 224 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 226 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 228 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 230 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 232 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 234 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 236 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 238 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 240 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 242 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 244 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 246 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 248 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 250 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 252 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 254 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 256 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 258 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 260 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 262 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 264 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 266 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 268 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 270 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 272 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 274 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 276 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 278 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 280 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 282 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 284 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 286 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 288 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 290 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 292 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 294 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 296 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 298 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 300 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 302 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 304 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 306 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 308 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 310 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 312 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 314 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 316 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 318 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 320 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 322 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 324 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 326 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 328 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 330 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 332 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 334 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 336 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 338 339 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 340 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 341 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 342 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 343 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 344 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 345 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 346 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 347 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 348 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 349 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 350 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 351 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 353 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 355 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 357 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 359 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 361 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 363 }; 364 365 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 366 { 367 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 368 .ethter_type = cpu_to_le16(ETH_P_LLDP), 369 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 370 .i_port_bitmap = 0x1, 371 }, 372 }; 373 374 static const u32 hclge_dfx_bd_offset_list[] = { 375 HCLGE_DFX_BIOS_BD_OFFSET, 376 HCLGE_DFX_SSU_0_BD_OFFSET, 377 HCLGE_DFX_SSU_1_BD_OFFSET, 378 HCLGE_DFX_IGU_BD_OFFSET, 379 HCLGE_DFX_RPU_0_BD_OFFSET, 380 HCLGE_DFX_RPU_1_BD_OFFSET, 381 HCLGE_DFX_NCSI_BD_OFFSET, 382 HCLGE_DFX_RTC_BD_OFFSET, 383 HCLGE_DFX_PPP_BD_OFFSET, 384 HCLGE_DFX_RCB_BD_OFFSET, 385 HCLGE_DFX_TQP_BD_OFFSET, 386 HCLGE_DFX_SSU_2_BD_OFFSET 387 }; 388 389 static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = { 390 HCLGE_OPC_DFX_BIOS_COMMON_REG, 391 HCLGE_OPC_DFX_SSU_REG_0, 392 HCLGE_OPC_DFX_SSU_REG_1, 393 HCLGE_OPC_DFX_IGU_EGU_REG, 394 HCLGE_OPC_DFX_RPU_REG_0, 395 HCLGE_OPC_DFX_RPU_REG_1, 396 HCLGE_OPC_DFX_NCSI_REG, 397 HCLGE_OPC_DFX_RTC_REG, 398 HCLGE_OPC_DFX_PPP_REG, 399 HCLGE_OPC_DFX_RCB_REG, 400 HCLGE_OPC_DFX_TQP_REG, 401 HCLGE_OPC_DFX_SSU_REG_2 402 }; 403 404 static const struct key_info meta_data_key_info[] = { 405 { PACKET_TYPE_ID, 6 }, 406 { IP_FRAGEMENT, 1 }, 407 { ROCE_TYPE, 1 }, 408 { NEXT_KEY, 5 }, 409 { VLAN_NUMBER, 2 }, 410 { SRC_VPORT, 12 }, 411 { DST_VPORT, 12 }, 412 { TUNNEL_PACKET, 1 }, 413 }; 414 415 static const struct key_info tuple_key_info[] = { 416 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 417 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 418 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 419 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 420 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 421 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 422 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 423 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 424 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 425 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 426 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 427 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 428 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 429 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 430 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 431 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 432 { INNER_DST_MAC, 48, KEY_OPT_MAC, 433 offsetof(struct hclge_fd_rule, tuples.dst_mac), 434 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 435 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 436 offsetof(struct hclge_fd_rule, tuples.src_mac), 437 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 438 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 439 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 440 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 441 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 442 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 443 offsetof(struct hclge_fd_rule, tuples.ether_proto), 444 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 445 { INNER_L2_RSV, 16, KEY_OPT_LE16, 446 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 447 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 448 { INNER_IP_TOS, 8, KEY_OPT_U8, 449 offsetof(struct hclge_fd_rule, tuples.ip_tos), 450 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 451 { INNER_IP_PROTO, 8, KEY_OPT_U8, 452 offsetof(struct hclge_fd_rule, tuples.ip_proto), 453 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 454 { INNER_SRC_IP, 32, KEY_OPT_IP, 455 offsetof(struct hclge_fd_rule, tuples.src_ip), 456 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 457 { INNER_DST_IP, 32, KEY_OPT_IP, 458 offsetof(struct hclge_fd_rule, tuples.dst_ip), 459 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 460 { INNER_L3_RSV, 16, KEY_OPT_LE16, 461 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 462 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 463 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 464 offsetof(struct hclge_fd_rule, tuples.src_port), 465 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 466 { INNER_DST_PORT, 16, KEY_OPT_LE16, 467 offsetof(struct hclge_fd_rule, tuples.dst_port), 468 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 469 { INNER_L4_RSV, 32, KEY_OPT_LE32, 470 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 471 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 472 }; 473 474 /** 475 * hclge_cmd_send - send command to command queue 476 * @hw: pointer to the hw struct 477 * @desc: prefilled descriptor for describing the command 478 * @num : the number of descriptors to be sent 479 * 480 * This is the main send command for command queue, it 481 * sends the queue, cleans the queue, etc 482 **/ 483 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 484 { 485 return hclge_comm_cmd_send(&hw->hw, desc, num); 486 } 487 488 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 489 { 490 #define HCLGE_MAC_CMD_NUM 21 491 492 u64 *data = (u64 *)(&hdev->mac_stats); 493 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 494 __le64 *desc_data; 495 u32 data_size; 496 int ret; 497 u32 i; 498 499 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 500 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 501 if (ret) { 502 dev_err(&hdev->pdev->dev, 503 "Get MAC pkt stats fail, status = %d.\n", ret); 504 505 return ret; 506 } 507 508 /* The first desc has a 64-bit header, so data size need to minus 1 */ 509 data_size = sizeof(desc) / (sizeof(u64)) - 1; 510 511 desc_data = (__le64 *)(&desc[0].data[0]); 512 for (i = 0; i < data_size; i++) { 513 /* data memory is continuous becase only the first desc has a 514 * header in this command 515 */ 516 *data += le64_to_cpu(*desc_data); 517 data++; 518 desc_data++; 519 } 520 521 return 0; 522 } 523 524 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 525 { 526 #define HCLGE_REG_NUM_PER_DESC 4 527 528 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 529 u64 *data = (u64 *)(&hdev->mac_stats); 530 struct hclge_desc *desc; 531 __le64 *desc_data; 532 u32 data_size; 533 u32 desc_num; 534 int ret; 535 u32 i; 536 537 /* The first desc has a 64-bit header, so need to consider it */ 538 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 539 540 /* This may be called inside atomic sections, 541 * so GFP_ATOMIC is more suitalbe here 542 */ 543 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 544 if (!desc) 545 return -ENOMEM; 546 547 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 548 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 549 if (ret) { 550 kfree(desc); 551 return ret; 552 } 553 554 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 555 556 desc_data = (__le64 *)(&desc[0].data[0]); 557 for (i = 0; i < data_size; i++) { 558 /* data memory is continuous becase only the first desc has a 559 * header in this command 560 */ 561 *data += le64_to_cpu(*desc_data); 562 data++; 563 desc_data++; 564 } 565 566 kfree(desc); 567 568 return 0; 569 } 570 571 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 572 { 573 struct hclge_desc desc; 574 int ret; 575 576 /* Driver needs total register number of both valid registers and 577 * reserved registers, but the old firmware only returns number 578 * of valid registers in device V2. To be compatible with these 579 * devices, driver uses a fixed value. 580 */ 581 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 582 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 583 return 0; 584 } 585 586 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 587 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 588 if (ret) { 589 dev_err(&hdev->pdev->dev, 590 "failed to query mac statistic reg number, ret = %d\n", 591 ret); 592 return ret; 593 } 594 595 *reg_num = le32_to_cpu(desc.data[0]); 596 if (*reg_num == 0) { 597 dev_err(&hdev->pdev->dev, 598 "mac statistic reg number is invalid!\n"); 599 return -ENODATA; 600 } 601 602 return 0; 603 } 604 605 int hclge_mac_update_stats(struct hclge_dev *hdev) 606 { 607 /* The firmware supports the new statistics acquisition method */ 608 if (hdev->ae_dev->dev_specs.mac_stats_num) 609 return hclge_mac_update_stats_complete(hdev); 610 else 611 return hclge_mac_update_stats_defective(hdev); 612 } 613 614 static int hclge_comm_get_count(struct hclge_dev *hdev, 615 const struct hclge_comm_stats_str strs[], 616 u32 size) 617 { 618 int count = 0; 619 u32 i; 620 621 for (i = 0; i < size; i++) 622 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 623 count++; 624 625 return count; 626 } 627 628 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 629 const struct hclge_comm_stats_str strs[], 630 int size, u64 *data) 631 { 632 u64 *buf = data; 633 u32 i; 634 635 for (i = 0; i < size; i++) { 636 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 637 continue; 638 639 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 640 buf++; 641 } 642 643 return buf; 644 } 645 646 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 647 const struct hclge_comm_stats_str strs[], 648 int size, u8 *data) 649 { 650 char *buff = (char *)data; 651 u32 i; 652 653 if (stringset != ETH_SS_STATS) 654 return buff; 655 656 for (i = 0; i < size; i++) { 657 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 658 continue; 659 660 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 661 buff = buff + ETH_GSTRING_LEN; 662 } 663 664 return (u8 *)buff; 665 } 666 667 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 668 { 669 struct hnae3_handle *handle; 670 int status; 671 672 handle = &hdev->vport[0].nic; 673 if (handle->client) { 674 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 675 if (status) { 676 dev_err(&hdev->pdev->dev, 677 "Update TQPS stats fail, status = %d.\n", 678 status); 679 } 680 } 681 682 status = hclge_mac_update_stats(hdev); 683 if (status) 684 dev_err(&hdev->pdev->dev, 685 "Update MAC stats fail, status = %d.\n", status); 686 } 687 688 static void hclge_update_stats(struct hnae3_handle *handle, 689 struct net_device_stats *net_stats) 690 { 691 struct hclge_vport *vport = hclge_get_vport(handle); 692 struct hclge_dev *hdev = vport->back; 693 int status; 694 695 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 696 return; 697 698 status = hclge_mac_update_stats(hdev); 699 if (status) 700 dev_err(&hdev->pdev->dev, 701 "Update MAC stats fail, status = %d.\n", 702 status); 703 704 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 705 if (status) 706 dev_err(&hdev->pdev->dev, 707 "Update TQPS stats fail, status = %d.\n", 708 status); 709 710 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 711 } 712 713 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 714 { 715 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 716 HNAE3_SUPPORT_PHY_LOOPBACK | \ 717 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 718 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) 719 720 struct hclge_vport *vport = hclge_get_vport(handle); 721 struct hclge_dev *hdev = vport->back; 722 int count = 0; 723 724 /* Loopback test support rules: 725 * mac: only GE mode support 726 * serdes: all mac mode will support include GE/XGE/LGE/CGE 727 * phy: only support when phy device exist on board 728 */ 729 if (stringset == ETH_SS_TEST) { 730 /* clear loopback bit flags at first */ 731 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 732 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 733 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 734 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 735 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 736 count += 1; 737 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 738 } 739 740 count += 2; 741 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 742 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 743 744 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 745 hdev->hw.mac.phydev->drv->set_loopback) || 746 hnae3_dev_phy_imp_supported(hdev)) { 747 count += 1; 748 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 749 } 750 } else if (stringset == ETH_SS_STATS) { 751 count = hclge_comm_get_count(hdev, g_mac_stats_string, 752 ARRAY_SIZE(g_mac_stats_string)) + 753 hclge_comm_tqps_get_sset_count(handle); 754 } 755 756 return count; 757 } 758 759 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 760 u8 *data) 761 { 762 struct hclge_vport *vport = hclge_get_vport(handle); 763 struct hclge_dev *hdev = vport->back; 764 u8 *p = (char *)data; 765 int size; 766 767 if (stringset == ETH_SS_STATS) { 768 size = ARRAY_SIZE(g_mac_stats_string); 769 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 770 size, p); 771 p = hclge_comm_tqps_get_strings(handle, p); 772 } else if (stringset == ETH_SS_TEST) { 773 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 774 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 775 ETH_GSTRING_LEN); 776 p += ETH_GSTRING_LEN; 777 } 778 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 779 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 780 ETH_GSTRING_LEN); 781 p += ETH_GSTRING_LEN; 782 } 783 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 784 memcpy(p, 785 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 786 ETH_GSTRING_LEN); 787 p += ETH_GSTRING_LEN; 788 } 789 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 790 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 791 ETH_GSTRING_LEN); 792 p += ETH_GSTRING_LEN; 793 } 794 } 795 } 796 797 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 798 { 799 struct hclge_vport *vport = hclge_get_vport(handle); 800 struct hclge_dev *hdev = vport->back; 801 u64 *p; 802 803 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 804 ARRAY_SIZE(g_mac_stats_string), data); 805 p = hclge_comm_tqps_get_stats(handle, p); 806 } 807 808 static void hclge_get_mac_stat(struct hnae3_handle *handle, 809 struct hns3_mac_stats *mac_stats) 810 { 811 struct hclge_vport *vport = hclge_get_vport(handle); 812 struct hclge_dev *hdev = vport->back; 813 814 hclge_update_stats(handle, NULL); 815 816 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 817 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 818 } 819 820 static int hclge_parse_func_status(struct hclge_dev *hdev, 821 struct hclge_func_status_cmd *status) 822 { 823 #define HCLGE_MAC_ID_MASK 0xF 824 825 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 826 return -EINVAL; 827 828 /* Set the pf to main pf */ 829 if (status->pf_state & HCLGE_PF_STATE_MAIN) 830 hdev->flag |= HCLGE_FLAG_MAIN; 831 else 832 hdev->flag &= ~HCLGE_FLAG_MAIN; 833 834 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 835 return 0; 836 } 837 838 static int hclge_query_function_status(struct hclge_dev *hdev) 839 { 840 #define HCLGE_QUERY_MAX_CNT 5 841 842 struct hclge_func_status_cmd *req; 843 struct hclge_desc desc; 844 int timeout = 0; 845 int ret; 846 847 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 848 req = (struct hclge_func_status_cmd *)desc.data; 849 850 do { 851 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 852 if (ret) { 853 dev_err(&hdev->pdev->dev, 854 "query function status failed %d.\n", ret); 855 return ret; 856 } 857 858 /* Check pf reset is done */ 859 if (req->pf_state) 860 break; 861 usleep_range(1000, 2000); 862 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 863 864 return hclge_parse_func_status(hdev, req); 865 } 866 867 static int hclge_query_pf_resource(struct hclge_dev *hdev) 868 { 869 struct hclge_pf_res_cmd *req; 870 struct hclge_desc desc; 871 int ret; 872 873 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 874 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 875 if (ret) { 876 dev_err(&hdev->pdev->dev, 877 "query pf resource failed %d.\n", ret); 878 return ret; 879 } 880 881 req = (struct hclge_pf_res_cmd *)desc.data; 882 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 883 le16_to_cpu(req->ext_tqp_num); 884 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 885 886 if (req->tx_buf_size) 887 hdev->tx_buf_size = 888 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 889 else 890 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 891 892 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 893 894 if (req->dv_buf_size) 895 hdev->dv_buf_size = 896 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 897 else 898 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 899 900 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 901 902 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 903 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 904 dev_err(&hdev->pdev->dev, 905 "only %u msi resources available, not enough for pf(min:2).\n", 906 hdev->num_nic_msi); 907 return -EINVAL; 908 } 909 910 if (hnae3_dev_roce_supported(hdev)) { 911 hdev->num_roce_msi = 912 le16_to_cpu(req->pf_intr_vector_number_roce); 913 914 /* PF should have NIC vectors and Roce vectors, 915 * NIC vectors are queued before Roce vectors. 916 */ 917 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 918 } else { 919 hdev->num_msi = hdev->num_nic_msi; 920 } 921 922 return 0; 923 } 924 925 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 926 { 927 switch (speed_cmd) { 928 case HCLGE_FW_MAC_SPEED_10M: 929 *speed = HCLGE_MAC_SPEED_10M; 930 break; 931 case HCLGE_FW_MAC_SPEED_100M: 932 *speed = HCLGE_MAC_SPEED_100M; 933 break; 934 case HCLGE_FW_MAC_SPEED_1G: 935 *speed = HCLGE_MAC_SPEED_1G; 936 break; 937 case HCLGE_FW_MAC_SPEED_10G: 938 *speed = HCLGE_MAC_SPEED_10G; 939 break; 940 case HCLGE_FW_MAC_SPEED_25G: 941 *speed = HCLGE_MAC_SPEED_25G; 942 break; 943 case HCLGE_FW_MAC_SPEED_40G: 944 *speed = HCLGE_MAC_SPEED_40G; 945 break; 946 case HCLGE_FW_MAC_SPEED_50G: 947 *speed = HCLGE_MAC_SPEED_50G; 948 break; 949 case HCLGE_FW_MAC_SPEED_100G: 950 *speed = HCLGE_MAC_SPEED_100G; 951 break; 952 case HCLGE_FW_MAC_SPEED_200G: 953 *speed = HCLGE_MAC_SPEED_200G; 954 break; 955 default: 956 return -EINVAL; 957 } 958 959 return 0; 960 } 961 962 static const struct hclge_speed_bit_map speed_bit_map[] = { 963 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 964 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 965 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 966 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 967 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 968 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 969 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 970 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 971 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 972 }; 973 974 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 975 { 976 u16 i; 977 978 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 979 if (speed == speed_bit_map[i].speed) { 980 *speed_bit = speed_bit_map[i].speed_bit; 981 return 0; 982 } 983 } 984 985 return -EINVAL; 986 } 987 988 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 989 { 990 struct hclge_vport *vport = hclge_get_vport(handle); 991 struct hclge_dev *hdev = vport->back; 992 u32 speed_ability = hdev->hw.mac.speed_ability; 993 u32 speed_bit = 0; 994 int ret; 995 996 ret = hclge_get_speed_bit(speed, &speed_bit); 997 if (ret) 998 return ret; 999 1000 if (speed_bit & speed_ability) 1001 return 0; 1002 1003 return -EINVAL; 1004 } 1005 1006 static void hclge_convert_setting_sr(u16 speed_ability, 1007 unsigned long *link_mode) 1008 { 1009 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1010 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1011 link_mode); 1012 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1013 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1014 link_mode); 1015 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1016 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1017 link_mode); 1018 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1019 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1020 link_mode); 1021 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1022 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1023 link_mode); 1024 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1025 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1026 link_mode); 1027 } 1028 1029 static void hclge_convert_setting_lr(u16 speed_ability, 1030 unsigned long *link_mode) 1031 { 1032 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1033 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1034 link_mode); 1035 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1036 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1037 link_mode); 1038 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1039 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1040 link_mode); 1041 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1042 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1043 link_mode); 1044 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1045 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1046 link_mode); 1047 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1048 linkmode_set_bit( 1049 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1050 link_mode); 1051 } 1052 1053 static void hclge_convert_setting_cr(u16 speed_ability, 1054 unsigned long *link_mode) 1055 { 1056 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1057 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1058 link_mode); 1059 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1060 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1061 link_mode); 1062 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1063 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1064 link_mode); 1065 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1066 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1067 link_mode); 1068 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1069 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1070 link_mode); 1071 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1072 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1073 link_mode); 1074 } 1075 1076 static void hclge_convert_setting_kr(u16 speed_ability, 1077 unsigned long *link_mode) 1078 { 1079 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1080 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1081 link_mode); 1082 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1083 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1084 link_mode); 1085 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1086 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1087 link_mode); 1088 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1089 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1090 link_mode); 1091 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1092 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1093 link_mode); 1094 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1095 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1096 link_mode); 1097 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1098 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1099 link_mode); 1100 } 1101 1102 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1103 { 1104 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 1105 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 1106 1107 switch (mac->speed) { 1108 case HCLGE_MAC_SPEED_10G: 1109 case HCLGE_MAC_SPEED_40G: 1110 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1111 mac->supported); 1112 mac->fec_ability = 1113 BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO); 1114 break; 1115 case HCLGE_MAC_SPEED_25G: 1116 case HCLGE_MAC_SPEED_50G: 1117 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1118 mac->supported); 1119 mac->fec_ability = 1120 BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1121 BIT(HNAE3_FEC_AUTO); 1122 break; 1123 case HCLGE_MAC_SPEED_100G: 1124 case HCLGE_MAC_SPEED_200G: 1125 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 1126 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO); 1127 break; 1128 default: 1129 mac->fec_ability = 0; 1130 break; 1131 } 1132 } 1133 1134 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1135 u16 speed_ability) 1136 { 1137 struct hclge_mac *mac = &hdev->hw.mac; 1138 1139 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1140 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1141 mac->supported); 1142 1143 hclge_convert_setting_sr(speed_ability, mac->supported); 1144 hclge_convert_setting_lr(speed_ability, mac->supported); 1145 hclge_convert_setting_cr(speed_ability, mac->supported); 1146 if (hnae3_dev_fec_supported(hdev)) 1147 hclge_convert_setting_fec(mac); 1148 1149 if (hnae3_dev_pause_supported(hdev)) 1150 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1151 1152 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1153 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1154 } 1155 1156 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1157 u16 speed_ability) 1158 { 1159 struct hclge_mac *mac = &hdev->hw.mac; 1160 1161 hclge_convert_setting_kr(speed_ability, mac->supported); 1162 if (hnae3_dev_fec_supported(hdev)) 1163 hclge_convert_setting_fec(mac); 1164 1165 if (hnae3_dev_pause_supported(hdev)) 1166 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1167 1168 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1169 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1170 } 1171 1172 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1173 u16 speed_ability) 1174 { 1175 unsigned long *supported = hdev->hw.mac.supported; 1176 1177 /* default to support all speed for GE port */ 1178 if (!speed_ability) 1179 speed_ability = HCLGE_SUPPORT_GE; 1180 1181 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1182 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1183 supported); 1184 1185 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1186 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1187 supported); 1188 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1189 supported); 1190 } 1191 1192 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1193 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1194 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1195 } 1196 1197 if (hnae3_dev_pause_supported(hdev)) { 1198 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1199 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1200 } 1201 1202 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1203 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1204 } 1205 1206 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1207 { 1208 u8 media_type = hdev->hw.mac.media_type; 1209 1210 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1211 hclge_parse_fiber_link_mode(hdev, speed_ability); 1212 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1213 hclge_parse_copper_link_mode(hdev, speed_ability); 1214 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1215 hclge_parse_backplane_link_mode(hdev, speed_ability); 1216 } 1217 1218 static u32 hclge_get_max_speed(u16 speed_ability) 1219 { 1220 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1221 return HCLGE_MAC_SPEED_200G; 1222 1223 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1224 return HCLGE_MAC_SPEED_100G; 1225 1226 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1227 return HCLGE_MAC_SPEED_50G; 1228 1229 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1230 return HCLGE_MAC_SPEED_40G; 1231 1232 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1233 return HCLGE_MAC_SPEED_25G; 1234 1235 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1236 return HCLGE_MAC_SPEED_10G; 1237 1238 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1239 return HCLGE_MAC_SPEED_1G; 1240 1241 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1242 return HCLGE_MAC_SPEED_100M; 1243 1244 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1245 return HCLGE_MAC_SPEED_10M; 1246 1247 return HCLGE_MAC_SPEED_1G; 1248 } 1249 1250 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1251 { 1252 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1253 #define SPEED_ABILITY_EXT_SHIFT 8 1254 1255 struct hclge_cfg_param_cmd *req; 1256 u64 mac_addr_tmp_high; 1257 u16 speed_ability_ext; 1258 u64 mac_addr_tmp; 1259 unsigned int i; 1260 1261 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1262 1263 /* get the configuration */ 1264 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1265 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1266 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1267 HCLGE_CFG_TQP_DESC_N_M, 1268 HCLGE_CFG_TQP_DESC_N_S); 1269 1270 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1271 HCLGE_CFG_PHY_ADDR_M, 1272 HCLGE_CFG_PHY_ADDR_S); 1273 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1274 HCLGE_CFG_MEDIA_TP_M, 1275 HCLGE_CFG_MEDIA_TP_S); 1276 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1277 HCLGE_CFG_RX_BUF_LEN_M, 1278 HCLGE_CFG_RX_BUF_LEN_S); 1279 /* get mac_address */ 1280 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1281 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1282 HCLGE_CFG_MAC_ADDR_H_M, 1283 HCLGE_CFG_MAC_ADDR_H_S); 1284 1285 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1286 1287 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1288 HCLGE_CFG_DEFAULT_SPEED_M, 1289 HCLGE_CFG_DEFAULT_SPEED_S); 1290 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1291 HCLGE_CFG_RSS_SIZE_M, 1292 HCLGE_CFG_RSS_SIZE_S); 1293 1294 for (i = 0; i < ETH_ALEN; i++) 1295 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1296 1297 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1298 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1299 1300 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1301 HCLGE_CFG_SPEED_ABILITY_M, 1302 HCLGE_CFG_SPEED_ABILITY_S); 1303 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1304 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1305 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1306 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1307 1308 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1309 HCLGE_CFG_VLAN_FLTR_CAP_M, 1310 HCLGE_CFG_VLAN_FLTR_CAP_S); 1311 1312 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1313 HCLGE_CFG_UMV_TBL_SPACE_M, 1314 HCLGE_CFG_UMV_TBL_SPACE_S); 1315 1316 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1317 HCLGE_CFG_PF_RSS_SIZE_M, 1318 HCLGE_CFG_PF_RSS_SIZE_S); 1319 1320 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1321 * power of 2, instead of reading out directly. This would 1322 * be more flexible for future changes and expansions. 1323 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1324 * it does not make sense if PF's field is 0. In this case, PF and VF 1325 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1326 */ 1327 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1328 1U << cfg->pf_rss_size_max : 1329 cfg->vf_rss_size_max; 1330 1331 /* The unit of the tx spare buffer size queried from configuration 1332 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1333 * needed here. 1334 */ 1335 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1336 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1337 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1338 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1339 } 1340 1341 /* hclge_get_cfg: query the static parameter from flash 1342 * @hdev: pointer to struct hclge_dev 1343 * @hcfg: the config structure to be getted 1344 */ 1345 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1346 { 1347 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1348 struct hclge_cfg_param_cmd *req; 1349 unsigned int i; 1350 int ret; 1351 1352 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1353 u32 offset = 0; 1354 1355 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1356 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1357 true); 1358 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1359 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1360 /* Len should be united by 4 bytes when send to hardware */ 1361 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1362 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1363 req->offset = cpu_to_le32(offset); 1364 } 1365 1366 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1367 if (ret) { 1368 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1369 return ret; 1370 } 1371 1372 hclge_parse_cfg(hcfg, desc); 1373 1374 return 0; 1375 } 1376 1377 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1378 { 1379 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1380 1381 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1382 1383 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1384 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1385 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1386 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1387 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1388 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1389 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1390 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1391 } 1392 1393 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1394 struct hclge_desc *desc) 1395 { 1396 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1397 struct hclge_dev_specs_0_cmd *req0; 1398 struct hclge_dev_specs_1_cmd *req1; 1399 1400 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1401 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1402 1403 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1404 ae_dev->dev_specs.rss_ind_tbl_size = 1405 le16_to_cpu(req0->rss_ind_tbl_size); 1406 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1407 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1408 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1409 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1410 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1411 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1412 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1413 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1414 } 1415 1416 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1417 { 1418 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1419 1420 if (!dev_specs->max_non_tso_bd_num) 1421 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1422 if (!dev_specs->rss_ind_tbl_size) 1423 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1424 if (!dev_specs->rss_key_size) 1425 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1426 if (!dev_specs->max_tm_rate) 1427 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1428 if (!dev_specs->max_qset_num) 1429 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1430 if (!dev_specs->max_int_gl) 1431 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1432 if (!dev_specs->max_frm_size) 1433 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1434 if (!dev_specs->umv_size) 1435 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1436 } 1437 1438 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1439 { 1440 u32 reg_num = 0; 1441 int ret; 1442 1443 ret = hclge_mac_query_reg_num(hdev, ®_num); 1444 if (ret && ret != -EOPNOTSUPP) 1445 return ret; 1446 1447 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1448 return 0; 1449 } 1450 1451 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1452 { 1453 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1454 int ret; 1455 int i; 1456 1457 ret = hclge_query_mac_stats_num(hdev); 1458 if (ret) 1459 return ret; 1460 1461 /* set default specifications as devices lower than version V3 do not 1462 * support querying specifications from firmware. 1463 */ 1464 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1465 hclge_set_default_dev_specs(hdev); 1466 return 0; 1467 } 1468 1469 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1470 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1471 true); 1472 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1473 } 1474 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1475 1476 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1477 if (ret) 1478 return ret; 1479 1480 hclge_parse_dev_specs(hdev, desc); 1481 hclge_check_dev_specs(hdev); 1482 1483 return 0; 1484 } 1485 1486 static int hclge_get_cap(struct hclge_dev *hdev) 1487 { 1488 int ret; 1489 1490 ret = hclge_query_function_status(hdev); 1491 if (ret) { 1492 dev_err(&hdev->pdev->dev, 1493 "query function status error %d.\n", ret); 1494 return ret; 1495 } 1496 1497 /* get pf resource */ 1498 return hclge_query_pf_resource(hdev); 1499 } 1500 1501 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1502 { 1503 #define HCLGE_MIN_TX_DESC 64 1504 #define HCLGE_MIN_RX_DESC 64 1505 1506 if (!is_kdump_kernel()) 1507 return; 1508 1509 dev_info(&hdev->pdev->dev, 1510 "Running kdump kernel. Using minimal resources\n"); 1511 1512 /* minimal queue pairs equals to the number of vports */ 1513 hdev->num_tqps = hdev->num_req_vfs + 1; 1514 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1515 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1516 } 1517 1518 static void hclge_init_tc_config(struct hclge_dev *hdev) 1519 { 1520 unsigned int i; 1521 1522 if (hdev->tc_max > HNAE3_MAX_TC || 1523 hdev->tc_max < 1) { 1524 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1525 hdev->tc_max); 1526 hdev->tc_max = 1; 1527 } 1528 1529 /* Dev does not support DCB */ 1530 if (!hnae3_dev_dcb_supported(hdev)) { 1531 hdev->tc_max = 1; 1532 hdev->pfc_max = 0; 1533 } else { 1534 hdev->pfc_max = hdev->tc_max; 1535 } 1536 1537 hdev->tm_info.num_tc = 1; 1538 1539 /* Currently not support uncontiuous tc */ 1540 for (i = 0; i < hdev->tm_info.num_tc; i++) 1541 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1542 1543 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1544 } 1545 1546 static int hclge_configure(struct hclge_dev *hdev) 1547 { 1548 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1549 const struct cpumask *cpumask = cpu_online_mask; 1550 struct hclge_cfg cfg; 1551 int node, ret; 1552 1553 ret = hclge_get_cfg(hdev, &cfg); 1554 if (ret) 1555 return ret; 1556 1557 hdev->base_tqp_pid = 0; 1558 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1559 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1560 hdev->rx_buf_len = cfg.rx_buf_len; 1561 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1562 hdev->hw.mac.media_type = cfg.media_type; 1563 hdev->hw.mac.phy_addr = cfg.phy_addr; 1564 hdev->num_tx_desc = cfg.tqp_desc_num; 1565 hdev->num_rx_desc = cfg.tqp_desc_num; 1566 hdev->tm_info.num_pg = 1; 1567 hdev->tc_max = cfg.tc_num; 1568 hdev->tm_info.hw_pfc_map = 0; 1569 if (cfg.umv_space) 1570 hdev->wanted_umv_size = cfg.umv_space; 1571 else 1572 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1573 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1574 hdev->gro_en = true; 1575 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1576 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1577 1578 if (hnae3_dev_fd_supported(hdev)) { 1579 hdev->fd_en = true; 1580 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1581 } 1582 1583 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1584 if (ret) { 1585 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1586 cfg.default_speed, ret); 1587 return ret; 1588 } 1589 1590 hclge_parse_link_mode(hdev, cfg.speed_ability); 1591 1592 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1593 1594 hclge_init_tc_config(hdev); 1595 hclge_init_kdump_kernel_config(hdev); 1596 1597 /* Set the affinity based on numa node */ 1598 node = dev_to_node(&hdev->pdev->dev); 1599 if (node != NUMA_NO_NODE) 1600 cpumask = cpumask_of_node(node); 1601 1602 cpumask_copy(&hdev->affinity_mask, cpumask); 1603 1604 return ret; 1605 } 1606 1607 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1608 u16 tso_mss_max) 1609 { 1610 struct hclge_cfg_tso_status_cmd *req; 1611 struct hclge_desc desc; 1612 1613 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1614 1615 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1616 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1617 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1618 1619 return hclge_cmd_send(&hdev->hw, &desc, 1); 1620 } 1621 1622 static int hclge_config_gro(struct hclge_dev *hdev) 1623 { 1624 struct hclge_cfg_gro_status_cmd *req; 1625 struct hclge_desc desc; 1626 int ret; 1627 1628 if (!hnae3_dev_gro_supported(hdev)) 1629 return 0; 1630 1631 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1632 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1633 1634 req->gro_en = hdev->gro_en ? 1 : 0; 1635 1636 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1637 if (ret) 1638 dev_err(&hdev->pdev->dev, 1639 "GRO hardware config cmd failed, ret = %d\n", ret); 1640 1641 return ret; 1642 } 1643 1644 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1645 { 1646 struct hclge_comm_tqp *tqp; 1647 int i; 1648 1649 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1650 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1651 if (!hdev->htqp) 1652 return -ENOMEM; 1653 1654 tqp = hdev->htqp; 1655 1656 for (i = 0; i < hdev->num_tqps; i++) { 1657 tqp->dev = &hdev->pdev->dev; 1658 tqp->index = i; 1659 1660 tqp->q.ae_algo = &ae_algo; 1661 tqp->q.buf_size = hdev->rx_buf_len; 1662 tqp->q.tx_desc_num = hdev->num_tx_desc; 1663 tqp->q.rx_desc_num = hdev->num_rx_desc; 1664 1665 /* need an extended offset to configure queues >= 1666 * HCLGE_TQP_MAX_SIZE_DEV_V2 1667 */ 1668 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1669 tqp->q.io_base = hdev->hw.hw.io_base + 1670 HCLGE_TQP_REG_OFFSET + 1671 i * HCLGE_TQP_REG_SIZE; 1672 else 1673 tqp->q.io_base = hdev->hw.hw.io_base + 1674 HCLGE_TQP_REG_OFFSET + 1675 HCLGE_TQP_EXT_REG_OFFSET + 1676 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1677 HCLGE_TQP_REG_SIZE; 1678 1679 tqp++; 1680 } 1681 1682 return 0; 1683 } 1684 1685 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1686 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1687 { 1688 struct hclge_tqp_map_cmd *req; 1689 struct hclge_desc desc; 1690 int ret; 1691 1692 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1693 1694 req = (struct hclge_tqp_map_cmd *)desc.data; 1695 req->tqp_id = cpu_to_le16(tqp_pid); 1696 req->tqp_vf = func_id; 1697 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1698 if (!is_pf) 1699 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1700 req->tqp_vid = cpu_to_le16(tqp_vid); 1701 1702 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1703 if (ret) 1704 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1705 1706 return ret; 1707 } 1708 1709 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1710 { 1711 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1712 struct hclge_dev *hdev = vport->back; 1713 int i, alloced; 1714 1715 for (i = 0, alloced = 0; i < hdev->num_tqps && 1716 alloced < num_tqps; i++) { 1717 if (!hdev->htqp[i].alloced) { 1718 hdev->htqp[i].q.handle = &vport->nic; 1719 hdev->htqp[i].q.tqp_index = alloced; 1720 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1721 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1722 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1723 hdev->htqp[i].alloced = true; 1724 alloced++; 1725 } 1726 } 1727 vport->alloc_tqps = alloced; 1728 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1729 vport->alloc_tqps / hdev->tm_info.num_tc); 1730 1731 /* ensure one to one mapping between irq and queue at default */ 1732 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1733 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1734 1735 return 0; 1736 } 1737 1738 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1739 u16 num_tx_desc, u16 num_rx_desc) 1740 1741 { 1742 struct hnae3_handle *nic = &vport->nic; 1743 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1744 struct hclge_dev *hdev = vport->back; 1745 int ret; 1746 1747 kinfo->num_tx_desc = num_tx_desc; 1748 kinfo->num_rx_desc = num_rx_desc; 1749 1750 kinfo->rx_buf_len = hdev->rx_buf_len; 1751 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1752 1753 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1754 sizeof(struct hnae3_queue *), GFP_KERNEL); 1755 if (!kinfo->tqp) 1756 return -ENOMEM; 1757 1758 ret = hclge_assign_tqp(vport, num_tqps); 1759 if (ret) 1760 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1761 1762 return ret; 1763 } 1764 1765 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1766 struct hclge_vport *vport) 1767 { 1768 struct hnae3_handle *nic = &vport->nic; 1769 struct hnae3_knic_private_info *kinfo; 1770 u16 i; 1771 1772 kinfo = &nic->kinfo; 1773 for (i = 0; i < vport->alloc_tqps; i++) { 1774 struct hclge_comm_tqp *q = 1775 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1776 bool is_pf; 1777 int ret; 1778 1779 is_pf = !(vport->vport_id); 1780 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1781 i, is_pf); 1782 if (ret) 1783 return ret; 1784 } 1785 1786 return 0; 1787 } 1788 1789 static int hclge_map_tqp(struct hclge_dev *hdev) 1790 { 1791 struct hclge_vport *vport = hdev->vport; 1792 u16 i, num_vport; 1793 1794 num_vport = hdev->num_req_vfs + 1; 1795 for (i = 0; i < num_vport; i++) { 1796 int ret; 1797 1798 ret = hclge_map_tqp_to_vport(hdev, vport); 1799 if (ret) 1800 return ret; 1801 1802 vport++; 1803 } 1804 1805 return 0; 1806 } 1807 1808 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1809 { 1810 struct hnae3_handle *nic = &vport->nic; 1811 struct hclge_dev *hdev = vport->back; 1812 int ret; 1813 1814 nic->pdev = hdev->pdev; 1815 nic->ae_algo = &ae_algo; 1816 nic->numa_node_mask = hdev->numa_node_mask; 1817 nic->kinfo.io_base = hdev->hw.hw.io_base; 1818 1819 ret = hclge_knic_setup(vport, num_tqps, 1820 hdev->num_tx_desc, hdev->num_rx_desc); 1821 if (ret) 1822 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1823 1824 return ret; 1825 } 1826 1827 static int hclge_alloc_vport(struct hclge_dev *hdev) 1828 { 1829 struct pci_dev *pdev = hdev->pdev; 1830 struct hclge_vport *vport; 1831 u32 tqp_main_vport; 1832 u32 tqp_per_vport; 1833 int num_vport, i; 1834 int ret; 1835 1836 /* We need to alloc a vport for main NIC of PF */ 1837 num_vport = hdev->num_req_vfs + 1; 1838 1839 if (hdev->num_tqps < num_vport) { 1840 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1841 hdev->num_tqps, num_vport); 1842 return -EINVAL; 1843 } 1844 1845 /* Alloc the same number of TQPs for every vport */ 1846 tqp_per_vport = hdev->num_tqps / num_vport; 1847 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1848 1849 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1850 GFP_KERNEL); 1851 if (!vport) 1852 return -ENOMEM; 1853 1854 hdev->vport = vport; 1855 hdev->num_alloc_vport = num_vport; 1856 1857 if (IS_ENABLED(CONFIG_PCI_IOV)) 1858 hdev->num_alloc_vfs = hdev->num_req_vfs; 1859 1860 for (i = 0; i < num_vport; i++) { 1861 vport->back = hdev; 1862 vport->vport_id = i; 1863 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1864 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1865 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1866 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1867 vport->req_vlan_fltr_en = true; 1868 INIT_LIST_HEAD(&vport->vlan_list); 1869 INIT_LIST_HEAD(&vport->uc_mac_list); 1870 INIT_LIST_HEAD(&vport->mc_mac_list); 1871 spin_lock_init(&vport->mac_list_lock); 1872 1873 if (i == 0) 1874 ret = hclge_vport_setup(vport, tqp_main_vport); 1875 else 1876 ret = hclge_vport_setup(vport, tqp_per_vport); 1877 if (ret) { 1878 dev_err(&pdev->dev, 1879 "vport setup failed for vport %d, %d\n", 1880 i, ret); 1881 return ret; 1882 } 1883 1884 vport++; 1885 } 1886 1887 return 0; 1888 } 1889 1890 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1891 struct hclge_pkt_buf_alloc *buf_alloc) 1892 { 1893 /* TX buffer size is unit by 128 byte */ 1894 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1895 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1896 struct hclge_tx_buff_alloc_cmd *req; 1897 struct hclge_desc desc; 1898 int ret; 1899 u8 i; 1900 1901 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1902 1903 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1904 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1905 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1906 1907 req->tx_pkt_buff[i] = 1908 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1909 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1910 } 1911 1912 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1913 if (ret) 1914 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1915 ret); 1916 1917 return ret; 1918 } 1919 1920 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1921 struct hclge_pkt_buf_alloc *buf_alloc) 1922 { 1923 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1924 1925 if (ret) 1926 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1927 1928 return ret; 1929 } 1930 1931 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1932 { 1933 unsigned int i; 1934 u32 cnt = 0; 1935 1936 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1937 if (hdev->hw_tc_map & BIT(i)) 1938 cnt++; 1939 return cnt; 1940 } 1941 1942 /* Get the number of pfc enabled TCs, which have private buffer */ 1943 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1944 struct hclge_pkt_buf_alloc *buf_alloc) 1945 { 1946 struct hclge_priv_buf *priv; 1947 unsigned int i; 1948 int cnt = 0; 1949 1950 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1951 priv = &buf_alloc->priv_buf[i]; 1952 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1953 priv->enable) 1954 cnt++; 1955 } 1956 1957 return cnt; 1958 } 1959 1960 /* Get the number of pfc disabled TCs, which have private buffer */ 1961 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1962 struct hclge_pkt_buf_alloc *buf_alloc) 1963 { 1964 struct hclge_priv_buf *priv; 1965 unsigned int i; 1966 int cnt = 0; 1967 1968 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1969 priv = &buf_alloc->priv_buf[i]; 1970 if (hdev->hw_tc_map & BIT(i) && 1971 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1972 priv->enable) 1973 cnt++; 1974 } 1975 1976 return cnt; 1977 } 1978 1979 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1980 { 1981 struct hclge_priv_buf *priv; 1982 u32 rx_priv = 0; 1983 int i; 1984 1985 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1986 priv = &buf_alloc->priv_buf[i]; 1987 if (priv->enable) 1988 rx_priv += priv->buf_size; 1989 } 1990 return rx_priv; 1991 } 1992 1993 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1994 { 1995 u32 i, total_tx_size = 0; 1996 1997 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1998 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1999 2000 return total_tx_size; 2001 } 2002 2003 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 2004 struct hclge_pkt_buf_alloc *buf_alloc, 2005 u32 rx_all) 2006 { 2007 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2008 u32 tc_num = hclge_get_tc_num(hdev); 2009 u32 shared_buf, aligned_mps; 2010 u32 rx_priv; 2011 int i; 2012 2013 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2014 2015 if (hnae3_dev_dcb_supported(hdev)) 2016 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2017 hdev->dv_buf_size; 2018 else 2019 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2020 + hdev->dv_buf_size; 2021 2022 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2023 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2024 HCLGE_BUF_SIZE_UNIT); 2025 2026 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2027 if (rx_all < rx_priv + shared_std) 2028 return false; 2029 2030 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2031 buf_alloc->s_buf.buf_size = shared_buf; 2032 if (hnae3_dev_dcb_supported(hdev)) { 2033 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2034 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2035 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2036 HCLGE_BUF_SIZE_UNIT); 2037 } else { 2038 buf_alloc->s_buf.self.high = aligned_mps + 2039 HCLGE_NON_DCB_ADDITIONAL_BUF; 2040 buf_alloc->s_buf.self.low = aligned_mps; 2041 } 2042 2043 if (hnae3_dev_dcb_supported(hdev)) { 2044 hi_thrd = shared_buf - hdev->dv_buf_size; 2045 2046 if (tc_num <= NEED_RESERVE_TC_NUM) 2047 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2048 / BUF_MAX_PERCENT; 2049 2050 if (tc_num) 2051 hi_thrd = hi_thrd / tc_num; 2052 2053 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2054 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2055 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2056 } else { 2057 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2058 lo_thrd = aligned_mps; 2059 } 2060 2061 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2062 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2063 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2064 } 2065 2066 return true; 2067 } 2068 2069 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2070 struct hclge_pkt_buf_alloc *buf_alloc) 2071 { 2072 u32 i, total_size; 2073 2074 total_size = hdev->pkt_buf_size; 2075 2076 /* alloc tx buffer for all enabled tc */ 2077 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2078 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2079 2080 if (hdev->hw_tc_map & BIT(i)) { 2081 if (total_size < hdev->tx_buf_size) 2082 return -ENOMEM; 2083 2084 priv->tx_buf_size = hdev->tx_buf_size; 2085 } else { 2086 priv->tx_buf_size = 0; 2087 } 2088 2089 total_size -= priv->tx_buf_size; 2090 } 2091 2092 return 0; 2093 } 2094 2095 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2096 struct hclge_pkt_buf_alloc *buf_alloc) 2097 { 2098 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2099 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2100 unsigned int i; 2101 2102 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2103 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2104 2105 priv->enable = 0; 2106 priv->wl.low = 0; 2107 priv->wl.high = 0; 2108 priv->buf_size = 0; 2109 2110 if (!(hdev->hw_tc_map & BIT(i))) 2111 continue; 2112 2113 priv->enable = 1; 2114 2115 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2116 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2117 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2118 HCLGE_BUF_SIZE_UNIT); 2119 } else { 2120 priv->wl.low = 0; 2121 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2122 aligned_mps; 2123 } 2124 2125 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2126 } 2127 2128 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2129 } 2130 2131 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2132 struct hclge_pkt_buf_alloc *buf_alloc) 2133 { 2134 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2135 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2136 int i; 2137 2138 /* let the last to be cleared first */ 2139 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2140 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2141 unsigned int mask = BIT((unsigned int)i); 2142 2143 if (hdev->hw_tc_map & mask && 2144 !(hdev->tm_info.hw_pfc_map & mask)) { 2145 /* Clear the no pfc TC private buffer */ 2146 priv->wl.low = 0; 2147 priv->wl.high = 0; 2148 priv->buf_size = 0; 2149 priv->enable = 0; 2150 no_pfc_priv_num--; 2151 } 2152 2153 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2154 no_pfc_priv_num == 0) 2155 break; 2156 } 2157 2158 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2159 } 2160 2161 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2162 struct hclge_pkt_buf_alloc *buf_alloc) 2163 { 2164 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2165 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2166 int i; 2167 2168 /* let the last to be cleared first */ 2169 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2170 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2171 unsigned int mask = BIT((unsigned int)i); 2172 2173 if (hdev->hw_tc_map & mask && 2174 hdev->tm_info.hw_pfc_map & mask) { 2175 /* Reduce the number of pfc TC with private buffer */ 2176 priv->wl.low = 0; 2177 priv->enable = 0; 2178 priv->wl.high = 0; 2179 priv->buf_size = 0; 2180 pfc_priv_num--; 2181 } 2182 2183 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2184 pfc_priv_num == 0) 2185 break; 2186 } 2187 2188 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2189 } 2190 2191 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2192 struct hclge_pkt_buf_alloc *buf_alloc) 2193 { 2194 #define COMPENSATE_BUFFER 0x3C00 2195 #define COMPENSATE_HALF_MPS_NUM 5 2196 #define PRIV_WL_GAP 0x1800 2197 2198 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2199 u32 tc_num = hclge_get_tc_num(hdev); 2200 u32 half_mps = hdev->mps >> 1; 2201 u32 min_rx_priv; 2202 unsigned int i; 2203 2204 if (tc_num) 2205 rx_priv = rx_priv / tc_num; 2206 2207 if (tc_num <= NEED_RESERVE_TC_NUM) 2208 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2209 2210 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2211 COMPENSATE_HALF_MPS_NUM * half_mps; 2212 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2213 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2214 if (rx_priv < min_rx_priv) 2215 return false; 2216 2217 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2218 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2219 2220 priv->enable = 0; 2221 priv->wl.low = 0; 2222 priv->wl.high = 0; 2223 priv->buf_size = 0; 2224 2225 if (!(hdev->hw_tc_map & BIT(i))) 2226 continue; 2227 2228 priv->enable = 1; 2229 priv->buf_size = rx_priv; 2230 priv->wl.high = rx_priv - hdev->dv_buf_size; 2231 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2232 } 2233 2234 buf_alloc->s_buf.buf_size = 0; 2235 2236 return true; 2237 } 2238 2239 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2240 * @hdev: pointer to struct hclge_dev 2241 * @buf_alloc: pointer to buffer calculation data 2242 * @return: 0: calculate successful, negative: fail 2243 */ 2244 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2245 struct hclge_pkt_buf_alloc *buf_alloc) 2246 { 2247 /* When DCB is not supported, rx private buffer is not allocated. */ 2248 if (!hnae3_dev_dcb_supported(hdev)) { 2249 u32 rx_all = hdev->pkt_buf_size; 2250 2251 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2252 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2253 return -ENOMEM; 2254 2255 return 0; 2256 } 2257 2258 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2259 return 0; 2260 2261 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2262 return 0; 2263 2264 /* try to decrease the buffer size */ 2265 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2266 return 0; 2267 2268 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2269 return 0; 2270 2271 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2272 return 0; 2273 2274 return -ENOMEM; 2275 } 2276 2277 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2278 struct hclge_pkt_buf_alloc *buf_alloc) 2279 { 2280 struct hclge_rx_priv_buff_cmd *req; 2281 struct hclge_desc desc; 2282 int ret; 2283 int i; 2284 2285 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2286 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2287 2288 /* Alloc private buffer TCs */ 2289 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2290 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2291 2292 req->buf_num[i] = 2293 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2294 req->buf_num[i] |= 2295 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2296 } 2297 2298 req->shared_buf = 2299 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2300 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2301 2302 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2303 if (ret) 2304 dev_err(&hdev->pdev->dev, 2305 "rx private buffer alloc cmd failed %d\n", ret); 2306 2307 return ret; 2308 } 2309 2310 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2311 struct hclge_pkt_buf_alloc *buf_alloc) 2312 { 2313 struct hclge_rx_priv_wl_buf *req; 2314 struct hclge_priv_buf *priv; 2315 struct hclge_desc desc[2]; 2316 int i, j; 2317 int ret; 2318 2319 for (i = 0; i < 2; i++) { 2320 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2321 false); 2322 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2323 2324 /* The first descriptor set the NEXT bit to 1 */ 2325 if (i == 0) 2326 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2327 else 2328 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2329 2330 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2331 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2332 2333 priv = &buf_alloc->priv_buf[idx]; 2334 req->tc_wl[j].high = 2335 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2336 req->tc_wl[j].high |= 2337 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2338 req->tc_wl[j].low = 2339 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2340 req->tc_wl[j].low |= 2341 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2342 } 2343 } 2344 2345 /* Send 2 descriptor at one time */ 2346 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2347 if (ret) 2348 dev_err(&hdev->pdev->dev, 2349 "rx private waterline config cmd failed %d\n", 2350 ret); 2351 return ret; 2352 } 2353 2354 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2355 struct hclge_pkt_buf_alloc *buf_alloc) 2356 { 2357 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2358 struct hclge_rx_com_thrd *req; 2359 struct hclge_desc desc[2]; 2360 struct hclge_tc_thrd *tc; 2361 int i, j; 2362 int ret; 2363 2364 for (i = 0; i < 2; i++) { 2365 hclge_cmd_setup_basic_desc(&desc[i], 2366 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2367 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2368 2369 /* The first descriptor set the NEXT bit to 1 */ 2370 if (i == 0) 2371 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2372 else 2373 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2374 2375 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2376 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2377 2378 req->com_thrd[j].high = 2379 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2380 req->com_thrd[j].high |= 2381 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2382 req->com_thrd[j].low = 2383 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2384 req->com_thrd[j].low |= 2385 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2386 } 2387 } 2388 2389 /* Send 2 descriptors at one time */ 2390 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2391 if (ret) 2392 dev_err(&hdev->pdev->dev, 2393 "common threshold config cmd failed %d\n", ret); 2394 return ret; 2395 } 2396 2397 static int hclge_common_wl_config(struct hclge_dev *hdev, 2398 struct hclge_pkt_buf_alloc *buf_alloc) 2399 { 2400 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2401 struct hclge_rx_com_wl *req; 2402 struct hclge_desc desc; 2403 int ret; 2404 2405 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2406 2407 req = (struct hclge_rx_com_wl *)desc.data; 2408 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2409 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2410 2411 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2412 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2413 2414 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2415 if (ret) 2416 dev_err(&hdev->pdev->dev, 2417 "common waterline config cmd failed %d\n", ret); 2418 2419 return ret; 2420 } 2421 2422 int hclge_buffer_alloc(struct hclge_dev *hdev) 2423 { 2424 struct hclge_pkt_buf_alloc *pkt_buf; 2425 int ret; 2426 2427 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2428 if (!pkt_buf) 2429 return -ENOMEM; 2430 2431 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2432 if (ret) { 2433 dev_err(&hdev->pdev->dev, 2434 "could not calc tx buffer size for all TCs %d\n", ret); 2435 goto out; 2436 } 2437 2438 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2439 if (ret) { 2440 dev_err(&hdev->pdev->dev, 2441 "could not alloc tx buffers %d\n", ret); 2442 goto out; 2443 } 2444 2445 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2446 if (ret) { 2447 dev_err(&hdev->pdev->dev, 2448 "could not calc rx priv buffer size for all TCs %d\n", 2449 ret); 2450 goto out; 2451 } 2452 2453 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2454 if (ret) { 2455 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2456 ret); 2457 goto out; 2458 } 2459 2460 if (hnae3_dev_dcb_supported(hdev)) { 2461 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2462 if (ret) { 2463 dev_err(&hdev->pdev->dev, 2464 "could not configure rx private waterline %d\n", 2465 ret); 2466 goto out; 2467 } 2468 2469 ret = hclge_common_thrd_config(hdev, pkt_buf); 2470 if (ret) { 2471 dev_err(&hdev->pdev->dev, 2472 "could not configure common threshold %d\n", 2473 ret); 2474 goto out; 2475 } 2476 } 2477 2478 ret = hclge_common_wl_config(hdev, pkt_buf); 2479 if (ret) 2480 dev_err(&hdev->pdev->dev, 2481 "could not configure common waterline %d\n", ret); 2482 2483 out: 2484 kfree(pkt_buf); 2485 return ret; 2486 } 2487 2488 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2489 { 2490 struct hnae3_handle *roce = &vport->roce; 2491 struct hnae3_handle *nic = &vport->nic; 2492 struct hclge_dev *hdev = vport->back; 2493 2494 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2495 2496 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2497 return -EINVAL; 2498 2499 roce->rinfo.base_vector = hdev->num_nic_msi; 2500 2501 roce->rinfo.netdev = nic->kinfo.netdev; 2502 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2503 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2504 2505 roce->pdev = nic->pdev; 2506 roce->ae_algo = nic->ae_algo; 2507 roce->numa_node_mask = nic->numa_node_mask; 2508 2509 return 0; 2510 } 2511 2512 static int hclge_init_msi(struct hclge_dev *hdev) 2513 { 2514 struct pci_dev *pdev = hdev->pdev; 2515 int vectors; 2516 int i; 2517 2518 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2519 hdev->num_msi, 2520 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2521 if (vectors < 0) { 2522 dev_err(&pdev->dev, 2523 "failed(%d) to allocate MSI/MSI-X vectors\n", 2524 vectors); 2525 return vectors; 2526 } 2527 if (vectors < hdev->num_msi) 2528 dev_warn(&hdev->pdev->dev, 2529 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2530 hdev->num_msi, vectors); 2531 2532 hdev->num_msi = vectors; 2533 hdev->num_msi_left = vectors; 2534 2535 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2536 sizeof(u16), GFP_KERNEL); 2537 if (!hdev->vector_status) { 2538 pci_free_irq_vectors(pdev); 2539 return -ENOMEM; 2540 } 2541 2542 for (i = 0; i < hdev->num_msi; i++) 2543 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2544 2545 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2546 sizeof(int), GFP_KERNEL); 2547 if (!hdev->vector_irq) { 2548 pci_free_irq_vectors(pdev); 2549 return -ENOMEM; 2550 } 2551 2552 return 0; 2553 } 2554 2555 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2556 { 2557 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2558 duplex = HCLGE_MAC_FULL; 2559 2560 return duplex; 2561 } 2562 2563 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2564 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2565 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2566 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2567 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2568 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2569 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2570 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2571 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2572 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2573 }; 2574 2575 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2576 { 2577 u16 i; 2578 2579 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2580 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2581 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2582 return 0; 2583 } 2584 } 2585 2586 return -EINVAL; 2587 } 2588 2589 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2590 u8 duplex) 2591 { 2592 struct hclge_config_mac_speed_dup_cmd *req; 2593 struct hclge_desc desc; 2594 u32 speed_fw; 2595 int ret; 2596 2597 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2598 2599 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2600 2601 if (duplex) 2602 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2603 2604 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2605 if (ret) { 2606 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2607 return ret; 2608 } 2609 2610 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2611 speed_fw); 2612 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2613 1); 2614 2615 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2616 if (ret) { 2617 dev_err(&hdev->pdev->dev, 2618 "mac speed/duplex config cmd failed %d.\n", ret); 2619 return ret; 2620 } 2621 2622 return 0; 2623 } 2624 2625 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) 2626 { 2627 struct hclge_mac *mac = &hdev->hw.mac; 2628 int ret; 2629 2630 duplex = hclge_check_speed_dup(duplex, speed); 2631 if (!mac->support_autoneg && mac->speed == speed && 2632 mac->duplex == duplex) 2633 return 0; 2634 2635 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex); 2636 if (ret) 2637 return ret; 2638 2639 hdev->hw.mac.speed = speed; 2640 hdev->hw.mac.duplex = duplex; 2641 2642 return 0; 2643 } 2644 2645 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2646 u8 duplex) 2647 { 2648 struct hclge_vport *vport = hclge_get_vport(handle); 2649 struct hclge_dev *hdev = vport->back; 2650 2651 return hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2652 } 2653 2654 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2655 { 2656 struct hclge_config_auto_neg_cmd *req; 2657 struct hclge_desc desc; 2658 u32 flag = 0; 2659 int ret; 2660 2661 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2662 2663 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2664 if (enable) 2665 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2666 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2667 2668 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2669 if (ret) 2670 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2671 ret); 2672 2673 return ret; 2674 } 2675 2676 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2677 { 2678 struct hclge_vport *vport = hclge_get_vport(handle); 2679 struct hclge_dev *hdev = vport->back; 2680 2681 if (!hdev->hw.mac.support_autoneg) { 2682 if (enable) { 2683 dev_err(&hdev->pdev->dev, 2684 "autoneg is not supported by current port\n"); 2685 return -EOPNOTSUPP; 2686 } else { 2687 return 0; 2688 } 2689 } 2690 2691 return hclge_set_autoneg_en(hdev, enable); 2692 } 2693 2694 static int hclge_get_autoneg(struct hnae3_handle *handle) 2695 { 2696 struct hclge_vport *vport = hclge_get_vport(handle); 2697 struct hclge_dev *hdev = vport->back; 2698 struct phy_device *phydev = hdev->hw.mac.phydev; 2699 2700 if (phydev) 2701 return phydev->autoneg; 2702 2703 return hdev->hw.mac.autoneg; 2704 } 2705 2706 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2707 { 2708 struct hclge_vport *vport = hclge_get_vport(handle); 2709 struct hclge_dev *hdev = vport->back; 2710 int ret; 2711 2712 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2713 2714 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2715 if (ret) 2716 return ret; 2717 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2718 } 2719 2720 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2721 { 2722 struct hclge_vport *vport = hclge_get_vport(handle); 2723 struct hclge_dev *hdev = vport->back; 2724 2725 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2726 return hclge_set_autoneg_en(hdev, !halt); 2727 2728 return 0; 2729 } 2730 2731 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2732 { 2733 struct hclge_config_fec_cmd *req; 2734 struct hclge_desc desc; 2735 int ret; 2736 2737 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2738 2739 req = (struct hclge_config_fec_cmd *)desc.data; 2740 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2741 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2742 if (fec_mode & BIT(HNAE3_FEC_RS)) 2743 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2744 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2745 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2746 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2747 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2748 2749 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2750 if (ret) 2751 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2752 2753 return ret; 2754 } 2755 2756 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2757 { 2758 struct hclge_vport *vport = hclge_get_vport(handle); 2759 struct hclge_dev *hdev = vport->back; 2760 struct hclge_mac *mac = &hdev->hw.mac; 2761 int ret; 2762 2763 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2764 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2765 return -EINVAL; 2766 } 2767 2768 ret = hclge_set_fec_hw(hdev, fec_mode); 2769 if (ret) 2770 return ret; 2771 2772 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2773 return 0; 2774 } 2775 2776 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2777 u8 *fec_mode) 2778 { 2779 struct hclge_vport *vport = hclge_get_vport(handle); 2780 struct hclge_dev *hdev = vport->back; 2781 struct hclge_mac *mac = &hdev->hw.mac; 2782 2783 if (fec_ability) 2784 *fec_ability = mac->fec_ability; 2785 if (fec_mode) 2786 *fec_mode = mac->fec_mode; 2787 } 2788 2789 static int hclge_mac_init(struct hclge_dev *hdev) 2790 { 2791 struct hclge_mac *mac = &hdev->hw.mac; 2792 int ret; 2793 2794 hdev->support_sfp_query = true; 2795 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2796 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2797 hdev->hw.mac.duplex); 2798 if (ret) 2799 return ret; 2800 2801 if (hdev->hw.mac.support_autoneg) { 2802 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2803 if (ret) 2804 return ret; 2805 } 2806 2807 mac->link = 0; 2808 2809 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2810 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2811 if (ret) 2812 return ret; 2813 } 2814 2815 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2816 if (ret) { 2817 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2818 return ret; 2819 } 2820 2821 ret = hclge_set_default_loopback(hdev); 2822 if (ret) 2823 return ret; 2824 2825 ret = hclge_buffer_alloc(hdev); 2826 if (ret) 2827 dev_err(&hdev->pdev->dev, 2828 "allocate buffer fail, ret=%d\n", ret); 2829 2830 return ret; 2831 } 2832 2833 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2834 { 2835 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2836 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2837 hdev->last_mbx_scheduled = jiffies; 2838 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2839 } 2840 } 2841 2842 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2843 { 2844 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2845 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2846 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2847 hdev->last_rst_scheduled = jiffies; 2848 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2849 } 2850 } 2851 2852 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2853 { 2854 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2855 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2856 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2857 } 2858 2859 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2860 { 2861 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2862 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2863 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2864 } 2865 2866 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2867 { 2868 struct hclge_link_status_cmd *req; 2869 struct hclge_desc desc; 2870 int ret; 2871 2872 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2873 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2874 if (ret) { 2875 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2876 ret); 2877 return ret; 2878 } 2879 2880 req = (struct hclge_link_status_cmd *)desc.data; 2881 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 2882 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 2883 2884 return 0; 2885 } 2886 2887 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 2888 { 2889 struct phy_device *phydev = hdev->hw.mac.phydev; 2890 2891 *link_status = HCLGE_LINK_STATUS_DOWN; 2892 2893 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 2894 return 0; 2895 2896 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 2897 return 0; 2898 2899 return hclge_get_mac_link_status(hdev, link_status); 2900 } 2901 2902 static void hclge_push_link_status(struct hclge_dev *hdev) 2903 { 2904 struct hclge_vport *vport; 2905 int ret; 2906 u16 i; 2907 2908 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 2909 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 2910 2911 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 2912 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 2913 continue; 2914 2915 ret = hclge_push_vf_link_status(vport); 2916 if (ret) { 2917 dev_err(&hdev->pdev->dev, 2918 "failed to push link status to vf%u, ret = %d\n", 2919 i, ret); 2920 } 2921 } 2922 } 2923 2924 static void hclge_update_link_status(struct hclge_dev *hdev) 2925 { 2926 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 2927 struct hnae3_handle *handle = &hdev->vport[0].nic; 2928 struct hnae3_client *rclient = hdev->roce_client; 2929 struct hnae3_client *client = hdev->nic_client; 2930 int state; 2931 int ret; 2932 2933 if (!client) 2934 return; 2935 2936 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 2937 return; 2938 2939 ret = hclge_get_mac_phy_link(hdev, &state); 2940 if (ret) { 2941 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 2942 return; 2943 } 2944 2945 if (state != hdev->hw.mac.link) { 2946 hdev->hw.mac.link = state; 2947 client->ops->link_status_change(handle, state); 2948 hclge_config_mac_tnl_int(hdev, state); 2949 if (rclient && rclient->ops->link_status_change) 2950 rclient->ops->link_status_change(rhandle, state); 2951 2952 hclge_push_link_status(hdev); 2953 } 2954 2955 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 2956 } 2957 2958 static void hclge_update_speed_advertising(struct hclge_mac *mac) 2959 { 2960 u32 speed_ability; 2961 2962 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 2963 return; 2964 2965 switch (mac->module_type) { 2966 case HNAE3_MODULE_TYPE_FIBRE_LR: 2967 hclge_convert_setting_lr(speed_ability, mac->advertising); 2968 break; 2969 case HNAE3_MODULE_TYPE_FIBRE_SR: 2970 case HNAE3_MODULE_TYPE_AOC: 2971 hclge_convert_setting_sr(speed_ability, mac->advertising); 2972 break; 2973 case HNAE3_MODULE_TYPE_CR: 2974 hclge_convert_setting_cr(speed_ability, mac->advertising); 2975 break; 2976 case HNAE3_MODULE_TYPE_KR: 2977 hclge_convert_setting_kr(speed_ability, mac->advertising); 2978 break; 2979 default: 2980 break; 2981 } 2982 } 2983 2984 static void hclge_update_fec_advertising(struct hclge_mac *mac) 2985 { 2986 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 2987 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2988 mac->advertising); 2989 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 2990 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2991 mac->advertising); 2992 else 2993 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2994 mac->advertising); 2995 } 2996 2997 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 2998 { 2999 struct hclge_mac *mac = &hdev->hw.mac; 3000 bool rx_en, tx_en; 3001 3002 switch (hdev->fc_mode_last_time) { 3003 case HCLGE_FC_RX_PAUSE: 3004 rx_en = true; 3005 tx_en = false; 3006 break; 3007 case HCLGE_FC_TX_PAUSE: 3008 rx_en = false; 3009 tx_en = true; 3010 break; 3011 case HCLGE_FC_FULL: 3012 rx_en = true; 3013 tx_en = true; 3014 break; 3015 default: 3016 rx_en = false; 3017 tx_en = false; 3018 break; 3019 } 3020 3021 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3022 } 3023 3024 static void hclge_update_advertising(struct hclge_dev *hdev) 3025 { 3026 struct hclge_mac *mac = &hdev->hw.mac; 3027 3028 linkmode_zero(mac->advertising); 3029 hclge_update_speed_advertising(mac); 3030 hclge_update_fec_advertising(mac); 3031 hclge_update_pause_advertising(hdev); 3032 } 3033 3034 static void hclge_update_port_capability(struct hclge_dev *hdev, 3035 struct hclge_mac *mac) 3036 { 3037 if (hnae3_dev_fec_supported(hdev)) 3038 /* update fec ability by speed */ 3039 hclge_convert_setting_fec(mac); 3040 3041 /* firmware can not identify back plane type, the media type 3042 * read from configuration can help deal it 3043 */ 3044 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3045 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3046 mac->module_type = HNAE3_MODULE_TYPE_KR; 3047 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3048 mac->module_type = HNAE3_MODULE_TYPE_TP; 3049 3050 if (mac->support_autoneg) { 3051 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3052 linkmode_copy(mac->advertising, mac->supported); 3053 } else { 3054 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3055 mac->supported); 3056 hclge_update_advertising(hdev); 3057 } 3058 } 3059 3060 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3061 { 3062 struct hclge_sfp_info_cmd *resp; 3063 struct hclge_desc desc; 3064 int ret; 3065 3066 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3067 resp = (struct hclge_sfp_info_cmd *)desc.data; 3068 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3069 if (ret == -EOPNOTSUPP) { 3070 dev_warn(&hdev->pdev->dev, 3071 "IMP do not support get SFP speed %d\n", ret); 3072 return ret; 3073 } else if (ret) { 3074 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3075 return ret; 3076 } 3077 3078 *speed = le32_to_cpu(resp->speed); 3079 3080 return 0; 3081 } 3082 3083 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3084 { 3085 struct hclge_sfp_info_cmd *resp; 3086 struct hclge_desc desc; 3087 int ret; 3088 3089 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3090 resp = (struct hclge_sfp_info_cmd *)desc.data; 3091 3092 resp->query_type = QUERY_ACTIVE_SPEED; 3093 3094 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3095 if (ret == -EOPNOTSUPP) { 3096 dev_warn(&hdev->pdev->dev, 3097 "IMP does not support get SFP info %d\n", ret); 3098 return ret; 3099 } else if (ret) { 3100 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3101 return ret; 3102 } 3103 3104 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3105 * set to mac->speed. 3106 */ 3107 if (!le32_to_cpu(resp->speed)) 3108 return 0; 3109 3110 mac->speed = le32_to_cpu(resp->speed); 3111 /* if resp->speed_ability is 0, it means it's an old version 3112 * firmware, do not update these params 3113 */ 3114 if (resp->speed_ability) { 3115 mac->module_type = le32_to_cpu(resp->module_type); 3116 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3117 mac->autoneg = resp->autoneg; 3118 mac->support_autoneg = resp->autoneg_ability; 3119 mac->speed_type = QUERY_ACTIVE_SPEED; 3120 if (!resp->active_fec) 3121 mac->fec_mode = 0; 3122 else 3123 mac->fec_mode = BIT(resp->active_fec); 3124 } else { 3125 mac->speed_type = QUERY_SFP_SPEED; 3126 } 3127 3128 return 0; 3129 } 3130 3131 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3132 struct ethtool_link_ksettings *cmd) 3133 { 3134 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3135 struct hclge_vport *vport = hclge_get_vport(handle); 3136 struct hclge_phy_link_ksetting_0_cmd *req0; 3137 struct hclge_phy_link_ksetting_1_cmd *req1; 3138 u32 supported, advertising, lp_advertising; 3139 struct hclge_dev *hdev = vport->back; 3140 int ret; 3141 3142 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3143 true); 3144 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3145 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3146 true); 3147 3148 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3149 if (ret) { 3150 dev_err(&hdev->pdev->dev, 3151 "failed to get phy link ksetting, ret = %d.\n", ret); 3152 return ret; 3153 } 3154 3155 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3156 cmd->base.autoneg = req0->autoneg; 3157 cmd->base.speed = le32_to_cpu(req0->speed); 3158 cmd->base.duplex = req0->duplex; 3159 cmd->base.port = req0->port; 3160 cmd->base.transceiver = req0->transceiver; 3161 cmd->base.phy_address = req0->phy_address; 3162 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3163 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3164 supported = le32_to_cpu(req0->supported); 3165 advertising = le32_to_cpu(req0->advertising); 3166 lp_advertising = le32_to_cpu(req0->lp_advertising); 3167 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3168 supported); 3169 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3170 advertising); 3171 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3172 lp_advertising); 3173 3174 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3175 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3176 cmd->base.master_slave_state = req1->master_slave_state; 3177 3178 return 0; 3179 } 3180 3181 static int 3182 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3183 const struct ethtool_link_ksettings *cmd) 3184 { 3185 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3186 struct hclge_vport *vport = hclge_get_vport(handle); 3187 struct hclge_phy_link_ksetting_0_cmd *req0; 3188 struct hclge_phy_link_ksetting_1_cmd *req1; 3189 struct hclge_dev *hdev = vport->back; 3190 u32 advertising; 3191 int ret; 3192 3193 if (cmd->base.autoneg == AUTONEG_DISABLE && 3194 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3195 (cmd->base.duplex != DUPLEX_HALF && 3196 cmd->base.duplex != DUPLEX_FULL))) 3197 return -EINVAL; 3198 3199 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3200 false); 3201 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3202 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3203 false); 3204 3205 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3206 req0->autoneg = cmd->base.autoneg; 3207 req0->speed = cpu_to_le32(cmd->base.speed); 3208 req0->duplex = cmd->base.duplex; 3209 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3210 cmd->link_modes.advertising); 3211 req0->advertising = cpu_to_le32(advertising); 3212 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3213 3214 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3215 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3216 3217 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3218 if (ret) { 3219 dev_err(&hdev->pdev->dev, 3220 "failed to set phy link ksettings, ret = %d.\n", ret); 3221 return ret; 3222 } 3223 3224 hdev->hw.mac.autoneg = cmd->base.autoneg; 3225 hdev->hw.mac.speed = cmd->base.speed; 3226 hdev->hw.mac.duplex = cmd->base.duplex; 3227 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3228 3229 return 0; 3230 } 3231 3232 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3233 { 3234 struct ethtool_link_ksettings cmd; 3235 int ret; 3236 3237 if (!hnae3_dev_phy_imp_supported(hdev)) 3238 return 0; 3239 3240 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3241 if (ret) 3242 return ret; 3243 3244 hdev->hw.mac.autoneg = cmd.base.autoneg; 3245 hdev->hw.mac.speed = cmd.base.speed; 3246 hdev->hw.mac.duplex = cmd.base.duplex; 3247 3248 return 0; 3249 } 3250 3251 static int hclge_tp_port_init(struct hclge_dev *hdev) 3252 { 3253 struct ethtool_link_ksettings cmd; 3254 3255 if (!hnae3_dev_phy_imp_supported(hdev)) 3256 return 0; 3257 3258 cmd.base.autoneg = hdev->hw.mac.autoneg; 3259 cmd.base.speed = hdev->hw.mac.speed; 3260 cmd.base.duplex = hdev->hw.mac.duplex; 3261 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3262 3263 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3264 } 3265 3266 static int hclge_update_port_info(struct hclge_dev *hdev) 3267 { 3268 struct hclge_mac *mac = &hdev->hw.mac; 3269 int speed = HCLGE_MAC_SPEED_UNKNOWN; 3270 int ret; 3271 3272 /* get the port info from SFP cmd if not copper port */ 3273 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3274 return hclge_update_tp_port_info(hdev); 3275 3276 /* if IMP does not support get SFP/qSFP info, return directly */ 3277 if (!hdev->support_sfp_query) 3278 return 0; 3279 3280 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 3281 ret = hclge_get_sfp_info(hdev, mac); 3282 else 3283 ret = hclge_get_sfp_speed(hdev, &speed); 3284 3285 if (ret == -EOPNOTSUPP) { 3286 hdev->support_sfp_query = false; 3287 return ret; 3288 } else if (ret) { 3289 return ret; 3290 } 3291 3292 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3293 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3294 hclge_update_port_capability(hdev, mac); 3295 return 0; 3296 } 3297 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3298 HCLGE_MAC_FULL); 3299 } else { 3300 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3301 return 0; /* do nothing if no SFP */ 3302 3303 /* must config full duplex for SFP */ 3304 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL); 3305 } 3306 } 3307 3308 static int hclge_get_status(struct hnae3_handle *handle) 3309 { 3310 struct hclge_vport *vport = hclge_get_vport(handle); 3311 struct hclge_dev *hdev = vport->back; 3312 3313 hclge_update_link_status(hdev); 3314 3315 return hdev->hw.mac.link; 3316 } 3317 3318 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3319 { 3320 if (!pci_num_vf(hdev->pdev)) { 3321 dev_err(&hdev->pdev->dev, 3322 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3323 return NULL; 3324 } 3325 3326 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3327 dev_err(&hdev->pdev->dev, 3328 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3329 vf, pci_num_vf(hdev->pdev)); 3330 return NULL; 3331 } 3332 3333 /* VF start from 1 in vport */ 3334 vf += HCLGE_VF_VPORT_START_NUM; 3335 return &hdev->vport[vf]; 3336 } 3337 3338 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3339 struct ifla_vf_info *ivf) 3340 { 3341 struct hclge_vport *vport = hclge_get_vport(handle); 3342 struct hclge_dev *hdev = vport->back; 3343 3344 vport = hclge_get_vf_vport(hdev, vf); 3345 if (!vport) 3346 return -EINVAL; 3347 3348 ivf->vf = vf; 3349 ivf->linkstate = vport->vf_info.link_state; 3350 ivf->spoofchk = vport->vf_info.spoofchk; 3351 ivf->trusted = vport->vf_info.trusted; 3352 ivf->min_tx_rate = 0; 3353 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3354 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3355 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3356 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3357 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3358 3359 return 0; 3360 } 3361 3362 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3363 int link_state) 3364 { 3365 struct hclge_vport *vport = hclge_get_vport(handle); 3366 struct hclge_dev *hdev = vport->back; 3367 int link_state_old; 3368 int ret; 3369 3370 vport = hclge_get_vf_vport(hdev, vf); 3371 if (!vport) 3372 return -EINVAL; 3373 3374 link_state_old = vport->vf_info.link_state; 3375 vport->vf_info.link_state = link_state; 3376 3377 ret = hclge_push_vf_link_status(vport); 3378 if (ret) { 3379 vport->vf_info.link_state = link_state_old; 3380 dev_err(&hdev->pdev->dev, 3381 "failed to push vf%d link status, ret = %d\n", vf, ret); 3382 } 3383 3384 return ret; 3385 } 3386 3387 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3388 { 3389 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3390 3391 /* fetch the events from their corresponding regs */ 3392 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3393 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3394 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3395 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3396 3397 /* Assumption: If by any chance reset and mailbox events are reported 3398 * together then we will only process reset event in this go and will 3399 * defer the processing of the mailbox events. Since, we would have not 3400 * cleared RX CMDQ event this time we would receive again another 3401 * interrupt from H/W just for the mailbox. 3402 * 3403 * check for vector0 reset event sources 3404 */ 3405 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3406 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3407 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3408 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3409 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3410 hdev->rst_stats.imp_rst_cnt++; 3411 return HCLGE_VECTOR0_EVENT_RST; 3412 } 3413 3414 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3415 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3416 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3417 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3418 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3419 hdev->rst_stats.global_rst_cnt++; 3420 return HCLGE_VECTOR0_EVENT_RST; 3421 } 3422 3423 /* check for vector0 msix event and hardware error event source */ 3424 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3425 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3426 return HCLGE_VECTOR0_EVENT_ERR; 3427 3428 /* check for vector0 ptp event source */ 3429 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3430 *clearval = msix_src_reg; 3431 return HCLGE_VECTOR0_EVENT_PTP; 3432 } 3433 3434 /* check for vector0 mailbox(=CMDQ RX) event source */ 3435 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3436 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3437 *clearval = cmdq_src_reg; 3438 return HCLGE_VECTOR0_EVENT_MBX; 3439 } 3440 3441 /* print other vector0 event source */ 3442 dev_info(&hdev->pdev->dev, 3443 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3444 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3445 3446 return HCLGE_VECTOR0_EVENT_OTHER; 3447 } 3448 3449 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3450 u32 regclr) 3451 { 3452 switch (event_type) { 3453 case HCLGE_VECTOR0_EVENT_PTP: 3454 case HCLGE_VECTOR0_EVENT_RST: 3455 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3456 break; 3457 case HCLGE_VECTOR0_EVENT_MBX: 3458 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3459 break; 3460 default: 3461 break; 3462 } 3463 } 3464 3465 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3466 { 3467 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3468 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3469 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3470 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3471 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3472 } 3473 3474 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3475 { 3476 writel(enable ? 1 : 0, vector->addr); 3477 } 3478 3479 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3480 { 3481 struct hclge_dev *hdev = data; 3482 unsigned long flags; 3483 u32 clearval = 0; 3484 u32 event_cause; 3485 3486 hclge_enable_vector(&hdev->misc_vector, false); 3487 event_cause = hclge_check_event_cause(hdev, &clearval); 3488 3489 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3490 switch (event_cause) { 3491 case HCLGE_VECTOR0_EVENT_ERR: 3492 hclge_errhand_task_schedule(hdev); 3493 break; 3494 case HCLGE_VECTOR0_EVENT_RST: 3495 hclge_reset_task_schedule(hdev); 3496 break; 3497 case HCLGE_VECTOR0_EVENT_PTP: 3498 spin_lock_irqsave(&hdev->ptp->lock, flags); 3499 hclge_ptp_clean_tx_hwts(hdev); 3500 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3501 break; 3502 case HCLGE_VECTOR0_EVENT_MBX: 3503 /* If we are here then, 3504 * 1. Either we are not handling any mbx task and we are not 3505 * scheduled as well 3506 * OR 3507 * 2. We could be handling a mbx task but nothing more is 3508 * scheduled. 3509 * In both cases, we should schedule mbx task as there are more 3510 * mbx messages reported by this interrupt. 3511 */ 3512 hclge_mbx_task_schedule(hdev); 3513 break; 3514 default: 3515 dev_warn(&hdev->pdev->dev, 3516 "received unknown or unhandled event of vector0\n"); 3517 break; 3518 } 3519 3520 hclge_clear_event_cause(hdev, event_cause, clearval); 3521 3522 /* Enable interrupt if it is not caused by reset event or error event */ 3523 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3524 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3525 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3526 hclge_enable_vector(&hdev->misc_vector, true); 3527 3528 return IRQ_HANDLED; 3529 } 3530 3531 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3532 { 3533 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3534 dev_warn(&hdev->pdev->dev, 3535 "vector(vector_id %d) has been freed.\n", vector_id); 3536 return; 3537 } 3538 3539 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3540 hdev->num_msi_left += 1; 3541 hdev->num_msi_used -= 1; 3542 } 3543 3544 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3545 { 3546 struct hclge_misc_vector *vector = &hdev->misc_vector; 3547 3548 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3549 3550 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3551 hdev->vector_status[0] = 0; 3552 3553 hdev->num_msi_left -= 1; 3554 hdev->num_msi_used += 1; 3555 } 3556 3557 static void hclge_misc_affinity_setup(struct hclge_dev *hdev) 3558 { 3559 irq_set_affinity_hint(hdev->misc_vector.vector_irq, 3560 &hdev->affinity_mask); 3561 } 3562 3563 static void hclge_misc_affinity_teardown(struct hclge_dev *hdev) 3564 { 3565 irq_set_affinity_hint(hdev->misc_vector.vector_irq, NULL); 3566 } 3567 3568 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3569 { 3570 int ret; 3571 3572 hclge_get_misc_vector(hdev); 3573 3574 /* this would be explicitly freed in the end */ 3575 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3576 HCLGE_NAME, pci_name(hdev->pdev)); 3577 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3578 0, hdev->misc_vector.name, hdev); 3579 if (ret) { 3580 hclge_free_vector(hdev, 0); 3581 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3582 hdev->misc_vector.vector_irq); 3583 } 3584 3585 return ret; 3586 } 3587 3588 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3589 { 3590 free_irq(hdev->misc_vector.vector_irq, hdev); 3591 hclge_free_vector(hdev, 0); 3592 } 3593 3594 int hclge_notify_client(struct hclge_dev *hdev, 3595 enum hnae3_reset_notify_type type) 3596 { 3597 struct hnae3_handle *handle = &hdev->vport[0].nic; 3598 struct hnae3_client *client = hdev->nic_client; 3599 int ret; 3600 3601 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3602 return 0; 3603 3604 if (!client->ops->reset_notify) 3605 return -EOPNOTSUPP; 3606 3607 ret = client->ops->reset_notify(handle, type); 3608 if (ret) 3609 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3610 type, ret); 3611 3612 return ret; 3613 } 3614 3615 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3616 enum hnae3_reset_notify_type type) 3617 { 3618 struct hnae3_handle *handle = &hdev->vport[0].roce; 3619 struct hnae3_client *client = hdev->roce_client; 3620 int ret; 3621 3622 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3623 return 0; 3624 3625 if (!client->ops->reset_notify) 3626 return -EOPNOTSUPP; 3627 3628 ret = client->ops->reset_notify(handle, type); 3629 if (ret) 3630 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3631 type, ret); 3632 3633 return ret; 3634 } 3635 3636 static int hclge_reset_wait(struct hclge_dev *hdev) 3637 { 3638 #define HCLGE_RESET_WATI_MS 100 3639 #define HCLGE_RESET_WAIT_CNT 350 3640 3641 u32 val, reg, reg_bit; 3642 u32 cnt = 0; 3643 3644 switch (hdev->reset_type) { 3645 case HNAE3_IMP_RESET: 3646 reg = HCLGE_GLOBAL_RESET_REG; 3647 reg_bit = HCLGE_IMP_RESET_BIT; 3648 break; 3649 case HNAE3_GLOBAL_RESET: 3650 reg = HCLGE_GLOBAL_RESET_REG; 3651 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3652 break; 3653 case HNAE3_FUNC_RESET: 3654 reg = HCLGE_FUN_RST_ING; 3655 reg_bit = HCLGE_FUN_RST_ING_B; 3656 break; 3657 default: 3658 dev_err(&hdev->pdev->dev, 3659 "Wait for unsupported reset type: %d\n", 3660 hdev->reset_type); 3661 return -EINVAL; 3662 } 3663 3664 val = hclge_read_dev(&hdev->hw, reg); 3665 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3666 msleep(HCLGE_RESET_WATI_MS); 3667 val = hclge_read_dev(&hdev->hw, reg); 3668 cnt++; 3669 } 3670 3671 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3672 dev_warn(&hdev->pdev->dev, 3673 "Wait for reset timeout: %d\n", hdev->reset_type); 3674 return -EBUSY; 3675 } 3676 3677 return 0; 3678 } 3679 3680 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3681 { 3682 struct hclge_vf_rst_cmd *req; 3683 struct hclge_desc desc; 3684 3685 req = (struct hclge_vf_rst_cmd *)desc.data; 3686 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3687 req->dest_vfid = func_id; 3688 3689 if (reset) 3690 req->vf_rst = 0x1; 3691 3692 return hclge_cmd_send(&hdev->hw, &desc, 1); 3693 } 3694 3695 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3696 { 3697 int i; 3698 3699 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3700 struct hclge_vport *vport = &hdev->vport[i]; 3701 int ret; 3702 3703 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3704 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3705 if (ret) { 3706 dev_err(&hdev->pdev->dev, 3707 "set vf(%u) rst failed %d!\n", 3708 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3709 ret); 3710 return ret; 3711 } 3712 3713 if (!reset || !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3714 continue; 3715 3716 /* Inform VF to process the reset. 3717 * hclge_inform_reset_assert_to_vf may fail if VF 3718 * driver is not loaded. 3719 */ 3720 ret = hclge_inform_reset_assert_to_vf(vport); 3721 if (ret) 3722 dev_warn(&hdev->pdev->dev, 3723 "inform reset to vf(%u) failed %d!\n", 3724 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3725 ret); 3726 } 3727 3728 return 0; 3729 } 3730 3731 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3732 { 3733 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3734 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3735 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3736 return; 3737 3738 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3739 HCLGE_MBX_SCHED_TIMEOUT)) 3740 dev_warn(&hdev->pdev->dev, 3741 "mbx service task is scheduled after %ums on cpu%u!\n", 3742 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3743 smp_processor_id()); 3744 3745 hclge_mbx_handler(hdev); 3746 3747 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3748 } 3749 3750 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3751 { 3752 struct hclge_pf_rst_sync_cmd *req; 3753 struct hclge_desc desc; 3754 int cnt = 0; 3755 int ret; 3756 3757 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3758 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3759 3760 do { 3761 /* vf need to down netdev by mbx during PF or FLR reset */ 3762 hclge_mailbox_service_task(hdev); 3763 3764 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3765 /* for compatible with old firmware, wait 3766 * 100 ms for VF to stop IO 3767 */ 3768 if (ret == -EOPNOTSUPP) { 3769 msleep(HCLGE_RESET_SYNC_TIME); 3770 return; 3771 } else if (ret) { 3772 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3773 ret); 3774 return; 3775 } else if (req->all_vf_ready) { 3776 return; 3777 } 3778 msleep(HCLGE_PF_RESET_SYNC_TIME); 3779 hclge_comm_cmd_reuse_desc(&desc, true); 3780 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3781 3782 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3783 } 3784 3785 void hclge_report_hw_error(struct hclge_dev *hdev, 3786 enum hnae3_hw_error_type type) 3787 { 3788 struct hnae3_client *client = hdev->nic_client; 3789 3790 if (!client || !client->ops->process_hw_error || 3791 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3792 return; 3793 3794 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3795 } 3796 3797 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3798 { 3799 u32 reg_val; 3800 3801 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3802 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3803 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3804 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3805 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3806 } 3807 3808 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3809 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3810 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 3811 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3812 } 3813 } 3814 3815 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 3816 { 3817 struct hclge_desc desc; 3818 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 3819 int ret; 3820 3821 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 3822 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 3823 req->fun_reset_vfid = func_id; 3824 3825 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3826 if (ret) 3827 dev_err(&hdev->pdev->dev, 3828 "send function reset cmd fail, status =%d\n", ret); 3829 3830 return ret; 3831 } 3832 3833 static void hclge_do_reset(struct hclge_dev *hdev) 3834 { 3835 struct hnae3_handle *handle = &hdev->vport[0].nic; 3836 struct pci_dev *pdev = hdev->pdev; 3837 u32 val; 3838 3839 if (hclge_get_hw_reset_stat(handle)) { 3840 dev_info(&pdev->dev, "hardware reset not finish\n"); 3841 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 3842 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 3843 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 3844 return; 3845 } 3846 3847 switch (hdev->reset_type) { 3848 case HNAE3_IMP_RESET: 3849 dev_info(&pdev->dev, "IMP reset requested\n"); 3850 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3851 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 3852 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 3853 break; 3854 case HNAE3_GLOBAL_RESET: 3855 dev_info(&pdev->dev, "global reset requested\n"); 3856 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 3857 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 3858 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 3859 break; 3860 case HNAE3_FUNC_RESET: 3861 dev_info(&pdev->dev, "PF reset requested\n"); 3862 /* schedule again to check later */ 3863 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 3864 hclge_reset_task_schedule(hdev); 3865 break; 3866 default: 3867 dev_warn(&pdev->dev, 3868 "unsupported reset type: %d\n", hdev->reset_type); 3869 break; 3870 } 3871 } 3872 3873 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 3874 unsigned long *addr) 3875 { 3876 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 3877 struct hclge_dev *hdev = ae_dev->priv; 3878 3879 /* return the highest priority reset level amongst all */ 3880 if (test_bit(HNAE3_IMP_RESET, addr)) { 3881 rst_level = HNAE3_IMP_RESET; 3882 clear_bit(HNAE3_IMP_RESET, addr); 3883 clear_bit(HNAE3_GLOBAL_RESET, addr); 3884 clear_bit(HNAE3_FUNC_RESET, addr); 3885 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 3886 rst_level = HNAE3_GLOBAL_RESET; 3887 clear_bit(HNAE3_GLOBAL_RESET, addr); 3888 clear_bit(HNAE3_FUNC_RESET, addr); 3889 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 3890 rst_level = HNAE3_FUNC_RESET; 3891 clear_bit(HNAE3_FUNC_RESET, addr); 3892 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 3893 rst_level = HNAE3_FLR_RESET; 3894 clear_bit(HNAE3_FLR_RESET, addr); 3895 } 3896 3897 if (hdev->reset_type != HNAE3_NONE_RESET && 3898 rst_level < hdev->reset_type) 3899 return HNAE3_NONE_RESET; 3900 3901 return rst_level; 3902 } 3903 3904 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 3905 { 3906 u32 clearval = 0; 3907 3908 switch (hdev->reset_type) { 3909 case HNAE3_IMP_RESET: 3910 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3911 break; 3912 case HNAE3_GLOBAL_RESET: 3913 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3914 break; 3915 default: 3916 break; 3917 } 3918 3919 if (!clearval) 3920 return; 3921 3922 /* For revision 0x20, the reset interrupt source 3923 * can only be cleared after hardware reset done 3924 */ 3925 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 3926 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 3927 clearval); 3928 3929 hclge_enable_vector(&hdev->misc_vector, true); 3930 } 3931 3932 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 3933 { 3934 u32 reg_val; 3935 3936 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 3937 if (enable) 3938 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 3939 else 3940 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 3941 3942 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 3943 } 3944 3945 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 3946 { 3947 int ret; 3948 3949 ret = hclge_set_all_vf_rst(hdev, true); 3950 if (ret) 3951 return ret; 3952 3953 hclge_func_reset_sync_vf(hdev); 3954 3955 return 0; 3956 } 3957 3958 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 3959 { 3960 u32 reg_val; 3961 int ret = 0; 3962 3963 switch (hdev->reset_type) { 3964 case HNAE3_FUNC_RESET: 3965 ret = hclge_func_reset_notify_vf(hdev); 3966 if (ret) 3967 return ret; 3968 3969 ret = hclge_func_reset_cmd(hdev, 0); 3970 if (ret) { 3971 dev_err(&hdev->pdev->dev, 3972 "asserting function reset fail %d!\n", ret); 3973 return ret; 3974 } 3975 3976 /* After performaning pf reset, it is not necessary to do the 3977 * mailbox handling or send any command to firmware, because 3978 * any mailbox handling or command to firmware is only valid 3979 * after hclge_comm_cmd_init is called. 3980 */ 3981 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3982 hdev->rst_stats.pf_rst_cnt++; 3983 break; 3984 case HNAE3_FLR_RESET: 3985 ret = hclge_func_reset_notify_vf(hdev); 3986 if (ret) 3987 return ret; 3988 break; 3989 case HNAE3_IMP_RESET: 3990 hclge_handle_imp_error(hdev); 3991 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3992 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 3993 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 3994 break; 3995 default: 3996 break; 3997 } 3998 3999 /* inform hardware that preparatory work is done */ 4000 msleep(HCLGE_RESET_SYNC_TIME); 4001 hclge_reset_handshake(hdev, true); 4002 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4003 4004 return ret; 4005 } 4006 4007 static void hclge_show_rst_info(struct hclge_dev *hdev) 4008 { 4009 char *buf; 4010 4011 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4012 if (!buf) 4013 return; 4014 4015 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4016 4017 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4018 4019 kfree(buf); 4020 } 4021 4022 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4023 { 4024 #define MAX_RESET_FAIL_CNT 5 4025 4026 if (hdev->reset_pending) { 4027 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4028 hdev->reset_pending); 4029 return true; 4030 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4031 HCLGE_RESET_INT_M) { 4032 dev_info(&hdev->pdev->dev, 4033 "reset failed because new reset interrupt\n"); 4034 hclge_clear_reset_cause(hdev); 4035 return false; 4036 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4037 hdev->rst_stats.reset_fail_cnt++; 4038 set_bit(hdev->reset_type, &hdev->reset_pending); 4039 dev_info(&hdev->pdev->dev, 4040 "re-schedule reset task(%u)\n", 4041 hdev->rst_stats.reset_fail_cnt); 4042 return true; 4043 } 4044 4045 hclge_clear_reset_cause(hdev); 4046 4047 /* recover the handshake status when reset fail */ 4048 hclge_reset_handshake(hdev, true); 4049 4050 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4051 4052 hclge_show_rst_info(hdev); 4053 4054 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4055 4056 return false; 4057 } 4058 4059 static void hclge_update_reset_level(struct hclge_dev *hdev) 4060 { 4061 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4062 enum hnae3_reset_type reset_level; 4063 4064 /* reset request will not be set during reset, so clear 4065 * pending reset request to avoid unnecessary reset 4066 * caused by the same reason. 4067 */ 4068 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4069 4070 /* if default_reset_request has a higher level reset request, 4071 * it should be handled as soon as possible. since some errors 4072 * need this kind of reset to fix. 4073 */ 4074 reset_level = hclge_get_reset_level(ae_dev, 4075 &hdev->default_reset_request); 4076 if (reset_level != HNAE3_NONE_RESET) 4077 set_bit(reset_level, &hdev->reset_request); 4078 } 4079 4080 static int hclge_set_rst_done(struct hclge_dev *hdev) 4081 { 4082 struct hclge_pf_rst_done_cmd *req; 4083 struct hclge_desc desc; 4084 int ret; 4085 4086 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4087 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4088 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4089 4090 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4091 /* To be compatible with the old firmware, which does not support 4092 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4093 * return success 4094 */ 4095 if (ret == -EOPNOTSUPP) { 4096 dev_warn(&hdev->pdev->dev, 4097 "current firmware does not support command(0x%x)!\n", 4098 HCLGE_OPC_PF_RST_DONE); 4099 return 0; 4100 } else if (ret) { 4101 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4102 ret); 4103 } 4104 4105 return ret; 4106 } 4107 4108 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4109 { 4110 int ret = 0; 4111 4112 switch (hdev->reset_type) { 4113 case HNAE3_FUNC_RESET: 4114 case HNAE3_FLR_RESET: 4115 ret = hclge_set_all_vf_rst(hdev, false); 4116 break; 4117 case HNAE3_GLOBAL_RESET: 4118 case HNAE3_IMP_RESET: 4119 ret = hclge_set_rst_done(hdev); 4120 break; 4121 default: 4122 break; 4123 } 4124 4125 /* clear up the handshake status after re-initialize done */ 4126 hclge_reset_handshake(hdev, false); 4127 4128 return ret; 4129 } 4130 4131 static int hclge_reset_stack(struct hclge_dev *hdev) 4132 { 4133 int ret; 4134 4135 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4136 if (ret) 4137 return ret; 4138 4139 ret = hclge_reset_ae_dev(hdev->ae_dev); 4140 if (ret) 4141 return ret; 4142 4143 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4144 } 4145 4146 static int hclge_reset_prepare(struct hclge_dev *hdev) 4147 { 4148 int ret; 4149 4150 hdev->rst_stats.reset_cnt++; 4151 /* perform reset of the stack & ae device for a client */ 4152 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4153 if (ret) 4154 return ret; 4155 4156 rtnl_lock(); 4157 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4158 rtnl_unlock(); 4159 if (ret) 4160 return ret; 4161 4162 return hclge_reset_prepare_wait(hdev); 4163 } 4164 4165 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4166 { 4167 int ret; 4168 4169 hdev->rst_stats.hw_reset_done_cnt++; 4170 4171 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4172 if (ret) 4173 return ret; 4174 4175 rtnl_lock(); 4176 ret = hclge_reset_stack(hdev); 4177 rtnl_unlock(); 4178 if (ret) 4179 return ret; 4180 4181 hclge_clear_reset_cause(hdev); 4182 4183 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4184 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4185 * times 4186 */ 4187 if (ret && 4188 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4189 return ret; 4190 4191 ret = hclge_reset_prepare_up(hdev); 4192 if (ret) 4193 return ret; 4194 4195 rtnl_lock(); 4196 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4197 rtnl_unlock(); 4198 if (ret) 4199 return ret; 4200 4201 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4202 if (ret) 4203 return ret; 4204 4205 hdev->last_reset_time = jiffies; 4206 hdev->rst_stats.reset_fail_cnt = 0; 4207 hdev->rst_stats.reset_done_cnt++; 4208 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4209 4210 hclge_update_reset_level(hdev); 4211 4212 return 0; 4213 } 4214 4215 static void hclge_reset(struct hclge_dev *hdev) 4216 { 4217 if (hclge_reset_prepare(hdev)) 4218 goto err_reset; 4219 4220 if (hclge_reset_wait(hdev)) 4221 goto err_reset; 4222 4223 if (hclge_reset_rebuild(hdev)) 4224 goto err_reset; 4225 4226 return; 4227 4228 err_reset: 4229 if (hclge_reset_err_handle(hdev)) 4230 hclge_reset_task_schedule(hdev); 4231 } 4232 4233 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4234 { 4235 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4236 struct hclge_dev *hdev = ae_dev->priv; 4237 4238 /* We might end up getting called broadly because of 2 below cases: 4239 * 1. Recoverable error was conveyed through APEI and only way to bring 4240 * normalcy is to reset. 4241 * 2. A new reset request from the stack due to timeout 4242 * 4243 * check if this is a new reset request and we are not here just because 4244 * last reset attempt did not succeed and watchdog hit us again. We will 4245 * know this if last reset request did not occur very recently (watchdog 4246 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4247 * In case of new request we reset the "reset level" to PF reset. 4248 * And if it is a repeat reset request of the most recent one then we 4249 * want to make sure we throttle the reset request. Therefore, we will 4250 * not allow it again before 3*HZ times. 4251 */ 4252 4253 if (time_before(jiffies, (hdev->last_reset_time + 4254 HCLGE_RESET_INTERVAL))) { 4255 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4256 return; 4257 } 4258 4259 if (hdev->default_reset_request) { 4260 hdev->reset_level = 4261 hclge_get_reset_level(ae_dev, 4262 &hdev->default_reset_request); 4263 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4264 hdev->reset_level = HNAE3_FUNC_RESET; 4265 } 4266 4267 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4268 hdev->reset_level); 4269 4270 /* request reset & schedule reset task */ 4271 set_bit(hdev->reset_level, &hdev->reset_request); 4272 hclge_reset_task_schedule(hdev); 4273 4274 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4275 hdev->reset_level++; 4276 } 4277 4278 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4279 enum hnae3_reset_type rst_type) 4280 { 4281 struct hclge_dev *hdev = ae_dev->priv; 4282 4283 set_bit(rst_type, &hdev->default_reset_request); 4284 } 4285 4286 static void hclge_reset_timer(struct timer_list *t) 4287 { 4288 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4289 4290 /* if default_reset_request has no value, it means that this reset 4291 * request has already be handled, so just return here 4292 */ 4293 if (!hdev->default_reset_request) 4294 return; 4295 4296 dev_info(&hdev->pdev->dev, 4297 "triggering reset in reset timer\n"); 4298 hclge_reset_event(hdev->pdev, NULL); 4299 } 4300 4301 static void hclge_reset_subtask(struct hclge_dev *hdev) 4302 { 4303 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4304 4305 /* check if there is any ongoing reset in the hardware. This status can 4306 * be checked from reset_pending. If there is then, we need to wait for 4307 * hardware to complete reset. 4308 * a. If we are able to figure out in reasonable time that hardware 4309 * has fully resetted then, we can proceed with driver, client 4310 * reset. 4311 * b. else, we can come back later to check this status so re-sched 4312 * now. 4313 */ 4314 hdev->last_reset_time = jiffies; 4315 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4316 if (hdev->reset_type != HNAE3_NONE_RESET) 4317 hclge_reset(hdev); 4318 4319 /* check if we got any *new* reset requests to be honored */ 4320 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4321 if (hdev->reset_type != HNAE3_NONE_RESET) 4322 hclge_do_reset(hdev); 4323 4324 hdev->reset_type = HNAE3_NONE_RESET; 4325 } 4326 4327 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4328 { 4329 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4330 enum hnae3_reset_type reset_type; 4331 4332 if (ae_dev->hw_err_reset_req) { 4333 reset_type = hclge_get_reset_level(ae_dev, 4334 &ae_dev->hw_err_reset_req); 4335 hclge_set_def_reset_request(ae_dev, reset_type); 4336 } 4337 4338 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4339 ae_dev->ops->reset_event(hdev->pdev, NULL); 4340 4341 /* enable interrupt after error handling complete */ 4342 hclge_enable_vector(&hdev->misc_vector, true); 4343 } 4344 4345 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4346 { 4347 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4348 4349 ae_dev->hw_err_reset_req = 0; 4350 4351 if (hclge_find_error_source(hdev)) { 4352 hclge_handle_error_info_log(ae_dev); 4353 hclge_handle_mac_tnl(hdev); 4354 } 4355 4356 hclge_handle_err_reset_request(hdev); 4357 } 4358 4359 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4360 { 4361 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4362 struct device *dev = &hdev->pdev->dev; 4363 u32 msix_sts_reg; 4364 4365 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4366 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4367 if (hclge_handle_hw_msix_error 4368 (hdev, &hdev->default_reset_request)) 4369 dev_info(dev, "received msix interrupt 0x%x\n", 4370 msix_sts_reg); 4371 } 4372 4373 hclge_handle_hw_ras_error(ae_dev); 4374 4375 hclge_handle_err_reset_request(hdev); 4376 } 4377 4378 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4379 { 4380 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4381 return; 4382 4383 if (hnae3_dev_ras_imp_supported(hdev)) 4384 hclge_handle_err_recovery(hdev); 4385 else 4386 hclge_misc_err_recovery(hdev); 4387 } 4388 4389 static void hclge_reset_service_task(struct hclge_dev *hdev) 4390 { 4391 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4392 return; 4393 4394 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4395 HCLGE_RESET_SCHED_TIMEOUT)) 4396 dev_warn(&hdev->pdev->dev, 4397 "reset service task is scheduled after %ums on cpu%u!\n", 4398 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4399 smp_processor_id()); 4400 4401 down(&hdev->reset_sem); 4402 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4403 4404 hclge_reset_subtask(hdev); 4405 4406 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4407 up(&hdev->reset_sem); 4408 } 4409 4410 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4411 { 4412 int i; 4413 4414 /* start from vport 1 for PF is always alive */ 4415 for (i = 1; i < hdev->num_alloc_vport; i++) { 4416 struct hclge_vport *vport = &hdev->vport[i]; 4417 4418 if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ)) 4419 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4420 4421 /* If vf is not alive, set to default value */ 4422 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4423 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 4424 } 4425 } 4426 4427 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4428 { 4429 unsigned long delta = round_jiffies_relative(HZ); 4430 4431 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4432 return; 4433 4434 /* Always handle the link updating to make sure link state is 4435 * updated when it is triggered by mbx. 4436 */ 4437 hclge_update_link_status(hdev); 4438 hclge_sync_mac_table(hdev); 4439 hclge_sync_promisc_mode(hdev); 4440 hclge_sync_fd_table(hdev); 4441 4442 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4443 delta = jiffies - hdev->last_serv_processed; 4444 4445 if (delta < round_jiffies_relative(HZ)) { 4446 delta = round_jiffies_relative(HZ) - delta; 4447 goto out; 4448 } 4449 } 4450 4451 hdev->serv_processed_cnt++; 4452 hclge_update_vport_alive(hdev); 4453 4454 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4455 hdev->last_serv_processed = jiffies; 4456 goto out; 4457 } 4458 4459 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4460 hclge_update_stats_for_all(hdev); 4461 4462 hclge_update_port_info(hdev); 4463 hclge_sync_vlan_filter(hdev); 4464 4465 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4466 hclge_rfs_filter_expire(hdev); 4467 4468 hdev->last_serv_processed = jiffies; 4469 4470 out: 4471 hclge_task_schedule(hdev, delta); 4472 } 4473 4474 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4475 { 4476 unsigned long flags; 4477 4478 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4479 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4480 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4481 return; 4482 4483 /* to prevent concurrence with the irq handler */ 4484 spin_lock_irqsave(&hdev->ptp->lock, flags); 4485 4486 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4487 * handler may handle it just before spin_lock_irqsave(). 4488 */ 4489 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4490 hclge_ptp_clean_tx_hwts(hdev); 4491 4492 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4493 } 4494 4495 static void hclge_service_task(struct work_struct *work) 4496 { 4497 struct hclge_dev *hdev = 4498 container_of(work, struct hclge_dev, service_task.work); 4499 4500 hclge_errhand_service_task(hdev); 4501 hclge_reset_service_task(hdev); 4502 hclge_ptp_service_task(hdev); 4503 hclge_mailbox_service_task(hdev); 4504 hclge_periodic_service_task(hdev); 4505 4506 /* Handle error recovery, reset and mbx again in case periodical task 4507 * delays the handling by calling hclge_task_schedule() in 4508 * hclge_periodic_service_task(). 4509 */ 4510 hclge_errhand_service_task(hdev); 4511 hclge_reset_service_task(hdev); 4512 hclge_mailbox_service_task(hdev); 4513 } 4514 4515 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4516 { 4517 /* VF handle has no client */ 4518 if (!handle->client) 4519 return container_of(handle, struct hclge_vport, nic); 4520 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4521 return container_of(handle, struct hclge_vport, roce); 4522 else 4523 return container_of(handle, struct hclge_vport, nic); 4524 } 4525 4526 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4527 struct hnae3_vector_info *vector_info) 4528 { 4529 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4530 4531 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4532 4533 /* need an extend offset to config vector >= 64 */ 4534 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4535 vector_info->io_addr = hdev->hw.hw.io_base + 4536 HCLGE_VECTOR_REG_BASE + 4537 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4538 else 4539 vector_info->io_addr = hdev->hw.hw.io_base + 4540 HCLGE_VECTOR_EXT_REG_BASE + 4541 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4542 HCLGE_VECTOR_REG_OFFSET_H + 4543 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4544 HCLGE_VECTOR_REG_OFFSET; 4545 4546 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4547 hdev->vector_irq[idx] = vector_info->vector; 4548 } 4549 4550 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4551 struct hnae3_vector_info *vector_info) 4552 { 4553 struct hclge_vport *vport = hclge_get_vport(handle); 4554 struct hnae3_vector_info *vector = vector_info; 4555 struct hclge_dev *hdev = vport->back; 4556 int alloc = 0; 4557 u16 i = 0; 4558 u16 j; 4559 4560 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4561 vector_num = min(hdev->num_msi_left, vector_num); 4562 4563 for (j = 0; j < vector_num; j++) { 4564 while (++i < hdev->num_nic_msi) { 4565 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4566 hclge_get_vector_info(hdev, i, vector); 4567 vector++; 4568 alloc++; 4569 4570 break; 4571 } 4572 } 4573 } 4574 hdev->num_msi_left -= alloc; 4575 hdev->num_msi_used += alloc; 4576 4577 return alloc; 4578 } 4579 4580 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4581 { 4582 int i; 4583 4584 for (i = 0; i < hdev->num_msi; i++) 4585 if (vector == hdev->vector_irq[i]) 4586 return i; 4587 4588 return -EINVAL; 4589 } 4590 4591 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4592 { 4593 struct hclge_vport *vport = hclge_get_vport(handle); 4594 struct hclge_dev *hdev = vport->back; 4595 int vector_id; 4596 4597 vector_id = hclge_get_vector_index(hdev, vector); 4598 if (vector_id < 0) { 4599 dev_err(&hdev->pdev->dev, 4600 "Get vector index fail. vector = %d\n", vector); 4601 return vector_id; 4602 } 4603 4604 hclge_free_vector(hdev, vector_id); 4605 4606 return 0; 4607 } 4608 4609 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4610 u8 *key, u8 *hfunc) 4611 { 4612 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4613 struct hclge_vport *vport = hclge_get_vport(handle); 4614 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4615 4616 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4617 4618 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4619 ae_dev->dev_specs.rss_ind_tbl_size); 4620 4621 return 0; 4622 } 4623 4624 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4625 const u8 *key, const u8 hfunc) 4626 { 4627 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4628 struct hclge_vport *vport = hclge_get_vport(handle); 4629 struct hclge_dev *hdev = vport->back; 4630 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4631 int ret, i; 4632 4633 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4634 if (ret) { 4635 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4636 return ret; 4637 } 4638 4639 /* Update the shadow RSS table with user specified qids */ 4640 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4641 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4642 4643 /* Update the hardware */ 4644 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4645 rss_cfg->rss_indirection_tbl); 4646 } 4647 4648 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4649 struct ethtool_rxnfc *nfc) 4650 { 4651 struct hclge_vport *vport = hclge_get_vport(handle); 4652 struct hclge_dev *hdev = vport->back; 4653 int ret; 4654 4655 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4656 &hdev->rss_cfg, nfc); 4657 if (ret) { 4658 dev_err(&hdev->pdev->dev, 4659 "failed to set rss tuple, ret = %d.\n", ret); 4660 return ret; 4661 } 4662 4663 hclge_comm_get_rss_type(&vport->nic, &hdev->rss_cfg.rss_tuple_sets); 4664 return 0; 4665 } 4666 4667 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4668 struct ethtool_rxnfc *nfc) 4669 { 4670 struct hclge_vport *vport = hclge_get_vport(handle); 4671 u8 tuple_sets; 4672 int ret; 4673 4674 nfc->data = 0; 4675 4676 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4677 &tuple_sets); 4678 if (ret || !tuple_sets) 4679 return ret; 4680 4681 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4682 4683 return 0; 4684 } 4685 4686 static int hclge_get_tc_size(struct hnae3_handle *handle) 4687 { 4688 struct hclge_vport *vport = hclge_get_vport(handle); 4689 struct hclge_dev *hdev = vport->back; 4690 4691 return hdev->pf_rss_size_max; 4692 } 4693 4694 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4695 { 4696 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4697 struct hclge_vport *vport = hdev->vport; 4698 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4699 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4700 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4701 struct hnae3_tc_info *tc_info; 4702 u16 roundup_size; 4703 u16 rss_size; 4704 int i; 4705 4706 tc_info = &vport->nic.kinfo.tc_info; 4707 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4708 rss_size = tc_info->tqp_count[i]; 4709 tc_valid[i] = 0; 4710 4711 if (!(hdev->hw_tc_map & BIT(i))) 4712 continue; 4713 4714 /* tc_size set to hardware is the log2 of roundup power of two 4715 * of rss_size, the acutal queue size is limited by indirection 4716 * table. 4717 */ 4718 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4719 rss_size == 0) { 4720 dev_err(&hdev->pdev->dev, 4721 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4722 rss_size); 4723 return -EINVAL; 4724 } 4725 4726 roundup_size = roundup_pow_of_two(rss_size); 4727 roundup_size = ilog2(roundup_size); 4728 4729 tc_valid[i] = 1; 4730 tc_size[i] = roundup_size; 4731 tc_offset[i] = tc_info->tqp_offset[i]; 4732 } 4733 4734 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4735 tc_size); 4736 } 4737 4738 int hclge_rss_init_hw(struct hclge_dev *hdev) 4739 { 4740 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4741 u8 *key = hdev->rss_cfg.rss_hash_key; 4742 u8 hfunc = hdev->rss_cfg.rss_algo; 4743 int ret; 4744 4745 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4746 rss_indir); 4747 if (ret) 4748 return ret; 4749 4750 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4751 if (ret) 4752 return ret; 4753 4754 ret = hclge_comm_set_rss_input_tuple(&hdev->vport[0].nic, 4755 &hdev->hw.hw, true, 4756 &hdev->rss_cfg); 4757 if (ret) 4758 return ret; 4759 4760 return hclge_init_rss_tc_mode(hdev); 4761 } 4762 4763 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4764 int vector_id, bool en, 4765 struct hnae3_ring_chain_node *ring_chain) 4766 { 4767 struct hclge_dev *hdev = vport->back; 4768 struct hnae3_ring_chain_node *node; 4769 struct hclge_desc desc; 4770 struct hclge_ctrl_vector_chain_cmd *req = 4771 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4772 enum hclge_comm_cmd_status status; 4773 enum hclge_opcode_type op; 4774 u16 tqp_type_and_id; 4775 int i; 4776 4777 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4778 hclge_cmd_setup_basic_desc(&desc, op, false); 4779 req->int_vector_id_l = hnae3_get_field(vector_id, 4780 HCLGE_VECTOR_ID_L_M, 4781 HCLGE_VECTOR_ID_L_S); 4782 req->int_vector_id_h = hnae3_get_field(vector_id, 4783 HCLGE_VECTOR_ID_H_M, 4784 HCLGE_VECTOR_ID_H_S); 4785 4786 i = 0; 4787 for (node = ring_chain; node; node = node->next) { 4788 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4789 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4790 HCLGE_INT_TYPE_S, 4791 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4792 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4793 HCLGE_TQP_ID_S, node->tqp_index); 4794 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4795 HCLGE_INT_GL_IDX_S, 4796 hnae3_get_field(node->int_gl_idx, 4797 HNAE3_RING_GL_IDX_M, 4798 HNAE3_RING_GL_IDX_S)); 4799 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4800 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4801 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4802 req->vfid = vport->vport_id; 4803 4804 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4805 if (status) { 4806 dev_err(&hdev->pdev->dev, 4807 "Map TQP fail, status is %d.\n", 4808 status); 4809 return -EIO; 4810 } 4811 i = 0; 4812 4813 hclge_cmd_setup_basic_desc(&desc, 4814 op, 4815 false); 4816 req->int_vector_id_l = 4817 hnae3_get_field(vector_id, 4818 HCLGE_VECTOR_ID_L_M, 4819 HCLGE_VECTOR_ID_L_S); 4820 req->int_vector_id_h = 4821 hnae3_get_field(vector_id, 4822 HCLGE_VECTOR_ID_H_M, 4823 HCLGE_VECTOR_ID_H_S); 4824 } 4825 } 4826 4827 if (i > 0) { 4828 req->int_cause_num = i; 4829 req->vfid = vport->vport_id; 4830 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4831 if (status) { 4832 dev_err(&hdev->pdev->dev, 4833 "Map TQP fail, status is %d.\n", status); 4834 return -EIO; 4835 } 4836 } 4837 4838 return 0; 4839 } 4840 4841 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 4842 struct hnae3_ring_chain_node *ring_chain) 4843 { 4844 struct hclge_vport *vport = hclge_get_vport(handle); 4845 struct hclge_dev *hdev = vport->back; 4846 int vector_id; 4847 4848 vector_id = hclge_get_vector_index(hdev, vector); 4849 if (vector_id < 0) { 4850 dev_err(&hdev->pdev->dev, 4851 "failed to get vector index. vector=%d\n", vector); 4852 return vector_id; 4853 } 4854 4855 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 4856 } 4857 4858 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 4859 struct hnae3_ring_chain_node *ring_chain) 4860 { 4861 struct hclge_vport *vport = hclge_get_vport(handle); 4862 struct hclge_dev *hdev = vport->back; 4863 int vector_id, ret; 4864 4865 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 4866 return 0; 4867 4868 vector_id = hclge_get_vector_index(hdev, vector); 4869 if (vector_id < 0) { 4870 dev_err(&handle->pdev->dev, 4871 "Get vector index fail. ret =%d\n", vector_id); 4872 return vector_id; 4873 } 4874 4875 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 4876 if (ret) 4877 dev_err(&handle->pdev->dev, 4878 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 4879 vector_id, ret); 4880 4881 return ret; 4882 } 4883 4884 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 4885 bool en_uc, bool en_mc, bool en_bc) 4886 { 4887 struct hclge_vport *vport = &hdev->vport[vf_id]; 4888 struct hnae3_handle *handle = &vport->nic; 4889 struct hclge_promisc_cfg_cmd *req; 4890 struct hclge_desc desc; 4891 bool uc_tx_en = en_uc; 4892 u8 promisc_cfg = 0; 4893 int ret; 4894 4895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 4896 4897 req = (struct hclge_promisc_cfg_cmd *)desc.data; 4898 req->vf_id = vf_id; 4899 4900 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 4901 uc_tx_en = false; 4902 4903 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 4904 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 4905 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 4906 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 4907 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 4908 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 4909 req->extend_promisc = promisc_cfg; 4910 4911 /* to be compatible with DEVICE_VERSION_V1/2 */ 4912 promisc_cfg = 0; 4913 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 4914 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 4915 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 4916 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 4917 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 4918 req->promisc = promisc_cfg; 4919 4920 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4921 if (ret) 4922 dev_err(&hdev->pdev->dev, 4923 "failed to set vport %u promisc mode, ret = %d.\n", 4924 vf_id, ret); 4925 4926 return ret; 4927 } 4928 4929 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 4930 bool en_mc_pmc, bool en_bc_pmc) 4931 { 4932 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 4933 en_uc_pmc, en_mc_pmc, en_bc_pmc); 4934 } 4935 4936 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 4937 bool en_mc_pmc) 4938 { 4939 struct hclge_vport *vport = hclge_get_vport(handle); 4940 struct hclge_dev *hdev = vport->back; 4941 bool en_bc_pmc = true; 4942 4943 /* For device whose version below V2, if broadcast promisc enabled, 4944 * vlan filter is always bypassed. So broadcast promisc should be 4945 * disabled until user enable promisc mode 4946 */ 4947 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4948 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 4949 4950 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 4951 en_bc_pmc); 4952 } 4953 4954 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 4955 { 4956 struct hclge_vport *vport = hclge_get_vport(handle); 4957 4958 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 4959 } 4960 4961 static void hclge_sync_fd_state(struct hclge_dev *hdev) 4962 { 4963 if (hlist_empty(&hdev->fd_rule_list)) 4964 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 4965 } 4966 4967 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 4968 { 4969 if (!test_bit(location, hdev->fd_bmap)) { 4970 set_bit(location, hdev->fd_bmap); 4971 hdev->hclge_fd_rule_num++; 4972 } 4973 } 4974 4975 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 4976 { 4977 if (test_bit(location, hdev->fd_bmap)) { 4978 clear_bit(location, hdev->fd_bmap); 4979 hdev->hclge_fd_rule_num--; 4980 } 4981 } 4982 4983 static void hclge_fd_free_node(struct hclge_dev *hdev, 4984 struct hclge_fd_rule *rule) 4985 { 4986 hlist_del(&rule->rule_node); 4987 kfree(rule); 4988 hclge_sync_fd_state(hdev); 4989 } 4990 4991 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 4992 struct hclge_fd_rule *old_rule, 4993 struct hclge_fd_rule *new_rule, 4994 enum HCLGE_FD_NODE_STATE state) 4995 { 4996 switch (state) { 4997 case HCLGE_FD_TO_ADD: 4998 case HCLGE_FD_ACTIVE: 4999 /* 1) if the new state is TO_ADD, just replace the old rule 5000 * with the same location, no matter its state, because the 5001 * new rule will be configured to the hardware. 5002 * 2) if the new state is ACTIVE, it means the new rule 5003 * has been configured to the hardware, so just replace 5004 * the old rule node with the same location. 5005 * 3) for it doesn't add a new node to the list, so it's 5006 * unnecessary to update the rule number and fd_bmap. 5007 */ 5008 new_rule->rule_node.next = old_rule->rule_node.next; 5009 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5010 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5011 kfree(new_rule); 5012 break; 5013 case HCLGE_FD_DELETED: 5014 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5015 hclge_fd_free_node(hdev, old_rule); 5016 break; 5017 case HCLGE_FD_TO_DEL: 5018 /* if new request is TO_DEL, and old rule is existent 5019 * 1) the state of old rule is TO_DEL, we need do nothing, 5020 * because we delete rule by location, other rule content 5021 * is unncessary. 5022 * 2) the state of old rule is ACTIVE, we need to change its 5023 * state to TO_DEL, so the rule will be deleted when periodic 5024 * task being scheduled. 5025 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5026 * been added to hardware, so we just delete the rule node from 5027 * fd_rule_list directly. 5028 */ 5029 if (old_rule->state == HCLGE_FD_TO_ADD) { 5030 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5031 hclge_fd_free_node(hdev, old_rule); 5032 return; 5033 } 5034 old_rule->state = HCLGE_FD_TO_DEL; 5035 break; 5036 } 5037 } 5038 5039 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5040 u16 location, 5041 struct hclge_fd_rule **parent) 5042 { 5043 struct hclge_fd_rule *rule; 5044 struct hlist_node *node; 5045 5046 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5047 if (rule->location == location) 5048 return rule; 5049 else if (rule->location > location) 5050 return NULL; 5051 /* record the parent node, use to keep the nodes in fd_rule_list 5052 * in ascend order. 5053 */ 5054 *parent = rule; 5055 } 5056 5057 return NULL; 5058 } 5059 5060 /* insert fd rule node in ascend order according to rule->location */ 5061 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5062 struct hclge_fd_rule *rule, 5063 struct hclge_fd_rule *parent) 5064 { 5065 INIT_HLIST_NODE(&rule->rule_node); 5066 5067 if (parent) 5068 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5069 else 5070 hlist_add_head(&rule->rule_node, hlist); 5071 } 5072 5073 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5074 struct hclge_fd_user_def_cfg *cfg) 5075 { 5076 struct hclge_fd_user_def_cfg_cmd *req; 5077 struct hclge_desc desc; 5078 u16 data = 0; 5079 int ret; 5080 5081 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5082 5083 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5084 5085 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5086 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5087 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5088 req->ol2_cfg = cpu_to_le16(data); 5089 5090 data = 0; 5091 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5092 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5093 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5094 req->ol3_cfg = cpu_to_le16(data); 5095 5096 data = 0; 5097 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5098 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5099 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5100 req->ol4_cfg = cpu_to_le16(data); 5101 5102 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5103 if (ret) 5104 dev_err(&hdev->pdev->dev, 5105 "failed to set fd user def data, ret= %d\n", ret); 5106 return ret; 5107 } 5108 5109 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5110 { 5111 int ret; 5112 5113 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5114 return; 5115 5116 if (!locked) 5117 spin_lock_bh(&hdev->fd_rule_lock); 5118 5119 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5120 if (ret) 5121 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5122 5123 if (!locked) 5124 spin_unlock_bh(&hdev->fd_rule_lock); 5125 } 5126 5127 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5128 struct hclge_fd_rule *rule) 5129 { 5130 struct hlist_head *hlist = &hdev->fd_rule_list; 5131 struct hclge_fd_rule *fd_rule, *parent = NULL; 5132 struct hclge_fd_user_def_info *info, *old_info; 5133 struct hclge_fd_user_def_cfg *cfg; 5134 5135 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5136 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5137 return 0; 5138 5139 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5140 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5141 info = &rule->ep.user_def; 5142 5143 if (!cfg->ref_cnt || cfg->offset == info->offset) 5144 return 0; 5145 5146 if (cfg->ref_cnt > 1) 5147 goto error; 5148 5149 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5150 if (fd_rule) { 5151 old_info = &fd_rule->ep.user_def; 5152 if (info->layer == old_info->layer) 5153 return 0; 5154 } 5155 5156 error: 5157 dev_err(&hdev->pdev->dev, 5158 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5159 info->layer + 1); 5160 return -ENOSPC; 5161 } 5162 5163 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5164 struct hclge_fd_rule *rule) 5165 { 5166 struct hclge_fd_user_def_cfg *cfg; 5167 5168 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5169 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5170 return; 5171 5172 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5173 if (!cfg->ref_cnt) { 5174 cfg->offset = rule->ep.user_def.offset; 5175 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5176 } 5177 cfg->ref_cnt++; 5178 } 5179 5180 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5181 struct hclge_fd_rule *rule) 5182 { 5183 struct hclge_fd_user_def_cfg *cfg; 5184 5185 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5186 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5187 return; 5188 5189 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5190 if (!cfg->ref_cnt) 5191 return; 5192 5193 cfg->ref_cnt--; 5194 if (!cfg->ref_cnt) { 5195 cfg->offset = 0; 5196 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5197 } 5198 } 5199 5200 static void hclge_update_fd_list(struct hclge_dev *hdev, 5201 enum HCLGE_FD_NODE_STATE state, u16 location, 5202 struct hclge_fd_rule *new_rule) 5203 { 5204 struct hlist_head *hlist = &hdev->fd_rule_list; 5205 struct hclge_fd_rule *fd_rule, *parent = NULL; 5206 5207 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5208 if (fd_rule) { 5209 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5210 if (state == HCLGE_FD_ACTIVE) 5211 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5212 hclge_sync_fd_user_def_cfg(hdev, true); 5213 5214 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5215 return; 5216 } 5217 5218 /* it's unlikely to fail here, because we have checked the rule 5219 * exist before. 5220 */ 5221 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5222 dev_warn(&hdev->pdev->dev, 5223 "failed to delete fd rule %u, it's inexistent\n", 5224 location); 5225 return; 5226 } 5227 5228 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5229 hclge_sync_fd_user_def_cfg(hdev, true); 5230 5231 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5232 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5233 5234 if (state == HCLGE_FD_TO_ADD) { 5235 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5236 hclge_task_schedule(hdev, 0); 5237 } 5238 } 5239 5240 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5241 { 5242 struct hclge_get_fd_mode_cmd *req; 5243 struct hclge_desc desc; 5244 int ret; 5245 5246 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5247 5248 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5249 5250 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5251 if (ret) { 5252 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5253 return ret; 5254 } 5255 5256 *fd_mode = req->mode; 5257 5258 return ret; 5259 } 5260 5261 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5262 u32 *stage1_entry_num, 5263 u32 *stage2_entry_num, 5264 u16 *stage1_counter_num, 5265 u16 *stage2_counter_num) 5266 { 5267 struct hclge_get_fd_allocation_cmd *req; 5268 struct hclge_desc desc; 5269 int ret; 5270 5271 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5272 5273 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5274 5275 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5276 if (ret) { 5277 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5278 ret); 5279 return ret; 5280 } 5281 5282 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5283 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5284 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5285 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5286 5287 return ret; 5288 } 5289 5290 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5291 enum HCLGE_FD_STAGE stage_num) 5292 { 5293 struct hclge_set_fd_key_config_cmd *req; 5294 struct hclge_fd_key_cfg *stage; 5295 struct hclge_desc desc; 5296 int ret; 5297 5298 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5299 5300 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5301 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5302 req->stage = stage_num; 5303 req->key_select = stage->key_sel; 5304 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5305 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5306 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5307 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5308 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5309 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5310 5311 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5312 if (ret) 5313 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5314 5315 return ret; 5316 } 5317 5318 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5319 { 5320 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5321 5322 spin_lock_bh(&hdev->fd_rule_lock); 5323 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5324 spin_unlock_bh(&hdev->fd_rule_lock); 5325 5326 hclge_fd_set_user_def_cmd(hdev, cfg); 5327 } 5328 5329 static int hclge_init_fd_config(struct hclge_dev *hdev) 5330 { 5331 #define LOW_2_WORDS 0x03 5332 struct hclge_fd_key_cfg *key_cfg; 5333 int ret; 5334 5335 if (!hnae3_dev_fd_supported(hdev)) 5336 return 0; 5337 5338 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5339 if (ret) 5340 return ret; 5341 5342 switch (hdev->fd_cfg.fd_mode) { 5343 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5344 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5345 break; 5346 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5347 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5348 break; 5349 default: 5350 dev_err(&hdev->pdev->dev, 5351 "Unsupported flow director mode %u\n", 5352 hdev->fd_cfg.fd_mode); 5353 return -EOPNOTSUPP; 5354 } 5355 5356 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5357 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5358 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5359 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5360 key_cfg->outer_sipv6_word_en = 0; 5361 key_cfg->outer_dipv6_word_en = 0; 5362 5363 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5364 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5365 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5366 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5367 5368 /* If use max 400bit key, we can support tuples for ether type */ 5369 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5370 key_cfg->tuple_active |= 5371 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5372 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5373 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5374 } 5375 5376 /* roce_type is used to filter roce frames 5377 * dst_vport is used to specify the rule 5378 */ 5379 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5380 5381 ret = hclge_get_fd_allocation(hdev, 5382 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5383 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5384 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5385 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5386 if (ret) 5387 return ret; 5388 5389 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5390 } 5391 5392 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5393 int loc, u8 *key, bool is_add) 5394 { 5395 struct hclge_fd_tcam_config_1_cmd *req1; 5396 struct hclge_fd_tcam_config_2_cmd *req2; 5397 struct hclge_fd_tcam_config_3_cmd *req3; 5398 struct hclge_desc desc[3]; 5399 int ret; 5400 5401 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5402 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5403 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5404 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5405 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5406 5407 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5408 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5409 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5410 5411 req1->stage = stage; 5412 req1->xy_sel = sel_x ? 1 : 0; 5413 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5414 req1->index = cpu_to_le32(loc); 5415 req1->entry_vld = sel_x ? is_add : 0; 5416 5417 if (key) { 5418 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5419 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5420 sizeof(req2->tcam_data)); 5421 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5422 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5423 } 5424 5425 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5426 if (ret) 5427 dev_err(&hdev->pdev->dev, 5428 "config tcam key fail, ret=%d\n", 5429 ret); 5430 5431 return ret; 5432 } 5433 5434 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5435 struct hclge_fd_ad_data *action) 5436 { 5437 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5438 struct hclge_fd_ad_config_cmd *req; 5439 struct hclge_desc desc; 5440 u64 ad_data = 0; 5441 int ret; 5442 5443 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5444 5445 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5446 req->index = cpu_to_le32(loc); 5447 req->stage = stage; 5448 5449 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5450 action->write_rule_id_to_bd); 5451 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5452 action->rule_id); 5453 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5454 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5455 action->override_tc); 5456 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5457 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5458 } 5459 ad_data <<= 32; 5460 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5461 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5462 action->forward_to_direct_queue); 5463 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5464 action->queue_id); 5465 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5466 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5467 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5468 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5469 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5470 action->counter_id); 5471 5472 req->ad_data = cpu_to_le64(ad_data); 5473 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5474 if (ret) 5475 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5476 5477 return ret; 5478 } 5479 5480 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5481 struct hclge_fd_rule *rule) 5482 { 5483 int offset, moffset, ip_offset; 5484 enum HCLGE_FD_KEY_OPT key_opt; 5485 u16 tmp_x_s, tmp_y_s; 5486 u32 tmp_x_l, tmp_y_l; 5487 u8 *p = (u8 *)rule; 5488 int i; 5489 5490 if (rule->unused_tuple & BIT(tuple_bit)) 5491 return true; 5492 5493 key_opt = tuple_key_info[tuple_bit].key_opt; 5494 offset = tuple_key_info[tuple_bit].offset; 5495 moffset = tuple_key_info[tuple_bit].moffset; 5496 5497 switch (key_opt) { 5498 case KEY_OPT_U8: 5499 calc_x(*key_x, p[offset], p[moffset]); 5500 calc_y(*key_y, p[offset], p[moffset]); 5501 5502 return true; 5503 case KEY_OPT_LE16: 5504 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5505 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5506 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5507 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5508 5509 return true; 5510 case KEY_OPT_LE32: 5511 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5512 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5513 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5514 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5515 5516 return true; 5517 case KEY_OPT_MAC: 5518 for (i = 0; i < ETH_ALEN; i++) { 5519 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5520 p[moffset + i]); 5521 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5522 p[moffset + i]); 5523 } 5524 5525 return true; 5526 case KEY_OPT_IP: 5527 ip_offset = IPV4_INDEX * sizeof(u32); 5528 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5529 *(u32 *)(&p[moffset + ip_offset])); 5530 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5531 *(u32 *)(&p[moffset + ip_offset])); 5532 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5533 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5534 5535 return true; 5536 default: 5537 return false; 5538 } 5539 } 5540 5541 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5542 u8 vf_id, u8 network_port_id) 5543 { 5544 u32 port_number = 0; 5545 5546 if (port_type == HOST_PORT) { 5547 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5548 pf_id); 5549 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5550 vf_id); 5551 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5552 } else { 5553 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5554 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5555 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5556 } 5557 5558 return port_number; 5559 } 5560 5561 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5562 __le32 *key_x, __le32 *key_y, 5563 struct hclge_fd_rule *rule) 5564 { 5565 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5566 u8 cur_pos = 0, tuple_size, shift_bits; 5567 unsigned int i; 5568 5569 for (i = 0; i < MAX_META_DATA; i++) { 5570 tuple_size = meta_data_key_info[i].key_length; 5571 tuple_bit = key_cfg->meta_data_active & BIT(i); 5572 5573 switch (tuple_bit) { 5574 case BIT(ROCE_TYPE): 5575 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5576 cur_pos += tuple_size; 5577 break; 5578 case BIT(DST_VPORT): 5579 port_number = hclge_get_port_number(HOST_PORT, 0, 5580 rule->vf_id, 0); 5581 hnae3_set_field(meta_data, 5582 GENMASK(cur_pos + tuple_size, cur_pos), 5583 cur_pos, port_number); 5584 cur_pos += tuple_size; 5585 break; 5586 default: 5587 break; 5588 } 5589 } 5590 5591 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5592 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5593 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5594 5595 *key_x = cpu_to_le32(tmp_x << shift_bits); 5596 *key_y = cpu_to_le32(tmp_y << shift_bits); 5597 } 5598 5599 /* A complete key is combined with meta data key and tuple key. 5600 * Meta data key is stored at the MSB region, and tuple key is stored at 5601 * the LSB region, unused bits will be filled 0. 5602 */ 5603 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5604 struct hclge_fd_rule *rule) 5605 { 5606 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5607 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5608 u8 *cur_key_x, *cur_key_y; 5609 u8 meta_data_region; 5610 u8 tuple_size; 5611 int ret; 5612 u32 i; 5613 5614 memset(key_x, 0, sizeof(key_x)); 5615 memset(key_y, 0, sizeof(key_y)); 5616 cur_key_x = key_x; 5617 cur_key_y = key_y; 5618 5619 for (i = 0; i < MAX_TUPLE; i++) { 5620 bool tuple_valid; 5621 5622 tuple_size = tuple_key_info[i].key_length / 8; 5623 if (!(key_cfg->tuple_active & BIT(i))) 5624 continue; 5625 5626 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5627 cur_key_y, rule); 5628 if (tuple_valid) { 5629 cur_key_x += tuple_size; 5630 cur_key_y += tuple_size; 5631 } 5632 } 5633 5634 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5635 MAX_META_DATA_LENGTH / 8; 5636 5637 hclge_fd_convert_meta_data(key_cfg, 5638 (__le32 *)(key_x + meta_data_region), 5639 (__le32 *)(key_y + meta_data_region), 5640 rule); 5641 5642 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5643 true); 5644 if (ret) { 5645 dev_err(&hdev->pdev->dev, 5646 "fd key_y config fail, loc=%u, ret=%d\n", 5647 rule->queue_id, ret); 5648 return ret; 5649 } 5650 5651 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5652 true); 5653 if (ret) 5654 dev_err(&hdev->pdev->dev, 5655 "fd key_x config fail, loc=%u, ret=%d\n", 5656 rule->queue_id, ret); 5657 return ret; 5658 } 5659 5660 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5661 struct hclge_fd_rule *rule) 5662 { 5663 struct hclge_vport *vport = hdev->vport; 5664 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5665 struct hclge_fd_ad_data ad_data; 5666 5667 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5668 ad_data.ad_id = rule->location; 5669 5670 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5671 ad_data.drop_packet = true; 5672 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5673 ad_data.override_tc = true; 5674 ad_data.queue_id = 5675 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5676 ad_data.tc_size = 5677 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5678 } else { 5679 ad_data.forward_to_direct_queue = true; 5680 ad_data.queue_id = rule->queue_id; 5681 } 5682 5683 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5684 ad_data.use_counter = true; 5685 ad_data.counter_id = rule->vf_id % 5686 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5687 } else { 5688 ad_data.use_counter = false; 5689 ad_data.counter_id = 0; 5690 } 5691 5692 ad_data.use_next_stage = false; 5693 ad_data.next_input_key = 0; 5694 5695 ad_data.write_rule_id_to_bd = true; 5696 ad_data.rule_id = rule->location; 5697 5698 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5699 } 5700 5701 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5702 u32 *unused_tuple) 5703 { 5704 if (!spec || !unused_tuple) 5705 return -EINVAL; 5706 5707 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5708 5709 if (!spec->ip4src) 5710 *unused_tuple |= BIT(INNER_SRC_IP); 5711 5712 if (!spec->ip4dst) 5713 *unused_tuple |= BIT(INNER_DST_IP); 5714 5715 if (!spec->psrc) 5716 *unused_tuple |= BIT(INNER_SRC_PORT); 5717 5718 if (!spec->pdst) 5719 *unused_tuple |= BIT(INNER_DST_PORT); 5720 5721 if (!spec->tos) 5722 *unused_tuple |= BIT(INNER_IP_TOS); 5723 5724 return 0; 5725 } 5726 5727 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5728 u32 *unused_tuple) 5729 { 5730 if (!spec || !unused_tuple) 5731 return -EINVAL; 5732 5733 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5734 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5735 5736 if (!spec->ip4src) 5737 *unused_tuple |= BIT(INNER_SRC_IP); 5738 5739 if (!spec->ip4dst) 5740 *unused_tuple |= BIT(INNER_DST_IP); 5741 5742 if (!spec->tos) 5743 *unused_tuple |= BIT(INNER_IP_TOS); 5744 5745 if (!spec->proto) 5746 *unused_tuple |= BIT(INNER_IP_PROTO); 5747 5748 if (spec->l4_4_bytes) 5749 return -EOPNOTSUPP; 5750 5751 if (spec->ip_ver != ETH_RX_NFC_IP4) 5752 return -EOPNOTSUPP; 5753 5754 return 0; 5755 } 5756 5757 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5758 u32 *unused_tuple) 5759 { 5760 if (!spec || !unused_tuple) 5761 return -EINVAL; 5762 5763 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5764 5765 /* check whether src/dst ip address used */ 5766 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5767 *unused_tuple |= BIT(INNER_SRC_IP); 5768 5769 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5770 *unused_tuple |= BIT(INNER_DST_IP); 5771 5772 if (!spec->psrc) 5773 *unused_tuple |= BIT(INNER_SRC_PORT); 5774 5775 if (!spec->pdst) 5776 *unused_tuple |= BIT(INNER_DST_PORT); 5777 5778 if (!spec->tclass) 5779 *unused_tuple |= BIT(INNER_IP_TOS); 5780 5781 return 0; 5782 } 5783 5784 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5785 u32 *unused_tuple) 5786 { 5787 if (!spec || !unused_tuple) 5788 return -EINVAL; 5789 5790 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5791 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5792 5793 /* check whether src/dst ip address used */ 5794 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5795 *unused_tuple |= BIT(INNER_SRC_IP); 5796 5797 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5798 *unused_tuple |= BIT(INNER_DST_IP); 5799 5800 if (!spec->l4_proto) 5801 *unused_tuple |= BIT(INNER_IP_PROTO); 5802 5803 if (!spec->tclass) 5804 *unused_tuple |= BIT(INNER_IP_TOS); 5805 5806 if (spec->l4_4_bytes) 5807 return -EOPNOTSUPP; 5808 5809 return 0; 5810 } 5811 5812 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 5813 { 5814 if (!spec || !unused_tuple) 5815 return -EINVAL; 5816 5817 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5818 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 5819 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 5820 5821 if (is_zero_ether_addr(spec->h_source)) 5822 *unused_tuple |= BIT(INNER_SRC_MAC); 5823 5824 if (is_zero_ether_addr(spec->h_dest)) 5825 *unused_tuple |= BIT(INNER_DST_MAC); 5826 5827 if (!spec->h_proto) 5828 *unused_tuple |= BIT(INNER_ETH_TYPE); 5829 5830 return 0; 5831 } 5832 5833 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 5834 struct ethtool_rx_flow_spec *fs, 5835 u32 *unused_tuple) 5836 { 5837 if (fs->flow_type & FLOW_EXT) { 5838 if (fs->h_ext.vlan_etype) { 5839 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 5840 return -EOPNOTSUPP; 5841 } 5842 5843 if (!fs->h_ext.vlan_tci) 5844 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5845 5846 if (fs->m_ext.vlan_tci && 5847 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 5848 dev_err(&hdev->pdev->dev, 5849 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 5850 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 5851 return -EINVAL; 5852 } 5853 } else { 5854 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5855 } 5856 5857 if (fs->flow_type & FLOW_MAC_EXT) { 5858 if (hdev->fd_cfg.fd_mode != 5859 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5860 dev_err(&hdev->pdev->dev, 5861 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 5862 return -EOPNOTSUPP; 5863 } 5864 5865 if (is_zero_ether_addr(fs->h_ext.h_dest)) 5866 *unused_tuple |= BIT(INNER_DST_MAC); 5867 else 5868 *unused_tuple &= ~BIT(INNER_DST_MAC); 5869 } 5870 5871 return 0; 5872 } 5873 5874 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 5875 struct hclge_fd_user_def_info *info) 5876 { 5877 switch (flow_type) { 5878 case ETHER_FLOW: 5879 info->layer = HCLGE_FD_USER_DEF_L2; 5880 *unused_tuple &= ~BIT(INNER_L2_RSV); 5881 break; 5882 case IP_USER_FLOW: 5883 case IPV6_USER_FLOW: 5884 info->layer = HCLGE_FD_USER_DEF_L3; 5885 *unused_tuple &= ~BIT(INNER_L3_RSV); 5886 break; 5887 case TCP_V4_FLOW: 5888 case UDP_V4_FLOW: 5889 case TCP_V6_FLOW: 5890 case UDP_V6_FLOW: 5891 info->layer = HCLGE_FD_USER_DEF_L4; 5892 *unused_tuple &= ~BIT(INNER_L4_RSV); 5893 break; 5894 default: 5895 return -EOPNOTSUPP; 5896 } 5897 5898 return 0; 5899 } 5900 5901 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 5902 { 5903 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 5904 } 5905 5906 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 5907 struct ethtool_rx_flow_spec *fs, 5908 u32 *unused_tuple, 5909 struct hclge_fd_user_def_info *info) 5910 { 5911 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 5912 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 5913 u16 data, offset, data_mask, offset_mask; 5914 int ret; 5915 5916 info->layer = HCLGE_FD_USER_DEF_NONE; 5917 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5918 5919 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 5920 return 0; 5921 5922 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 5923 * for data, and bit32~47 is used for offset. 5924 */ 5925 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 5926 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 5927 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 5928 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 5929 5930 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 5931 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 5932 return -EOPNOTSUPP; 5933 } 5934 5935 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 5936 dev_err(&hdev->pdev->dev, 5937 "user-def offset[%u] should be no more than %u\n", 5938 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 5939 return -EINVAL; 5940 } 5941 5942 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 5943 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 5944 return -EINVAL; 5945 } 5946 5947 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 5948 if (ret) { 5949 dev_err(&hdev->pdev->dev, 5950 "unsupported flow type for user-def bytes, ret = %d\n", 5951 ret); 5952 return ret; 5953 } 5954 5955 info->data = data; 5956 info->data_mask = data_mask; 5957 info->offset = offset; 5958 5959 return 0; 5960 } 5961 5962 static int hclge_fd_check_spec(struct hclge_dev *hdev, 5963 struct ethtool_rx_flow_spec *fs, 5964 u32 *unused_tuple, 5965 struct hclge_fd_user_def_info *info) 5966 { 5967 u32 flow_type; 5968 int ret; 5969 5970 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 5971 dev_err(&hdev->pdev->dev, 5972 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 5973 fs->location, 5974 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 5975 return -EINVAL; 5976 } 5977 5978 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 5979 if (ret) 5980 return ret; 5981 5982 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 5983 switch (flow_type) { 5984 case SCTP_V4_FLOW: 5985 case TCP_V4_FLOW: 5986 case UDP_V4_FLOW: 5987 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 5988 unused_tuple); 5989 break; 5990 case IP_USER_FLOW: 5991 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 5992 unused_tuple); 5993 break; 5994 case SCTP_V6_FLOW: 5995 case TCP_V6_FLOW: 5996 case UDP_V6_FLOW: 5997 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 5998 unused_tuple); 5999 break; 6000 case IPV6_USER_FLOW: 6001 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6002 unused_tuple); 6003 break; 6004 case ETHER_FLOW: 6005 if (hdev->fd_cfg.fd_mode != 6006 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6007 dev_err(&hdev->pdev->dev, 6008 "ETHER_FLOW is not supported in current fd mode!\n"); 6009 return -EOPNOTSUPP; 6010 } 6011 6012 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6013 unused_tuple); 6014 break; 6015 default: 6016 dev_err(&hdev->pdev->dev, 6017 "unsupported protocol type, protocol type = %#x\n", 6018 flow_type); 6019 return -EOPNOTSUPP; 6020 } 6021 6022 if (ret) { 6023 dev_err(&hdev->pdev->dev, 6024 "failed to check flow union tuple, ret = %d\n", 6025 ret); 6026 return ret; 6027 } 6028 6029 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6030 } 6031 6032 static void hclge_fd_get_tcpip4_tuple(struct hclge_dev *hdev, 6033 struct ethtool_rx_flow_spec *fs, 6034 struct hclge_fd_rule *rule, u8 ip_proto) 6035 { 6036 rule->tuples.src_ip[IPV4_INDEX] = 6037 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6038 rule->tuples_mask.src_ip[IPV4_INDEX] = 6039 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6040 6041 rule->tuples.dst_ip[IPV4_INDEX] = 6042 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6043 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6044 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6045 6046 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6047 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6048 6049 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6050 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6051 6052 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6053 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6054 6055 rule->tuples.ether_proto = ETH_P_IP; 6056 rule->tuples_mask.ether_proto = 0xFFFF; 6057 6058 rule->tuples.ip_proto = ip_proto; 6059 rule->tuples_mask.ip_proto = 0xFF; 6060 } 6061 6062 static void hclge_fd_get_ip4_tuple(struct hclge_dev *hdev, 6063 struct ethtool_rx_flow_spec *fs, 6064 struct hclge_fd_rule *rule) 6065 { 6066 rule->tuples.src_ip[IPV4_INDEX] = 6067 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6068 rule->tuples_mask.src_ip[IPV4_INDEX] = 6069 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6070 6071 rule->tuples.dst_ip[IPV4_INDEX] = 6072 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6073 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6074 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6075 6076 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6077 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6078 6079 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6080 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6081 6082 rule->tuples.ether_proto = ETH_P_IP; 6083 rule->tuples_mask.ether_proto = 0xFFFF; 6084 } 6085 6086 static void hclge_fd_get_tcpip6_tuple(struct hclge_dev *hdev, 6087 struct ethtool_rx_flow_spec *fs, 6088 struct hclge_fd_rule *rule, u8 ip_proto) 6089 { 6090 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6091 IPV6_SIZE); 6092 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6093 IPV6_SIZE); 6094 6095 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6096 IPV6_SIZE); 6097 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6098 IPV6_SIZE); 6099 6100 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6101 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6102 6103 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6104 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6105 6106 rule->tuples.ether_proto = ETH_P_IPV6; 6107 rule->tuples_mask.ether_proto = 0xFFFF; 6108 6109 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6110 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6111 6112 rule->tuples.ip_proto = ip_proto; 6113 rule->tuples_mask.ip_proto = 0xFF; 6114 } 6115 6116 static void hclge_fd_get_ip6_tuple(struct hclge_dev *hdev, 6117 struct ethtool_rx_flow_spec *fs, 6118 struct hclge_fd_rule *rule) 6119 { 6120 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6121 IPV6_SIZE); 6122 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6123 IPV6_SIZE); 6124 6125 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6126 IPV6_SIZE); 6127 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6128 IPV6_SIZE); 6129 6130 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6131 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6132 6133 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6134 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6135 6136 rule->tuples.ether_proto = ETH_P_IPV6; 6137 rule->tuples_mask.ether_proto = 0xFFFF; 6138 } 6139 6140 static void hclge_fd_get_ether_tuple(struct hclge_dev *hdev, 6141 struct ethtool_rx_flow_spec *fs, 6142 struct hclge_fd_rule *rule) 6143 { 6144 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6145 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6146 6147 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6148 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6149 6150 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6151 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6152 } 6153 6154 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6155 struct hclge_fd_rule *rule) 6156 { 6157 switch (info->layer) { 6158 case HCLGE_FD_USER_DEF_L2: 6159 rule->tuples.l2_user_def = info->data; 6160 rule->tuples_mask.l2_user_def = info->data_mask; 6161 break; 6162 case HCLGE_FD_USER_DEF_L3: 6163 rule->tuples.l3_user_def = info->data; 6164 rule->tuples_mask.l3_user_def = info->data_mask; 6165 break; 6166 case HCLGE_FD_USER_DEF_L4: 6167 rule->tuples.l4_user_def = (u32)info->data << 16; 6168 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6169 break; 6170 default: 6171 break; 6172 } 6173 6174 rule->ep.user_def = *info; 6175 } 6176 6177 static int hclge_fd_get_tuple(struct hclge_dev *hdev, 6178 struct ethtool_rx_flow_spec *fs, 6179 struct hclge_fd_rule *rule, 6180 struct hclge_fd_user_def_info *info) 6181 { 6182 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6183 6184 switch (flow_type) { 6185 case SCTP_V4_FLOW: 6186 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_SCTP); 6187 break; 6188 case TCP_V4_FLOW: 6189 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_TCP); 6190 break; 6191 case UDP_V4_FLOW: 6192 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_UDP); 6193 break; 6194 case IP_USER_FLOW: 6195 hclge_fd_get_ip4_tuple(hdev, fs, rule); 6196 break; 6197 case SCTP_V6_FLOW: 6198 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_SCTP); 6199 break; 6200 case TCP_V6_FLOW: 6201 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_TCP); 6202 break; 6203 case UDP_V6_FLOW: 6204 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_UDP); 6205 break; 6206 case IPV6_USER_FLOW: 6207 hclge_fd_get_ip6_tuple(hdev, fs, rule); 6208 break; 6209 case ETHER_FLOW: 6210 hclge_fd_get_ether_tuple(hdev, fs, rule); 6211 break; 6212 default: 6213 return -EOPNOTSUPP; 6214 } 6215 6216 if (fs->flow_type & FLOW_EXT) { 6217 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6218 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6219 hclge_fd_get_user_def_tuple(info, rule); 6220 } 6221 6222 if (fs->flow_type & FLOW_MAC_EXT) { 6223 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6224 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6225 } 6226 6227 return 0; 6228 } 6229 6230 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6231 struct hclge_fd_rule *rule) 6232 { 6233 int ret; 6234 6235 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6236 if (ret) 6237 return ret; 6238 6239 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6240 } 6241 6242 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6243 struct hclge_fd_rule *rule) 6244 { 6245 int ret; 6246 6247 spin_lock_bh(&hdev->fd_rule_lock); 6248 6249 if (hdev->fd_active_type != rule->rule_type && 6250 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6251 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6252 dev_err(&hdev->pdev->dev, 6253 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6254 rule->rule_type, hdev->fd_active_type); 6255 spin_unlock_bh(&hdev->fd_rule_lock); 6256 return -EINVAL; 6257 } 6258 6259 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6260 if (ret) 6261 goto out; 6262 6263 ret = hclge_clear_arfs_rules(hdev); 6264 if (ret) 6265 goto out; 6266 6267 ret = hclge_fd_config_rule(hdev, rule); 6268 if (ret) 6269 goto out; 6270 6271 rule->state = HCLGE_FD_ACTIVE; 6272 hdev->fd_active_type = rule->rule_type; 6273 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6274 6275 out: 6276 spin_unlock_bh(&hdev->fd_rule_lock); 6277 return ret; 6278 } 6279 6280 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6281 { 6282 struct hclge_vport *vport = hclge_get_vport(handle); 6283 struct hclge_dev *hdev = vport->back; 6284 6285 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6286 } 6287 6288 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6289 u16 *vport_id, u8 *action, u16 *queue_id) 6290 { 6291 struct hclge_vport *vport = hdev->vport; 6292 6293 if (ring_cookie == RX_CLS_FLOW_DISC) { 6294 *action = HCLGE_FD_ACTION_DROP_PACKET; 6295 } else { 6296 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6297 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6298 u16 tqps; 6299 6300 /* To keep consistent with user's configuration, minus 1 when 6301 * printing 'vf', because vf id from ethtool is added 1 for vf. 6302 */ 6303 if (vf > hdev->num_req_vfs) { 6304 dev_err(&hdev->pdev->dev, 6305 "Error: vf id (%u) should be less than %u\n", 6306 vf - 1U, hdev->num_req_vfs); 6307 return -EINVAL; 6308 } 6309 6310 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6311 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6312 6313 if (ring >= tqps) { 6314 dev_err(&hdev->pdev->dev, 6315 "Error: queue id (%u) > max tqp num (%u)\n", 6316 ring, tqps - 1U); 6317 return -EINVAL; 6318 } 6319 6320 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6321 *queue_id = ring; 6322 } 6323 6324 return 0; 6325 } 6326 6327 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6328 struct ethtool_rxnfc *cmd) 6329 { 6330 struct hclge_vport *vport = hclge_get_vport(handle); 6331 struct hclge_dev *hdev = vport->back; 6332 struct hclge_fd_user_def_info info; 6333 u16 dst_vport_id = 0, q_index = 0; 6334 struct ethtool_rx_flow_spec *fs; 6335 struct hclge_fd_rule *rule; 6336 u32 unused = 0; 6337 u8 action; 6338 int ret; 6339 6340 if (!hnae3_dev_fd_supported(hdev)) { 6341 dev_err(&hdev->pdev->dev, 6342 "flow table director is not supported\n"); 6343 return -EOPNOTSUPP; 6344 } 6345 6346 if (!hdev->fd_en) { 6347 dev_err(&hdev->pdev->dev, 6348 "please enable flow director first\n"); 6349 return -EOPNOTSUPP; 6350 } 6351 6352 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6353 6354 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6355 if (ret) 6356 return ret; 6357 6358 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6359 &action, &q_index); 6360 if (ret) 6361 return ret; 6362 6363 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6364 if (!rule) 6365 return -ENOMEM; 6366 6367 ret = hclge_fd_get_tuple(hdev, fs, rule, &info); 6368 if (ret) { 6369 kfree(rule); 6370 return ret; 6371 } 6372 6373 rule->flow_type = fs->flow_type; 6374 rule->location = fs->location; 6375 rule->unused_tuple = unused; 6376 rule->vf_id = dst_vport_id; 6377 rule->queue_id = q_index; 6378 rule->action = action; 6379 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6380 6381 ret = hclge_add_fd_entry_common(hdev, rule); 6382 if (ret) 6383 kfree(rule); 6384 6385 return ret; 6386 } 6387 6388 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6389 struct ethtool_rxnfc *cmd) 6390 { 6391 struct hclge_vport *vport = hclge_get_vport(handle); 6392 struct hclge_dev *hdev = vport->back; 6393 struct ethtool_rx_flow_spec *fs; 6394 int ret; 6395 6396 if (!hnae3_dev_fd_supported(hdev)) 6397 return -EOPNOTSUPP; 6398 6399 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6400 6401 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6402 return -EINVAL; 6403 6404 spin_lock_bh(&hdev->fd_rule_lock); 6405 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6406 !test_bit(fs->location, hdev->fd_bmap)) { 6407 dev_err(&hdev->pdev->dev, 6408 "Delete fail, rule %u is inexistent\n", fs->location); 6409 spin_unlock_bh(&hdev->fd_rule_lock); 6410 return -ENOENT; 6411 } 6412 6413 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6414 NULL, false); 6415 if (ret) 6416 goto out; 6417 6418 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6419 6420 out: 6421 spin_unlock_bh(&hdev->fd_rule_lock); 6422 return ret; 6423 } 6424 6425 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6426 bool clear_list) 6427 { 6428 struct hclge_fd_rule *rule; 6429 struct hlist_node *node; 6430 u16 location; 6431 6432 if (!hnae3_dev_fd_supported(hdev)) 6433 return; 6434 6435 spin_lock_bh(&hdev->fd_rule_lock); 6436 6437 for_each_set_bit(location, hdev->fd_bmap, 6438 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6439 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6440 NULL, false); 6441 6442 if (clear_list) { 6443 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6444 rule_node) { 6445 hlist_del(&rule->rule_node); 6446 kfree(rule); 6447 } 6448 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6449 hdev->hclge_fd_rule_num = 0; 6450 bitmap_zero(hdev->fd_bmap, 6451 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6452 } 6453 6454 spin_unlock_bh(&hdev->fd_rule_lock); 6455 } 6456 6457 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6458 { 6459 hclge_clear_fd_rules_in_list(hdev, true); 6460 hclge_fd_disable_user_def(hdev); 6461 } 6462 6463 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6464 { 6465 struct hclge_vport *vport = hclge_get_vport(handle); 6466 struct hclge_dev *hdev = vport->back; 6467 struct hclge_fd_rule *rule; 6468 struct hlist_node *node; 6469 6470 /* Return ok here, because reset error handling will check this 6471 * return value. If error is returned here, the reset process will 6472 * fail. 6473 */ 6474 if (!hnae3_dev_fd_supported(hdev)) 6475 return 0; 6476 6477 /* if fd is disabled, should not restore it when reset */ 6478 if (!hdev->fd_en) 6479 return 0; 6480 6481 spin_lock_bh(&hdev->fd_rule_lock); 6482 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6483 if (rule->state == HCLGE_FD_ACTIVE) 6484 rule->state = HCLGE_FD_TO_ADD; 6485 } 6486 spin_unlock_bh(&hdev->fd_rule_lock); 6487 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6488 6489 return 0; 6490 } 6491 6492 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6493 struct ethtool_rxnfc *cmd) 6494 { 6495 struct hclge_vport *vport = hclge_get_vport(handle); 6496 struct hclge_dev *hdev = vport->back; 6497 6498 if (!hnae3_dev_fd_supported(hdev) || hclge_is_cls_flower_active(handle)) 6499 return -EOPNOTSUPP; 6500 6501 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6502 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6503 6504 return 0; 6505 } 6506 6507 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6508 struct ethtool_tcpip4_spec *spec, 6509 struct ethtool_tcpip4_spec *spec_mask) 6510 { 6511 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6512 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6513 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6514 6515 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6516 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6517 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6518 6519 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6520 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6521 0 : cpu_to_be16(rule->tuples_mask.src_port); 6522 6523 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6524 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6525 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6526 6527 spec->tos = rule->tuples.ip_tos; 6528 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6529 0 : rule->tuples_mask.ip_tos; 6530 } 6531 6532 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6533 struct ethtool_usrip4_spec *spec, 6534 struct ethtool_usrip4_spec *spec_mask) 6535 { 6536 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6537 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6538 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6539 6540 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6541 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6542 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6543 6544 spec->tos = rule->tuples.ip_tos; 6545 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6546 0 : rule->tuples_mask.ip_tos; 6547 6548 spec->proto = rule->tuples.ip_proto; 6549 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6550 0 : rule->tuples_mask.ip_proto; 6551 6552 spec->ip_ver = ETH_RX_NFC_IP4; 6553 } 6554 6555 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6556 struct ethtool_tcpip6_spec *spec, 6557 struct ethtool_tcpip6_spec *spec_mask) 6558 { 6559 cpu_to_be32_array(spec->ip6src, 6560 rule->tuples.src_ip, IPV6_SIZE); 6561 cpu_to_be32_array(spec->ip6dst, 6562 rule->tuples.dst_ip, IPV6_SIZE); 6563 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6564 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6565 else 6566 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6567 IPV6_SIZE); 6568 6569 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6570 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6571 else 6572 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6573 IPV6_SIZE); 6574 6575 spec->tclass = rule->tuples.ip_tos; 6576 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6577 0 : rule->tuples_mask.ip_tos; 6578 6579 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6580 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6581 0 : cpu_to_be16(rule->tuples_mask.src_port); 6582 6583 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6584 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6585 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6586 } 6587 6588 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6589 struct ethtool_usrip6_spec *spec, 6590 struct ethtool_usrip6_spec *spec_mask) 6591 { 6592 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6593 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6594 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6595 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6596 else 6597 cpu_to_be32_array(spec_mask->ip6src, 6598 rule->tuples_mask.src_ip, IPV6_SIZE); 6599 6600 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6601 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6602 else 6603 cpu_to_be32_array(spec_mask->ip6dst, 6604 rule->tuples_mask.dst_ip, IPV6_SIZE); 6605 6606 spec->tclass = rule->tuples.ip_tos; 6607 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6608 0 : rule->tuples_mask.ip_tos; 6609 6610 spec->l4_proto = rule->tuples.ip_proto; 6611 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6612 0 : rule->tuples_mask.ip_proto; 6613 } 6614 6615 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6616 struct ethhdr *spec, 6617 struct ethhdr *spec_mask) 6618 { 6619 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6620 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6621 6622 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6623 eth_zero_addr(spec_mask->h_source); 6624 else 6625 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6626 6627 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6628 eth_zero_addr(spec_mask->h_dest); 6629 else 6630 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6631 6632 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6633 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6634 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6635 } 6636 6637 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6638 struct hclge_fd_rule *rule) 6639 { 6640 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6641 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6642 fs->h_ext.data[0] = 0; 6643 fs->h_ext.data[1] = 0; 6644 fs->m_ext.data[0] = 0; 6645 fs->m_ext.data[1] = 0; 6646 } else { 6647 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6648 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6649 fs->m_ext.data[0] = 6650 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6651 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6652 } 6653 } 6654 6655 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6656 struct hclge_fd_rule *rule) 6657 { 6658 if (fs->flow_type & FLOW_EXT) { 6659 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6660 fs->m_ext.vlan_tci = 6661 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6662 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6663 6664 hclge_fd_get_user_def_info(fs, rule); 6665 } 6666 6667 if (fs->flow_type & FLOW_MAC_EXT) { 6668 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6669 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6670 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6671 else 6672 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6673 rule->tuples_mask.dst_mac); 6674 } 6675 } 6676 6677 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6678 u16 location) 6679 { 6680 struct hclge_fd_rule *rule = NULL; 6681 struct hlist_node *node2; 6682 6683 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6684 if (rule->location == location) 6685 return rule; 6686 else if (rule->location > location) 6687 return NULL; 6688 } 6689 6690 return NULL; 6691 } 6692 6693 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6694 struct hclge_fd_rule *rule) 6695 { 6696 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6697 fs->ring_cookie = RX_CLS_FLOW_DISC; 6698 } else { 6699 u64 vf_id; 6700 6701 fs->ring_cookie = rule->queue_id; 6702 vf_id = rule->vf_id; 6703 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6704 fs->ring_cookie |= vf_id; 6705 } 6706 } 6707 6708 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6709 struct ethtool_rxnfc *cmd) 6710 { 6711 struct hclge_vport *vport = hclge_get_vport(handle); 6712 struct hclge_fd_rule *rule = NULL; 6713 struct hclge_dev *hdev = vport->back; 6714 struct ethtool_rx_flow_spec *fs; 6715 6716 if (!hnae3_dev_fd_supported(hdev)) 6717 return -EOPNOTSUPP; 6718 6719 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6720 6721 spin_lock_bh(&hdev->fd_rule_lock); 6722 6723 rule = hclge_get_fd_rule(hdev, fs->location); 6724 if (!rule) { 6725 spin_unlock_bh(&hdev->fd_rule_lock); 6726 return -ENOENT; 6727 } 6728 6729 fs->flow_type = rule->flow_type; 6730 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6731 case SCTP_V4_FLOW: 6732 case TCP_V4_FLOW: 6733 case UDP_V4_FLOW: 6734 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6735 &fs->m_u.tcp_ip4_spec); 6736 break; 6737 case IP_USER_FLOW: 6738 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6739 &fs->m_u.usr_ip4_spec); 6740 break; 6741 case SCTP_V6_FLOW: 6742 case TCP_V6_FLOW: 6743 case UDP_V6_FLOW: 6744 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6745 &fs->m_u.tcp_ip6_spec); 6746 break; 6747 case IPV6_USER_FLOW: 6748 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6749 &fs->m_u.usr_ip6_spec); 6750 break; 6751 /* The flow type of fd rule has been checked before adding in to rule 6752 * list. As other flow types have been handled, it must be ETHER_FLOW 6753 * for the default case 6754 */ 6755 default: 6756 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6757 &fs->m_u.ether_spec); 6758 break; 6759 } 6760 6761 hclge_fd_get_ext_info(fs, rule); 6762 6763 hclge_fd_get_ring_cookie(fs, rule); 6764 6765 spin_unlock_bh(&hdev->fd_rule_lock); 6766 6767 return 0; 6768 } 6769 6770 static int hclge_get_all_rules(struct hnae3_handle *handle, 6771 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6772 { 6773 struct hclge_vport *vport = hclge_get_vport(handle); 6774 struct hclge_dev *hdev = vport->back; 6775 struct hclge_fd_rule *rule; 6776 struct hlist_node *node2; 6777 int cnt = 0; 6778 6779 if (!hnae3_dev_fd_supported(hdev)) 6780 return -EOPNOTSUPP; 6781 6782 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6783 6784 spin_lock_bh(&hdev->fd_rule_lock); 6785 hlist_for_each_entry_safe(rule, node2, 6786 &hdev->fd_rule_list, rule_node) { 6787 if (cnt == cmd->rule_cnt) { 6788 spin_unlock_bh(&hdev->fd_rule_lock); 6789 return -EMSGSIZE; 6790 } 6791 6792 if (rule->state == HCLGE_FD_TO_DEL) 6793 continue; 6794 6795 rule_locs[cnt] = rule->location; 6796 cnt++; 6797 } 6798 6799 spin_unlock_bh(&hdev->fd_rule_lock); 6800 6801 cmd->rule_cnt = cnt; 6802 6803 return 0; 6804 } 6805 6806 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 6807 struct hclge_fd_rule_tuples *tuples) 6808 { 6809 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 6810 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 6811 6812 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 6813 tuples->ip_proto = fkeys->basic.ip_proto; 6814 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 6815 6816 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 6817 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 6818 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 6819 } else { 6820 int i; 6821 6822 for (i = 0; i < IPV6_SIZE; i++) { 6823 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 6824 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 6825 } 6826 } 6827 } 6828 6829 /* traverse all rules, check whether an existed rule has the same tuples */ 6830 static struct hclge_fd_rule * 6831 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 6832 const struct hclge_fd_rule_tuples *tuples) 6833 { 6834 struct hclge_fd_rule *rule = NULL; 6835 struct hlist_node *node; 6836 6837 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6838 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 6839 return rule; 6840 } 6841 6842 return NULL; 6843 } 6844 6845 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 6846 struct hclge_fd_rule *rule) 6847 { 6848 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6849 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 6850 BIT(INNER_SRC_PORT); 6851 rule->action = 0; 6852 rule->vf_id = 0; 6853 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 6854 rule->state = HCLGE_FD_TO_ADD; 6855 if (tuples->ether_proto == ETH_P_IP) { 6856 if (tuples->ip_proto == IPPROTO_TCP) 6857 rule->flow_type = TCP_V4_FLOW; 6858 else 6859 rule->flow_type = UDP_V4_FLOW; 6860 } else { 6861 if (tuples->ip_proto == IPPROTO_TCP) 6862 rule->flow_type = TCP_V6_FLOW; 6863 else 6864 rule->flow_type = UDP_V6_FLOW; 6865 } 6866 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 6867 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 6868 } 6869 6870 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 6871 u16 flow_id, struct flow_keys *fkeys) 6872 { 6873 struct hclge_vport *vport = hclge_get_vport(handle); 6874 struct hclge_fd_rule_tuples new_tuples = {}; 6875 struct hclge_dev *hdev = vport->back; 6876 struct hclge_fd_rule *rule; 6877 u16 bit_id; 6878 6879 if (!hnae3_dev_fd_supported(hdev)) 6880 return -EOPNOTSUPP; 6881 6882 /* when there is already fd rule existed add by user, 6883 * arfs should not work 6884 */ 6885 spin_lock_bh(&hdev->fd_rule_lock); 6886 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 6887 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 6888 spin_unlock_bh(&hdev->fd_rule_lock); 6889 return -EOPNOTSUPP; 6890 } 6891 6892 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 6893 6894 /* check is there flow director filter existed for this flow, 6895 * if not, create a new filter for it; 6896 * if filter exist with different queue id, modify the filter; 6897 * if filter exist with same queue id, do nothing 6898 */ 6899 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 6900 if (!rule) { 6901 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 6902 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6903 spin_unlock_bh(&hdev->fd_rule_lock); 6904 return -ENOSPC; 6905 } 6906 6907 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 6908 if (!rule) { 6909 spin_unlock_bh(&hdev->fd_rule_lock); 6910 return -ENOMEM; 6911 } 6912 6913 rule->location = bit_id; 6914 rule->arfs.flow_id = flow_id; 6915 rule->queue_id = queue_id; 6916 hclge_fd_build_arfs_rule(&new_tuples, rule); 6917 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6918 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 6919 } else if (rule->queue_id != queue_id) { 6920 rule->queue_id = queue_id; 6921 rule->state = HCLGE_FD_TO_ADD; 6922 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6923 hclge_task_schedule(hdev, 0); 6924 } 6925 spin_unlock_bh(&hdev->fd_rule_lock); 6926 return rule->location; 6927 } 6928 6929 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 6930 { 6931 #ifdef CONFIG_RFS_ACCEL 6932 struct hnae3_handle *handle = &hdev->vport[0].nic; 6933 struct hclge_fd_rule *rule; 6934 struct hlist_node *node; 6935 6936 spin_lock_bh(&hdev->fd_rule_lock); 6937 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 6938 spin_unlock_bh(&hdev->fd_rule_lock); 6939 return; 6940 } 6941 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6942 if (rule->state != HCLGE_FD_ACTIVE) 6943 continue; 6944 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 6945 rule->arfs.flow_id, rule->location)) { 6946 rule->state = HCLGE_FD_TO_DEL; 6947 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6948 } 6949 } 6950 spin_unlock_bh(&hdev->fd_rule_lock); 6951 #endif 6952 } 6953 6954 /* make sure being called after lock up with fd_rule_lock */ 6955 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 6956 { 6957 #ifdef CONFIG_RFS_ACCEL 6958 struct hclge_fd_rule *rule; 6959 struct hlist_node *node; 6960 int ret; 6961 6962 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 6963 return 0; 6964 6965 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6966 switch (rule->state) { 6967 case HCLGE_FD_TO_DEL: 6968 case HCLGE_FD_ACTIVE: 6969 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 6970 rule->location, NULL, false); 6971 if (ret) 6972 return ret; 6973 fallthrough; 6974 case HCLGE_FD_TO_ADD: 6975 hclge_fd_dec_rule_cnt(hdev, rule->location); 6976 hlist_del(&rule->rule_node); 6977 kfree(rule); 6978 break; 6979 default: 6980 break; 6981 } 6982 } 6983 hclge_sync_fd_state(hdev); 6984 6985 #endif 6986 return 0; 6987 } 6988 6989 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 6990 struct hclge_fd_rule *rule) 6991 { 6992 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 6993 struct flow_match_basic match; 6994 u16 ethtype_key, ethtype_mask; 6995 6996 flow_rule_match_basic(flow, &match); 6997 ethtype_key = ntohs(match.key->n_proto); 6998 ethtype_mask = ntohs(match.mask->n_proto); 6999 7000 if (ethtype_key == ETH_P_ALL) { 7001 ethtype_key = 0; 7002 ethtype_mask = 0; 7003 } 7004 rule->tuples.ether_proto = ethtype_key; 7005 rule->tuples_mask.ether_proto = ethtype_mask; 7006 rule->tuples.ip_proto = match.key->ip_proto; 7007 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7008 } else { 7009 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7010 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7011 } 7012 } 7013 7014 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7015 struct hclge_fd_rule *rule) 7016 { 7017 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7018 struct flow_match_eth_addrs match; 7019 7020 flow_rule_match_eth_addrs(flow, &match); 7021 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7022 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7023 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7024 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7025 } else { 7026 rule->unused_tuple |= BIT(INNER_DST_MAC); 7027 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7028 } 7029 } 7030 7031 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7032 struct hclge_fd_rule *rule) 7033 { 7034 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7035 struct flow_match_vlan match; 7036 7037 flow_rule_match_vlan(flow, &match); 7038 rule->tuples.vlan_tag1 = match.key->vlan_id | 7039 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7040 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7041 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7042 } else { 7043 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7044 } 7045 } 7046 7047 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7048 struct hclge_fd_rule *rule) 7049 { 7050 u16 addr_type = 0; 7051 7052 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7053 struct flow_match_control match; 7054 7055 flow_rule_match_control(flow, &match); 7056 addr_type = match.key->addr_type; 7057 } 7058 7059 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7060 struct flow_match_ipv4_addrs match; 7061 7062 flow_rule_match_ipv4_addrs(flow, &match); 7063 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7064 rule->tuples_mask.src_ip[IPV4_INDEX] = 7065 be32_to_cpu(match.mask->src); 7066 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7067 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7068 be32_to_cpu(match.mask->dst); 7069 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7070 struct flow_match_ipv6_addrs match; 7071 7072 flow_rule_match_ipv6_addrs(flow, &match); 7073 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7074 IPV6_SIZE); 7075 be32_to_cpu_array(rule->tuples_mask.src_ip, 7076 match.mask->src.s6_addr32, IPV6_SIZE); 7077 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7078 IPV6_SIZE); 7079 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7080 match.mask->dst.s6_addr32, IPV6_SIZE); 7081 } else { 7082 rule->unused_tuple |= BIT(INNER_SRC_IP); 7083 rule->unused_tuple |= BIT(INNER_DST_IP); 7084 } 7085 } 7086 7087 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7088 struct hclge_fd_rule *rule) 7089 { 7090 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7091 struct flow_match_ports match; 7092 7093 flow_rule_match_ports(flow, &match); 7094 7095 rule->tuples.src_port = be16_to_cpu(match.key->src); 7096 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7097 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7098 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7099 } else { 7100 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7101 rule->unused_tuple |= BIT(INNER_DST_PORT); 7102 } 7103 } 7104 7105 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7106 struct flow_cls_offload *cls_flower, 7107 struct hclge_fd_rule *rule) 7108 { 7109 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7110 struct flow_dissector *dissector = flow->match.dissector; 7111 7112 if (dissector->used_keys & 7113 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 7114 BIT(FLOW_DISSECTOR_KEY_BASIC) | 7115 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7116 BIT(FLOW_DISSECTOR_KEY_VLAN) | 7117 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7118 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7119 BIT(FLOW_DISSECTOR_KEY_PORTS))) { 7120 dev_err(&hdev->pdev->dev, "unsupported key set: %#x\n", 7121 dissector->used_keys); 7122 return -EOPNOTSUPP; 7123 } 7124 7125 hclge_get_cls_key_basic(flow, rule); 7126 hclge_get_cls_key_mac(flow, rule); 7127 hclge_get_cls_key_vlan(flow, rule); 7128 hclge_get_cls_key_ip(flow, rule); 7129 hclge_get_cls_key_port(flow, rule); 7130 7131 return 0; 7132 } 7133 7134 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7135 struct flow_cls_offload *cls_flower, int tc) 7136 { 7137 u32 prio = cls_flower->common.prio; 7138 7139 if (tc < 0 || tc > hdev->tc_max) { 7140 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7141 return -EINVAL; 7142 } 7143 7144 if (prio == 0 || 7145 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7146 dev_err(&hdev->pdev->dev, 7147 "prio %u should be in range[1, %u]\n", 7148 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7149 return -EINVAL; 7150 } 7151 7152 if (test_bit(prio - 1, hdev->fd_bmap)) { 7153 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7154 return -EINVAL; 7155 } 7156 return 0; 7157 } 7158 7159 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7160 struct flow_cls_offload *cls_flower, 7161 int tc) 7162 { 7163 struct hclge_vport *vport = hclge_get_vport(handle); 7164 struct hclge_dev *hdev = vport->back; 7165 struct hclge_fd_rule *rule; 7166 int ret; 7167 7168 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7169 if (ret) { 7170 dev_err(&hdev->pdev->dev, 7171 "failed to check cls flower params, ret = %d\n", ret); 7172 return ret; 7173 } 7174 7175 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7176 if (!rule) 7177 return -ENOMEM; 7178 7179 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7180 if (ret) { 7181 kfree(rule); 7182 return ret; 7183 } 7184 7185 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7186 rule->cls_flower.tc = tc; 7187 rule->location = cls_flower->common.prio - 1; 7188 rule->vf_id = 0; 7189 rule->cls_flower.cookie = cls_flower->cookie; 7190 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7191 7192 ret = hclge_add_fd_entry_common(hdev, rule); 7193 if (ret) 7194 kfree(rule); 7195 7196 return ret; 7197 } 7198 7199 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7200 unsigned long cookie) 7201 { 7202 struct hclge_fd_rule *rule; 7203 struct hlist_node *node; 7204 7205 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7206 if (rule->cls_flower.cookie == cookie) 7207 return rule; 7208 } 7209 7210 return NULL; 7211 } 7212 7213 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7214 struct flow_cls_offload *cls_flower) 7215 { 7216 struct hclge_vport *vport = hclge_get_vport(handle); 7217 struct hclge_dev *hdev = vport->back; 7218 struct hclge_fd_rule *rule; 7219 int ret; 7220 7221 spin_lock_bh(&hdev->fd_rule_lock); 7222 7223 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7224 if (!rule) { 7225 spin_unlock_bh(&hdev->fd_rule_lock); 7226 return -EINVAL; 7227 } 7228 7229 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7230 NULL, false); 7231 if (ret) { 7232 spin_unlock_bh(&hdev->fd_rule_lock); 7233 return ret; 7234 } 7235 7236 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7237 spin_unlock_bh(&hdev->fd_rule_lock); 7238 7239 return 0; 7240 } 7241 7242 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7243 { 7244 struct hclge_fd_rule *rule; 7245 struct hlist_node *node; 7246 int ret = 0; 7247 7248 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7249 return; 7250 7251 spin_lock_bh(&hdev->fd_rule_lock); 7252 7253 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7254 switch (rule->state) { 7255 case HCLGE_FD_TO_ADD: 7256 ret = hclge_fd_config_rule(hdev, rule); 7257 if (ret) 7258 goto out; 7259 rule->state = HCLGE_FD_ACTIVE; 7260 break; 7261 case HCLGE_FD_TO_DEL: 7262 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7263 rule->location, NULL, false); 7264 if (ret) 7265 goto out; 7266 hclge_fd_dec_rule_cnt(hdev, rule->location); 7267 hclge_fd_free_node(hdev, rule); 7268 break; 7269 default: 7270 break; 7271 } 7272 } 7273 7274 out: 7275 if (ret) 7276 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7277 7278 spin_unlock_bh(&hdev->fd_rule_lock); 7279 } 7280 7281 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7282 { 7283 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7284 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7285 7286 hclge_clear_fd_rules_in_list(hdev, clear_list); 7287 } 7288 7289 hclge_sync_fd_user_def_cfg(hdev, false); 7290 7291 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7292 } 7293 7294 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7295 { 7296 struct hclge_vport *vport = hclge_get_vport(handle); 7297 struct hclge_dev *hdev = vport->back; 7298 7299 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7300 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7301 } 7302 7303 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7304 { 7305 struct hclge_vport *vport = hclge_get_vport(handle); 7306 struct hclge_dev *hdev = vport->back; 7307 7308 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7309 } 7310 7311 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7312 { 7313 struct hclge_vport *vport = hclge_get_vport(handle); 7314 struct hclge_dev *hdev = vport->back; 7315 7316 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7317 } 7318 7319 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7320 { 7321 struct hclge_vport *vport = hclge_get_vport(handle); 7322 struct hclge_dev *hdev = vport->back; 7323 7324 return hdev->rst_stats.hw_reset_done_cnt; 7325 } 7326 7327 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7328 { 7329 struct hclge_vport *vport = hclge_get_vport(handle); 7330 struct hclge_dev *hdev = vport->back; 7331 7332 hdev->fd_en = enable; 7333 7334 if (!enable) 7335 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7336 else 7337 hclge_restore_fd_entries(handle); 7338 7339 hclge_task_schedule(hdev, 0); 7340 } 7341 7342 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7343 { 7344 struct hclge_desc desc; 7345 struct hclge_config_mac_mode_cmd *req = 7346 (struct hclge_config_mac_mode_cmd *)desc.data; 7347 u32 loop_en = 0; 7348 int ret; 7349 7350 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7351 7352 if (enable) { 7353 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7354 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7355 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7356 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7357 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7358 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7359 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7360 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7361 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7362 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7363 } 7364 7365 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7366 7367 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7368 if (ret) 7369 dev_err(&hdev->pdev->dev, 7370 "mac enable fail, ret =%d.\n", ret); 7371 } 7372 7373 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7374 u8 switch_param, u8 param_mask) 7375 { 7376 struct hclge_mac_vlan_switch_cmd *req; 7377 struct hclge_desc desc; 7378 u32 func_id; 7379 int ret; 7380 7381 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7382 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7383 7384 /* read current config parameter */ 7385 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7386 true); 7387 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7388 req->func_id = cpu_to_le32(func_id); 7389 7390 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7391 if (ret) { 7392 dev_err(&hdev->pdev->dev, 7393 "read mac vlan switch parameter fail, ret = %d\n", ret); 7394 return ret; 7395 } 7396 7397 /* modify and write new config parameter */ 7398 hclge_comm_cmd_reuse_desc(&desc, false); 7399 req->switch_param = (req->switch_param & param_mask) | switch_param; 7400 req->param_mask = param_mask; 7401 7402 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7403 if (ret) 7404 dev_err(&hdev->pdev->dev, 7405 "set mac vlan switch parameter fail, ret = %d\n", ret); 7406 return ret; 7407 } 7408 7409 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7410 int link_ret) 7411 { 7412 #define HCLGE_PHY_LINK_STATUS_NUM 200 7413 7414 struct phy_device *phydev = hdev->hw.mac.phydev; 7415 int i = 0; 7416 int ret; 7417 7418 do { 7419 ret = phy_read_status(phydev); 7420 if (ret) { 7421 dev_err(&hdev->pdev->dev, 7422 "phy update link status fail, ret = %d\n", ret); 7423 return; 7424 } 7425 7426 if (phydev->link == link_ret) 7427 break; 7428 7429 msleep(HCLGE_LINK_STATUS_MS); 7430 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7431 } 7432 7433 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret) 7434 { 7435 #define HCLGE_MAC_LINK_STATUS_NUM 100 7436 7437 int link_status; 7438 int i = 0; 7439 int ret; 7440 7441 do { 7442 ret = hclge_get_mac_link_status(hdev, &link_status); 7443 if (ret) 7444 return ret; 7445 if (link_status == link_ret) 7446 return 0; 7447 7448 msleep(HCLGE_LINK_STATUS_MS); 7449 } while (++i < HCLGE_MAC_LINK_STATUS_NUM); 7450 return -EBUSY; 7451 } 7452 7453 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7454 bool is_phy) 7455 { 7456 int link_ret; 7457 7458 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7459 7460 if (is_phy) 7461 hclge_phy_link_status_wait(hdev, link_ret); 7462 7463 return hclge_mac_link_status_wait(hdev, link_ret); 7464 } 7465 7466 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7467 { 7468 struct hclge_config_mac_mode_cmd *req; 7469 struct hclge_desc desc; 7470 u32 loop_en; 7471 int ret; 7472 7473 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7474 /* 1 Read out the MAC mode config at first */ 7475 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7476 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7477 if (ret) { 7478 dev_err(&hdev->pdev->dev, 7479 "mac loopback get fail, ret =%d.\n", ret); 7480 return ret; 7481 } 7482 7483 /* 2 Then setup the loopback flag */ 7484 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7485 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7486 7487 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7488 7489 /* 3 Config mac work mode with loopback flag 7490 * and its original configure parameters 7491 */ 7492 hclge_comm_cmd_reuse_desc(&desc, false); 7493 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7494 if (ret) 7495 dev_err(&hdev->pdev->dev, 7496 "mac loopback set fail, ret =%d.\n", ret); 7497 return ret; 7498 } 7499 7500 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7501 enum hnae3_loop loop_mode) 7502 { 7503 struct hclge_common_lb_cmd *req; 7504 struct hclge_desc desc; 7505 u8 loop_mode_b; 7506 int ret; 7507 7508 req = (struct hclge_common_lb_cmd *)desc.data; 7509 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7510 7511 switch (loop_mode) { 7512 case HNAE3_LOOP_SERIAL_SERDES: 7513 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7514 break; 7515 case HNAE3_LOOP_PARALLEL_SERDES: 7516 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7517 break; 7518 case HNAE3_LOOP_PHY: 7519 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7520 break; 7521 default: 7522 dev_err(&hdev->pdev->dev, 7523 "unsupported loopback mode %d\n", loop_mode); 7524 return -ENOTSUPP; 7525 } 7526 7527 req->mask = loop_mode_b; 7528 if (en) 7529 req->enable = loop_mode_b; 7530 7531 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7532 if (ret) 7533 dev_err(&hdev->pdev->dev, 7534 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7535 loop_mode, ret); 7536 7537 return ret; 7538 } 7539 7540 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7541 { 7542 #define HCLGE_COMMON_LB_RETRY_MS 10 7543 #define HCLGE_COMMON_LB_RETRY_NUM 100 7544 7545 struct hclge_common_lb_cmd *req; 7546 struct hclge_desc desc; 7547 u32 i = 0; 7548 int ret; 7549 7550 req = (struct hclge_common_lb_cmd *)desc.data; 7551 7552 do { 7553 msleep(HCLGE_COMMON_LB_RETRY_MS); 7554 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7555 true); 7556 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7557 if (ret) { 7558 dev_err(&hdev->pdev->dev, 7559 "failed to get loopback done status, ret = %d\n", 7560 ret); 7561 return ret; 7562 } 7563 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7564 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7565 7566 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7567 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7568 return -EBUSY; 7569 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7570 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7571 return -EIO; 7572 } 7573 7574 return 0; 7575 } 7576 7577 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7578 enum hnae3_loop loop_mode) 7579 { 7580 int ret; 7581 7582 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7583 if (ret) 7584 return ret; 7585 7586 return hclge_cfg_common_loopback_wait(hdev); 7587 } 7588 7589 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7590 enum hnae3_loop loop_mode) 7591 { 7592 int ret; 7593 7594 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7595 if (ret) 7596 return ret; 7597 7598 hclge_cfg_mac_mode(hdev, en); 7599 7600 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7601 if (ret) 7602 dev_err(&hdev->pdev->dev, 7603 "serdes loopback config mac mode timeout\n"); 7604 7605 return ret; 7606 } 7607 7608 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7609 struct phy_device *phydev) 7610 { 7611 int ret; 7612 7613 if (!phydev->suspended) { 7614 ret = phy_suspend(phydev); 7615 if (ret) 7616 return ret; 7617 } 7618 7619 ret = phy_resume(phydev); 7620 if (ret) 7621 return ret; 7622 7623 return phy_loopback(phydev, true); 7624 } 7625 7626 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7627 struct phy_device *phydev) 7628 { 7629 int ret; 7630 7631 ret = phy_loopback(phydev, false); 7632 if (ret) 7633 return ret; 7634 7635 return phy_suspend(phydev); 7636 } 7637 7638 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7639 { 7640 struct phy_device *phydev = hdev->hw.mac.phydev; 7641 int ret; 7642 7643 if (!phydev) { 7644 if (hnae3_dev_phy_imp_supported(hdev)) 7645 return hclge_set_common_loopback(hdev, en, 7646 HNAE3_LOOP_PHY); 7647 return -ENOTSUPP; 7648 } 7649 7650 if (en) 7651 ret = hclge_enable_phy_loopback(hdev, phydev); 7652 else 7653 ret = hclge_disable_phy_loopback(hdev, phydev); 7654 if (ret) { 7655 dev_err(&hdev->pdev->dev, 7656 "set phy loopback fail, ret = %d\n", ret); 7657 return ret; 7658 } 7659 7660 hclge_cfg_mac_mode(hdev, en); 7661 7662 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7663 if (ret) 7664 dev_err(&hdev->pdev->dev, 7665 "phy loopback config mac mode timeout\n"); 7666 7667 return ret; 7668 } 7669 7670 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7671 u16 stream_id, bool enable) 7672 { 7673 struct hclge_desc desc; 7674 struct hclge_cfg_com_tqp_queue_cmd *req = 7675 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7676 7677 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7678 req->tqp_id = cpu_to_le16(tqp_id); 7679 req->stream_id = cpu_to_le16(stream_id); 7680 if (enable) 7681 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7682 7683 return hclge_cmd_send(&hdev->hw, &desc, 1); 7684 } 7685 7686 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7687 { 7688 struct hclge_vport *vport = hclge_get_vport(handle); 7689 struct hclge_dev *hdev = vport->back; 7690 int ret; 7691 u16 i; 7692 7693 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7694 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7695 if (ret) 7696 return ret; 7697 } 7698 return 0; 7699 } 7700 7701 static int hclge_set_loopback(struct hnae3_handle *handle, 7702 enum hnae3_loop loop_mode, bool en) 7703 { 7704 struct hclge_vport *vport = hclge_get_vport(handle); 7705 struct hclge_dev *hdev = vport->back; 7706 int ret; 7707 7708 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7709 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7710 * the same, the packets are looped back in the SSU. If SSU loopback 7711 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7712 */ 7713 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7714 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7715 7716 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7717 HCLGE_SWITCH_ALW_LPBK_MASK); 7718 if (ret) 7719 return ret; 7720 } 7721 7722 switch (loop_mode) { 7723 case HNAE3_LOOP_APP: 7724 ret = hclge_set_app_loopback(hdev, en); 7725 break; 7726 case HNAE3_LOOP_SERIAL_SERDES: 7727 case HNAE3_LOOP_PARALLEL_SERDES: 7728 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7729 break; 7730 case HNAE3_LOOP_PHY: 7731 ret = hclge_set_phy_loopback(hdev, en); 7732 break; 7733 default: 7734 ret = -ENOTSUPP; 7735 dev_err(&hdev->pdev->dev, 7736 "loop_mode %d is not supported\n", loop_mode); 7737 break; 7738 } 7739 7740 if (ret) 7741 return ret; 7742 7743 ret = hclge_tqp_enable(handle, en); 7744 if (ret) 7745 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7746 en ? "enable" : "disable", ret); 7747 7748 return ret; 7749 } 7750 7751 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7752 { 7753 int ret; 7754 7755 ret = hclge_set_app_loopback(hdev, false); 7756 if (ret) 7757 return ret; 7758 7759 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7760 if (ret) 7761 return ret; 7762 7763 return hclge_cfg_common_loopback(hdev, false, 7764 HNAE3_LOOP_PARALLEL_SERDES); 7765 } 7766 7767 static void hclge_flush_link_update(struct hclge_dev *hdev) 7768 { 7769 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7770 7771 unsigned long last = hdev->serv_processed_cnt; 7772 int i = 0; 7773 7774 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7775 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7776 last == hdev->serv_processed_cnt) 7777 usleep_range(1, 1); 7778 } 7779 7780 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 7781 { 7782 struct hclge_vport *vport = hclge_get_vport(handle); 7783 struct hclge_dev *hdev = vport->back; 7784 7785 if (enable) { 7786 hclge_task_schedule(hdev, 0); 7787 } else { 7788 /* Set the DOWN flag here to disable link updating */ 7789 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7790 7791 /* flush memory to make sure DOWN is seen by service task */ 7792 smp_mb__before_atomic(); 7793 hclge_flush_link_update(hdev); 7794 } 7795 } 7796 7797 static int hclge_ae_start(struct hnae3_handle *handle) 7798 { 7799 struct hclge_vport *vport = hclge_get_vport(handle); 7800 struct hclge_dev *hdev = vport->back; 7801 7802 /* mac enable */ 7803 hclge_cfg_mac_mode(hdev, true); 7804 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 7805 hdev->hw.mac.link = 0; 7806 7807 /* reset tqp stats */ 7808 hclge_comm_reset_tqp_stats(handle); 7809 7810 hclge_mac_start_phy(hdev); 7811 7812 return 0; 7813 } 7814 7815 static void hclge_ae_stop(struct hnae3_handle *handle) 7816 { 7817 struct hclge_vport *vport = hclge_get_vport(handle); 7818 struct hclge_dev *hdev = vport->back; 7819 7820 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7821 spin_lock_bh(&hdev->fd_rule_lock); 7822 hclge_clear_arfs_rules(hdev); 7823 spin_unlock_bh(&hdev->fd_rule_lock); 7824 7825 /* If it is not PF reset or FLR, the firmware will disable the MAC, 7826 * so it only need to stop phy here. 7827 */ 7828 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) && 7829 hdev->reset_type != HNAE3_FUNC_RESET && 7830 hdev->reset_type != HNAE3_FLR_RESET) { 7831 hclge_mac_stop_phy(hdev); 7832 hclge_update_link_status(hdev); 7833 return; 7834 } 7835 7836 hclge_reset_tqp(handle); 7837 7838 hclge_config_mac_tnl_int(hdev, false); 7839 7840 /* Mac disable */ 7841 hclge_cfg_mac_mode(hdev, false); 7842 7843 hclge_mac_stop_phy(hdev); 7844 7845 /* reset tqp stats */ 7846 hclge_comm_reset_tqp_stats(handle); 7847 hclge_update_link_status(hdev); 7848 } 7849 7850 int hclge_vport_start(struct hclge_vport *vport) 7851 { 7852 struct hclge_dev *hdev = vport->back; 7853 7854 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 7855 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 7856 vport->last_active_jiffies = jiffies; 7857 7858 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 7859 if (vport->vport_id) { 7860 hclge_restore_mac_table_common(vport); 7861 hclge_restore_vport_vlan_table(vport); 7862 } else { 7863 hclge_restore_hw_table(hdev); 7864 } 7865 } 7866 7867 clear_bit(vport->vport_id, hdev->vport_config_block); 7868 7869 return 0; 7870 } 7871 7872 void hclge_vport_stop(struct hclge_vport *vport) 7873 { 7874 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 7875 } 7876 7877 static int hclge_client_start(struct hnae3_handle *handle) 7878 { 7879 struct hclge_vport *vport = hclge_get_vport(handle); 7880 7881 return hclge_vport_start(vport); 7882 } 7883 7884 static void hclge_client_stop(struct hnae3_handle *handle) 7885 { 7886 struct hclge_vport *vport = hclge_get_vport(handle); 7887 7888 hclge_vport_stop(vport); 7889 } 7890 7891 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 7892 u16 cmdq_resp, u8 resp_code, 7893 enum hclge_mac_vlan_tbl_opcode op) 7894 { 7895 struct hclge_dev *hdev = vport->back; 7896 7897 if (cmdq_resp) { 7898 dev_err(&hdev->pdev->dev, 7899 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 7900 cmdq_resp); 7901 return -EIO; 7902 } 7903 7904 if (op == HCLGE_MAC_VLAN_ADD) { 7905 if (!resp_code || resp_code == 1) 7906 return 0; 7907 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 7908 resp_code == HCLGE_ADD_MC_OVERFLOW) 7909 return -ENOSPC; 7910 7911 dev_err(&hdev->pdev->dev, 7912 "add mac addr failed for undefined, code=%u.\n", 7913 resp_code); 7914 return -EIO; 7915 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 7916 if (!resp_code) { 7917 return 0; 7918 } else if (resp_code == 1) { 7919 dev_dbg(&hdev->pdev->dev, 7920 "remove mac addr failed for miss.\n"); 7921 return -ENOENT; 7922 } 7923 7924 dev_err(&hdev->pdev->dev, 7925 "remove mac addr failed for undefined, code=%u.\n", 7926 resp_code); 7927 return -EIO; 7928 } else if (op == HCLGE_MAC_VLAN_LKUP) { 7929 if (!resp_code) { 7930 return 0; 7931 } else if (resp_code == 1) { 7932 dev_dbg(&hdev->pdev->dev, 7933 "lookup mac addr failed for miss.\n"); 7934 return -ENOENT; 7935 } 7936 7937 dev_err(&hdev->pdev->dev, 7938 "lookup mac addr failed for undefined, code=%u.\n", 7939 resp_code); 7940 return -EIO; 7941 } 7942 7943 dev_err(&hdev->pdev->dev, 7944 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 7945 7946 return -EINVAL; 7947 } 7948 7949 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 7950 { 7951 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 7952 7953 unsigned int word_num; 7954 unsigned int bit_num; 7955 7956 if (vfid > 255 || vfid < 0) 7957 return -EIO; 7958 7959 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 7960 word_num = vfid / 32; 7961 bit_num = vfid % 32; 7962 if (clr) 7963 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 7964 else 7965 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 7966 } else { 7967 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 7968 bit_num = vfid % 32; 7969 if (clr) 7970 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 7971 else 7972 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 7973 } 7974 7975 return 0; 7976 } 7977 7978 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 7979 { 7980 #define HCLGE_DESC_NUMBER 3 7981 #define HCLGE_FUNC_NUMBER_PER_DESC 6 7982 int i, j; 7983 7984 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 7985 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 7986 if (desc[i].data[j]) 7987 return false; 7988 7989 return true; 7990 } 7991 7992 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 7993 const u8 *addr, bool is_mc) 7994 { 7995 const unsigned char *mac_addr = addr; 7996 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 7997 (mac_addr[0]) | (mac_addr[1] << 8); 7998 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 7999 8000 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8001 if (is_mc) { 8002 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8003 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8004 } 8005 8006 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8007 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8008 } 8009 8010 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8011 struct hclge_mac_vlan_tbl_entry_cmd *req) 8012 { 8013 struct hclge_dev *hdev = vport->back; 8014 struct hclge_desc desc; 8015 u8 resp_code; 8016 u16 retval; 8017 int ret; 8018 8019 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8020 8021 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8022 8023 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8024 if (ret) { 8025 dev_err(&hdev->pdev->dev, 8026 "del mac addr failed for cmd_send, ret =%d.\n", 8027 ret); 8028 return ret; 8029 } 8030 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8031 retval = le16_to_cpu(desc.retval); 8032 8033 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8034 HCLGE_MAC_VLAN_REMOVE); 8035 } 8036 8037 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8038 struct hclge_mac_vlan_tbl_entry_cmd *req, 8039 struct hclge_desc *desc, 8040 bool is_mc) 8041 { 8042 struct hclge_dev *hdev = vport->back; 8043 u8 resp_code; 8044 u16 retval; 8045 int ret; 8046 8047 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8048 if (is_mc) { 8049 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8050 memcpy(desc[0].data, 8051 req, 8052 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8053 hclge_cmd_setup_basic_desc(&desc[1], 8054 HCLGE_OPC_MAC_VLAN_ADD, 8055 true); 8056 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8057 hclge_cmd_setup_basic_desc(&desc[2], 8058 HCLGE_OPC_MAC_VLAN_ADD, 8059 true); 8060 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8061 } else { 8062 memcpy(desc[0].data, 8063 req, 8064 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8065 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8066 } 8067 if (ret) { 8068 dev_err(&hdev->pdev->dev, 8069 "lookup mac addr failed for cmd_send, ret =%d.\n", 8070 ret); 8071 return ret; 8072 } 8073 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8074 retval = le16_to_cpu(desc[0].retval); 8075 8076 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8077 HCLGE_MAC_VLAN_LKUP); 8078 } 8079 8080 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8081 struct hclge_mac_vlan_tbl_entry_cmd *req, 8082 struct hclge_desc *mc_desc) 8083 { 8084 struct hclge_dev *hdev = vport->back; 8085 int cfg_status; 8086 u8 resp_code; 8087 u16 retval; 8088 int ret; 8089 8090 if (!mc_desc) { 8091 struct hclge_desc desc; 8092 8093 hclge_cmd_setup_basic_desc(&desc, 8094 HCLGE_OPC_MAC_VLAN_ADD, 8095 false); 8096 memcpy(desc.data, req, 8097 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8098 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8099 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8100 retval = le16_to_cpu(desc.retval); 8101 8102 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8103 resp_code, 8104 HCLGE_MAC_VLAN_ADD); 8105 } else { 8106 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8107 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8108 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8109 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8110 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8111 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8112 memcpy(mc_desc[0].data, req, 8113 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8114 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8115 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8116 retval = le16_to_cpu(mc_desc[0].retval); 8117 8118 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8119 resp_code, 8120 HCLGE_MAC_VLAN_ADD); 8121 } 8122 8123 if (ret) { 8124 dev_err(&hdev->pdev->dev, 8125 "add mac addr failed for cmd_send, ret =%d.\n", 8126 ret); 8127 return ret; 8128 } 8129 8130 return cfg_status; 8131 } 8132 8133 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8134 u16 *allocated_size) 8135 { 8136 struct hclge_umv_spc_alc_cmd *req; 8137 struct hclge_desc desc; 8138 int ret; 8139 8140 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8141 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8142 8143 req->space_size = cpu_to_le32(space_size); 8144 8145 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8146 if (ret) { 8147 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8148 ret); 8149 return ret; 8150 } 8151 8152 *allocated_size = le32_to_cpu(desc.data[1]); 8153 8154 return 0; 8155 } 8156 8157 static int hclge_init_umv_space(struct hclge_dev *hdev) 8158 { 8159 u16 allocated_size = 0; 8160 int ret; 8161 8162 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8163 if (ret) 8164 return ret; 8165 8166 if (allocated_size < hdev->wanted_umv_size) 8167 dev_warn(&hdev->pdev->dev, 8168 "failed to alloc umv space, want %u, get %u\n", 8169 hdev->wanted_umv_size, allocated_size); 8170 8171 hdev->max_umv_size = allocated_size; 8172 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8173 hdev->share_umv_size = hdev->priv_umv_size + 8174 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8175 8176 if (hdev->ae_dev->dev_specs.mc_mac_size) 8177 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8178 8179 return 0; 8180 } 8181 8182 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8183 { 8184 struct hclge_vport *vport; 8185 int i; 8186 8187 for (i = 0; i < hdev->num_alloc_vport; i++) { 8188 vport = &hdev->vport[i]; 8189 vport->used_umv_num = 0; 8190 } 8191 8192 mutex_lock(&hdev->vport_lock); 8193 hdev->share_umv_size = hdev->priv_umv_size + 8194 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8195 mutex_unlock(&hdev->vport_lock); 8196 8197 hdev->used_mc_mac_num = 0; 8198 } 8199 8200 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8201 { 8202 struct hclge_dev *hdev = vport->back; 8203 bool is_full; 8204 8205 if (need_lock) 8206 mutex_lock(&hdev->vport_lock); 8207 8208 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8209 hdev->share_umv_size == 0); 8210 8211 if (need_lock) 8212 mutex_unlock(&hdev->vport_lock); 8213 8214 return is_full; 8215 } 8216 8217 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8218 { 8219 struct hclge_dev *hdev = vport->back; 8220 8221 if (is_free) { 8222 if (vport->used_umv_num > hdev->priv_umv_size) 8223 hdev->share_umv_size++; 8224 8225 if (vport->used_umv_num > 0) 8226 vport->used_umv_num--; 8227 } else { 8228 if (vport->used_umv_num >= hdev->priv_umv_size && 8229 hdev->share_umv_size > 0) 8230 hdev->share_umv_size--; 8231 vport->used_umv_num++; 8232 } 8233 } 8234 8235 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8236 const u8 *mac_addr) 8237 { 8238 struct hclge_mac_node *mac_node, *tmp; 8239 8240 list_for_each_entry_safe(mac_node, tmp, list, node) 8241 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8242 return mac_node; 8243 8244 return NULL; 8245 } 8246 8247 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8248 enum HCLGE_MAC_NODE_STATE state) 8249 { 8250 switch (state) { 8251 /* from set_rx_mode or tmp_add_list */ 8252 case HCLGE_MAC_TO_ADD: 8253 if (mac_node->state == HCLGE_MAC_TO_DEL) 8254 mac_node->state = HCLGE_MAC_ACTIVE; 8255 break; 8256 /* only from set_rx_mode */ 8257 case HCLGE_MAC_TO_DEL: 8258 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8259 list_del(&mac_node->node); 8260 kfree(mac_node); 8261 } else { 8262 mac_node->state = HCLGE_MAC_TO_DEL; 8263 } 8264 break; 8265 /* only from tmp_add_list, the mac_node->state won't be 8266 * ACTIVE. 8267 */ 8268 case HCLGE_MAC_ACTIVE: 8269 if (mac_node->state == HCLGE_MAC_TO_ADD) 8270 mac_node->state = HCLGE_MAC_ACTIVE; 8271 8272 break; 8273 } 8274 } 8275 8276 int hclge_update_mac_list(struct hclge_vport *vport, 8277 enum HCLGE_MAC_NODE_STATE state, 8278 enum HCLGE_MAC_ADDR_TYPE mac_type, 8279 const unsigned char *addr) 8280 { 8281 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8282 struct hclge_dev *hdev = vport->back; 8283 struct hclge_mac_node *mac_node; 8284 struct list_head *list; 8285 8286 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8287 &vport->uc_mac_list : &vport->mc_mac_list; 8288 8289 spin_lock_bh(&vport->mac_list_lock); 8290 8291 /* if the mac addr is already in the mac list, no need to add a new 8292 * one into it, just check the mac addr state, convert it to a new 8293 * state, or just remove it, or do nothing. 8294 */ 8295 mac_node = hclge_find_mac_node(list, addr); 8296 if (mac_node) { 8297 hclge_update_mac_node(mac_node, state); 8298 spin_unlock_bh(&vport->mac_list_lock); 8299 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8300 return 0; 8301 } 8302 8303 /* if this address is never added, unnecessary to delete */ 8304 if (state == HCLGE_MAC_TO_DEL) { 8305 spin_unlock_bh(&vport->mac_list_lock); 8306 hnae3_format_mac_addr(format_mac_addr, addr); 8307 dev_err(&hdev->pdev->dev, 8308 "failed to delete address %s from mac list\n", 8309 format_mac_addr); 8310 return -ENOENT; 8311 } 8312 8313 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8314 if (!mac_node) { 8315 spin_unlock_bh(&vport->mac_list_lock); 8316 return -ENOMEM; 8317 } 8318 8319 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8320 8321 mac_node->state = state; 8322 ether_addr_copy(mac_node->mac_addr, addr); 8323 list_add_tail(&mac_node->node, list); 8324 8325 spin_unlock_bh(&vport->mac_list_lock); 8326 8327 return 0; 8328 } 8329 8330 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8331 const unsigned char *addr) 8332 { 8333 struct hclge_vport *vport = hclge_get_vport(handle); 8334 8335 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8336 addr); 8337 } 8338 8339 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8340 const unsigned char *addr) 8341 { 8342 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8343 struct hclge_dev *hdev = vport->back; 8344 struct hclge_mac_vlan_tbl_entry_cmd req; 8345 struct hclge_desc desc; 8346 u16 egress_port = 0; 8347 int ret; 8348 8349 /* mac addr check */ 8350 if (is_zero_ether_addr(addr) || 8351 is_broadcast_ether_addr(addr) || 8352 is_multicast_ether_addr(addr)) { 8353 hnae3_format_mac_addr(format_mac_addr, addr); 8354 dev_err(&hdev->pdev->dev, 8355 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8356 format_mac_addr, is_zero_ether_addr(addr), 8357 is_broadcast_ether_addr(addr), 8358 is_multicast_ether_addr(addr)); 8359 return -EINVAL; 8360 } 8361 8362 memset(&req, 0, sizeof(req)); 8363 8364 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8365 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8366 8367 req.egress_port = cpu_to_le16(egress_port); 8368 8369 hclge_prepare_mac_addr(&req, addr, false); 8370 8371 /* Lookup the mac address in the mac_vlan table, and add 8372 * it if the entry is inexistent. Repeated unicast entry 8373 * is not allowed in the mac vlan table. 8374 */ 8375 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8376 if (ret == -ENOENT) { 8377 mutex_lock(&hdev->vport_lock); 8378 if (!hclge_is_umv_space_full(vport, false)) { 8379 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8380 if (!ret) 8381 hclge_update_umv_space(vport, false); 8382 mutex_unlock(&hdev->vport_lock); 8383 return ret; 8384 } 8385 mutex_unlock(&hdev->vport_lock); 8386 8387 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8388 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8389 hdev->priv_umv_size); 8390 8391 return -ENOSPC; 8392 } 8393 8394 /* check if we just hit the duplicate */ 8395 if (!ret) 8396 return -EEXIST; 8397 8398 return ret; 8399 } 8400 8401 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8402 const unsigned char *addr) 8403 { 8404 struct hclge_vport *vport = hclge_get_vport(handle); 8405 8406 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8407 addr); 8408 } 8409 8410 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8411 const unsigned char *addr) 8412 { 8413 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8414 struct hclge_dev *hdev = vport->back; 8415 struct hclge_mac_vlan_tbl_entry_cmd req; 8416 int ret; 8417 8418 /* mac addr check */ 8419 if (is_zero_ether_addr(addr) || 8420 is_broadcast_ether_addr(addr) || 8421 is_multicast_ether_addr(addr)) { 8422 hnae3_format_mac_addr(format_mac_addr, addr); 8423 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8424 format_mac_addr); 8425 return -EINVAL; 8426 } 8427 8428 memset(&req, 0, sizeof(req)); 8429 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8430 hclge_prepare_mac_addr(&req, addr, false); 8431 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8432 if (!ret) { 8433 mutex_lock(&hdev->vport_lock); 8434 hclge_update_umv_space(vport, true); 8435 mutex_unlock(&hdev->vport_lock); 8436 } else if (ret == -ENOENT) { 8437 ret = 0; 8438 } 8439 8440 return ret; 8441 } 8442 8443 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8444 const unsigned char *addr) 8445 { 8446 struct hclge_vport *vport = hclge_get_vport(handle); 8447 8448 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8449 addr); 8450 } 8451 8452 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8453 const unsigned char *addr) 8454 { 8455 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8456 struct hclge_dev *hdev = vport->back; 8457 struct hclge_mac_vlan_tbl_entry_cmd req; 8458 struct hclge_desc desc[3]; 8459 bool is_new_addr = false; 8460 int status; 8461 8462 /* mac addr check */ 8463 if (!is_multicast_ether_addr(addr)) { 8464 hnae3_format_mac_addr(format_mac_addr, addr); 8465 dev_err(&hdev->pdev->dev, 8466 "Add mc mac err! invalid mac:%s.\n", 8467 format_mac_addr); 8468 return -EINVAL; 8469 } 8470 memset(&req, 0, sizeof(req)); 8471 hclge_prepare_mac_addr(&req, addr, true); 8472 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8473 if (status) { 8474 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8475 hdev->used_mc_mac_num >= 8476 hdev->ae_dev->dev_specs.mc_mac_size) 8477 goto err_no_space; 8478 8479 is_new_addr = true; 8480 8481 /* This mac addr do not exist, add new entry for it */ 8482 memset(desc[0].data, 0, sizeof(desc[0].data)); 8483 memset(desc[1].data, 0, sizeof(desc[0].data)); 8484 memset(desc[2].data, 0, sizeof(desc[0].data)); 8485 } 8486 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8487 if (status) 8488 return status; 8489 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8490 if (status == -ENOSPC) 8491 goto err_no_space; 8492 else if (!status && is_new_addr) 8493 hdev->used_mc_mac_num++; 8494 8495 return status; 8496 8497 err_no_space: 8498 /* if already overflow, not to print each time */ 8499 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8500 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8501 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8502 } 8503 8504 return -ENOSPC; 8505 } 8506 8507 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8508 const unsigned char *addr) 8509 { 8510 struct hclge_vport *vport = hclge_get_vport(handle); 8511 8512 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8513 addr); 8514 } 8515 8516 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8517 const unsigned char *addr) 8518 { 8519 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8520 struct hclge_dev *hdev = vport->back; 8521 struct hclge_mac_vlan_tbl_entry_cmd req; 8522 enum hclge_comm_cmd_status status; 8523 struct hclge_desc desc[3]; 8524 8525 /* mac addr check */ 8526 if (!is_multicast_ether_addr(addr)) { 8527 hnae3_format_mac_addr(format_mac_addr, addr); 8528 dev_dbg(&hdev->pdev->dev, 8529 "Remove mc mac err! invalid mac:%s.\n", 8530 format_mac_addr); 8531 return -EINVAL; 8532 } 8533 8534 memset(&req, 0, sizeof(req)); 8535 hclge_prepare_mac_addr(&req, addr, true); 8536 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8537 if (!status) { 8538 /* This mac addr exist, remove this handle's VFID for it */ 8539 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8540 if (status) 8541 return status; 8542 8543 if (hclge_is_all_function_id_zero(desc)) { 8544 /* All the vfid is zero, so need to delete this entry */ 8545 status = hclge_remove_mac_vlan_tbl(vport, &req); 8546 if (!status) 8547 hdev->used_mc_mac_num--; 8548 } else { 8549 /* Not all the vfid is zero, update the vfid */ 8550 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8551 } 8552 } else if (status == -ENOENT) { 8553 status = 0; 8554 } 8555 8556 return status; 8557 } 8558 8559 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8560 struct list_head *list, 8561 enum HCLGE_MAC_ADDR_TYPE mac_type) 8562 { 8563 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8564 struct hclge_mac_node *mac_node, *tmp; 8565 int ret; 8566 8567 if (mac_type == HCLGE_MAC_ADDR_UC) 8568 sync = hclge_add_uc_addr_common; 8569 else 8570 sync = hclge_add_mc_addr_common; 8571 8572 list_for_each_entry_safe(mac_node, tmp, list, node) { 8573 ret = sync(vport, mac_node->mac_addr); 8574 if (!ret) { 8575 mac_node->state = HCLGE_MAC_ACTIVE; 8576 } else { 8577 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8578 &vport->state); 8579 8580 /* If one unicast mac address is existing in hardware, 8581 * we need to try whether other unicast mac addresses 8582 * are new addresses that can be added. 8583 * Multicast mac address can be reusable, even though 8584 * there is no space to add new multicast mac address, 8585 * we should check whether other mac addresses are 8586 * existing in hardware for reuse. 8587 */ 8588 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8589 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8590 break; 8591 } 8592 } 8593 } 8594 8595 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8596 struct list_head *list, 8597 enum HCLGE_MAC_ADDR_TYPE mac_type) 8598 { 8599 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8600 struct hclge_mac_node *mac_node, *tmp; 8601 int ret; 8602 8603 if (mac_type == HCLGE_MAC_ADDR_UC) 8604 unsync = hclge_rm_uc_addr_common; 8605 else 8606 unsync = hclge_rm_mc_addr_common; 8607 8608 list_for_each_entry_safe(mac_node, tmp, list, node) { 8609 ret = unsync(vport, mac_node->mac_addr); 8610 if (!ret || ret == -ENOENT) { 8611 list_del(&mac_node->node); 8612 kfree(mac_node); 8613 } else { 8614 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8615 &vport->state); 8616 break; 8617 } 8618 } 8619 } 8620 8621 static bool hclge_sync_from_add_list(struct list_head *add_list, 8622 struct list_head *mac_list) 8623 { 8624 struct hclge_mac_node *mac_node, *tmp, *new_node; 8625 bool all_added = true; 8626 8627 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8628 if (mac_node->state == HCLGE_MAC_TO_ADD) 8629 all_added = false; 8630 8631 /* if the mac address from tmp_add_list is not in the 8632 * uc/mc_mac_list, it means have received a TO_DEL request 8633 * during the time window of adding the mac address into mac 8634 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8635 * then it will be removed at next time. else it must be TO_ADD, 8636 * this address hasn't been added into mac table, 8637 * so just remove the mac node. 8638 */ 8639 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8640 if (new_node) { 8641 hclge_update_mac_node(new_node, mac_node->state); 8642 list_del(&mac_node->node); 8643 kfree(mac_node); 8644 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8645 mac_node->state = HCLGE_MAC_TO_DEL; 8646 list_move_tail(&mac_node->node, mac_list); 8647 } else { 8648 list_del(&mac_node->node); 8649 kfree(mac_node); 8650 } 8651 } 8652 8653 return all_added; 8654 } 8655 8656 static void hclge_sync_from_del_list(struct list_head *del_list, 8657 struct list_head *mac_list) 8658 { 8659 struct hclge_mac_node *mac_node, *tmp, *new_node; 8660 8661 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8662 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8663 if (new_node) { 8664 /* If the mac addr exists in the mac list, it means 8665 * received a new TO_ADD request during the time window 8666 * of configuring the mac address. For the mac node 8667 * state is TO_ADD, and the address is already in the 8668 * in the hardware(due to delete fail), so we just need 8669 * to change the mac node state to ACTIVE. 8670 */ 8671 new_node->state = HCLGE_MAC_ACTIVE; 8672 list_del(&mac_node->node); 8673 kfree(mac_node); 8674 } else { 8675 list_move_tail(&mac_node->node, mac_list); 8676 } 8677 } 8678 } 8679 8680 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8681 enum HCLGE_MAC_ADDR_TYPE mac_type, 8682 bool is_all_added) 8683 { 8684 if (mac_type == HCLGE_MAC_ADDR_UC) { 8685 if (is_all_added) 8686 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8687 else 8688 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8689 } else { 8690 if (is_all_added) 8691 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8692 else 8693 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8694 } 8695 } 8696 8697 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8698 enum HCLGE_MAC_ADDR_TYPE mac_type) 8699 { 8700 struct hclge_mac_node *mac_node, *tmp, *new_node; 8701 struct list_head tmp_add_list, tmp_del_list; 8702 struct list_head *list; 8703 bool all_added; 8704 8705 INIT_LIST_HEAD(&tmp_add_list); 8706 INIT_LIST_HEAD(&tmp_del_list); 8707 8708 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8709 * we can add/delete these mac addr outside the spin lock 8710 */ 8711 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8712 &vport->uc_mac_list : &vport->mc_mac_list; 8713 8714 spin_lock_bh(&vport->mac_list_lock); 8715 8716 list_for_each_entry_safe(mac_node, tmp, list, node) { 8717 switch (mac_node->state) { 8718 case HCLGE_MAC_TO_DEL: 8719 list_move_tail(&mac_node->node, &tmp_del_list); 8720 break; 8721 case HCLGE_MAC_TO_ADD: 8722 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8723 if (!new_node) 8724 goto stop_traverse; 8725 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8726 new_node->state = mac_node->state; 8727 list_add_tail(&new_node->node, &tmp_add_list); 8728 break; 8729 default: 8730 break; 8731 } 8732 } 8733 8734 stop_traverse: 8735 spin_unlock_bh(&vport->mac_list_lock); 8736 8737 /* delete first, in order to get max mac table space for adding */ 8738 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8739 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8740 8741 /* if some mac addresses were added/deleted fail, move back to the 8742 * mac_list, and retry at next time. 8743 */ 8744 spin_lock_bh(&vport->mac_list_lock); 8745 8746 hclge_sync_from_del_list(&tmp_del_list, list); 8747 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8748 8749 spin_unlock_bh(&vport->mac_list_lock); 8750 8751 hclge_update_overflow_flags(vport, mac_type, all_added); 8752 } 8753 8754 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8755 { 8756 struct hclge_dev *hdev = vport->back; 8757 8758 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8759 return false; 8760 8761 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8762 return true; 8763 8764 return false; 8765 } 8766 8767 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8768 { 8769 int i; 8770 8771 for (i = 0; i < hdev->num_alloc_vport; i++) { 8772 struct hclge_vport *vport = &hdev->vport[i]; 8773 8774 if (!hclge_need_sync_mac_table(vport)) 8775 continue; 8776 8777 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 8778 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 8779 } 8780 } 8781 8782 static void hclge_build_del_list(struct list_head *list, 8783 bool is_del_list, 8784 struct list_head *tmp_del_list) 8785 { 8786 struct hclge_mac_node *mac_cfg, *tmp; 8787 8788 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 8789 switch (mac_cfg->state) { 8790 case HCLGE_MAC_TO_DEL: 8791 case HCLGE_MAC_ACTIVE: 8792 list_move_tail(&mac_cfg->node, tmp_del_list); 8793 break; 8794 case HCLGE_MAC_TO_ADD: 8795 if (is_del_list) { 8796 list_del(&mac_cfg->node); 8797 kfree(mac_cfg); 8798 } 8799 break; 8800 } 8801 } 8802 } 8803 8804 static void hclge_unsync_del_list(struct hclge_vport *vport, 8805 int (*unsync)(struct hclge_vport *vport, 8806 const unsigned char *addr), 8807 bool is_del_list, 8808 struct list_head *tmp_del_list) 8809 { 8810 struct hclge_mac_node *mac_cfg, *tmp; 8811 int ret; 8812 8813 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 8814 ret = unsync(vport, mac_cfg->mac_addr); 8815 if (!ret || ret == -ENOENT) { 8816 /* clear all mac addr from hardware, but remain these 8817 * mac addr in the mac list, and restore them after 8818 * vf reset finished. 8819 */ 8820 if (!is_del_list && 8821 mac_cfg->state == HCLGE_MAC_ACTIVE) { 8822 mac_cfg->state = HCLGE_MAC_TO_ADD; 8823 } else { 8824 list_del(&mac_cfg->node); 8825 kfree(mac_cfg); 8826 } 8827 } else if (is_del_list) { 8828 mac_cfg->state = HCLGE_MAC_TO_DEL; 8829 } 8830 } 8831 } 8832 8833 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 8834 enum HCLGE_MAC_ADDR_TYPE mac_type) 8835 { 8836 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8837 struct hclge_dev *hdev = vport->back; 8838 struct list_head tmp_del_list, *list; 8839 8840 if (mac_type == HCLGE_MAC_ADDR_UC) { 8841 list = &vport->uc_mac_list; 8842 unsync = hclge_rm_uc_addr_common; 8843 } else { 8844 list = &vport->mc_mac_list; 8845 unsync = hclge_rm_mc_addr_common; 8846 } 8847 8848 INIT_LIST_HEAD(&tmp_del_list); 8849 8850 if (!is_del_list) 8851 set_bit(vport->vport_id, hdev->vport_config_block); 8852 8853 spin_lock_bh(&vport->mac_list_lock); 8854 8855 hclge_build_del_list(list, is_del_list, &tmp_del_list); 8856 8857 spin_unlock_bh(&vport->mac_list_lock); 8858 8859 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 8860 8861 spin_lock_bh(&vport->mac_list_lock); 8862 8863 hclge_sync_from_del_list(&tmp_del_list, list); 8864 8865 spin_unlock_bh(&vport->mac_list_lock); 8866 } 8867 8868 /* remove all mac address when uninitailize */ 8869 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 8870 enum HCLGE_MAC_ADDR_TYPE mac_type) 8871 { 8872 struct hclge_mac_node *mac_node, *tmp; 8873 struct hclge_dev *hdev = vport->back; 8874 struct list_head tmp_del_list, *list; 8875 8876 INIT_LIST_HEAD(&tmp_del_list); 8877 8878 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8879 &vport->uc_mac_list : &vport->mc_mac_list; 8880 8881 spin_lock_bh(&vport->mac_list_lock); 8882 8883 list_for_each_entry_safe(mac_node, tmp, list, node) { 8884 switch (mac_node->state) { 8885 case HCLGE_MAC_TO_DEL: 8886 case HCLGE_MAC_ACTIVE: 8887 list_move_tail(&mac_node->node, &tmp_del_list); 8888 break; 8889 case HCLGE_MAC_TO_ADD: 8890 list_del(&mac_node->node); 8891 kfree(mac_node); 8892 break; 8893 } 8894 } 8895 8896 spin_unlock_bh(&vport->mac_list_lock); 8897 8898 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8899 8900 if (!list_empty(&tmp_del_list)) 8901 dev_warn(&hdev->pdev->dev, 8902 "uninit %s mac list for vport %u not completely.\n", 8903 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 8904 vport->vport_id); 8905 8906 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 8907 list_del(&mac_node->node); 8908 kfree(mac_node); 8909 } 8910 } 8911 8912 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 8913 { 8914 struct hclge_vport *vport; 8915 int i; 8916 8917 for (i = 0; i < hdev->num_alloc_vport; i++) { 8918 vport = &hdev->vport[i]; 8919 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 8920 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 8921 } 8922 } 8923 8924 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 8925 u16 cmdq_resp, u8 resp_code) 8926 { 8927 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 8928 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 8929 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 8930 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 8931 8932 int return_status; 8933 8934 if (cmdq_resp) { 8935 dev_err(&hdev->pdev->dev, 8936 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 8937 cmdq_resp); 8938 return -EIO; 8939 } 8940 8941 switch (resp_code) { 8942 case HCLGE_ETHERTYPE_SUCCESS_ADD: 8943 case HCLGE_ETHERTYPE_ALREADY_ADD: 8944 return_status = 0; 8945 break; 8946 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 8947 dev_err(&hdev->pdev->dev, 8948 "add mac ethertype failed for manager table overflow.\n"); 8949 return_status = -EIO; 8950 break; 8951 case HCLGE_ETHERTYPE_KEY_CONFLICT: 8952 dev_err(&hdev->pdev->dev, 8953 "add mac ethertype failed for key conflict.\n"); 8954 return_status = -EIO; 8955 break; 8956 default: 8957 dev_err(&hdev->pdev->dev, 8958 "add mac ethertype failed for undefined, code=%u.\n", 8959 resp_code); 8960 return_status = -EIO; 8961 } 8962 8963 return return_status; 8964 } 8965 8966 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 8967 u8 *mac_addr) 8968 { 8969 struct hclge_vport *vport = hclge_get_vport(handle); 8970 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8971 struct hclge_dev *hdev = vport->back; 8972 8973 vport = hclge_get_vf_vport(hdev, vf); 8974 if (!vport) 8975 return -EINVAL; 8976 8977 hnae3_format_mac_addr(format_mac_addr, mac_addr); 8978 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 8979 dev_info(&hdev->pdev->dev, 8980 "Specified MAC(=%s) is same as before, no change committed!\n", 8981 format_mac_addr); 8982 return 0; 8983 } 8984 8985 ether_addr_copy(vport->vf_info.mac, mac_addr); 8986 8987 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 8988 dev_info(&hdev->pdev->dev, 8989 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 8990 vf, format_mac_addr); 8991 return hclge_inform_reset_assert_to_vf(vport); 8992 } 8993 8994 dev_info(&hdev->pdev->dev, "MAC of VF %d has been set to %s\n", 8995 vf, format_mac_addr); 8996 return 0; 8997 } 8998 8999 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9000 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9001 { 9002 struct hclge_desc desc; 9003 u8 resp_code; 9004 u16 retval; 9005 int ret; 9006 9007 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9008 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9009 9010 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9011 if (ret) { 9012 dev_err(&hdev->pdev->dev, 9013 "add mac ethertype failed for cmd_send, ret =%d.\n", 9014 ret); 9015 return ret; 9016 } 9017 9018 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9019 retval = le16_to_cpu(desc.retval); 9020 9021 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9022 } 9023 9024 static int init_mgr_tbl(struct hclge_dev *hdev) 9025 { 9026 int ret; 9027 int i; 9028 9029 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9030 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9031 if (ret) { 9032 dev_err(&hdev->pdev->dev, 9033 "add mac ethertype failed, ret =%d.\n", 9034 ret); 9035 return ret; 9036 } 9037 } 9038 9039 return 0; 9040 } 9041 9042 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9043 { 9044 struct hclge_vport *vport = hclge_get_vport(handle); 9045 struct hclge_dev *hdev = vport->back; 9046 9047 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9048 } 9049 9050 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9051 const u8 *old_addr, const u8 *new_addr) 9052 { 9053 struct list_head *list = &vport->uc_mac_list; 9054 struct hclge_mac_node *old_node, *new_node; 9055 9056 new_node = hclge_find_mac_node(list, new_addr); 9057 if (!new_node) { 9058 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9059 if (!new_node) 9060 return -ENOMEM; 9061 9062 new_node->state = HCLGE_MAC_TO_ADD; 9063 ether_addr_copy(new_node->mac_addr, new_addr); 9064 list_add(&new_node->node, list); 9065 } else { 9066 if (new_node->state == HCLGE_MAC_TO_DEL) 9067 new_node->state = HCLGE_MAC_ACTIVE; 9068 9069 /* make sure the new addr is in the list head, avoid dev 9070 * addr may be not re-added into mac table for the umv space 9071 * limitation after global/imp reset which will clear mac 9072 * table by hardware. 9073 */ 9074 list_move(&new_node->node, list); 9075 } 9076 9077 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9078 old_node = hclge_find_mac_node(list, old_addr); 9079 if (old_node) { 9080 if (old_node->state == HCLGE_MAC_TO_ADD) { 9081 list_del(&old_node->node); 9082 kfree(old_node); 9083 } else { 9084 old_node->state = HCLGE_MAC_TO_DEL; 9085 } 9086 } 9087 } 9088 9089 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9090 9091 return 0; 9092 } 9093 9094 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9095 bool is_first) 9096 { 9097 const unsigned char *new_addr = (const unsigned char *)p; 9098 struct hclge_vport *vport = hclge_get_vport(handle); 9099 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9100 struct hclge_dev *hdev = vport->back; 9101 unsigned char *old_addr = NULL; 9102 int ret; 9103 9104 /* mac addr check */ 9105 if (is_zero_ether_addr(new_addr) || 9106 is_broadcast_ether_addr(new_addr) || 9107 is_multicast_ether_addr(new_addr)) { 9108 hnae3_format_mac_addr(format_mac_addr, new_addr); 9109 dev_err(&hdev->pdev->dev, 9110 "change uc mac err! invalid mac: %s.\n", 9111 format_mac_addr); 9112 return -EINVAL; 9113 } 9114 9115 ret = hclge_pause_addr_cfg(hdev, new_addr); 9116 if (ret) { 9117 dev_err(&hdev->pdev->dev, 9118 "failed to configure mac pause address, ret = %d\n", 9119 ret); 9120 return ret; 9121 } 9122 9123 if (!is_first) 9124 old_addr = hdev->hw.mac.mac_addr; 9125 9126 spin_lock_bh(&vport->mac_list_lock); 9127 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9128 if (ret) { 9129 hnae3_format_mac_addr(format_mac_addr, new_addr); 9130 dev_err(&hdev->pdev->dev, 9131 "failed to change the mac addr:%s, ret = %d\n", 9132 format_mac_addr, ret); 9133 spin_unlock_bh(&vport->mac_list_lock); 9134 9135 if (!is_first) 9136 hclge_pause_addr_cfg(hdev, old_addr); 9137 9138 return ret; 9139 } 9140 /* we must update dev addr with spin lock protect, preventing dev addr 9141 * being removed by set_rx_mode path. 9142 */ 9143 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9144 spin_unlock_bh(&vport->mac_list_lock); 9145 9146 hclge_task_schedule(hdev, 0); 9147 9148 return 0; 9149 } 9150 9151 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9152 { 9153 struct mii_ioctl_data *data = if_mii(ifr); 9154 9155 if (!hnae3_dev_phy_imp_supported(hdev)) 9156 return -EOPNOTSUPP; 9157 9158 switch (cmd) { 9159 case SIOCGMIIPHY: 9160 data->phy_id = hdev->hw.mac.phy_addr; 9161 /* this command reads phy id and register at the same time */ 9162 fallthrough; 9163 case SIOCGMIIREG: 9164 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9165 return 0; 9166 9167 case SIOCSMIIREG: 9168 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9169 default: 9170 return -EOPNOTSUPP; 9171 } 9172 } 9173 9174 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9175 int cmd) 9176 { 9177 struct hclge_vport *vport = hclge_get_vport(handle); 9178 struct hclge_dev *hdev = vport->back; 9179 9180 switch (cmd) { 9181 case SIOCGHWTSTAMP: 9182 return hclge_ptp_get_cfg(hdev, ifr); 9183 case SIOCSHWTSTAMP: 9184 return hclge_ptp_set_cfg(hdev, ifr); 9185 default: 9186 if (!hdev->hw.mac.phydev) 9187 return hclge_mii_ioctl(hdev, ifr, cmd); 9188 } 9189 9190 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9191 } 9192 9193 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9194 bool bypass_en) 9195 { 9196 struct hclge_port_vlan_filter_bypass_cmd *req; 9197 struct hclge_desc desc; 9198 int ret; 9199 9200 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9201 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9202 req->vf_id = vf_id; 9203 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9204 bypass_en ? 1 : 0); 9205 9206 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9207 if (ret) 9208 dev_err(&hdev->pdev->dev, 9209 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9210 vf_id, ret); 9211 9212 return ret; 9213 } 9214 9215 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9216 u8 fe_type, bool filter_en, u8 vf_id) 9217 { 9218 struct hclge_vlan_filter_ctrl_cmd *req; 9219 struct hclge_desc desc; 9220 int ret; 9221 9222 /* read current vlan filter parameter */ 9223 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9224 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9225 req->vlan_type = vlan_type; 9226 req->vf_id = vf_id; 9227 9228 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9229 if (ret) { 9230 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9231 vf_id, ret); 9232 return ret; 9233 } 9234 9235 /* modify and write new config parameter */ 9236 hclge_comm_cmd_reuse_desc(&desc, false); 9237 req->vlan_fe = filter_en ? 9238 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9239 9240 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9241 if (ret) 9242 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9243 vf_id, ret); 9244 9245 return ret; 9246 } 9247 9248 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9249 { 9250 struct hclge_dev *hdev = vport->back; 9251 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9252 int ret; 9253 9254 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9255 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9256 HCLGE_FILTER_FE_EGRESS_V1_B, 9257 enable, vport->vport_id); 9258 9259 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9260 HCLGE_FILTER_FE_EGRESS, enable, 9261 vport->vport_id); 9262 if (ret) 9263 return ret; 9264 9265 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9266 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9267 !enable); 9268 } else if (!vport->vport_id) { 9269 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9270 enable = false; 9271 9272 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9273 HCLGE_FILTER_FE_INGRESS, 9274 enable, 0); 9275 } 9276 9277 return ret; 9278 } 9279 9280 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9281 { 9282 struct hnae3_handle *handle = &vport->nic; 9283 struct hclge_vport_vlan_cfg *vlan, *tmp; 9284 struct hclge_dev *hdev = vport->back; 9285 9286 if (vport->vport_id) { 9287 if (vport->port_base_vlan_cfg.state != 9288 HNAE3_PORT_BASE_VLAN_DISABLE) 9289 return true; 9290 9291 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9292 return false; 9293 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9294 return false; 9295 } 9296 9297 if (!vport->req_vlan_fltr_en) 9298 return false; 9299 9300 /* compatible with former device, always enable vlan filter */ 9301 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9302 return true; 9303 9304 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9305 if (vlan->vlan_id != 0) 9306 return true; 9307 9308 return false; 9309 } 9310 9311 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9312 { 9313 struct hclge_dev *hdev = vport->back; 9314 bool need_en; 9315 int ret; 9316 9317 mutex_lock(&hdev->vport_lock); 9318 9319 vport->req_vlan_fltr_en = request_en; 9320 9321 need_en = hclge_need_enable_vport_vlan_filter(vport); 9322 if (need_en == vport->cur_vlan_fltr_en) { 9323 mutex_unlock(&hdev->vport_lock); 9324 return 0; 9325 } 9326 9327 ret = hclge_set_vport_vlan_filter(vport, need_en); 9328 if (ret) { 9329 mutex_unlock(&hdev->vport_lock); 9330 return ret; 9331 } 9332 9333 vport->cur_vlan_fltr_en = need_en; 9334 9335 mutex_unlock(&hdev->vport_lock); 9336 9337 return 0; 9338 } 9339 9340 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9341 { 9342 struct hclge_vport *vport = hclge_get_vport(handle); 9343 9344 return hclge_enable_vport_vlan_filter(vport, enable); 9345 } 9346 9347 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9348 bool is_kill, u16 vlan, 9349 struct hclge_desc *desc) 9350 { 9351 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9352 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9353 u8 vf_byte_val; 9354 u8 vf_byte_off; 9355 int ret; 9356 9357 hclge_cmd_setup_basic_desc(&desc[0], 9358 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9359 hclge_cmd_setup_basic_desc(&desc[1], 9360 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9361 9362 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9363 9364 vf_byte_off = vfid / 8; 9365 vf_byte_val = 1 << (vfid % 8); 9366 9367 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9368 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9369 9370 req0->vlan_id = cpu_to_le16(vlan); 9371 req0->vlan_cfg = is_kill; 9372 9373 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9374 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9375 else 9376 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9377 9378 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9379 if (ret) { 9380 dev_err(&hdev->pdev->dev, 9381 "Send vf vlan command fail, ret =%d.\n", 9382 ret); 9383 return ret; 9384 } 9385 9386 return 0; 9387 } 9388 9389 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9390 bool is_kill, struct hclge_desc *desc) 9391 { 9392 struct hclge_vlan_filter_vf_cfg_cmd *req; 9393 9394 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9395 9396 if (!is_kill) { 9397 #define HCLGE_VF_VLAN_NO_ENTRY 2 9398 if (!req->resp_code || req->resp_code == 1) 9399 return 0; 9400 9401 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9402 set_bit(vfid, hdev->vf_vlan_full); 9403 dev_warn(&hdev->pdev->dev, 9404 "vf vlan table is full, vf vlan filter is disabled\n"); 9405 return 0; 9406 } 9407 9408 dev_err(&hdev->pdev->dev, 9409 "Add vf vlan filter fail, ret =%u.\n", 9410 req->resp_code); 9411 } else { 9412 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9413 if (!req->resp_code) 9414 return 0; 9415 9416 /* vf vlan filter is disabled when vf vlan table is full, 9417 * then new vlan id will not be added into vf vlan table. 9418 * Just return 0 without warning, avoid massive verbose 9419 * print logs when unload. 9420 */ 9421 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9422 return 0; 9423 9424 dev_err(&hdev->pdev->dev, 9425 "Kill vf vlan filter fail, ret =%u.\n", 9426 req->resp_code); 9427 } 9428 9429 return -EIO; 9430 } 9431 9432 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9433 bool is_kill, u16 vlan) 9434 { 9435 struct hclge_vport *vport = &hdev->vport[vfid]; 9436 struct hclge_desc desc[2]; 9437 int ret; 9438 9439 /* if vf vlan table is full, firmware will close vf vlan filter, it 9440 * is unable and unnecessary to add new vlan id to vf vlan filter. 9441 * If spoof check is enable, and vf vlan is full, it shouldn't add 9442 * new vlan, because tx packets with these vlan id will be dropped. 9443 */ 9444 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9445 if (vport->vf_info.spoofchk && vlan) { 9446 dev_err(&hdev->pdev->dev, 9447 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9448 return -EPERM; 9449 } 9450 return 0; 9451 } 9452 9453 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9454 if (ret) 9455 return ret; 9456 9457 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9458 } 9459 9460 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9461 u16 vlan_id, bool is_kill) 9462 { 9463 struct hclge_vlan_filter_pf_cfg_cmd *req; 9464 struct hclge_desc desc; 9465 u8 vlan_offset_byte_val; 9466 u8 vlan_offset_byte; 9467 u8 vlan_offset_160; 9468 int ret; 9469 9470 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9471 9472 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9473 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9474 HCLGE_VLAN_BYTE_SIZE; 9475 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9476 9477 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9478 req->vlan_offset = vlan_offset_160; 9479 req->vlan_cfg = is_kill; 9480 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9481 9482 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9483 if (ret) 9484 dev_err(&hdev->pdev->dev, 9485 "port vlan command, send fail, ret =%d.\n", ret); 9486 return ret; 9487 } 9488 9489 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9490 u16 vlan_id, bool is_kill) 9491 { 9492 /* vlan 0 may be added twice when 8021q module is enabled */ 9493 if (!is_kill && !vlan_id && 9494 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9495 return false; 9496 9497 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9498 dev_warn(&hdev->pdev->dev, 9499 "Add port vlan failed, vport %u is already in vlan %u\n", 9500 vport_id, vlan_id); 9501 return false; 9502 } 9503 9504 if (is_kill && 9505 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9506 dev_warn(&hdev->pdev->dev, 9507 "Delete port vlan failed, vport %u is not in vlan %u\n", 9508 vport_id, vlan_id); 9509 return false; 9510 } 9511 9512 return true; 9513 } 9514 9515 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9516 u16 vport_id, u16 vlan_id, 9517 bool is_kill) 9518 { 9519 u16 vport_idx, vport_num = 0; 9520 int ret; 9521 9522 if (is_kill && !vlan_id) 9523 return 0; 9524 9525 if (vlan_id >= VLAN_N_VID) 9526 return -EINVAL; 9527 9528 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9529 if (ret) { 9530 dev_err(&hdev->pdev->dev, 9531 "Set %u vport vlan filter config fail, ret =%d.\n", 9532 vport_id, ret); 9533 return ret; 9534 } 9535 9536 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9537 return 0; 9538 9539 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9540 vport_num++; 9541 9542 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9543 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9544 is_kill); 9545 9546 return ret; 9547 } 9548 9549 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9550 { 9551 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9552 struct hclge_vport_vtag_tx_cfg_cmd *req; 9553 struct hclge_dev *hdev = vport->back; 9554 struct hclge_desc desc; 9555 u16 bmap_index; 9556 int status; 9557 9558 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9559 9560 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9561 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9562 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9563 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9564 vcfg->accept_tag1 ? 1 : 0); 9565 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9566 vcfg->accept_untag1 ? 1 : 0); 9567 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9568 vcfg->accept_tag2 ? 1 : 0); 9569 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9570 vcfg->accept_untag2 ? 1 : 0); 9571 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9572 vcfg->insert_tag1_en ? 1 : 0); 9573 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9574 vcfg->insert_tag2_en ? 1 : 0); 9575 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9576 vcfg->tag_shift_mode_en ? 1 : 0); 9577 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9578 9579 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9580 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9581 HCLGE_VF_NUM_PER_BYTE; 9582 req->vf_bitmap[bmap_index] = 9583 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9584 9585 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9586 if (status) 9587 dev_err(&hdev->pdev->dev, 9588 "Send port txvlan cfg command fail, ret =%d\n", 9589 status); 9590 9591 return status; 9592 } 9593 9594 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9595 { 9596 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9597 struct hclge_vport_vtag_rx_cfg_cmd *req; 9598 struct hclge_dev *hdev = vport->back; 9599 struct hclge_desc desc; 9600 u16 bmap_index; 9601 int status; 9602 9603 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9604 9605 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9606 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9607 vcfg->strip_tag1_en ? 1 : 0); 9608 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9609 vcfg->strip_tag2_en ? 1 : 0); 9610 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9611 vcfg->vlan1_vlan_prionly ? 1 : 0); 9612 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9613 vcfg->vlan2_vlan_prionly ? 1 : 0); 9614 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9615 vcfg->strip_tag1_discard_en ? 1 : 0); 9616 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9617 vcfg->strip_tag2_discard_en ? 1 : 0); 9618 9619 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9620 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9621 HCLGE_VF_NUM_PER_BYTE; 9622 req->vf_bitmap[bmap_index] = 9623 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9624 9625 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9626 if (status) 9627 dev_err(&hdev->pdev->dev, 9628 "Send port rxvlan cfg command fail, ret =%d\n", 9629 status); 9630 9631 return status; 9632 } 9633 9634 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9635 u16 port_base_vlan_state, 9636 u16 vlan_tag, u8 qos) 9637 { 9638 int ret; 9639 9640 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9641 vport->txvlan_cfg.accept_tag1 = true; 9642 vport->txvlan_cfg.insert_tag1_en = false; 9643 vport->txvlan_cfg.default_tag1 = 0; 9644 } else { 9645 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9646 9647 vport->txvlan_cfg.accept_tag1 = 9648 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9649 vport->txvlan_cfg.insert_tag1_en = true; 9650 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9651 vlan_tag; 9652 } 9653 9654 vport->txvlan_cfg.accept_untag1 = true; 9655 9656 /* accept_tag2 and accept_untag2 are not supported on 9657 * pdev revision(0x20), new revision support them, 9658 * this two fields can not be configured by user. 9659 */ 9660 vport->txvlan_cfg.accept_tag2 = true; 9661 vport->txvlan_cfg.accept_untag2 = true; 9662 vport->txvlan_cfg.insert_tag2_en = false; 9663 vport->txvlan_cfg.default_tag2 = 0; 9664 vport->txvlan_cfg.tag_shift_mode_en = true; 9665 9666 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9667 vport->rxvlan_cfg.strip_tag1_en = false; 9668 vport->rxvlan_cfg.strip_tag2_en = 9669 vport->rxvlan_cfg.rx_vlan_offload_en; 9670 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9671 } else { 9672 vport->rxvlan_cfg.strip_tag1_en = 9673 vport->rxvlan_cfg.rx_vlan_offload_en; 9674 vport->rxvlan_cfg.strip_tag2_en = true; 9675 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9676 } 9677 9678 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9679 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9680 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9681 9682 ret = hclge_set_vlan_tx_offload_cfg(vport); 9683 if (ret) 9684 return ret; 9685 9686 return hclge_set_vlan_rx_offload_cfg(vport); 9687 } 9688 9689 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9690 { 9691 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9692 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9693 struct hclge_desc desc; 9694 int status; 9695 9696 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9697 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9698 rx_req->ot_fst_vlan_type = 9699 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9700 rx_req->ot_sec_vlan_type = 9701 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9702 rx_req->in_fst_vlan_type = 9703 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9704 rx_req->in_sec_vlan_type = 9705 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9706 9707 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9708 if (status) { 9709 dev_err(&hdev->pdev->dev, 9710 "Send rxvlan protocol type command fail, ret =%d\n", 9711 status); 9712 return status; 9713 } 9714 9715 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9716 9717 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9718 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9719 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9720 9721 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9722 if (status) 9723 dev_err(&hdev->pdev->dev, 9724 "Send txvlan protocol type command fail, ret =%d\n", 9725 status); 9726 9727 return status; 9728 } 9729 9730 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9731 { 9732 struct hclge_vport *vport; 9733 int ret; 9734 int i; 9735 9736 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9737 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9738 HCLGE_FILTER_FE_EGRESS_V1_B, 9739 true, 0); 9740 9741 /* for revision 0x21, vf vlan filter is per function */ 9742 for (i = 0; i < hdev->num_alloc_vport; i++) { 9743 vport = &hdev->vport[i]; 9744 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9745 HCLGE_FILTER_FE_EGRESS, true, 9746 vport->vport_id); 9747 if (ret) 9748 return ret; 9749 vport->cur_vlan_fltr_en = true; 9750 } 9751 9752 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9753 HCLGE_FILTER_FE_INGRESS, true, 0); 9754 } 9755 9756 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9757 { 9758 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9759 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9760 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9761 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9762 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9763 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9764 9765 return hclge_set_vlan_protocol_type(hdev); 9766 } 9767 9768 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 9769 { 9770 struct hclge_port_base_vlan_config *cfg; 9771 struct hclge_vport *vport; 9772 int ret; 9773 int i; 9774 9775 for (i = 0; i < hdev->num_alloc_vport; i++) { 9776 vport = &hdev->vport[i]; 9777 cfg = &vport->port_base_vlan_cfg; 9778 9779 ret = hclge_vlan_offload_cfg(vport, cfg->state, 9780 cfg->vlan_info.vlan_tag, 9781 cfg->vlan_info.qos); 9782 if (ret) 9783 return ret; 9784 } 9785 return 0; 9786 } 9787 9788 static int hclge_init_vlan_config(struct hclge_dev *hdev) 9789 { 9790 struct hnae3_handle *handle = &hdev->vport[0].nic; 9791 int ret; 9792 9793 ret = hclge_init_vlan_filter(hdev); 9794 if (ret) 9795 return ret; 9796 9797 ret = hclge_init_vlan_type(hdev); 9798 if (ret) 9799 return ret; 9800 9801 ret = hclge_init_vport_vlan_offload(hdev); 9802 if (ret) 9803 return ret; 9804 9805 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 9806 } 9807 9808 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 9809 bool writen_to_tbl) 9810 { 9811 struct hclge_vport_vlan_cfg *vlan, *tmp; 9812 9813 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9814 if (vlan->vlan_id == vlan_id) 9815 return; 9816 9817 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 9818 if (!vlan) 9819 return; 9820 9821 vlan->hd_tbl_status = writen_to_tbl; 9822 vlan->vlan_id = vlan_id; 9823 9824 list_add_tail(&vlan->node, &vport->vlan_list); 9825 } 9826 9827 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 9828 { 9829 struct hclge_vport_vlan_cfg *vlan, *tmp; 9830 struct hclge_dev *hdev = vport->back; 9831 int ret; 9832 9833 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 9834 if (!vlan->hd_tbl_status) { 9835 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 9836 vport->vport_id, 9837 vlan->vlan_id, false); 9838 if (ret) { 9839 dev_err(&hdev->pdev->dev, 9840 "restore vport vlan list failed, ret=%d\n", 9841 ret); 9842 return ret; 9843 } 9844 } 9845 vlan->hd_tbl_status = true; 9846 } 9847 9848 return 0; 9849 } 9850 9851 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 9852 bool is_write_tbl) 9853 { 9854 struct hclge_vport_vlan_cfg *vlan, *tmp; 9855 struct hclge_dev *hdev = vport->back; 9856 9857 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 9858 if (vlan->vlan_id == vlan_id) { 9859 if (is_write_tbl && vlan->hd_tbl_status) 9860 hclge_set_vlan_filter_hw(hdev, 9861 htons(ETH_P_8021Q), 9862 vport->vport_id, 9863 vlan_id, 9864 true); 9865 9866 list_del(&vlan->node); 9867 kfree(vlan); 9868 break; 9869 } 9870 } 9871 } 9872 9873 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 9874 { 9875 struct hclge_vport_vlan_cfg *vlan, *tmp; 9876 struct hclge_dev *hdev = vport->back; 9877 9878 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 9879 if (vlan->hd_tbl_status) 9880 hclge_set_vlan_filter_hw(hdev, 9881 htons(ETH_P_8021Q), 9882 vport->vport_id, 9883 vlan->vlan_id, 9884 true); 9885 9886 vlan->hd_tbl_status = false; 9887 if (is_del_list) { 9888 list_del(&vlan->node); 9889 kfree(vlan); 9890 } 9891 } 9892 clear_bit(vport->vport_id, hdev->vf_vlan_full); 9893 } 9894 9895 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 9896 { 9897 struct hclge_vport_vlan_cfg *vlan, *tmp; 9898 struct hclge_vport *vport; 9899 int i; 9900 9901 for (i = 0; i < hdev->num_alloc_vport; i++) { 9902 vport = &hdev->vport[i]; 9903 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 9904 list_del(&vlan->node); 9905 kfree(vlan); 9906 } 9907 } 9908 } 9909 9910 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 9911 { 9912 struct hclge_vport_vlan_cfg *vlan, *tmp; 9913 struct hclge_dev *hdev = vport->back; 9914 u16 vlan_proto; 9915 u16 vlan_id; 9916 u16 state; 9917 int ret; 9918 9919 vlan_proto = vport->port_base_vlan_cfg.vlan_info.vlan_proto; 9920 vlan_id = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 9921 state = vport->port_base_vlan_cfg.state; 9922 9923 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 9924 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 9925 hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 9926 vport->vport_id, vlan_id, 9927 false); 9928 return; 9929 } 9930 9931 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 9932 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 9933 vport->vport_id, 9934 vlan->vlan_id, false); 9935 if (ret) 9936 break; 9937 vlan->hd_tbl_status = true; 9938 } 9939 } 9940 9941 /* For global reset and imp reset, hardware will clear the mac table, 9942 * so we change the mac address state from ACTIVE to TO_ADD, then they 9943 * can be restored in the service task after reset complete. Furtherly, 9944 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 9945 * be restored after reset, so just remove these mac nodes from mac_list. 9946 */ 9947 static void hclge_mac_node_convert_for_reset(struct list_head *list) 9948 { 9949 struct hclge_mac_node *mac_node, *tmp; 9950 9951 list_for_each_entry_safe(mac_node, tmp, list, node) { 9952 if (mac_node->state == HCLGE_MAC_ACTIVE) { 9953 mac_node->state = HCLGE_MAC_TO_ADD; 9954 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 9955 list_del(&mac_node->node); 9956 kfree(mac_node); 9957 } 9958 } 9959 } 9960 9961 void hclge_restore_mac_table_common(struct hclge_vport *vport) 9962 { 9963 spin_lock_bh(&vport->mac_list_lock); 9964 9965 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 9966 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 9967 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9968 9969 spin_unlock_bh(&vport->mac_list_lock); 9970 } 9971 9972 static void hclge_restore_hw_table(struct hclge_dev *hdev) 9973 { 9974 struct hclge_vport *vport = &hdev->vport[0]; 9975 struct hnae3_handle *handle = &vport->nic; 9976 9977 hclge_restore_mac_table_common(vport); 9978 hclge_restore_vport_vlan_table(vport); 9979 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 9980 hclge_restore_fd_entries(handle); 9981 } 9982 9983 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 9984 { 9985 struct hclge_vport *vport = hclge_get_vport(handle); 9986 9987 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9988 vport->rxvlan_cfg.strip_tag1_en = false; 9989 vport->rxvlan_cfg.strip_tag2_en = enable; 9990 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9991 } else { 9992 vport->rxvlan_cfg.strip_tag1_en = enable; 9993 vport->rxvlan_cfg.strip_tag2_en = true; 9994 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9995 } 9996 9997 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9998 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9999 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10000 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10001 10002 return hclge_set_vlan_rx_offload_cfg(vport); 10003 } 10004 10005 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10006 { 10007 struct hclge_dev *hdev = vport->back; 10008 10009 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10010 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10011 } 10012 10013 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10014 u16 port_base_vlan_state, 10015 struct hclge_vlan_info *new_info, 10016 struct hclge_vlan_info *old_info) 10017 { 10018 struct hclge_dev *hdev = vport->back; 10019 int ret; 10020 10021 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10022 hclge_rm_vport_all_vlan_table(vport, false); 10023 /* force clear VLAN 0 */ 10024 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10025 if (ret) 10026 return ret; 10027 return hclge_set_vlan_filter_hw(hdev, 10028 htons(new_info->vlan_proto), 10029 vport->vport_id, 10030 new_info->vlan_tag, 10031 false); 10032 } 10033 10034 /* force add VLAN 0 */ 10035 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10036 if (ret) 10037 return ret; 10038 10039 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10040 vport->vport_id, old_info->vlan_tag, 10041 true); 10042 if (ret) 10043 return ret; 10044 10045 return hclge_add_vport_all_vlan_table(vport); 10046 } 10047 10048 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10049 const struct hclge_vlan_info *old_cfg) 10050 { 10051 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10052 return true; 10053 10054 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10055 return true; 10056 10057 return false; 10058 } 10059 10060 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10061 struct hclge_vlan_info *new_info, 10062 struct hclge_vlan_info *old_info) 10063 { 10064 struct hclge_dev *hdev = vport->back; 10065 int ret; 10066 10067 /* add new VLAN tag */ 10068 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10069 vport->vport_id, new_info->vlan_tag, 10070 false); 10071 if (ret) 10072 return ret; 10073 10074 /* remove old VLAN tag */ 10075 if (old_info->vlan_tag == 0) 10076 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10077 true, 0); 10078 else 10079 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10080 vport->vport_id, 10081 old_info->vlan_tag, true); 10082 if (ret) 10083 dev_err(&hdev->pdev->dev, 10084 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10085 vport->vport_id, old_info->vlan_tag, ret); 10086 10087 return ret; 10088 } 10089 10090 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10091 struct hclge_vlan_info *vlan_info) 10092 { 10093 struct hnae3_handle *nic = &vport->nic; 10094 struct hclge_vlan_info *old_vlan_info; 10095 int ret; 10096 10097 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10098 10099 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10100 vlan_info->qos); 10101 if (ret) 10102 return ret; 10103 10104 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10105 goto out; 10106 10107 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10108 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10109 old_vlan_info); 10110 else 10111 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10112 old_vlan_info); 10113 if (ret) 10114 return ret; 10115 10116 out: 10117 vport->port_base_vlan_cfg.state = state; 10118 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10119 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10120 else 10121 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10122 10123 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10124 hclge_set_vport_vlan_fltr_change(vport); 10125 10126 return 0; 10127 } 10128 10129 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10130 enum hnae3_port_base_vlan_state state, 10131 u16 vlan, u8 qos) 10132 { 10133 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10134 if (!vlan && !qos) 10135 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10136 10137 return HNAE3_PORT_BASE_VLAN_ENABLE; 10138 } 10139 10140 if (!vlan && !qos) 10141 return HNAE3_PORT_BASE_VLAN_DISABLE; 10142 10143 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10144 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10145 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10146 10147 return HNAE3_PORT_BASE_VLAN_MODIFY; 10148 } 10149 10150 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10151 u16 vlan, u8 qos, __be16 proto) 10152 { 10153 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10154 struct hclge_vport *vport = hclge_get_vport(handle); 10155 struct hclge_dev *hdev = vport->back; 10156 struct hclge_vlan_info vlan_info; 10157 u16 state; 10158 int ret; 10159 10160 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10161 return -EOPNOTSUPP; 10162 10163 vport = hclge_get_vf_vport(hdev, vfid); 10164 if (!vport) 10165 return -EINVAL; 10166 10167 /* qos is a 3 bits value, so can not be bigger than 7 */ 10168 if (vlan > VLAN_N_VID - 1 || qos > 7) 10169 return -EINVAL; 10170 if (proto != htons(ETH_P_8021Q)) 10171 return -EPROTONOSUPPORT; 10172 10173 state = hclge_get_port_base_vlan_state(vport, 10174 vport->port_base_vlan_cfg.state, 10175 vlan, qos); 10176 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10177 return 0; 10178 10179 vlan_info.vlan_tag = vlan; 10180 vlan_info.qos = qos; 10181 vlan_info.vlan_proto = ntohs(proto); 10182 10183 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10184 if (ret) { 10185 dev_err(&hdev->pdev->dev, 10186 "failed to update port base vlan for vf %d, ret = %d\n", 10187 vfid, ret); 10188 return ret; 10189 } 10190 10191 /* for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10192 * VLAN state. 10193 */ 10194 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3 && 10195 test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10196 hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10197 vport->vport_id, state, 10198 &vlan_info); 10199 10200 return 0; 10201 } 10202 10203 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10204 { 10205 struct hclge_vlan_info *vlan_info; 10206 struct hclge_vport *vport; 10207 int ret; 10208 int vf; 10209 10210 /* clear port base vlan for all vf */ 10211 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10212 vport = &hdev->vport[vf]; 10213 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10214 10215 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10216 vport->vport_id, 10217 vlan_info->vlan_tag, true); 10218 if (ret) 10219 dev_err(&hdev->pdev->dev, 10220 "failed to clear vf vlan for vf%d, ret = %d\n", 10221 vf - HCLGE_VF_VPORT_START_NUM, ret); 10222 } 10223 } 10224 10225 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10226 u16 vlan_id, bool is_kill) 10227 { 10228 struct hclge_vport *vport = hclge_get_vport(handle); 10229 struct hclge_dev *hdev = vport->back; 10230 bool writen_to_tbl = false; 10231 int ret = 0; 10232 10233 /* When device is resetting or reset failed, firmware is unable to 10234 * handle mailbox. Just record the vlan id, and remove it after 10235 * reset finished. 10236 */ 10237 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10238 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10239 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10240 return -EBUSY; 10241 } 10242 10243 /* when port base vlan enabled, we use port base vlan as the vlan 10244 * filter entry. In this case, we don't update vlan filter table 10245 * when user add new vlan or remove exist vlan, just update the vport 10246 * vlan list. The vlan id in vlan list will be writen in vlan filter 10247 * table until port base vlan disabled 10248 */ 10249 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10250 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10251 vlan_id, is_kill); 10252 writen_to_tbl = true; 10253 } 10254 10255 if (!ret) { 10256 if (is_kill) 10257 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10258 else 10259 hclge_add_vport_vlan_table(vport, vlan_id, 10260 writen_to_tbl); 10261 } else if (is_kill) { 10262 /* when remove hw vlan filter failed, record the vlan id, 10263 * and try to remove it from hw later, to be consistence 10264 * with stack 10265 */ 10266 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10267 } 10268 10269 hclge_set_vport_vlan_fltr_change(vport); 10270 10271 return ret; 10272 } 10273 10274 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10275 { 10276 struct hclge_vport *vport; 10277 int ret; 10278 u16 i; 10279 10280 for (i = 0; i < hdev->num_alloc_vport; i++) { 10281 vport = &hdev->vport[i]; 10282 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10283 &vport->state)) 10284 continue; 10285 10286 ret = hclge_enable_vport_vlan_filter(vport, 10287 vport->req_vlan_fltr_en); 10288 if (ret) { 10289 dev_err(&hdev->pdev->dev, 10290 "failed to sync vlan filter state for vport%u, ret = %d\n", 10291 vport->vport_id, ret); 10292 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10293 &vport->state); 10294 return; 10295 } 10296 } 10297 } 10298 10299 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10300 { 10301 #define HCLGE_MAX_SYNC_COUNT 60 10302 10303 int i, ret, sync_cnt = 0; 10304 u16 vlan_id; 10305 10306 /* start from vport 1 for PF is always alive */ 10307 for (i = 0; i < hdev->num_alloc_vport; i++) { 10308 struct hclge_vport *vport = &hdev->vport[i]; 10309 10310 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10311 VLAN_N_VID); 10312 while (vlan_id != VLAN_N_VID) { 10313 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10314 vport->vport_id, vlan_id, 10315 true); 10316 if (ret && ret != -EINVAL) 10317 return; 10318 10319 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10320 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10321 hclge_set_vport_vlan_fltr_change(vport); 10322 10323 sync_cnt++; 10324 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) 10325 return; 10326 10327 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10328 VLAN_N_VID); 10329 } 10330 } 10331 10332 hclge_sync_vlan_fltr_state(hdev); 10333 } 10334 10335 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10336 { 10337 struct hclge_config_max_frm_size_cmd *req; 10338 struct hclge_desc desc; 10339 10340 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10341 10342 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10343 req->max_frm_size = cpu_to_le16(new_mps); 10344 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10345 10346 return hclge_cmd_send(&hdev->hw, &desc, 1); 10347 } 10348 10349 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10350 { 10351 struct hclge_vport *vport = hclge_get_vport(handle); 10352 10353 return hclge_set_vport_mtu(vport, new_mtu); 10354 } 10355 10356 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10357 { 10358 struct hclge_dev *hdev = vport->back; 10359 int i, max_frm_size, ret; 10360 10361 /* HW supprt 2 layer vlan */ 10362 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10363 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10364 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10365 return -EINVAL; 10366 10367 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10368 mutex_lock(&hdev->vport_lock); 10369 /* VF's mps must fit within hdev->mps */ 10370 if (vport->vport_id && max_frm_size > hdev->mps) { 10371 mutex_unlock(&hdev->vport_lock); 10372 return -EINVAL; 10373 } else if (vport->vport_id) { 10374 vport->mps = max_frm_size; 10375 mutex_unlock(&hdev->vport_lock); 10376 return 0; 10377 } 10378 10379 /* PF's mps must be greater then VF's mps */ 10380 for (i = 1; i < hdev->num_alloc_vport; i++) 10381 if (max_frm_size < hdev->vport[i].mps) { 10382 mutex_unlock(&hdev->vport_lock); 10383 return -EINVAL; 10384 } 10385 10386 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10387 10388 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10389 if (ret) { 10390 dev_err(&hdev->pdev->dev, 10391 "Change mtu fail, ret =%d\n", ret); 10392 goto out; 10393 } 10394 10395 hdev->mps = max_frm_size; 10396 vport->mps = max_frm_size; 10397 10398 ret = hclge_buffer_alloc(hdev); 10399 if (ret) 10400 dev_err(&hdev->pdev->dev, 10401 "Allocate buffer fail, ret =%d\n", ret); 10402 10403 out: 10404 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10405 mutex_unlock(&hdev->vport_lock); 10406 return ret; 10407 } 10408 10409 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10410 bool enable) 10411 { 10412 struct hclge_reset_tqp_queue_cmd *req; 10413 struct hclge_desc desc; 10414 int ret; 10415 10416 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10417 10418 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10419 req->tqp_id = cpu_to_le16(queue_id); 10420 if (enable) 10421 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10422 10423 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10424 if (ret) { 10425 dev_err(&hdev->pdev->dev, 10426 "Send tqp reset cmd error, status =%d\n", ret); 10427 return ret; 10428 } 10429 10430 return 0; 10431 } 10432 10433 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10434 u8 *reset_status) 10435 { 10436 struct hclge_reset_tqp_queue_cmd *req; 10437 struct hclge_desc desc; 10438 int ret; 10439 10440 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10441 10442 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10443 req->tqp_id = cpu_to_le16(queue_id); 10444 10445 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10446 if (ret) { 10447 dev_err(&hdev->pdev->dev, 10448 "Get reset status error, status =%d\n", ret); 10449 return ret; 10450 } 10451 10452 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10453 10454 return 0; 10455 } 10456 10457 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10458 { 10459 struct hclge_comm_tqp *tqp; 10460 struct hnae3_queue *queue; 10461 10462 queue = handle->kinfo.tqp[queue_id]; 10463 tqp = container_of(queue, struct hclge_comm_tqp, q); 10464 10465 return tqp->index; 10466 } 10467 10468 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10469 { 10470 struct hclge_vport *vport = hclge_get_vport(handle); 10471 struct hclge_dev *hdev = vport->back; 10472 u16 reset_try_times = 0; 10473 u8 reset_status; 10474 u16 queue_gid; 10475 int ret; 10476 u16 i; 10477 10478 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10479 queue_gid = hclge_covert_handle_qid_global(handle, i); 10480 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10481 if (ret) { 10482 dev_err(&hdev->pdev->dev, 10483 "failed to send reset tqp cmd, ret = %d\n", 10484 ret); 10485 return ret; 10486 } 10487 10488 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10489 ret = hclge_get_reset_status(hdev, queue_gid, 10490 &reset_status); 10491 if (ret) 10492 return ret; 10493 10494 if (reset_status) 10495 break; 10496 10497 /* Wait for tqp hw reset */ 10498 usleep_range(1000, 1200); 10499 } 10500 10501 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10502 dev_err(&hdev->pdev->dev, 10503 "wait for tqp hw reset timeout\n"); 10504 return -ETIME; 10505 } 10506 10507 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10508 if (ret) { 10509 dev_err(&hdev->pdev->dev, 10510 "failed to deassert soft reset, ret = %d\n", 10511 ret); 10512 return ret; 10513 } 10514 reset_try_times = 0; 10515 } 10516 return 0; 10517 } 10518 10519 static int hclge_reset_rcb(struct hnae3_handle *handle) 10520 { 10521 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10522 #define HCLGE_RESET_RCB_SUCCESS 1U 10523 10524 struct hclge_vport *vport = hclge_get_vport(handle); 10525 struct hclge_dev *hdev = vport->back; 10526 struct hclge_reset_cmd *req; 10527 struct hclge_desc desc; 10528 u8 return_status; 10529 u16 queue_gid; 10530 int ret; 10531 10532 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10533 10534 req = (struct hclge_reset_cmd *)desc.data; 10535 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10536 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10537 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10538 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10539 10540 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10541 if (ret) { 10542 dev_err(&hdev->pdev->dev, 10543 "failed to send rcb reset cmd, ret = %d\n", ret); 10544 return ret; 10545 } 10546 10547 return_status = req->fun_reset_rcb_return_status; 10548 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10549 return 0; 10550 10551 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10552 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10553 return_status); 10554 return -EIO; 10555 } 10556 10557 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10558 * again to reset all tqps 10559 */ 10560 return hclge_reset_tqp_cmd(handle); 10561 } 10562 10563 int hclge_reset_tqp(struct hnae3_handle *handle) 10564 { 10565 struct hclge_vport *vport = hclge_get_vport(handle); 10566 struct hclge_dev *hdev = vport->back; 10567 int ret; 10568 10569 /* only need to disable PF's tqp */ 10570 if (!vport->vport_id) { 10571 ret = hclge_tqp_enable(handle, false); 10572 if (ret) { 10573 dev_err(&hdev->pdev->dev, 10574 "failed to disable tqp, ret = %d\n", ret); 10575 return ret; 10576 } 10577 } 10578 10579 return hclge_reset_rcb(handle); 10580 } 10581 10582 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10583 { 10584 struct hclge_vport *vport = hclge_get_vport(handle); 10585 struct hclge_dev *hdev = vport->back; 10586 10587 return hdev->fw_version; 10588 } 10589 10590 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10591 { 10592 struct phy_device *phydev = hdev->hw.mac.phydev; 10593 10594 if (!phydev) 10595 return; 10596 10597 phy_set_asym_pause(phydev, rx_en, tx_en); 10598 } 10599 10600 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10601 { 10602 int ret; 10603 10604 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10605 return 0; 10606 10607 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10608 if (ret) 10609 dev_err(&hdev->pdev->dev, 10610 "configure pauseparam error, ret = %d.\n", ret); 10611 10612 return ret; 10613 } 10614 10615 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10616 { 10617 struct phy_device *phydev = hdev->hw.mac.phydev; 10618 u16 remote_advertising = 0; 10619 u16 local_advertising; 10620 u32 rx_pause, tx_pause; 10621 u8 flowctl; 10622 10623 if (!phydev->link || !phydev->autoneg) 10624 return 0; 10625 10626 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10627 10628 if (phydev->pause) 10629 remote_advertising = LPA_PAUSE_CAP; 10630 10631 if (phydev->asym_pause) 10632 remote_advertising |= LPA_PAUSE_ASYM; 10633 10634 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10635 remote_advertising); 10636 tx_pause = flowctl & FLOW_CTRL_TX; 10637 rx_pause = flowctl & FLOW_CTRL_RX; 10638 10639 if (phydev->duplex == HCLGE_MAC_HALF) { 10640 tx_pause = 0; 10641 rx_pause = 0; 10642 } 10643 10644 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10645 } 10646 10647 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10648 u32 *rx_en, u32 *tx_en) 10649 { 10650 struct hclge_vport *vport = hclge_get_vport(handle); 10651 struct hclge_dev *hdev = vport->back; 10652 u8 media_type = hdev->hw.mac.media_type; 10653 10654 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10655 hclge_get_autoneg(handle) : 0; 10656 10657 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10658 *rx_en = 0; 10659 *tx_en = 0; 10660 return; 10661 } 10662 10663 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10664 *rx_en = 1; 10665 *tx_en = 0; 10666 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10667 *tx_en = 1; 10668 *rx_en = 0; 10669 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10670 *rx_en = 1; 10671 *tx_en = 1; 10672 } else { 10673 *rx_en = 0; 10674 *tx_en = 0; 10675 } 10676 } 10677 10678 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10679 u32 rx_en, u32 tx_en) 10680 { 10681 if (rx_en && tx_en) 10682 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10683 else if (rx_en && !tx_en) 10684 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10685 else if (!rx_en && tx_en) 10686 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10687 else 10688 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10689 10690 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10691 } 10692 10693 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10694 u32 rx_en, u32 tx_en) 10695 { 10696 struct hclge_vport *vport = hclge_get_vport(handle); 10697 struct hclge_dev *hdev = vport->back; 10698 struct phy_device *phydev = hdev->hw.mac.phydev; 10699 u32 fc_autoneg; 10700 10701 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10702 fc_autoneg = hclge_get_autoneg(handle); 10703 if (auto_neg != fc_autoneg) { 10704 dev_info(&hdev->pdev->dev, 10705 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 10706 return -EOPNOTSUPP; 10707 } 10708 } 10709 10710 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10711 dev_info(&hdev->pdev->dev, 10712 "Priority flow control enabled. Cannot set link flow control.\n"); 10713 return -EOPNOTSUPP; 10714 } 10715 10716 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 10717 10718 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 10719 10720 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 10721 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 10722 10723 if (phydev) 10724 return phy_start_aneg(phydev); 10725 10726 return -EOPNOTSUPP; 10727 } 10728 10729 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 10730 u8 *auto_neg, u32 *speed, u8 *duplex) 10731 { 10732 struct hclge_vport *vport = hclge_get_vport(handle); 10733 struct hclge_dev *hdev = vport->back; 10734 10735 if (speed) 10736 *speed = hdev->hw.mac.speed; 10737 if (duplex) 10738 *duplex = hdev->hw.mac.duplex; 10739 if (auto_neg) 10740 *auto_neg = hdev->hw.mac.autoneg; 10741 } 10742 10743 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 10744 u8 *module_type) 10745 { 10746 struct hclge_vport *vport = hclge_get_vport(handle); 10747 struct hclge_dev *hdev = vport->back; 10748 10749 /* When nic is down, the service task is not running, doesn't update 10750 * the port information per second. Query the port information before 10751 * return the media type, ensure getting the correct media information. 10752 */ 10753 hclge_update_port_info(hdev); 10754 10755 if (media_type) 10756 *media_type = hdev->hw.mac.media_type; 10757 10758 if (module_type) 10759 *module_type = hdev->hw.mac.module_type; 10760 } 10761 10762 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 10763 u8 *tp_mdix_ctrl, u8 *tp_mdix) 10764 { 10765 struct hclge_vport *vport = hclge_get_vport(handle); 10766 struct hclge_dev *hdev = vport->back; 10767 struct phy_device *phydev = hdev->hw.mac.phydev; 10768 int mdix_ctrl, mdix, is_resolved; 10769 unsigned int retval; 10770 10771 if (!phydev) { 10772 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 10773 *tp_mdix = ETH_TP_MDI_INVALID; 10774 return; 10775 } 10776 10777 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 10778 10779 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 10780 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 10781 HCLGE_PHY_MDIX_CTRL_S); 10782 10783 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 10784 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 10785 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 10786 10787 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 10788 10789 switch (mdix_ctrl) { 10790 case 0x0: 10791 *tp_mdix_ctrl = ETH_TP_MDI; 10792 break; 10793 case 0x1: 10794 *tp_mdix_ctrl = ETH_TP_MDI_X; 10795 break; 10796 case 0x3: 10797 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 10798 break; 10799 default: 10800 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 10801 break; 10802 } 10803 10804 if (!is_resolved) 10805 *tp_mdix = ETH_TP_MDI_INVALID; 10806 else if (mdix) 10807 *tp_mdix = ETH_TP_MDI_X; 10808 else 10809 *tp_mdix = ETH_TP_MDI; 10810 } 10811 10812 static void hclge_info_show(struct hclge_dev *hdev) 10813 { 10814 struct device *dev = &hdev->pdev->dev; 10815 10816 dev_info(dev, "PF info begin:\n"); 10817 10818 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 10819 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 10820 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 10821 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 10822 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 10823 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 10824 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 10825 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 10826 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 10827 dev_info(dev, "This is %s PF\n", 10828 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 10829 dev_info(dev, "DCB %s\n", 10830 hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable"); 10831 dev_info(dev, "MQPRIO %s\n", 10832 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable"); 10833 dev_info(dev, "Default tx spare buffer size: %u\n", 10834 hdev->tx_spare_buf_size); 10835 10836 dev_info(dev, "PF info end.\n"); 10837 } 10838 10839 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 10840 struct hclge_vport *vport) 10841 { 10842 struct hnae3_client *client = vport->nic.client; 10843 struct hclge_dev *hdev = ae_dev->priv; 10844 int rst_cnt = hdev->rst_stats.reset_cnt; 10845 int ret; 10846 10847 ret = client->ops->init_instance(&vport->nic); 10848 if (ret) 10849 return ret; 10850 10851 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 10852 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10853 rst_cnt != hdev->rst_stats.reset_cnt) { 10854 ret = -EBUSY; 10855 goto init_nic_err; 10856 } 10857 10858 /* Enable nic hw error interrupts */ 10859 ret = hclge_config_nic_hw_error(hdev, true); 10860 if (ret) { 10861 dev_err(&ae_dev->pdev->dev, 10862 "fail(%d) to enable hw error interrupts\n", ret); 10863 goto init_nic_err; 10864 } 10865 10866 hnae3_set_client_init_flag(client, ae_dev, 1); 10867 10868 if (netif_msg_drv(&hdev->vport->nic)) 10869 hclge_info_show(hdev); 10870 10871 return ret; 10872 10873 init_nic_err: 10874 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 10875 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 10876 msleep(HCLGE_WAIT_RESET_DONE); 10877 10878 client->ops->uninit_instance(&vport->nic, 0); 10879 10880 return ret; 10881 } 10882 10883 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 10884 struct hclge_vport *vport) 10885 { 10886 struct hclge_dev *hdev = ae_dev->priv; 10887 struct hnae3_client *client; 10888 int rst_cnt; 10889 int ret; 10890 10891 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 10892 !hdev->nic_client) 10893 return 0; 10894 10895 client = hdev->roce_client; 10896 ret = hclge_init_roce_base_info(vport); 10897 if (ret) 10898 return ret; 10899 10900 rst_cnt = hdev->rst_stats.reset_cnt; 10901 ret = client->ops->init_instance(&vport->roce); 10902 if (ret) 10903 return ret; 10904 10905 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 10906 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10907 rst_cnt != hdev->rst_stats.reset_cnt) { 10908 ret = -EBUSY; 10909 goto init_roce_err; 10910 } 10911 10912 /* Enable roce ras interrupts */ 10913 ret = hclge_config_rocee_ras_interrupt(hdev, true); 10914 if (ret) { 10915 dev_err(&ae_dev->pdev->dev, 10916 "fail(%d) to enable roce ras interrupts\n", ret); 10917 goto init_roce_err; 10918 } 10919 10920 hnae3_set_client_init_flag(client, ae_dev, 1); 10921 10922 return 0; 10923 10924 init_roce_err: 10925 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 10926 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 10927 msleep(HCLGE_WAIT_RESET_DONE); 10928 10929 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 10930 10931 return ret; 10932 } 10933 10934 static int hclge_init_client_instance(struct hnae3_client *client, 10935 struct hnae3_ae_dev *ae_dev) 10936 { 10937 struct hclge_dev *hdev = ae_dev->priv; 10938 struct hclge_vport *vport = &hdev->vport[0]; 10939 int ret; 10940 10941 switch (client->type) { 10942 case HNAE3_CLIENT_KNIC: 10943 hdev->nic_client = client; 10944 vport->nic.client = client; 10945 ret = hclge_init_nic_client_instance(ae_dev, vport); 10946 if (ret) 10947 goto clear_nic; 10948 10949 ret = hclge_init_roce_client_instance(ae_dev, vport); 10950 if (ret) 10951 goto clear_roce; 10952 10953 break; 10954 case HNAE3_CLIENT_ROCE: 10955 if (hnae3_dev_roce_supported(hdev)) { 10956 hdev->roce_client = client; 10957 vport->roce.client = client; 10958 } 10959 10960 ret = hclge_init_roce_client_instance(ae_dev, vport); 10961 if (ret) 10962 goto clear_roce; 10963 10964 break; 10965 default: 10966 return -EINVAL; 10967 } 10968 10969 return 0; 10970 10971 clear_nic: 10972 hdev->nic_client = NULL; 10973 vport->nic.client = NULL; 10974 return ret; 10975 clear_roce: 10976 hdev->roce_client = NULL; 10977 vport->roce.client = NULL; 10978 return ret; 10979 } 10980 10981 static void hclge_uninit_client_instance(struct hnae3_client *client, 10982 struct hnae3_ae_dev *ae_dev) 10983 { 10984 struct hclge_dev *hdev = ae_dev->priv; 10985 struct hclge_vport *vport = &hdev->vport[0]; 10986 10987 if (hdev->roce_client) { 10988 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 10989 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 10990 msleep(HCLGE_WAIT_RESET_DONE); 10991 10992 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 10993 hdev->roce_client = NULL; 10994 vport->roce.client = NULL; 10995 } 10996 if (client->type == HNAE3_CLIENT_ROCE) 10997 return; 10998 if (hdev->nic_client && client->ops->uninit_instance) { 10999 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11000 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11001 msleep(HCLGE_WAIT_RESET_DONE); 11002 11003 client->ops->uninit_instance(&vport->nic, 0); 11004 hdev->nic_client = NULL; 11005 vport->nic.client = NULL; 11006 } 11007 } 11008 11009 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11010 { 11011 #define HCLGE_MEM_BAR 4 11012 11013 struct pci_dev *pdev = hdev->pdev; 11014 struct hclge_hw *hw = &hdev->hw; 11015 11016 /* for device does not have device memory, return directly */ 11017 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11018 return 0; 11019 11020 hw->hw.mem_base = 11021 devm_ioremap_wc(&pdev->dev, 11022 pci_resource_start(pdev, HCLGE_MEM_BAR), 11023 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11024 if (!hw->hw.mem_base) { 11025 dev_err(&pdev->dev, "failed to map device memory\n"); 11026 return -EFAULT; 11027 } 11028 11029 return 0; 11030 } 11031 11032 static int hclge_pci_init(struct hclge_dev *hdev) 11033 { 11034 struct pci_dev *pdev = hdev->pdev; 11035 struct hclge_hw *hw; 11036 int ret; 11037 11038 ret = pci_enable_device(pdev); 11039 if (ret) { 11040 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11041 return ret; 11042 } 11043 11044 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11045 if (ret) { 11046 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11047 if (ret) { 11048 dev_err(&pdev->dev, 11049 "can't set consistent PCI DMA"); 11050 goto err_disable_device; 11051 } 11052 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11053 } 11054 11055 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11056 if (ret) { 11057 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11058 goto err_disable_device; 11059 } 11060 11061 pci_set_master(pdev); 11062 hw = &hdev->hw; 11063 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11064 if (!hw->hw.io_base) { 11065 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11066 ret = -ENOMEM; 11067 goto err_clr_master; 11068 } 11069 11070 ret = hclge_dev_mem_map(hdev); 11071 if (ret) 11072 goto err_unmap_io_base; 11073 11074 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11075 11076 return 0; 11077 11078 err_unmap_io_base: 11079 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11080 err_clr_master: 11081 pci_clear_master(pdev); 11082 pci_release_regions(pdev); 11083 err_disable_device: 11084 pci_disable_device(pdev); 11085 11086 return ret; 11087 } 11088 11089 static void hclge_pci_uninit(struct hclge_dev *hdev) 11090 { 11091 struct pci_dev *pdev = hdev->pdev; 11092 11093 if (hdev->hw.hw.mem_base) 11094 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11095 11096 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11097 pci_free_irq_vectors(pdev); 11098 pci_clear_master(pdev); 11099 pci_release_mem_regions(pdev); 11100 pci_disable_device(pdev); 11101 } 11102 11103 static void hclge_state_init(struct hclge_dev *hdev) 11104 { 11105 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11106 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11107 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11108 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11109 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11110 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11111 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11112 } 11113 11114 static void hclge_state_uninit(struct hclge_dev *hdev) 11115 { 11116 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11117 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11118 11119 if (hdev->reset_timer.function) 11120 del_timer_sync(&hdev->reset_timer); 11121 if (hdev->service_task.work.func) 11122 cancel_delayed_work_sync(&hdev->service_task); 11123 } 11124 11125 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11126 enum hnae3_reset_type rst_type) 11127 { 11128 #define HCLGE_RESET_RETRY_WAIT_MS 500 11129 #define HCLGE_RESET_RETRY_CNT 5 11130 11131 struct hclge_dev *hdev = ae_dev->priv; 11132 int retry_cnt = 0; 11133 int ret; 11134 11135 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11136 down(&hdev->reset_sem); 11137 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11138 hdev->reset_type = rst_type; 11139 ret = hclge_reset_prepare(hdev); 11140 if (!ret && !hdev->reset_pending) 11141 break; 11142 11143 dev_err(&hdev->pdev->dev, 11144 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11145 ret, hdev->reset_pending, retry_cnt); 11146 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11147 up(&hdev->reset_sem); 11148 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11149 } 11150 11151 /* disable misc vector before reset done */ 11152 hclge_enable_vector(&hdev->misc_vector, false); 11153 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11154 11155 if (hdev->reset_type == HNAE3_FLR_RESET) 11156 hdev->rst_stats.flr_rst_cnt++; 11157 } 11158 11159 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11160 { 11161 struct hclge_dev *hdev = ae_dev->priv; 11162 int ret; 11163 11164 hclge_enable_vector(&hdev->misc_vector, true); 11165 11166 ret = hclge_reset_rebuild(hdev); 11167 if (ret) 11168 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11169 11170 hdev->reset_type = HNAE3_NONE_RESET; 11171 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11172 up(&hdev->reset_sem); 11173 } 11174 11175 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11176 { 11177 u16 i; 11178 11179 for (i = 0; i < hdev->num_alloc_vport; i++) { 11180 struct hclge_vport *vport = &hdev->vport[i]; 11181 int ret; 11182 11183 /* Send cmd to clear vport's FUNC_RST_ING */ 11184 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11185 if (ret) 11186 dev_warn(&hdev->pdev->dev, 11187 "clear vport(%u) rst failed %d!\n", 11188 vport->vport_id, ret); 11189 } 11190 } 11191 11192 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11193 { 11194 struct hclge_desc desc; 11195 int ret; 11196 11197 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11198 11199 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11200 /* This new command is only supported by new firmware, it will 11201 * fail with older firmware. Error value -EOPNOSUPP can only be 11202 * returned by older firmware running this command, to keep code 11203 * backward compatible we will override this value and return 11204 * success. 11205 */ 11206 if (ret && ret != -EOPNOTSUPP) { 11207 dev_err(&hdev->pdev->dev, 11208 "failed to clear hw resource, ret = %d\n", ret); 11209 return ret; 11210 } 11211 return 0; 11212 } 11213 11214 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11215 { 11216 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11217 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11218 } 11219 11220 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11221 { 11222 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11223 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11224 } 11225 11226 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11227 { 11228 struct pci_dev *pdev = ae_dev->pdev; 11229 struct hclge_dev *hdev; 11230 int ret; 11231 11232 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11233 if (!hdev) 11234 return -ENOMEM; 11235 11236 hdev->pdev = pdev; 11237 hdev->ae_dev = ae_dev; 11238 hdev->reset_type = HNAE3_NONE_RESET; 11239 hdev->reset_level = HNAE3_FUNC_RESET; 11240 ae_dev->priv = hdev; 11241 11242 /* HW supprt 2 layer vlan */ 11243 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11244 11245 mutex_init(&hdev->vport_lock); 11246 spin_lock_init(&hdev->fd_rule_lock); 11247 sema_init(&hdev->reset_sem, 1); 11248 11249 ret = hclge_pci_init(hdev); 11250 if (ret) 11251 goto out; 11252 11253 ret = hclge_devlink_init(hdev); 11254 if (ret) 11255 goto err_pci_uninit; 11256 11257 /* Firmware command queue initialize */ 11258 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11259 if (ret) 11260 goto err_devlink_uninit; 11261 11262 /* Firmware command initialize */ 11263 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11264 true, hdev->reset_pending); 11265 if (ret) 11266 goto err_cmd_uninit; 11267 11268 ret = hclge_clear_hw_resource(hdev); 11269 if (ret) 11270 goto err_cmd_uninit; 11271 11272 ret = hclge_get_cap(hdev); 11273 if (ret) 11274 goto err_cmd_uninit; 11275 11276 ret = hclge_query_dev_specs(hdev); 11277 if (ret) { 11278 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11279 ret); 11280 goto err_cmd_uninit; 11281 } 11282 11283 ret = hclge_configure(hdev); 11284 if (ret) { 11285 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11286 goto err_cmd_uninit; 11287 } 11288 11289 ret = hclge_init_msi(hdev); 11290 if (ret) { 11291 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11292 goto err_cmd_uninit; 11293 } 11294 11295 ret = hclge_misc_irq_init(hdev); 11296 if (ret) 11297 goto err_msi_uninit; 11298 11299 ret = hclge_alloc_tqps(hdev); 11300 if (ret) { 11301 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11302 goto err_msi_irq_uninit; 11303 } 11304 11305 ret = hclge_alloc_vport(hdev); 11306 if (ret) 11307 goto err_msi_irq_uninit; 11308 11309 ret = hclge_map_tqp(hdev); 11310 if (ret) 11311 goto err_msi_irq_uninit; 11312 11313 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER && 11314 !hnae3_dev_phy_imp_supported(hdev)) { 11315 ret = hclge_mac_mdio_config(hdev); 11316 if (ret) 11317 goto err_msi_irq_uninit; 11318 } 11319 11320 ret = hclge_init_umv_space(hdev); 11321 if (ret) 11322 goto err_mdiobus_unreg; 11323 11324 ret = hclge_mac_init(hdev); 11325 if (ret) { 11326 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11327 goto err_mdiobus_unreg; 11328 } 11329 11330 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11331 if (ret) { 11332 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11333 goto err_mdiobus_unreg; 11334 } 11335 11336 ret = hclge_config_gro(hdev); 11337 if (ret) 11338 goto err_mdiobus_unreg; 11339 11340 ret = hclge_init_vlan_config(hdev); 11341 if (ret) { 11342 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11343 goto err_mdiobus_unreg; 11344 } 11345 11346 ret = hclge_tm_schd_init(hdev); 11347 if (ret) { 11348 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11349 goto err_mdiobus_unreg; 11350 } 11351 11352 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11353 &hdev->rss_cfg); 11354 if (ret) { 11355 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11356 goto err_mdiobus_unreg; 11357 } 11358 11359 ret = hclge_rss_init_hw(hdev); 11360 if (ret) { 11361 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11362 goto err_mdiobus_unreg; 11363 } 11364 11365 ret = init_mgr_tbl(hdev); 11366 if (ret) { 11367 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11368 goto err_mdiobus_unreg; 11369 } 11370 11371 ret = hclge_init_fd_config(hdev); 11372 if (ret) { 11373 dev_err(&pdev->dev, 11374 "fd table init fail, ret=%d\n", ret); 11375 goto err_mdiobus_unreg; 11376 } 11377 11378 ret = hclge_ptp_init(hdev); 11379 if (ret) 11380 goto err_mdiobus_unreg; 11381 11382 INIT_KFIFO(hdev->mac_tnl_log); 11383 11384 hclge_dcb_ops_set(hdev); 11385 11386 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11387 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11388 11389 /* Setup affinity after service timer setup because add_timer_on 11390 * is called in affinity notify. 11391 */ 11392 hclge_misc_affinity_setup(hdev); 11393 11394 hclge_clear_all_event_cause(hdev); 11395 hclge_clear_resetting_state(hdev); 11396 11397 /* Log and clear the hw errors those already occurred */ 11398 if (hnae3_dev_ras_imp_supported(hdev)) 11399 hclge_handle_occurred_error(hdev); 11400 else 11401 hclge_handle_all_hns_hw_errors(ae_dev); 11402 11403 /* request delayed reset for the error recovery because an immediate 11404 * global reset on a PF affecting pending initialization of other PFs 11405 */ 11406 if (ae_dev->hw_err_reset_req) { 11407 enum hnae3_reset_type reset_level; 11408 11409 reset_level = hclge_get_reset_level(ae_dev, 11410 &ae_dev->hw_err_reset_req); 11411 hclge_set_def_reset_request(ae_dev, reset_level); 11412 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11413 } 11414 11415 hclge_init_rxd_adv_layout(hdev); 11416 11417 /* Enable MISC vector(vector0) */ 11418 hclge_enable_vector(&hdev->misc_vector, true); 11419 11420 hclge_state_init(hdev); 11421 hdev->last_reset_time = jiffies; 11422 11423 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11424 HCLGE_DRIVER_NAME); 11425 11426 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11427 11428 return 0; 11429 11430 err_mdiobus_unreg: 11431 if (hdev->hw.mac.phydev) 11432 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11433 err_msi_irq_uninit: 11434 hclge_misc_irq_uninit(hdev); 11435 err_msi_uninit: 11436 pci_free_irq_vectors(pdev); 11437 err_cmd_uninit: 11438 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11439 err_devlink_uninit: 11440 hclge_devlink_uninit(hdev); 11441 err_pci_uninit: 11442 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11443 pci_clear_master(pdev); 11444 pci_release_regions(pdev); 11445 pci_disable_device(pdev); 11446 out: 11447 mutex_destroy(&hdev->vport_lock); 11448 return ret; 11449 } 11450 11451 static void hclge_stats_clear(struct hclge_dev *hdev) 11452 { 11453 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11454 } 11455 11456 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11457 { 11458 return hclge_config_switch_param(hdev, vf, enable, 11459 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11460 } 11461 11462 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11463 { 11464 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11465 HCLGE_FILTER_FE_NIC_INGRESS_B, 11466 enable, vf); 11467 } 11468 11469 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11470 { 11471 int ret; 11472 11473 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11474 if (ret) { 11475 dev_err(&hdev->pdev->dev, 11476 "Set vf %d mac spoof check %s failed, ret=%d\n", 11477 vf, enable ? "on" : "off", ret); 11478 return ret; 11479 } 11480 11481 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11482 if (ret) 11483 dev_err(&hdev->pdev->dev, 11484 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11485 vf, enable ? "on" : "off", ret); 11486 11487 return ret; 11488 } 11489 11490 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11491 bool enable) 11492 { 11493 struct hclge_vport *vport = hclge_get_vport(handle); 11494 struct hclge_dev *hdev = vport->back; 11495 u32 new_spoofchk = enable ? 1 : 0; 11496 int ret; 11497 11498 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11499 return -EOPNOTSUPP; 11500 11501 vport = hclge_get_vf_vport(hdev, vf); 11502 if (!vport) 11503 return -EINVAL; 11504 11505 if (vport->vf_info.spoofchk == new_spoofchk) 11506 return 0; 11507 11508 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11509 dev_warn(&hdev->pdev->dev, 11510 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11511 vf); 11512 else if (enable && hclge_is_umv_space_full(vport, true)) 11513 dev_warn(&hdev->pdev->dev, 11514 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11515 vf); 11516 11517 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11518 if (ret) 11519 return ret; 11520 11521 vport->vf_info.spoofchk = new_spoofchk; 11522 return 0; 11523 } 11524 11525 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11526 { 11527 struct hclge_vport *vport = hdev->vport; 11528 int ret; 11529 int i; 11530 11531 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11532 return 0; 11533 11534 /* resume the vf spoof check state after reset */ 11535 for (i = 0; i < hdev->num_alloc_vport; i++) { 11536 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11537 vport->vf_info.spoofchk); 11538 if (ret) 11539 return ret; 11540 11541 vport++; 11542 } 11543 11544 return 0; 11545 } 11546 11547 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11548 { 11549 struct hclge_vport *vport = hclge_get_vport(handle); 11550 struct hclge_dev *hdev = vport->back; 11551 u32 new_trusted = enable ? 1 : 0; 11552 11553 vport = hclge_get_vf_vport(hdev, vf); 11554 if (!vport) 11555 return -EINVAL; 11556 11557 if (vport->vf_info.trusted == new_trusted) 11558 return 0; 11559 11560 vport->vf_info.trusted = new_trusted; 11561 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11562 hclge_task_schedule(hdev, 0); 11563 11564 return 0; 11565 } 11566 11567 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11568 { 11569 int ret; 11570 int vf; 11571 11572 /* reset vf rate to default value */ 11573 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11574 struct hclge_vport *vport = &hdev->vport[vf]; 11575 11576 vport->vf_info.max_tx_rate = 0; 11577 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11578 if (ret) 11579 dev_err(&hdev->pdev->dev, 11580 "vf%d failed to reset to default, ret=%d\n", 11581 vf - HCLGE_VF_VPORT_START_NUM, ret); 11582 } 11583 } 11584 11585 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11586 int min_tx_rate, int max_tx_rate) 11587 { 11588 if (min_tx_rate != 0 || 11589 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11590 dev_err(&hdev->pdev->dev, 11591 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11592 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11593 return -EINVAL; 11594 } 11595 11596 return 0; 11597 } 11598 11599 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11600 int min_tx_rate, int max_tx_rate, bool force) 11601 { 11602 struct hclge_vport *vport = hclge_get_vport(handle); 11603 struct hclge_dev *hdev = vport->back; 11604 int ret; 11605 11606 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 11607 if (ret) 11608 return ret; 11609 11610 vport = hclge_get_vf_vport(hdev, vf); 11611 if (!vport) 11612 return -EINVAL; 11613 11614 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 11615 return 0; 11616 11617 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 11618 if (ret) 11619 return ret; 11620 11621 vport->vf_info.max_tx_rate = max_tx_rate; 11622 11623 return 0; 11624 } 11625 11626 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 11627 { 11628 struct hnae3_handle *handle = &hdev->vport->nic; 11629 struct hclge_vport *vport; 11630 int ret; 11631 int vf; 11632 11633 /* resume the vf max_tx_rate after reset */ 11634 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 11635 vport = hclge_get_vf_vport(hdev, vf); 11636 if (!vport) 11637 return -EINVAL; 11638 11639 /* zero means max rate, after reset, firmware already set it to 11640 * max rate, so just continue. 11641 */ 11642 if (!vport->vf_info.max_tx_rate) 11643 continue; 11644 11645 ret = hclge_set_vf_rate(handle, vf, 0, 11646 vport->vf_info.max_tx_rate, true); 11647 if (ret) { 11648 dev_err(&hdev->pdev->dev, 11649 "vf%d failed to resume tx_rate:%u, ret=%d\n", 11650 vf, vport->vf_info.max_tx_rate, ret); 11651 return ret; 11652 } 11653 } 11654 11655 return 0; 11656 } 11657 11658 static void hclge_reset_vport_state(struct hclge_dev *hdev) 11659 { 11660 struct hclge_vport *vport = hdev->vport; 11661 int i; 11662 11663 for (i = 0; i < hdev->num_alloc_vport; i++) { 11664 hclge_vport_stop(vport); 11665 vport++; 11666 } 11667 } 11668 11669 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 11670 { 11671 struct hclge_dev *hdev = ae_dev->priv; 11672 struct pci_dev *pdev = ae_dev->pdev; 11673 int ret; 11674 11675 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11676 11677 hclge_stats_clear(hdev); 11678 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 11679 * so here should not clean table in memory. 11680 */ 11681 if (hdev->reset_type == HNAE3_IMP_RESET || 11682 hdev->reset_type == HNAE3_GLOBAL_RESET) { 11683 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 11684 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 11685 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 11686 hclge_reset_umv_space(hdev); 11687 } 11688 11689 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11690 true, hdev->reset_pending); 11691 if (ret) { 11692 dev_err(&pdev->dev, "Cmd queue init failed\n"); 11693 return ret; 11694 } 11695 11696 ret = hclge_map_tqp(hdev); 11697 if (ret) { 11698 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 11699 return ret; 11700 } 11701 11702 ret = hclge_mac_init(hdev); 11703 if (ret) { 11704 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11705 return ret; 11706 } 11707 11708 ret = hclge_tp_port_init(hdev); 11709 if (ret) { 11710 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 11711 ret); 11712 return ret; 11713 } 11714 11715 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11716 if (ret) { 11717 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11718 return ret; 11719 } 11720 11721 ret = hclge_config_gro(hdev); 11722 if (ret) 11723 return ret; 11724 11725 ret = hclge_init_vlan_config(hdev); 11726 if (ret) { 11727 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11728 return ret; 11729 } 11730 11731 ret = hclge_tm_init_hw(hdev, true); 11732 if (ret) { 11733 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 11734 return ret; 11735 } 11736 11737 ret = hclge_rss_init_hw(hdev); 11738 if (ret) { 11739 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11740 return ret; 11741 } 11742 11743 ret = init_mgr_tbl(hdev); 11744 if (ret) { 11745 dev_err(&pdev->dev, 11746 "failed to reinit manager table, ret = %d\n", ret); 11747 return ret; 11748 } 11749 11750 ret = hclge_init_fd_config(hdev); 11751 if (ret) { 11752 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 11753 return ret; 11754 } 11755 11756 ret = hclge_ptp_init(hdev); 11757 if (ret) 11758 return ret; 11759 11760 /* Log and clear the hw errors those already occurred */ 11761 if (hnae3_dev_ras_imp_supported(hdev)) 11762 hclge_handle_occurred_error(hdev); 11763 else 11764 hclge_handle_all_hns_hw_errors(ae_dev); 11765 11766 /* Re-enable the hw error interrupts because 11767 * the interrupts get disabled on global reset. 11768 */ 11769 ret = hclge_config_nic_hw_error(hdev, true); 11770 if (ret) { 11771 dev_err(&pdev->dev, 11772 "fail(%d) to re-enable NIC hw error interrupts\n", 11773 ret); 11774 return ret; 11775 } 11776 11777 if (hdev->roce_client) { 11778 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11779 if (ret) { 11780 dev_err(&pdev->dev, 11781 "fail(%d) to re-enable roce ras interrupts\n", 11782 ret); 11783 return ret; 11784 } 11785 } 11786 11787 hclge_reset_vport_state(hdev); 11788 ret = hclge_reset_vport_spoofchk(hdev); 11789 if (ret) 11790 return ret; 11791 11792 ret = hclge_resume_vf_rate(hdev); 11793 if (ret) 11794 return ret; 11795 11796 hclge_init_rxd_adv_layout(hdev); 11797 11798 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 11799 HCLGE_DRIVER_NAME); 11800 11801 return 0; 11802 } 11803 11804 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 11805 { 11806 struct hclge_dev *hdev = ae_dev->priv; 11807 struct hclge_mac *mac = &hdev->hw.mac; 11808 11809 hclge_reset_vf_rate(hdev); 11810 hclge_clear_vf_vlan(hdev); 11811 hclge_misc_affinity_teardown(hdev); 11812 hclge_state_uninit(hdev); 11813 hclge_ptp_uninit(hdev); 11814 hclge_uninit_rxd_adv_layout(hdev); 11815 hclge_uninit_mac_table(hdev); 11816 hclge_del_all_fd_entries(hdev); 11817 11818 if (mac->phydev) 11819 mdiobus_unregister(mac->mdio_bus); 11820 11821 /* Disable MISC vector(vector0) */ 11822 hclge_enable_vector(&hdev->misc_vector, false); 11823 synchronize_irq(hdev->misc_vector.vector_irq); 11824 11825 /* Disable all hw interrupts */ 11826 hclge_config_mac_tnl_int(hdev, false); 11827 hclge_config_nic_hw_error(hdev, false); 11828 hclge_config_rocee_ras_interrupt(hdev, false); 11829 11830 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11831 hclge_misc_irq_uninit(hdev); 11832 hclge_devlink_uninit(hdev); 11833 hclge_pci_uninit(hdev); 11834 mutex_destroy(&hdev->vport_lock); 11835 hclge_uninit_vport_vlan_table(hdev); 11836 ae_dev->priv = NULL; 11837 } 11838 11839 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 11840 { 11841 struct hclge_vport *vport = hclge_get_vport(handle); 11842 struct hclge_dev *hdev = vport->back; 11843 11844 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 11845 } 11846 11847 static void hclge_get_channels(struct hnae3_handle *handle, 11848 struct ethtool_channels *ch) 11849 { 11850 ch->max_combined = hclge_get_max_channels(handle); 11851 ch->other_count = 1; 11852 ch->max_other = 1; 11853 ch->combined_count = handle->kinfo.rss_size; 11854 } 11855 11856 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 11857 u16 *alloc_tqps, u16 *max_rss_size) 11858 { 11859 struct hclge_vport *vport = hclge_get_vport(handle); 11860 struct hclge_dev *hdev = vport->back; 11861 11862 *alloc_tqps = vport->alloc_tqps; 11863 *max_rss_size = hdev->pf_rss_size_max; 11864 } 11865 11866 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 11867 { 11868 struct hclge_vport *vport = hclge_get_vport(handle); 11869 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 11870 struct hclge_dev *hdev = vport->back; 11871 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 11872 u16 tc_valid[HCLGE_MAX_TC_NUM]; 11873 u16 roundup_size; 11874 unsigned int i; 11875 11876 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 11877 roundup_size = ilog2(roundup_size); 11878 /* Set the RSS TC mode according to the new RSS size */ 11879 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 11880 tc_valid[i] = 0; 11881 11882 if (!(hdev->hw_tc_map & BIT(i))) 11883 continue; 11884 11885 tc_valid[i] = 1; 11886 tc_size[i] = roundup_size; 11887 tc_offset[i] = vport->nic.kinfo.rss_size * i; 11888 } 11889 11890 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 11891 tc_size); 11892 } 11893 11894 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 11895 bool rxfh_configured) 11896 { 11897 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 11898 struct hclge_vport *vport = hclge_get_vport(handle); 11899 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 11900 struct hclge_dev *hdev = vport->back; 11901 u16 cur_rss_size = kinfo->rss_size; 11902 u16 cur_tqps = kinfo->num_tqps; 11903 u32 *rss_indir; 11904 unsigned int i; 11905 int ret; 11906 11907 kinfo->req_rss_size = new_tqps_num; 11908 11909 ret = hclge_tm_vport_map_update(hdev); 11910 if (ret) { 11911 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 11912 return ret; 11913 } 11914 11915 ret = hclge_set_rss_tc_mode_cfg(handle); 11916 if (ret) 11917 return ret; 11918 11919 /* RSS indirection table has been configured by user */ 11920 if (rxfh_configured) 11921 goto out; 11922 11923 /* Reinitializes the rss indirect table according to the new RSS size */ 11924 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 11925 GFP_KERNEL); 11926 if (!rss_indir) 11927 return -ENOMEM; 11928 11929 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 11930 rss_indir[i] = i % kinfo->rss_size; 11931 11932 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 11933 if (ret) 11934 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 11935 ret); 11936 11937 kfree(rss_indir); 11938 11939 out: 11940 if (!ret) 11941 dev_info(&hdev->pdev->dev, 11942 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 11943 cur_rss_size, kinfo->rss_size, 11944 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 11945 11946 return ret; 11947 } 11948 11949 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 11950 u32 *regs_num_64_bit) 11951 { 11952 struct hclge_desc desc; 11953 u32 total_num; 11954 int ret; 11955 11956 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 11957 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11958 if (ret) { 11959 dev_err(&hdev->pdev->dev, 11960 "Query register number cmd failed, ret = %d.\n", ret); 11961 return ret; 11962 } 11963 11964 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 11965 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 11966 11967 total_num = *regs_num_32_bit + *regs_num_64_bit; 11968 if (!total_num) 11969 return -EINVAL; 11970 11971 return 0; 11972 } 11973 11974 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 11975 void *data) 11976 { 11977 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 11978 #define HCLGE_32_BIT_DESC_NODATA_LEN 2 11979 11980 struct hclge_desc *desc; 11981 u32 *reg_val = data; 11982 __le32 *desc_data; 11983 int nodata_num; 11984 int cmd_num; 11985 int i, k, n; 11986 int ret; 11987 11988 if (regs_num == 0) 11989 return 0; 11990 11991 nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN; 11992 cmd_num = DIV_ROUND_UP(regs_num + nodata_num, 11993 HCLGE_32_BIT_REG_RTN_DATANUM); 11994 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 11995 if (!desc) 11996 return -ENOMEM; 11997 11998 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 11999 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12000 if (ret) { 12001 dev_err(&hdev->pdev->dev, 12002 "Query 32 bit register cmd failed, ret = %d.\n", ret); 12003 kfree(desc); 12004 return ret; 12005 } 12006 12007 for (i = 0; i < cmd_num; i++) { 12008 if (i == 0) { 12009 desc_data = (__le32 *)(&desc[i].data[0]); 12010 n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num; 12011 } else { 12012 desc_data = (__le32 *)(&desc[i]); 12013 n = HCLGE_32_BIT_REG_RTN_DATANUM; 12014 } 12015 for (k = 0; k < n; k++) { 12016 *reg_val++ = le32_to_cpu(*desc_data++); 12017 12018 regs_num--; 12019 if (!regs_num) 12020 break; 12021 } 12022 } 12023 12024 kfree(desc); 12025 return 0; 12026 } 12027 12028 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12029 void *data) 12030 { 12031 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 12032 #define HCLGE_64_BIT_DESC_NODATA_LEN 1 12033 12034 struct hclge_desc *desc; 12035 u64 *reg_val = data; 12036 __le64 *desc_data; 12037 int nodata_len; 12038 int cmd_num; 12039 int i, k, n; 12040 int ret; 12041 12042 if (regs_num == 0) 12043 return 0; 12044 12045 nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN; 12046 cmd_num = DIV_ROUND_UP(regs_num + nodata_len, 12047 HCLGE_64_BIT_REG_RTN_DATANUM); 12048 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12049 if (!desc) 12050 return -ENOMEM; 12051 12052 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 12053 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12054 if (ret) { 12055 dev_err(&hdev->pdev->dev, 12056 "Query 64 bit register cmd failed, ret = %d.\n", ret); 12057 kfree(desc); 12058 return ret; 12059 } 12060 12061 for (i = 0; i < cmd_num; i++) { 12062 if (i == 0) { 12063 desc_data = (__le64 *)(&desc[i].data[0]); 12064 n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len; 12065 } else { 12066 desc_data = (__le64 *)(&desc[i]); 12067 n = HCLGE_64_BIT_REG_RTN_DATANUM; 12068 } 12069 for (k = 0; k < n; k++) { 12070 *reg_val++ = le64_to_cpu(*desc_data++); 12071 12072 regs_num--; 12073 if (!regs_num) 12074 break; 12075 } 12076 } 12077 12078 kfree(desc); 12079 return 0; 12080 } 12081 12082 #define MAX_SEPARATE_NUM 4 12083 #define SEPARATOR_VALUE 0xFDFCFBFA 12084 #define REG_NUM_PER_LINE 4 12085 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 12086 #define REG_SEPARATOR_LINE 1 12087 #define REG_NUM_REMAIN_MASK 3 12088 12089 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc) 12090 { 12091 int i; 12092 12093 /* initialize command BD except the last one */ 12094 for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) { 12095 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, 12096 true); 12097 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12098 } 12099 12100 /* initialize the last command BD */ 12101 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true); 12102 12103 return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT); 12104 } 12105 12106 static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev, 12107 int *bd_num_list, 12108 u32 type_num) 12109 { 12110 u32 entries_per_desc, desc_index, index, offset, i; 12111 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT]; 12112 int ret; 12113 12114 ret = hclge_query_bd_num_cmd_send(hdev, desc); 12115 if (ret) { 12116 dev_err(&hdev->pdev->dev, 12117 "Get dfx bd num fail, status is %d.\n", ret); 12118 return ret; 12119 } 12120 12121 entries_per_desc = ARRAY_SIZE(desc[0].data); 12122 for (i = 0; i < type_num; i++) { 12123 offset = hclge_dfx_bd_offset_list[i]; 12124 index = offset % entries_per_desc; 12125 desc_index = offset / entries_per_desc; 12126 bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]); 12127 } 12128 12129 return ret; 12130 } 12131 12132 static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev, 12133 struct hclge_desc *desc_src, int bd_num, 12134 enum hclge_opcode_type cmd) 12135 { 12136 struct hclge_desc *desc = desc_src; 12137 int i, ret; 12138 12139 hclge_cmd_setup_basic_desc(desc, cmd, true); 12140 for (i = 0; i < bd_num - 1; i++) { 12141 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12142 desc++; 12143 hclge_cmd_setup_basic_desc(desc, cmd, true); 12144 } 12145 12146 desc = desc_src; 12147 ret = hclge_cmd_send(&hdev->hw, desc, bd_num); 12148 if (ret) 12149 dev_err(&hdev->pdev->dev, 12150 "Query dfx reg cmd(0x%x) send fail, status is %d.\n", 12151 cmd, ret); 12152 12153 return ret; 12154 } 12155 12156 static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num, 12157 void *data) 12158 { 12159 int entries_per_desc, reg_num, separator_num, desc_index, index, i; 12160 struct hclge_desc *desc = desc_src; 12161 u32 *reg = data; 12162 12163 entries_per_desc = ARRAY_SIZE(desc->data); 12164 reg_num = entries_per_desc * bd_num; 12165 separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK); 12166 for (i = 0; i < reg_num; i++) { 12167 index = i % entries_per_desc; 12168 desc_index = i / entries_per_desc; 12169 *reg++ = le32_to_cpu(desc[desc_index].data[index]); 12170 } 12171 for (i = 0; i < separator_num; i++) 12172 *reg++ = SEPARATOR_VALUE; 12173 12174 return reg_num + separator_num; 12175 } 12176 12177 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len) 12178 { 12179 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12180 int data_len_per_desc, bd_num, i; 12181 int *bd_num_list; 12182 u32 data_len; 12183 int ret; 12184 12185 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12186 if (!bd_num_list) 12187 return -ENOMEM; 12188 12189 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12190 if (ret) { 12191 dev_err(&hdev->pdev->dev, 12192 "Get dfx reg bd num fail, status is %d.\n", ret); 12193 goto out; 12194 } 12195 12196 data_len_per_desc = sizeof_field(struct hclge_desc, data); 12197 *len = 0; 12198 for (i = 0; i < dfx_reg_type_num; i++) { 12199 bd_num = bd_num_list[i]; 12200 data_len = data_len_per_desc * bd_num; 12201 *len += (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE; 12202 } 12203 12204 out: 12205 kfree(bd_num_list); 12206 return ret; 12207 } 12208 12209 static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data) 12210 { 12211 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12212 int bd_num, bd_num_max, buf_len, i; 12213 struct hclge_desc *desc_src; 12214 int *bd_num_list; 12215 u32 *reg = data; 12216 int ret; 12217 12218 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12219 if (!bd_num_list) 12220 return -ENOMEM; 12221 12222 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12223 if (ret) { 12224 dev_err(&hdev->pdev->dev, 12225 "Get dfx reg bd num fail, status is %d.\n", ret); 12226 goto out; 12227 } 12228 12229 bd_num_max = bd_num_list[0]; 12230 for (i = 1; i < dfx_reg_type_num; i++) 12231 bd_num_max = max_t(int, bd_num_max, bd_num_list[i]); 12232 12233 buf_len = sizeof(*desc_src) * bd_num_max; 12234 desc_src = kzalloc(buf_len, GFP_KERNEL); 12235 if (!desc_src) { 12236 ret = -ENOMEM; 12237 goto out; 12238 } 12239 12240 for (i = 0; i < dfx_reg_type_num; i++) { 12241 bd_num = bd_num_list[i]; 12242 ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num, 12243 hclge_dfx_reg_opcode_list[i]); 12244 if (ret) { 12245 dev_err(&hdev->pdev->dev, 12246 "Get dfx reg fail, status is %d.\n", ret); 12247 break; 12248 } 12249 12250 reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg); 12251 } 12252 12253 kfree(desc_src); 12254 out: 12255 kfree(bd_num_list); 12256 return ret; 12257 } 12258 12259 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, 12260 struct hnae3_knic_private_info *kinfo) 12261 { 12262 #define HCLGE_RING_REG_OFFSET 0x200 12263 #define HCLGE_RING_INT_REG_OFFSET 0x4 12264 12265 int i, j, reg_num, separator_num; 12266 int data_num_sum; 12267 u32 *reg = data; 12268 12269 /* fetching per-PF registers valus from PF PCIe register space */ 12270 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); 12271 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12272 for (i = 0; i < reg_num; i++) 12273 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 12274 for (i = 0; i < separator_num; i++) 12275 *reg++ = SEPARATOR_VALUE; 12276 data_num_sum = reg_num + separator_num; 12277 12278 reg_num = ARRAY_SIZE(common_reg_addr_list); 12279 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12280 for (i = 0; i < reg_num; i++) 12281 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]); 12282 for (i = 0; i < separator_num; i++) 12283 *reg++ = SEPARATOR_VALUE; 12284 data_num_sum += reg_num + separator_num; 12285 12286 reg_num = ARRAY_SIZE(ring_reg_addr_list); 12287 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12288 for (j = 0; j < kinfo->num_tqps; j++) { 12289 for (i = 0; i < reg_num; i++) 12290 *reg++ = hclge_read_dev(&hdev->hw, 12291 ring_reg_addr_list[i] + 12292 HCLGE_RING_REG_OFFSET * j); 12293 for (i = 0; i < separator_num; i++) 12294 *reg++ = SEPARATOR_VALUE; 12295 } 12296 data_num_sum += (reg_num + separator_num) * kinfo->num_tqps; 12297 12298 reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); 12299 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12300 for (j = 0; j < hdev->num_msi_used - 1; j++) { 12301 for (i = 0; i < reg_num; i++) 12302 *reg++ = hclge_read_dev(&hdev->hw, 12303 tqp_intr_reg_addr_list[i] + 12304 HCLGE_RING_INT_REG_OFFSET * j); 12305 for (i = 0; i < separator_num; i++) 12306 *reg++ = SEPARATOR_VALUE; 12307 } 12308 data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1); 12309 12310 return data_num_sum; 12311 } 12312 12313 static int hclge_get_regs_len(struct hnae3_handle *handle) 12314 { 12315 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 12316 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12317 struct hclge_vport *vport = hclge_get_vport(handle); 12318 struct hclge_dev *hdev = vport->back; 12319 int regs_num_32_bit, regs_num_64_bit, dfx_regs_len; 12320 int regs_lines_32_bit, regs_lines_64_bit; 12321 int ret; 12322 12323 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12324 if (ret) { 12325 dev_err(&hdev->pdev->dev, 12326 "Get register number failed, ret = %d.\n", ret); 12327 return ret; 12328 } 12329 12330 ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len); 12331 if (ret) { 12332 dev_err(&hdev->pdev->dev, 12333 "Get dfx reg len failed, ret = %d.\n", ret); 12334 return ret; 12335 } 12336 12337 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 12338 REG_SEPARATOR_LINE; 12339 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 12340 REG_SEPARATOR_LINE; 12341 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 12342 REG_SEPARATOR_LINE; 12343 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 12344 REG_SEPARATOR_LINE; 12345 regs_lines_32_bit = regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE + 12346 REG_SEPARATOR_LINE; 12347 regs_lines_64_bit = regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE + 12348 REG_SEPARATOR_LINE; 12349 12350 return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps + 12351 tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit + 12352 regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len; 12353 } 12354 12355 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 12356 void *data) 12357 { 12358 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12359 struct hclge_vport *vport = hclge_get_vport(handle); 12360 struct hclge_dev *hdev = vport->back; 12361 u32 regs_num_32_bit, regs_num_64_bit; 12362 int i, reg_num, separator_num, ret; 12363 u32 *reg = data; 12364 12365 *version = hdev->fw_version; 12366 12367 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12368 if (ret) { 12369 dev_err(&hdev->pdev->dev, 12370 "Get register number failed, ret = %d.\n", ret); 12371 return; 12372 } 12373 12374 reg += hclge_fetch_pf_reg(hdev, reg, kinfo); 12375 12376 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg); 12377 if (ret) { 12378 dev_err(&hdev->pdev->dev, 12379 "Get 32 bit register failed, ret = %d.\n", ret); 12380 return; 12381 } 12382 reg_num = regs_num_32_bit; 12383 reg += reg_num; 12384 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12385 for (i = 0; i < separator_num; i++) 12386 *reg++ = SEPARATOR_VALUE; 12387 12388 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg); 12389 if (ret) { 12390 dev_err(&hdev->pdev->dev, 12391 "Get 64 bit register failed, ret = %d.\n", ret); 12392 return; 12393 } 12394 reg_num = regs_num_64_bit * 2; 12395 reg += reg_num; 12396 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12397 for (i = 0; i < separator_num; i++) 12398 *reg++ = SEPARATOR_VALUE; 12399 12400 ret = hclge_get_dfx_reg(hdev, reg); 12401 if (ret) 12402 dev_err(&hdev->pdev->dev, 12403 "Get dfx register failed, ret = %d.\n", ret); 12404 } 12405 12406 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12407 { 12408 struct hclge_set_led_state_cmd *req; 12409 struct hclge_desc desc; 12410 int ret; 12411 12412 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12413 12414 req = (struct hclge_set_led_state_cmd *)desc.data; 12415 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12416 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12417 12418 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12419 if (ret) 12420 dev_err(&hdev->pdev->dev, 12421 "Send set led state cmd error, ret =%d\n", ret); 12422 12423 return ret; 12424 } 12425 12426 enum hclge_led_status { 12427 HCLGE_LED_OFF, 12428 HCLGE_LED_ON, 12429 HCLGE_LED_NO_CHANGE = 0xFF, 12430 }; 12431 12432 static int hclge_set_led_id(struct hnae3_handle *handle, 12433 enum ethtool_phys_id_state status) 12434 { 12435 struct hclge_vport *vport = hclge_get_vport(handle); 12436 struct hclge_dev *hdev = vport->back; 12437 12438 switch (status) { 12439 case ETHTOOL_ID_ACTIVE: 12440 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12441 case ETHTOOL_ID_INACTIVE: 12442 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12443 default: 12444 return -EINVAL; 12445 } 12446 } 12447 12448 static void hclge_get_link_mode(struct hnae3_handle *handle, 12449 unsigned long *supported, 12450 unsigned long *advertising) 12451 { 12452 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12453 struct hclge_vport *vport = hclge_get_vport(handle); 12454 struct hclge_dev *hdev = vport->back; 12455 unsigned int idx = 0; 12456 12457 for (; idx < size; idx++) { 12458 supported[idx] = hdev->hw.mac.supported[idx]; 12459 advertising[idx] = hdev->hw.mac.advertising[idx]; 12460 } 12461 } 12462 12463 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12464 { 12465 struct hclge_vport *vport = hclge_get_vport(handle); 12466 struct hclge_dev *hdev = vport->back; 12467 bool gro_en_old = hdev->gro_en; 12468 int ret; 12469 12470 hdev->gro_en = enable; 12471 ret = hclge_config_gro(hdev); 12472 if (ret) 12473 hdev->gro_en = gro_en_old; 12474 12475 return ret; 12476 } 12477 12478 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12479 { 12480 struct hclge_vport *vport = &hdev->vport[0]; 12481 struct hnae3_handle *handle = &vport->nic; 12482 u8 tmp_flags; 12483 int ret; 12484 u16 i; 12485 12486 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12487 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12488 vport->last_promisc_flags = vport->overflow_promisc_flags; 12489 } 12490 12491 if (test_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state)) { 12492 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12493 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12494 tmp_flags & HNAE3_MPE); 12495 if (!ret) { 12496 clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12497 &vport->state); 12498 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12499 &vport->state); 12500 } 12501 } 12502 12503 for (i = 1; i < hdev->num_alloc_vport; i++) { 12504 bool uc_en = false; 12505 bool mc_en = false; 12506 bool bc_en; 12507 12508 vport = &hdev->vport[i]; 12509 12510 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12511 &vport->state)) 12512 continue; 12513 12514 if (vport->vf_info.trusted) { 12515 uc_en = vport->vf_info.request_uc_en > 0 || 12516 vport->overflow_promisc_flags & 12517 HNAE3_OVERFLOW_UPE; 12518 mc_en = vport->vf_info.request_mc_en > 0 || 12519 vport->overflow_promisc_flags & 12520 HNAE3_OVERFLOW_MPE; 12521 } 12522 bc_en = vport->vf_info.request_bc_en > 0; 12523 12524 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12525 mc_en, bc_en); 12526 if (ret) { 12527 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12528 &vport->state); 12529 return; 12530 } 12531 hclge_set_vport_vlan_fltr_change(vport); 12532 } 12533 } 12534 12535 static bool hclge_module_existed(struct hclge_dev *hdev) 12536 { 12537 struct hclge_desc desc; 12538 u32 existed; 12539 int ret; 12540 12541 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12542 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12543 if (ret) { 12544 dev_err(&hdev->pdev->dev, 12545 "failed to get SFP exist state, ret = %d\n", ret); 12546 return false; 12547 } 12548 12549 existed = le32_to_cpu(desc.data[0]); 12550 12551 return existed != 0; 12552 } 12553 12554 /* need 6 bds(total 140 bytes) in one reading 12555 * return the number of bytes actually read, 0 means read failed. 12556 */ 12557 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12558 u32 len, u8 *data) 12559 { 12560 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12561 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12562 u16 read_len; 12563 u16 copy_len; 12564 int ret; 12565 int i; 12566 12567 /* setup all 6 bds to read module eeprom info. */ 12568 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12569 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12570 true); 12571 12572 /* bd0~bd4 need next flag */ 12573 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12574 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12575 } 12576 12577 /* setup bd0, this bd contains offset and read length. */ 12578 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12579 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12580 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12581 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12582 12583 ret = hclge_cmd_send(&hdev->hw, desc, i); 12584 if (ret) { 12585 dev_err(&hdev->pdev->dev, 12586 "failed to get SFP eeprom info, ret = %d\n", ret); 12587 return 0; 12588 } 12589 12590 /* copy sfp info from bd0 to out buffer. */ 12591 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12592 memcpy(data, sfp_info_bd0->data, copy_len); 12593 read_len = copy_len; 12594 12595 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12596 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12597 if (read_len >= len) 12598 return read_len; 12599 12600 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12601 memcpy(data + read_len, desc[i].data, copy_len); 12602 read_len += copy_len; 12603 } 12604 12605 return read_len; 12606 } 12607 12608 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12609 u32 len, u8 *data) 12610 { 12611 struct hclge_vport *vport = hclge_get_vport(handle); 12612 struct hclge_dev *hdev = vport->back; 12613 u32 read_len = 0; 12614 u16 data_len; 12615 12616 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12617 return -EOPNOTSUPP; 12618 12619 if (!hclge_module_existed(hdev)) 12620 return -ENXIO; 12621 12622 while (read_len < len) { 12623 data_len = hclge_get_sfp_eeprom_info(hdev, 12624 offset + read_len, 12625 len - read_len, 12626 data + read_len); 12627 if (!data_len) 12628 return -EIO; 12629 12630 read_len += data_len; 12631 } 12632 12633 return 0; 12634 } 12635 12636 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12637 u32 *status_code) 12638 { 12639 struct hclge_vport *vport = hclge_get_vport(handle); 12640 struct hclge_dev *hdev = vport->back; 12641 struct hclge_desc desc; 12642 int ret; 12643 12644 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12645 return -EOPNOTSUPP; 12646 12647 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12648 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12649 if (ret) { 12650 dev_err(&hdev->pdev->dev, 12651 "failed to query link diagnosis info, ret = %d\n", ret); 12652 return ret; 12653 } 12654 12655 *status_code = le32_to_cpu(desc.data[0]); 12656 return 0; 12657 } 12658 12659 static const struct hnae3_ae_ops hclge_ops = { 12660 .init_ae_dev = hclge_init_ae_dev, 12661 .uninit_ae_dev = hclge_uninit_ae_dev, 12662 .reset_prepare = hclge_reset_prepare_general, 12663 .reset_done = hclge_reset_done, 12664 .init_client_instance = hclge_init_client_instance, 12665 .uninit_client_instance = hclge_uninit_client_instance, 12666 .map_ring_to_vector = hclge_map_ring_to_vector, 12667 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12668 .get_vector = hclge_get_vector, 12669 .put_vector = hclge_put_vector, 12670 .set_promisc_mode = hclge_set_promisc_mode, 12671 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12672 .set_loopback = hclge_set_loopback, 12673 .start = hclge_ae_start, 12674 .stop = hclge_ae_stop, 12675 .client_start = hclge_client_start, 12676 .client_stop = hclge_client_stop, 12677 .get_status = hclge_get_status, 12678 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12679 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12680 .get_media_type = hclge_get_media_type, 12681 .check_port_speed = hclge_check_port_speed, 12682 .get_fec = hclge_get_fec, 12683 .set_fec = hclge_set_fec, 12684 .get_rss_key_size = hclge_comm_get_rss_key_size, 12685 .get_rss = hclge_get_rss, 12686 .set_rss = hclge_set_rss, 12687 .set_rss_tuple = hclge_set_rss_tuple, 12688 .get_rss_tuple = hclge_get_rss_tuple, 12689 .get_tc_size = hclge_get_tc_size, 12690 .get_mac_addr = hclge_get_mac_addr, 12691 .set_mac_addr = hclge_set_mac_addr, 12692 .do_ioctl = hclge_do_ioctl, 12693 .add_uc_addr = hclge_add_uc_addr, 12694 .rm_uc_addr = hclge_rm_uc_addr, 12695 .add_mc_addr = hclge_add_mc_addr, 12696 .rm_mc_addr = hclge_rm_mc_addr, 12697 .set_autoneg = hclge_set_autoneg, 12698 .get_autoneg = hclge_get_autoneg, 12699 .restart_autoneg = hclge_restart_autoneg, 12700 .halt_autoneg = hclge_halt_autoneg, 12701 .get_pauseparam = hclge_get_pauseparam, 12702 .set_pauseparam = hclge_set_pauseparam, 12703 .set_mtu = hclge_set_mtu, 12704 .reset_queue = hclge_reset_tqp, 12705 .get_stats = hclge_get_stats, 12706 .get_mac_stats = hclge_get_mac_stat, 12707 .update_stats = hclge_update_stats, 12708 .get_strings = hclge_get_strings, 12709 .get_sset_count = hclge_get_sset_count, 12710 .get_fw_version = hclge_get_fw_version, 12711 .get_mdix_mode = hclge_get_mdix_mode, 12712 .enable_vlan_filter = hclge_enable_vlan_filter, 12713 .set_vlan_filter = hclge_set_vlan_filter, 12714 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12715 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12716 .reset_event = hclge_reset_event, 12717 .get_reset_level = hclge_get_reset_level, 12718 .set_default_reset_request = hclge_set_def_reset_request, 12719 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12720 .set_channels = hclge_set_channels, 12721 .get_channels = hclge_get_channels, 12722 .get_regs_len = hclge_get_regs_len, 12723 .get_regs = hclge_get_regs, 12724 .set_led_id = hclge_set_led_id, 12725 .get_link_mode = hclge_get_link_mode, 12726 .add_fd_entry = hclge_add_fd_entry, 12727 .del_fd_entry = hclge_del_fd_entry, 12728 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12729 .get_fd_rule_info = hclge_get_fd_rule_info, 12730 .get_fd_all_rules = hclge_get_all_rules, 12731 .enable_fd = hclge_enable_fd, 12732 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12733 .dbg_read_cmd = hclge_dbg_read_cmd, 12734 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12735 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12736 .ae_dev_resetting = hclge_ae_dev_resetting, 12737 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12738 .set_gro_en = hclge_gro_en, 12739 .get_global_queue_id = hclge_covert_handle_qid_global, 12740 .set_timer_task = hclge_set_timer_task, 12741 .mac_connect_phy = hclge_mac_connect_phy, 12742 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12743 .get_vf_config = hclge_get_vf_config, 12744 .set_vf_link_state = hclge_set_vf_link_state, 12745 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12746 .set_vf_trust = hclge_set_vf_trust, 12747 .set_vf_rate = hclge_set_vf_rate, 12748 .set_vf_mac = hclge_set_vf_mac, 12749 .get_module_eeprom = hclge_get_module_eeprom, 12750 .get_cmdq_stat = hclge_get_cmdq_stat, 12751 .add_cls_flower = hclge_add_cls_flower, 12752 .del_cls_flower = hclge_del_cls_flower, 12753 .cls_flower_active = hclge_is_cls_flower_active, 12754 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12755 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12756 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12757 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12758 .get_ts_info = hclge_ptp_get_ts_info, 12759 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12760 }; 12761 12762 static struct hnae3_ae_algo ae_algo = { 12763 .ops = &hclge_ops, 12764 .pdev_id_table = ae_algo_pci_tbl, 12765 }; 12766 12767 static int hclge_init(void) 12768 { 12769 pr_info("%s is initializing\n", HCLGE_NAME); 12770 12771 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 12772 if (!hclge_wq) { 12773 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12774 return -ENOMEM; 12775 } 12776 12777 hnae3_register_ae_algo(&ae_algo); 12778 12779 return 0; 12780 } 12781 12782 static void hclge_exit(void) 12783 { 12784 hnae3_unregister_ae_algo_prepare(&ae_algo); 12785 hnae3_unregister_ae_algo(&ae_algo); 12786 destroy_workqueue(hclge_wq); 12787 } 12788 module_init(hclge_init); 12789 module_exit(hclge_exit); 12790 12791 MODULE_LICENSE("GPL"); 12792 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12793 MODULE_DESCRIPTION("HCLGE Driver"); 12794 MODULE_VERSION(HCLGE_MOD_VERSION); 12795