1 /* 2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device 3 * 4 * Copyright (C) 1995 Jay Estabrook 5 * Copyright (C) 1997 Geert Uytterhoeven 6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha 7 * Copyright (C) 2002 Richard Henderson 8 * Copyright (C) 2006, 2007 Maciej W. Rozycki 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive for 12 * more details. 13 */ 14 15 #include <linux/aperture.h> 16 #include <linux/bitrev.h> 17 #include <linux/compiler.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/errno.h> 21 #include <linux/fb.h> 22 #include <linux/init.h> 23 #include <linux/ioport.h> 24 #include <linux/kernel.h> 25 #include <linux/mm.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include <linux/selection.h> 29 #include <linux/string.h> 30 #include <linux/tc.h> 31 32 #include <asm/io.h> 33 34 #include <video/tgafb.h> 35 36 #ifdef CONFIG_TC 37 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type) 38 #else 39 #define TGA_BUS_TC(dev) 0 40 #endif 41 42 /* 43 * Local functions. 44 */ 45 46 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *); 47 static int tgafb_set_par(struct fb_info *); 48 static void tgafb_set_pll(struct tga_par *, int); 49 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned, 50 unsigned, struct fb_info *); 51 static int tgafb_blank(int, struct fb_info *); 52 static void tgafb_init_fix(struct fb_info *); 53 54 static void tgafb_imageblit(struct fb_info *, const struct fb_image *); 55 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *); 56 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *); 57 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); 58 59 static int tgafb_register(struct device *dev); 60 static void tgafb_unregister(struct device *dev); 61 62 static const char *mode_option; 63 static const char *mode_option_pci = "640x480@60"; 64 static const char *mode_option_tc = "1280x1024@72"; 65 66 67 static struct pci_driver tgafb_pci_driver; 68 static struct tc_driver tgafb_tc_driver; 69 70 /* 71 * Frame buffer operations 72 */ 73 74 static const struct fb_ops tgafb_ops = { 75 .owner = THIS_MODULE, 76 .fb_check_var = tgafb_check_var, 77 .fb_set_par = tgafb_set_par, 78 .fb_setcolreg = tgafb_setcolreg, 79 .fb_blank = tgafb_blank, 80 .fb_pan_display = tgafb_pan_display, 81 .fb_fillrect = tgafb_fillrect, 82 .fb_copyarea = tgafb_copyarea, 83 .fb_imageblit = tgafb_imageblit, 84 }; 85 86 87 #ifdef CONFIG_PCI 88 /* 89 * PCI registration operations 90 */ 91 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *); 92 static void tgafb_pci_unregister(struct pci_dev *); 93 94 static struct pci_device_id const tgafb_pci_table[] = { 95 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) }, 96 { } 97 }; 98 MODULE_DEVICE_TABLE(pci, tgafb_pci_table); 99 100 static struct pci_driver tgafb_pci_driver = { 101 .name = "tgafb", 102 .id_table = tgafb_pci_table, 103 .probe = tgafb_pci_register, 104 .remove = tgafb_pci_unregister, 105 }; 106 107 static int tgafb_pci_register(struct pci_dev *pdev, 108 const struct pci_device_id *ent) 109 { 110 int ret; 111 112 ret = aperture_remove_conflicting_pci_devices(pdev, "tgafb"); 113 if (ret) 114 return ret; 115 116 return tgafb_register(&pdev->dev); 117 } 118 119 static void tgafb_pci_unregister(struct pci_dev *pdev) 120 { 121 tgafb_unregister(&pdev->dev); 122 } 123 #endif /* CONFIG_PCI */ 124 125 #ifdef CONFIG_TC 126 /* 127 * TC registration operations 128 */ 129 static int tgafb_tc_register(struct device *); 130 static int tgafb_tc_unregister(struct device *); 131 132 static struct tc_device_id const tgafb_tc_table[] = { 133 { "DEC ", "PMAGD-AA" }, 134 { "DEC ", "PMAGD " }, 135 { } 136 }; 137 MODULE_DEVICE_TABLE(tc, tgafb_tc_table); 138 139 static struct tc_driver tgafb_tc_driver = { 140 .id_table = tgafb_tc_table, 141 .driver = { 142 .name = "tgafb", 143 .bus = &tc_bus_type, 144 .probe = tgafb_tc_register, 145 .remove = tgafb_tc_unregister, 146 }, 147 }; 148 149 static int tgafb_tc_register(struct device *dev) 150 { 151 int status = tgafb_register(dev); 152 if (!status) 153 get_device(dev); 154 return status; 155 } 156 157 static int tgafb_tc_unregister(struct device *dev) 158 { 159 put_device(dev); 160 tgafb_unregister(dev); 161 return 0; 162 } 163 #endif /* CONFIG_TC */ 164 165 166 /** 167 * tgafb_check_var - Optional function. Validates a var passed in. 168 * @var: frame buffer variable screen structure 169 * @info: frame buffer structure that represents a single frame buffer 170 */ 171 static int 172 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 173 { 174 struct tga_par *par = (struct tga_par *)info->par; 175 176 if (par->tga_type == TGA_TYPE_8PLANE) { 177 if (var->bits_per_pixel != 8) 178 return -EINVAL; 179 } else { 180 if (var->bits_per_pixel != 32) 181 return -EINVAL; 182 } 183 var->red.length = var->green.length = var->blue.length = 8; 184 if (var->bits_per_pixel == 32) { 185 var->red.offset = 16; 186 var->green.offset = 8; 187 var->blue.offset = 0; 188 } 189 190 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres) 191 return -EINVAL; 192 if (var->xres * var->yres * (var->bits_per_pixel >> 3) > info->fix.smem_len) 193 return -EINVAL; 194 if (var->nonstd) 195 return -EINVAL; 196 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ) 197 return -EINVAL; 198 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 199 return -EINVAL; 200 201 /* Some of the acceleration routines assume the line width is 202 a multiple of 8 bytes. */ 203 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 8) 204 return -EINVAL; 205 206 return 0; 207 } 208 209 /** 210 * tgafb_set_par - Optional function. Alters the hardware state. 211 * @info: frame buffer structure that represents a single frame buffer 212 */ 213 static int 214 tgafb_set_par(struct fb_info *info) 215 { 216 static unsigned int const deep_presets[4] = { 217 0x00004000, 218 0x0000440d, 219 0xffffffff, 220 0x0000441d 221 }; 222 static unsigned int const rasterop_presets[4] = { 223 0x00000003, 224 0x00000303, 225 0xffffffff, 226 0x00000303 227 }; 228 static unsigned int const mode_presets[4] = { 229 0x00000000, 230 0x00000300, 231 0xffffffff, 232 0x00000300 233 }; 234 static unsigned int const base_addr_presets[4] = { 235 0x00000000, 236 0x00000001, 237 0xffffffff, 238 0x00000001 239 }; 240 241 struct tga_par *par = (struct tga_par *) info->par; 242 int tga_bus_pci = dev_is_pci(par->dev); 243 int tga_bus_tc = TGA_BUS_TC(par->dev); 244 u32 htimings, vtimings, pll_freq; 245 u8 tga_type; 246 int i; 247 248 /* Encode video timings. */ 249 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB) 250 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB)); 251 vtimings = (info->var.yres & TGA_VERT_ACTIVE); 252 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP; 253 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP; 254 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC; 255 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC; 256 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP; 257 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP; 258 259 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 260 htimings |= TGA_HORIZ_POLARITY; 261 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 262 vtimings |= TGA_VERT_POLARITY; 263 264 par->htimings = htimings; 265 par->vtimings = vtimings; 266 267 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN); 268 269 /* Store other useful values in par. */ 270 par->xres = info->var.xres; 271 par->yres = info->var.yres; 272 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock; 273 par->bits_per_pixel = info->var.bits_per_pixel; 274 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3); 275 276 tga_type = par->tga_type; 277 278 /* First, disable video. */ 279 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG); 280 281 /* Write the DEEP register. */ 282 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */ 283 continue; 284 mb(); 285 TGA_WRITE_REG(par, deep_presets[tga_type] | 286 (par->sync_on_green ? 0x0 : 0x00010000), 287 TGA_DEEP_REG); 288 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */ 289 continue; 290 mb(); 291 292 /* Write some more registers. */ 293 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG); 294 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG); 295 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG); 296 297 /* Calculate & write the PLL. */ 298 tgafb_set_pll(par, pll_freq); 299 300 /* Write some more registers. */ 301 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG); 302 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG); 303 304 /* Init video timing regs. */ 305 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG); 306 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG); 307 308 /* Initialise RAMDAC. */ 309 if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) { 310 311 /* Init BT485 RAMDAC registers. */ 312 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0), 313 BT485_CMD_0); 314 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE); 315 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */ 316 BT485_WRITE(par, 0x40, BT485_CMD_1); 317 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */ 318 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK); 319 320 /* Fill palette registers. */ 321 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE); 322 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); 323 324 for (i = 0; i < 256 * 3; i += 4) { 325 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8), 326 TGA_RAMDAC_REG); 327 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8), 328 TGA_RAMDAC_REG); 329 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8), 330 TGA_RAMDAC_REG); 331 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8), 332 TGA_RAMDAC_REG); 333 } 334 335 } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) { 336 337 /* Init BT459 RAMDAC registers. */ 338 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40); 339 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00); 340 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2, 341 (par->sync_on_green ? 0xc0 : 0x40)); 342 343 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00); 344 345 /* Fill the palette. */ 346 BT459_LOAD_ADDR(par, 0x0000); 347 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG); 348 349 for (i = 0; i < 256 * 3; i += 4) { 350 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG); 351 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 352 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 353 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 354 } 355 356 } else { /* 24-plane or 24plusZ */ 357 358 /* Init BT463 RAMDAC registers. */ 359 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40); 360 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08); 361 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2, 362 (par->sync_on_green ? 0xc0 : 0x40)); 363 364 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff); 365 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff); 366 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff); 367 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f); 368 369 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00); 370 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00); 371 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00); 372 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00); 373 374 /* Fill the palette. */ 375 BT463_LOAD_ADDR(par, 0x0000); 376 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG); 377 378 #ifdef CONFIG_HW_CONSOLE 379 for (i = 0; i < 16; i++) { 380 int j = color_table[i]; 381 382 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG); 383 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG); 384 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG); 385 } 386 for (i = 0; i < 512 * 3; i += 4) { 387 #else 388 for (i = 0; i < 528 * 3; i += 4) { 389 #endif 390 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG); 391 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 392 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 393 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 394 } 395 396 /* Fill window type table after start of vertical retrace. */ 397 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01)) 398 continue; 399 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG); 400 mb(); 401 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01)) 402 continue; 403 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG); 404 405 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE); 406 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG); 407 408 for (i = 0; i < 16; i++) { 409 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 410 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG); 411 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG); 412 } 413 414 } 415 416 /* Finally, enable video scan (and pray for the monitor... :-) */ 417 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG); 418 419 return 0; 420 } 421 422 #define DIFFCHECK(X) \ 423 do { \ 424 if (m <= 0x3f) { \ 425 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \ 426 if (delta < 0) \ 427 delta = -delta; \ 428 if (delta < min_diff) \ 429 min_diff = delta, vm = m, va = a, vr = r; \ 430 } \ 431 } while (0) 432 433 static void 434 tgafb_set_pll(struct tga_par *par, int f) 435 { 436 int n, shift, base, min_diff, target; 437 int r,a,m,vm = 34, va = 1, vr = 30; 438 439 for (r = 0 ; r < 12 ; r++) 440 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG); 441 442 if (f > TGA_PLL_MAX_FREQ) 443 f = TGA_PLL_MAX_FREQ; 444 445 if (f >= TGA_PLL_MAX_FREQ / 2) 446 shift = 0; 447 else if (f >= TGA_PLL_MAX_FREQ / 4) 448 shift = 1; 449 else 450 shift = 2; 451 452 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG); 453 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG); 454 455 for (r = 0 ; r < 10 ; r++) 456 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 457 458 if (f <= 120000) { 459 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 461 } 462 else if (f <= 200000) { 463 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 464 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 465 } 466 else { 467 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 468 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 469 } 470 471 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 472 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 473 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 474 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 475 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG); 476 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG); 477 478 target = (f << shift) / TGA_PLL_BASE_FREQ; 479 min_diff = TGA_PLL_MAX_FREQ; 480 481 r = 7 / target; 482 if (!r) r = 1; 483 484 base = target * r; 485 while (base < 449) { 486 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) { 487 m = ((n + 3) / 7) - 1; 488 a = 0; 489 DIFFCHECK((m + 1) * 7); 490 m++; 491 DIFFCHECK((m + 1) * 7); 492 m = (n / 6) - 1; 493 if ((a = n % 6)) 494 DIFFCHECK(n); 495 } 496 r++; 497 base += target; 498 } 499 500 vr--; 501 502 for (r = 0; r < 8; r++) 503 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG); 504 for (r = 0; r < 8 ; r++) 505 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG); 506 for (r = 0; r < 7 ; r++) 507 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG); 508 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG); 509 } 510 511 512 /** 513 * tgafb_setcolreg - Optional function. Sets a color register. 514 * @regno: boolean, 0 copy local, 1 get_user() function 515 * @red: frame buffer colormap structure 516 * @green: The green value which can be up to 16 bits wide 517 * @blue: The blue value which can be up to 16 bits wide. 518 * @transp: If supported the alpha value which can be up to 16 bits wide. 519 * @info: frame buffer info structure 520 */ 521 static int 522 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, 523 unsigned transp, struct fb_info *info) 524 { 525 struct tga_par *par = (struct tga_par *) info->par; 526 int tga_bus_pci = dev_is_pci(par->dev); 527 int tga_bus_tc = TGA_BUS_TC(par->dev); 528 529 if (regno > 255) 530 return 1; 531 red >>= 8; 532 green >>= 8; 533 blue >>= 8; 534 535 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) { 536 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE); 537 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); 538 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 539 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 540 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 541 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) { 542 BT459_LOAD_ADDR(par, regno); 543 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG); 544 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG); 545 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG); 546 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG); 547 } else { 548 if (regno < 16) { 549 u32 value = (regno << 16) | (regno << 8) | regno; 550 ((u32 *)info->pseudo_palette)[regno] = value; 551 } 552 BT463_LOAD_ADDR(par, regno); 553 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG); 554 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG); 555 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG); 556 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG); 557 } 558 559 return 0; 560 } 561 562 563 /** 564 * tgafb_blank - Optional function. Blanks the display. 565 * @blank: the blank mode we want. 566 * @info: frame buffer structure that represents a single frame buffer 567 */ 568 static int 569 tgafb_blank(int blank, struct fb_info *info) 570 { 571 struct tga_par *par = (struct tga_par *) info->par; 572 u32 vhcr, vvcr, vvvr; 573 unsigned long flags; 574 575 local_irq_save(flags); 576 577 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG); 578 vvcr = TGA_READ_REG(par, TGA_VERT_REG); 579 vvvr = TGA_READ_REG(par, TGA_VALID_REG); 580 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK); 581 582 switch (blank) { 583 case FB_BLANK_UNBLANK: /* Unblanking */ 584 if (par->vesa_blanked) { 585 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG); 586 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG); 587 par->vesa_blanked = 0; 588 } 589 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG); 590 break; 591 592 case FB_BLANK_NORMAL: /* Normal blanking */ 593 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK, 594 TGA_VALID_REG); 595 break; 596 597 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ 598 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG); 599 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 600 par->vesa_blanked = 1; 601 break; 602 603 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ 604 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG); 605 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 606 par->vesa_blanked = 1; 607 break; 608 609 case FB_BLANK_POWERDOWN: /* Poweroff */ 610 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG); 611 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG); 612 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG); 613 par->vesa_blanked = 1; 614 break; 615 } 616 617 local_irq_restore(flags); 618 return 0; 619 } 620 621 622 /* 623 * Acceleration. 624 */ 625 626 static void 627 tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image) 628 { 629 struct tga_par *par = (struct tga_par *) info->par; 630 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask; 631 unsigned long rincr, line_length, shift, pos, is8bpp; 632 unsigned long i, j; 633 const unsigned char *data; 634 void __iomem *regs_base; 635 void __iomem *fb_base; 636 637 is8bpp = info->var.bits_per_pixel == 8; 638 639 dx = image->dx; 640 dy = image->dy; 641 width = image->width; 642 height = image->height; 643 vxres = info->var.xres_virtual; 644 vyres = info->var.yres_virtual; 645 line_length = info->fix.line_length; 646 rincr = (width + 7) / 8; 647 648 /* A shift below cannot cope with. */ 649 if (unlikely(width == 0)) 650 return; 651 /* Crop the image to the screen. */ 652 if (dx > vxres || dy > vyres) 653 return; 654 if (dx + width > vxres) 655 width = vxres - dx; 656 if (dy + height > vyres) 657 height = vyres - dy; 658 659 regs_base = par->tga_regs_base; 660 fb_base = par->tga_fb_base; 661 662 /* Expand the color values to fill 32-bits. */ 663 /* ??? Would be nice to notice colour changes elsewhere, so 664 that we can do this only when necessary. */ 665 fgcolor = image->fg_color; 666 bgcolor = image->bg_color; 667 if (is8bpp) { 668 fgcolor |= fgcolor << 8; 669 fgcolor |= fgcolor << 16; 670 bgcolor |= bgcolor << 8; 671 bgcolor |= bgcolor << 16; 672 } else { 673 if (fgcolor < 16) 674 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor]; 675 if (bgcolor < 16) 676 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor]; 677 } 678 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG); 679 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG); 680 681 /* Acquire proper alignment; set up the PIXELMASK register 682 so that we only write the proper character cell. */ 683 pos = dy * line_length; 684 if (is8bpp) { 685 pos += dx; 686 shift = pos & 3; 687 pos &= -4; 688 } else { 689 pos += dx * 4; 690 shift = (pos & 7) >> 2; 691 pos &= -8; 692 } 693 694 data = (const unsigned char *) image->data; 695 696 /* Enable opaque stipple mode. */ 697 __raw_writel((is8bpp 698 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE 699 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE), 700 regs_base + TGA_MODE_REG); 701 702 if (width + shift <= 32) { 703 unsigned long bwidth; 704 705 /* Handle common case of imaging a single character, in 706 a font less than or 32 pixels wide. */ 707 708 /* Avoid a shift by 32; width > 0 implied. */ 709 pixelmask = (2ul << (width - 1)) - 1; 710 pixelmask <<= shift; 711 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 712 wmb(); 713 714 bwidth = (width + 7) / 8; 715 716 for (i = 0; i < height; ++i) { 717 u32 mask = 0; 718 719 /* The image data is bit big endian; we need 720 little endian. */ 721 for (j = 0; j < bwidth; ++j) 722 mask |= bitrev8(data[j]) << (j * 8); 723 724 __raw_writel(mask << shift, fb_base + pos); 725 726 pos += line_length; 727 data += rincr; 728 } 729 wmb(); 730 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); 731 } else if (shift == 0) { 732 unsigned long pos0 = pos; 733 const unsigned char *data0 = data; 734 unsigned long bincr = (is8bpp ? 8 : 8*4); 735 unsigned long bwidth; 736 737 /* Handle another common case in which accel_putcs 738 generates a large bitmap, which happens to be aligned. 739 Allow the tail to be misaligned. This case is 740 interesting because we've not got to hold partial 741 bytes across the words being written. */ 742 743 wmb(); 744 745 bwidth = (width / 8) & -4; 746 for (i = 0; i < height; ++i) { 747 for (j = 0; j < bwidth; j += 4) { 748 u32 mask = 0; 749 mask |= bitrev8(data[j+0]) << (0 * 8); 750 mask |= bitrev8(data[j+1]) << (1 * 8); 751 mask |= bitrev8(data[j+2]) << (2 * 8); 752 mask |= bitrev8(data[j+3]) << (3 * 8); 753 __raw_writel(mask, fb_base + pos + j*bincr); 754 } 755 pos += line_length; 756 data += rincr; 757 } 758 wmb(); 759 760 pixelmask = (1ul << (width & 31)) - 1; 761 if (pixelmask) { 762 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 763 wmb(); 764 765 pos = pos0 + bwidth*bincr; 766 data = data0 + bwidth; 767 bwidth = ((width & 31) + 7) / 8; 768 769 for (i = 0; i < height; ++i) { 770 u32 mask = 0; 771 for (j = 0; j < bwidth; ++j) 772 mask |= bitrev8(data[j]) << (j * 8); 773 __raw_writel(mask, fb_base + pos); 774 pos += line_length; 775 data += rincr; 776 } 777 wmb(); 778 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); 779 } 780 } else { 781 unsigned long pos0 = pos; 782 const unsigned char *data0 = data; 783 unsigned long bincr = (is8bpp ? 8 : 8*4); 784 unsigned long bwidth; 785 786 /* Finally, handle the generic case of misaligned start. 787 Here we split the write into 16-bit spans. This allows 788 us to use only one pixel mask, instead of four as would 789 be required by writing 24-bit spans. */ 790 791 pixelmask = 0xffff << shift; 792 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 793 wmb(); 794 795 bwidth = (width / 8) & -2; 796 for (i = 0; i < height; ++i) { 797 for (j = 0; j < bwidth; j += 2) { 798 u32 mask = 0; 799 mask |= bitrev8(data[j+0]) << (0 * 8); 800 mask |= bitrev8(data[j+1]) << (1 * 8); 801 mask <<= shift; 802 __raw_writel(mask, fb_base + pos + j*bincr); 803 } 804 pos += line_length; 805 data += rincr; 806 } 807 wmb(); 808 809 pixelmask = ((1ul << (width & 15)) - 1) << shift; 810 if (pixelmask) { 811 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 812 wmb(); 813 814 pos = pos0 + bwidth*bincr; 815 data = data0 + bwidth; 816 bwidth = (width & 15) > 8; 817 818 for (i = 0; i < height; ++i) { 819 u32 mask = bitrev8(data[0]); 820 if (bwidth) 821 mask |= bitrev8(data[1]) << 8; 822 mask <<= shift; 823 __raw_writel(mask, fb_base + pos); 824 pos += line_length; 825 data += rincr; 826 } 827 wmb(); 828 } 829 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); 830 } 831 832 /* Disable opaque stipple mode. */ 833 __raw_writel((is8bpp 834 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE 835 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE), 836 regs_base + TGA_MODE_REG); 837 } 838 839 static void 840 tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image) 841 { 842 struct tga_par *par = (struct tga_par *) info->par; 843 u32 color, dx, dy, width, height, vxres, vyres; 844 u32 *palette = ((u32 *)info->pseudo_palette); 845 unsigned long pos, line_length, i, j; 846 const unsigned char *data; 847 void __iomem *fb_base; 848 849 dx = image->dx; 850 dy = image->dy; 851 width = image->width; 852 height = image->height; 853 vxres = info->var.xres_virtual; 854 vyres = info->var.yres_virtual; 855 line_length = info->fix.line_length; 856 857 /* Crop the image to the screen. */ 858 if (dx > vxres || dy > vyres) 859 return; 860 if (dx + width > vxres) 861 width = vxres - dx; 862 if (dy + height > vyres) 863 height = vyres - dy; 864 865 fb_base = par->tga_fb_base; 866 867 pos = dy * line_length + (dx * 4); 868 data = image->data; 869 870 /* Now copy the image, color_expanding via the palette. */ 871 for (i = 0; i < height; i++) { 872 for (j = 0; j < width; j++) { 873 color = palette[*data++]; 874 __raw_writel(color, fb_base + pos + j*4); 875 } 876 pos += line_length; 877 } 878 } 879 880 /** 881 * tgafb_imageblit - REQUIRED function. Can use generic routines if 882 * non acclerated hardware and packed pixel based. 883 * Copies a image from system memory to the screen. 884 * 885 * @info: frame buffer structure that represents a single frame buffer 886 * @image: structure defining the image. 887 */ 888 static void 889 tgafb_imageblit(struct fb_info *info, const struct fb_image *image) 890 { 891 unsigned int is8bpp = info->var.bits_per_pixel == 8; 892 893 /* If a mono image, regardless of FB depth, go do it. */ 894 if (image->depth == 1) { 895 tgafb_mono_imageblit(info, image); 896 return; 897 } 898 899 /* For copies that aren't pixel expansion, there's little we 900 can do better than the generic code. */ 901 /* ??? There is a DMA write mode; I wonder if that could be 902 made to pull the data from the image buffer... */ 903 if (image->depth == info->var.bits_per_pixel) { 904 cfb_imageblit(info, image); 905 return; 906 } 907 908 /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */ 909 if (!is8bpp && image->depth == 8) { 910 tgafb_clut_imageblit(info, image); 911 return; 912 } 913 914 /* Silently return... */ 915 } 916 917 /** 918 * tgafb_fillrect - REQUIRED function. Can use generic routines if 919 * non acclerated hardware and packed pixel based. 920 * Draws a rectangle on the screen. 921 * 922 * @info: frame buffer structure that represents a single frame buffer 923 * @rect: structure defining the rectagle and operation. 924 */ 925 static void 926 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 927 { 928 struct tga_par *par = (struct tga_par *) info->par; 929 int is8bpp = info->var.bits_per_pixel == 8; 930 u32 dx, dy, width, height, vxres, vyres, color; 931 unsigned long pos, align, line_length, i, j; 932 void __iomem *regs_base; 933 void __iomem *fb_base; 934 935 dx = rect->dx; 936 dy = rect->dy; 937 width = rect->width; 938 height = rect->height; 939 vxres = info->var.xres_virtual; 940 vyres = info->var.yres_virtual; 941 line_length = info->fix.line_length; 942 regs_base = par->tga_regs_base; 943 fb_base = par->tga_fb_base; 944 945 /* Crop the rectangle to the screen. */ 946 if (dx > vxres || dy > vyres || !width || !height) 947 return; 948 if (dx + width > vxres) 949 width = vxres - dx; 950 if (dy + height > vyres) 951 height = vyres - dy; 952 953 pos = dy * line_length + dx * (is8bpp ? 1 : 4); 954 955 /* ??? We could implement ROP_XOR with opaque fill mode 956 and a RasterOp setting of GXxor, but as far as I can 957 tell, this mode is not actually used in the kernel. 958 Thus I am ignoring it for now. */ 959 if (rect->rop != ROP_COPY) { 960 cfb_fillrect(info, rect); 961 return; 962 } 963 964 /* Expand the color value to fill 8 pixels. */ 965 color = rect->color; 966 if (is8bpp) { 967 color |= color << 8; 968 color |= color << 16; 969 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG); 970 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG); 971 } else { 972 if (color < 16) 973 color = ((u32 *)info->pseudo_palette)[color]; 974 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG); 975 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG); 976 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG); 977 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG); 978 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG); 979 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG); 980 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG); 981 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG); 982 } 983 984 /* The DATA register holds the fill mask for block fill mode. 985 Since we're not stippling, this is all ones. */ 986 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG); 987 988 /* Enable block fill mode. */ 989 __raw_writel((is8bpp 990 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL 991 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL), 992 regs_base + TGA_MODE_REG); 993 wmb(); 994 995 /* We can fill 2k pixels per operation. Notice blocks that fit 996 the width of the screen so that we can take advantage of this 997 and fill more than one line per write. */ 998 if (width == line_length) { 999 width *= height; 1000 height = 1; 1001 } 1002 1003 /* The write into the frame buffer must be aligned to 4 bytes, 1004 but we are allowed to encode the offset within the word in 1005 the data word written. */ 1006 align = (pos & 3) << 16; 1007 pos &= -4; 1008 1009 if (width <= 2048) { 1010 u32 data; 1011 1012 data = (width - 1) | align; 1013 1014 for (i = 0; i < height; ++i) { 1015 __raw_writel(data, fb_base + pos); 1016 pos += line_length; 1017 } 1018 } else { 1019 unsigned long Bpp = (is8bpp ? 1 : 4); 1020 unsigned long nwidth = width & -2048; 1021 u32 fdata, ldata; 1022 1023 fdata = (2048 - 1) | align; 1024 ldata = ((width & 2047) - 1) | align; 1025 1026 for (i = 0; i < height; ++i) { 1027 for (j = 0; j < nwidth; j += 2048) 1028 __raw_writel(fdata, fb_base + pos + j*Bpp); 1029 if (j < width) 1030 __raw_writel(ldata, fb_base + pos + j*Bpp); 1031 pos += line_length; 1032 } 1033 } 1034 wmb(); 1035 1036 /* Disable block fill mode. */ 1037 __raw_writel((is8bpp 1038 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE 1039 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE), 1040 regs_base + TGA_MODE_REG); 1041 } 1042 1043 /* 1044 * tgafb_copyarea - REQUIRED function. Can use generic routines if 1045 * non acclerated hardware and packed pixel based. 1046 * Copies on area of the screen to another area. 1047 * 1048 * @info: frame buffer structure that represents a single frame buffer 1049 * @area: structure defining the source and destination. 1050 */ 1051 1052 /* Handle the special case of copying entire lines, e.g. during scrolling. 1053 We can avoid a lot of needless computation in this case. In the 8bpp 1054 case we need to use the COPY64 registers instead of mask writes into 1055 the frame buffer to achieve maximum performance. */ 1056 1057 static inline void 1058 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy, 1059 u32 height, u32 width) 1060 { 1061 struct tga_par *par = (struct tga_par *) info->par; 1062 void __iomem *tga_regs = par->tga_regs_base; 1063 unsigned long dpos, spos, i, n64; 1064 1065 /* Set up the MODE and PIXELSHIFT registers. */ 1066 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG); 1067 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); 1068 wmb(); 1069 1070 n64 = (height * width) / 64; 1071 1072 if (sy < dy) { 1073 spos = (sy + height) * width; 1074 dpos = (dy + height) * width; 1075 1076 for (i = 0; i < n64; ++i) { 1077 spos -= 64; 1078 dpos -= 64; 1079 __raw_writel(spos, tga_regs+TGA_COPY64_SRC); 1080 wmb(); 1081 __raw_writel(dpos, tga_regs+TGA_COPY64_DST); 1082 wmb(); 1083 } 1084 } else { 1085 spos = sy * width; 1086 dpos = dy * width; 1087 1088 for (i = 0; i < n64; ++i) { 1089 __raw_writel(spos, tga_regs+TGA_COPY64_SRC); 1090 wmb(); 1091 __raw_writel(dpos, tga_regs+TGA_COPY64_DST); 1092 wmb(); 1093 spos += 64; 1094 dpos += 64; 1095 } 1096 } 1097 1098 /* Reset the MODE register to normal. */ 1099 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); 1100 } 1101 1102 static inline void 1103 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy, 1104 u32 height, u32 width) 1105 { 1106 struct tga_par *par = (struct tga_par *) info->par; 1107 void __iomem *tga_regs = par->tga_regs_base; 1108 void __iomem *tga_fb = par->tga_fb_base; 1109 void __iomem *src; 1110 void __iomem *dst; 1111 unsigned long i, n16; 1112 1113 /* Set up the MODE and PIXELSHIFT registers. */ 1114 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG); 1115 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); 1116 wmb(); 1117 1118 n16 = (height * width) / 16; 1119 1120 if (sy < dy) { 1121 src = tga_fb + (sy + height) * width * 4; 1122 dst = tga_fb + (dy + height) * width * 4; 1123 1124 for (i = 0; i < n16; ++i) { 1125 src -= 64; 1126 dst -= 64; 1127 __raw_writel(0xffff, src); 1128 wmb(); 1129 __raw_writel(0xffff, dst); 1130 wmb(); 1131 } 1132 } else { 1133 src = tga_fb + sy * width * 4; 1134 dst = tga_fb + dy * width * 4; 1135 1136 for (i = 0; i < n16; ++i) { 1137 __raw_writel(0xffff, src); 1138 wmb(); 1139 __raw_writel(0xffff, dst); 1140 wmb(); 1141 src += 64; 1142 dst += 64; 1143 } 1144 } 1145 1146 /* Reset the MODE register to normal. */ 1147 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); 1148 } 1149 1150 /* The (almost) general case of backward copy in 8bpp mode. */ 1151 static inline void 1152 copyarea_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy, 1153 u32 height, u32 width, u32 line_length, 1154 const struct fb_copyarea *area) 1155 { 1156 struct tga_par *par = (struct tga_par *) info->par; 1157 unsigned i, yincr; 1158 int depos, sepos, backward, last_step, step; 1159 u32 mask_last; 1160 unsigned n32; 1161 void __iomem *tga_regs; 1162 void __iomem *tga_fb; 1163 1164 /* Do acceleration only if we are aligned on 8 pixels */ 1165 if ((dx | sx | width) & 7) { 1166 cfb_copyarea(info, area); 1167 return; 1168 } 1169 1170 yincr = line_length; 1171 if (dy > sy) { 1172 dy += height - 1; 1173 sy += height - 1; 1174 yincr = -yincr; 1175 } 1176 backward = dy == sy && dx > sx && dx < sx + width; 1177 1178 /* Compute the offsets and alignments in the frame buffer. 1179 More than anything else, these control how we do copies. */ 1180 depos = dy * line_length + dx; 1181 sepos = sy * line_length + sx; 1182 if (backward) { 1183 depos += width; 1184 sepos += width; 1185 } 1186 1187 /* Next copy full words at a time. */ 1188 n32 = width / 32; 1189 last_step = width % 32; 1190 1191 /* Finally copy the unaligned head of the span. */ 1192 mask_last = (1ul << last_step) - 1; 1193 1194 if (!backward) { 1195 step = 32; 1196 last_step = 32; 1197 } else { 1198 step = -32; 1199 last_step = -last_step; 1200 sepos -= 32; 1201 depos -= 32; 1202 } 1203 1204 tga_regs = par->tga_regs_base; 1205 tga_fb = par->tga_fb_base; 1206 1207 /* Set up the MODE and PIXELSHIFT registers. */ 1208 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG); 1209 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG); 1210 wmb(); 1211 1212 for (i = 0; i < height; ++i) { 1213 unsigned long j; 1214 void __iomem *sfb; 1215 void __iomem *dfb; 1216 1217 sfb = tga_fb + sepos; 1218 dfb = tga_fb + depos; 1219 1220 for (j = 0; j < n32; j++) { 1221 if (j < 2 && j + 1 < n32 && !backward && 1222 !(((unsigned long)sfb | (unsigned long)dfb) & 63)) { 1223 do { 1224 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC); 1225 wmb(); 1226 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST); 1227 wmb(); 1228 sfb += 64; 1229 dfb += 64; 1230 j += 2; 1231 } while (j + 1 < n32); 1232 j--; 1233 continue; 1234 } 1235 __raw_writel(0xffffffff, sfb); 1236 wmb(); 1237 __raw_writel(0xffffffff, dfb); 1238 wmb(); 1239 sfb += step; 1240 dfb += step; 1241 } 1242 1243 if (mask_last) { 1244 sfb += last_step - step; 1245 dfb += last_step - step; 1246 __raw_writel(mask_last, sfb); 1247 wmb(); 1248 __raw_writel(mask_last, dfb); 1249 wmb(); 1250 } 1251 1252 sepos += yincr; 1253 depos += yincr; 1254 } 1255 1256 /* Reset the MODE register to normal. */ 1257 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG); 1258 } 1259 1260 static void 1261 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 1262 { 1263 unsigned long dx, dy, width, height, sx, sy, vxres, vyres; 1264 unsigned long line_length, bpp; 1265 1266 dx = area->dx; 1267 dy = area->dy; 1268 width = area->width; 1269 height = area->height; 1270 sx = area->sx; 1271 sy = area->sy; 1272 vxres = info->var.xres_virtual; 1273 vyres = info->var.yres_virtual; 1274 line_length = info->fix.line_length; 1275 1276 /* The top left corners must be in the virtual screen. */ 1277 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres) 1278 return; 1279 1280 /* Clip the destination. */ 1281 if (dx + width > vxres) 1282 width = vxres - dx; 1283 if (dy + height > vyres) 1284 height = vyres - dy; 1285 1286 /* The source must be completely inside the virtual screen. */ 1287 if (sx + width > vxres || sy + height > vyres) 1288 return; 1289 1290 bpp = info->var.bits_per_pixel; 1291 1292 /* Detect copies of the entire line. */ 1293 if (!(line_length & 63) && width * (bpp >> 3) == line_length) { 1294 if (bpp == 8) 1295 copyarea_line_8bpp(info, dy, sy, height, width); 1296 else 1297 copyarea_line_32bpp(info, dy, sy, height, width); 1298 } 1299 1300 /* ??? The documentation is unclear to me exactly how the pixelshift 1301 register works in 32bpp mode. Since I don't have hardware to test, 1302 give up for now and fall back on the generic routines. */ 1303 else if (bpp == 32) 1304 cfb_copyarea(info, area); 1305 1306 else 1307 copyarea_8bpp(info, dx, dy, sx, sy, height, 1308 width, line_length, area); 1309 } 1310 1311 1312 /* 1313 * Initialisation 1314 */ 1315 1316 static void 1317 tgafb_init_fix(struct fb_info *info) 1318 { 1319 struct tga_par *par = (struct tga_par *)info->par; 1320 int tga_bus_pci = dev_is_pci(par->dev); 1321 int tga_bus_tc = TGA_BUS_TC(par->dev); 1322 u8 tga_type = par->tga_type; 1323 const char *tga_type_name = NULL; 1324 unsigned memory_size; 1325 1326 switch (tga_type) { 1327 case TGA_TYPE_8PLANE: 1328 if (tga_bus_pci) 1329 tga_type_name = "Digital ZLXp-E1"; 1330 if (tga_bus_tc) 1331 tga_type_name = "Digital ZLX-E1"; 1332 memory_size = 2097152; 1333 break; 1334 case TGA_TYPE_24PLANE: 1335 if (tga_bus_pci) 1336 tga_type_name = "Digital ZLXp-E2"; 1337 if (tga_bus_tc) 1338 tga_type_name = "Digital ZLX-E2"; 1339 memory_size = 8388608; 1340 break; 1341 case TGA_TYPE_24PLUSZ: 1342 if (tga_bus_pci) 1343 tga_type_name = "Digital ZLXp-E3"; 1344 if (tga_bus_tc) 1345 tga_type_name = "Digital ZLX-E3"; 1346 memory_size = 16777216; 1347 break; 1348 } 1349 if (!tga_type_name) { 1350 tga_type_name = "Unknown"; 1351 memory_size = 16777216; 1352 } 1353 1354 strscpy(info->fix.id, tga_type_name, sizeof(info->fix.id)); 1355 1356 info->fix.type = FB_TYPE_PACKED_PIXELS; 1357 info->fix.type_aux = 0; 1358 info->fix.visual = (tga_type == TGA_TYPE_8PLANE 1359 ? FB_VISUAL_PSEUDOCOLOR 1360 : FB_VISUAL_DIRECTCOLOR); 1361 1362 info->fix.smem_start = (size_t) par->tga_fb_base; 1363 info->fix.smem_len = memory_size; 1364 info->fix.mmio_start = (size_t) par->tga_regs_base; 1365 info->fix.mmio_len = 512; 1366 1367 info->fix.xpanstep = 0; 1368 info->fix.ypanstep = 0; 1369 info->fix.ywrapstep = 0; 1370 1371 info->fix.accel = FB_ACCEL_DEC_TGA; 1372 1373 /* 1374 * These are needed by fb_set_logo_truepalette(), so we 1375 * set them here for 24-plane cards. 1376 */ 1377 if (tga_type != TGA_TYPE_8PLANE) { 1378 info->var.red.length = 8; 1379 info->var.green.length = 8; 1380 info->var.blue.length = 8; 1381 info->var.red.offset = 16; 1382 info->var.green.offset = 8; 1383 info->var.blue.offset = 0; 1384 } 1385 } 1386 1387 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 1388 { 1389 /* We just use this to catch switches out of graphics mode. */ 1390 tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */ 1391 return 0; 1392 } 1393 1394 static int tgafb_register(struct device *dev) 1395 { 1396 static const struct fb_videomode modedb_tc = { 1397 /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */ 1398 "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3, 1399 FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED 1400 }; 1401 1402 static unsigned int const fb_offset_presets[4] = { 1403 TGA_8PLANE_FB_OFFSET, 1404 TGA_24PLANE_FB_OFFSET, 1405 0xffffffff, 1406 TGA_24PLUSZ_FB_OFFSET 1407 }; 1408 1409 const struct fb_videomode *modedb_tga = NULL; 1410 resource_size_t bar0_start = 0, bar0_len = 0; 1411 const char *mode_option_tga = NULL; 1412 int tga_bus_pci = dev_is_pci(dev); 1413 int tga_bus_tc = TGA_BUS_TC(dev); 1414 unsigned int modedbsize_tga = 0; 1415 void __iomem *mem_base; 1416 struct fb_info *info; 1417 struct tga_par *par; 1418 u8 tga_type; 1419 int ret = 0; 1420 1421 /* Enable device in PCI config. */ 1422 if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) { 1423 printk(KERN_ERR "tgafb: Cannot enable PCI device\n"); 1424 return -ENODEV; 1425 } 1426 1427 /* Allocate the fb and par structures. */ 1428 info = framebuffer_alloc(sizeof(struct tga_par), dev); 1429 if (!info) 1430 return -ENOMEM; 1431 1432 par = info->par; 1433 dev_set_drvdata(dev, info); 1434 1435 /* Request the mem regions. */ 1436 ret = -ENODEV; 1437 if (tga_bus_pci) { 1438 bar0_start = pci_resource_start(to_pci_dev(dev), 0); 1439 bar0_len = pci_resource_len(to_pci_dev(dev), 0); 1440 } 1441 if (tga_bus_tc) { 1442 bar0_start = to_tc_dev(dev)->resource.start; 1443 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1; 1444 } 1445 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) { 1446 printk(KERN_ERR "tgafb: cannot reserve FB region\n"); 1447 goto err0; 1448 } 1449 1450 /* Map the framebuffer. */ 1451 mem_base = ioremap(bar0_start, bar0_len); 1452 if (!mem_base) { 1453 printk(KERN_ERR "tgafb: Cannot map MMIO\n"); 1454 goto err1; 1455 } 1456 1457 /* Grab info about the card. */ 1458 tga_type = (readl(mem_base) >> 12) & 0x0f; 1459 par->dev = dev; 1460 par->tga_mem_base = mem_base; 1461 par->tga_fb_base = mem_base + fb_offset_presets[tga_type]; 1462 par->tga_regs_base = mem_base + TGA_REGS_OFFSET; 1463 par->tga_type = tga_type; 1464 if (tga_bus_pci) 1465 par->tga_chip_rev = (to_pci_dev(dev))->revision; 1466 if (tga_bus_tc) 1467 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff; 1468 1469 /* Setup framebuffer. */ 1470 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | 1471 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT; 1472 info->fbops = &tgafb_ops; 1473 info->screen_base = par->tga_fb_base; 1474 info->pseudo_palette = par->palette; 1475 1476 /* This should give a reasonable default video mode. */ 1477 if (tga_bus_pci) { 1478 mode_option_tga = mode_option_pci; 1479 } 1480 if (tga_bus_tc) { 1481 mode_option_tga = mode_option_tc; 1482 modedb_tga = &modedb_tc; 1483 modedbsize_tga = 1; 1484 } 1485 1486 tgafb_init_fix(info); 1487 1488 ret = fb_find_mode(&info->var, info, 1489 mode_option ? mode_option : mode_option_tga, 1490 modedb_tga, modedbsize_tga, NULL, 1491 tga_type == TGA_TYPE_8PLANE ? 8 : 32); 1492 if (ret == 0 || ret == 4) { 1493 printk(KERN_ERR "tgafb: Could not find valid video mode\n"); 1494 ret = -EINVAL; 1495 goto err1; 1496 } 1497 1498 if (fb_alloc_cmap(&info->cmap, 256, 0)) { 1499 printk(KERN_ERR "tgafb: Could not allocate color map\n"); 1500 ret = -ENOMEM; 1501 goto err1; 1502 } 1503 1504 tgafb_set_par(info); 1505 1506 if (register_framebuffer(info) < 0) { 1507 printk(KERN_ERR "tgafb: Could not register framebuffer\n"); 1508 ret = -EINVAL; 1509 goto err2; 1510 } 1511 1512 if (tga_bus_pci) { 1513 pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n", 1514 par->tga_chip_rev); 1515 pr_info("tgafb: at PCI bus %d, device %d, function %d\n", 1516 to_pci_dev(dev)->bus->number, 1517 PCI_SLOT(to_pci_dev(dev)->devfn), 1518 PCI_FUNC(to_pci_dev(dev)->devfn)); 1519 } 1520 if (tga_bus_tc) 1521 pr_info("tgafb: SFB+ detected, rev=0x%02x\n", 1522 par->tga_chip_rev); 1523 fb_info(info, "%s frame buffer device at 0x%lx\n", 1524 info->fix.id, (long)bar0_start); 1525 1526 return 0; 1527 1528 err2: 1529 fb_dealloc_cmap(&info->cmap); 1530 err1: 1531 if (mem_base) 1532 iounmap(mem_base); 1533 release_mem_region(bar0_start, bar0_len); 1534 err0: 1535 framebuffer_release(info); 1536 return ret; 1537 } 1538 1539 static void tgafb_unregister(struct device *dev) 1540 { 1541 resource_size_t bar0_start = 0, bar0_len = 0; 1542 int tga_bus_pci = dev_is_pci(dev); 1543 int tga_bus_tc = TGA_BUS_TC(dev); 1544 struct fb_info *info = NULL; 1545 struct tga_par *par; 1546 1547 info = dev_get_drvdata(dev); 1548 if (!info) 1549 return; 1550 1551 par = info->par; 1552 unregister_framebuffer(info); 1553 fb_dealloc_cmap(&info->cmap); 1554 iounmap(par->tga_mem_base); 1555 if (tga_bus_pci) { 1556 bar0_start = pci_resource_start(to_pci_dev(dev), 0); 1557 bar0_len = pci_resource_len(to_pci_dev(dev), 0); 1558 } 1559 if (tga_bus_tc) { 1560 bar0_start = to_tc_dev(dev)->resource.start; 1561 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1; 1562 } 1563 release_mem_region(bar0_start, bar0_len); 1564 framebuffer_release(info); 1565 } 1566 1567 static void tgafb_exit(void) 1568 { 1569 tc_unregister_driver(&tgafb_tc_driver); 1570 pci_unregister_driver(&tgafb_pci_driver); 1571 } 1572 1573 #ifndef MODULE 1574 static int tgafb_setup(char *arg) 1575 { 1576 char *this_opt; 1577 1578 if (arg && *arg) { 1579 while ((this_opt = strsep(&arg, ","))) { 1580 if (!*this_opt) 1581 continue; 1582 if (!strncmp(this_opt, "mode:", 5)) 1583 mode_option = this_opt+5; 1584 else 1585 printk(KERN_ERR 1586 "tgafb: unknown parameter %s\n", 1587 this_opt); 1588 } 1589 } 1590 1591 return 0; 1592 } 1593 #endif /* !MODULE */ 1594 1595 static int tgafb_init(void) 1596 { 1597 int status; 1598 #ifndef MODULE 1599 char *option = NULL; 1600 1601 if (fb_get_options("tgafb", &option)) 1602 return -ENODEV; 1603 tgafb_setup(option); 1604 #endif 1605 status = pci_register_driver(&tgafb_pci_driver); 1606 if (!status) 1607 status = tc_register_driver(&tgafb_tc_driver); 1608 return status; 1609 } 1610 1611 /* 1612 * Modularisation 1613 */ 1614 1615 module_init(tgafb_init); 1616 module_exit(tgafb_exit); 1617 1618 MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset"); 1619 MODULE_LICENSE("GPL"); 1620