1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "icl_dsi.h" 32 #include "intel_atomic.h" 33 #include "intel_backlight.h" 34 #include "intel_combo_phy.h" 35 #include "intel_connector.h" 36 #include "intel_crtc.h" 37 #include "intel_ddi.h" 38 #include "intel_de.h" 39 #include "intel_dsi.h" 40 #include "intel_dsi_vbt.h" 41 #include "intel_panel.h" 42 #include "intel_vdsc.h" 43 #include "skl_scaler.h" 44 #include "skl_universal_plane.h" 45 46 static int header_credits_available(struct drm_i915_private *dev_priv, 47 enum transcoder dsi_trans) 48 { 49 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 50 >> FREE_HEADER_CREDIT_SHIFT; 51 } 52 53 static int payload_credits_available(struct drm_i915_private *dev_priv, 54 enum transcoder dsi_trans) 55 { 56 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 57 >> FREE_PLOAD_CREDIT_SHIFT; 58 } 59 60 static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 61 enum transcoder dsi_trans, int hdr_credit) 62 { 63 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 64 hdr_credit, 100)) { 65 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 66 return false; 67 } 68 69 return true; 70 } 71 72 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 73 enum transcoder dsi_trans, int payld_credit) 74 { 75 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 76 payld_credit, 100)) { 77 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 78 return false; 79 } 80 81 return true; 82 } 83 84 static enum transcoder dsi_port_to_transcoder(enum port port) 85 { 86 if (port == PORT_A) 87 return TRANSCODER_DSI_0; 88 else 89 return TRANSCODER_DSI_1; 90 } 91 92 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 93 { 94 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 95 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 96 struct mipi_dsi_device *dsi; 97 enum port port; 98 enum transcoder dsi_trans; 99 int ret; 100 101 /* wait for header/payload credits to be released */ 102 for_each_dsi_port(port, intel_dsi->ports) { 103 dsi_trans = dsi_port_to_transcoder(port); 104 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 105 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 106 } 107 108 /* send nop DCS command */ 109 for_each_dsi_port(port, intel_dsi->ports) { 110 dsi = intel_dsi->dsi_hosts[port]->device; 111 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 112 dsi->channel = 0; 113 ret = mipi_dsi_dcs_nop(dsi); 114 if (ret < 0) 115 drm_err(&dev_priv->drm, 116 "error sending DCS NOP command\n"); 117 } 118 119 /* wait for header credits to be released */ 120 for_each_dsi_port(port, intel_dsi->ports) { 121 dsi_trans = dsi_port_to_transcoder(port); 122 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 123 } 124 125 /* wait for LP TX in progress bit to be cleared */ 126 for_each_dsi_port(port, intel_dsi->ports) { 127 dsi_trans = dsi_port_to_transcoder(port); 128 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 129 LPTX_IN_PROGRESS), 20)) 130 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 131 } 132 } 133 134 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 135 const struct mipi_dsi_packet *packet) 136 { 137 struct intel_dsi *intel_dsi = host->intel_dsi; 138 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 139 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 140 const u8 *data = packet->payload; 141 u32 len = packet->payload_length; 142 int i, j; 143 144 /* payload queue can accept *256 bytes*, check limit */ 145 if (len > MAX_PLOAD_CREDIT * 4) { 146 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 147 return -EINVAL; 148 } 149 150 for (i = 0; i < len; i += 4) { 151 u32 tmp = 0; 152 153 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 154 return -EBUSY; 155 156 for (j = 0; j < min_t(u32, len - i, 4); j++) 157 tmp |= *data++ << 8 * j; 158 159 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 160 } 161 162 return 0; 163 } 164 165 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 166 const struct mipi_dsi_packet *packet, 167 bool enable_lpdt) 168 { 169 struct intel_dsi *intel_dsi = host->intel_dsi; 170 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 171 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 172 u32 tmp; 173 174 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 175 return -EBUSY; 176 177 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 178 179 if (packet->payload) 180 tmp |= PAYLOAD_PRESENT; 181 else 182 tmp &= ~PAYLOAD_PRESENT; 183 184 tmp &= ~VBLANK_FENCE; 185 186 if (enable_lpdt) 187 tmp |= LP_DATA_TRANSFER; 188 else 189 tmp &= ~LP_DATA_TRANSFER; 190 191 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 192 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 193 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 194 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 195 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 196 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 197 198 return 0; 199 } 200 201 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 202 { 203 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 204 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 205 u32 tmp, mode_flags; 206 enum port port; 207 208 mode_flags = crtc_state->mode_flags; 209 210 /* 211 * case 1 also covers dual link 212 * In case of dual link, frame update should be set on 213 * DSI_0 214 */ 215 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 216 port = PORT_A; 217 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 218 port = PORT_B; 219 else 220 return; 221 222 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 223 tmp |= DSI_FRAME_UPDATE_REQUEST; 224 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 225 } 226 227 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 228 { 229 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 230 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 231 enum phy phy; 232 u32 tmp; 233 int lane; 234 235 for_each_dsi_phy(phy, intel_dsi->phys) { 236 /* 237 * Program voltage swing and pre-emphasis level values as per 238 * table in BSPEC under DDI buffer programing 239 */ 240 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 241 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 242 tmp |= SCALING_MODE_SEL(0x2); 243 tmp |= TAP2_DISABLE | TAP3_DISABLE; 244 tmp |= RTERM_SELECT(0x6); 245 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 246 247 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 248 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 249 tmp |= SCALING_MODE_SEL(0x2); 250 tmp |= TAP2_DISABLE | TAP3_DISABLE; 251 tmp |= RTERM_SELECT(0x6); 252 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 253 254 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 255 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 256 RCOMP_SCALAR_MASK); 257 tmp |= SWING_SEL_UPPER(0x2); 258 tmp |= SWING_SEL_LOWER(0x2); 259 tmp |= RCOMP_SCALAR(0x98); 260 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 261 262 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 263 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 264 RCOMP_SCALAR_MASK); 265 tmp |= SWING_SEL_UPPER(0x2); 266 tmp |= SWING_SEL_LOWER(0x2); 267 tmp |= RCOMP_SCALAR(0x98); 268 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 269 270 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 271 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 272 CURSOR_COEFF_MASK); 273 tmp |= POST_CURSOR_1(0x0); 274 tmp |= POST_CURSOR_2(0x0); 275 tmp |= CURSOR_COEFF(0x3f); 276 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 277 278 for (lane = 0; lane <= 3; lane++) { 279 /* Bspec: must not use GRP register for write */ 280 tmp = intel_de_read(dev_priv, 281 ICL_PORT_TX_DW4_LN(lane, phy)); 282 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 283 CURSOR_COEFF_MASK); 284 tmp |= POST_CURSOR_1(0x0); 285 tmp |= POST_CURSOR_2(0x0); 286 tmp |= CURSOR_COEFF(0x3f); 287 intel_de_write(dev_priv, 288 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 289 } 290 } 291 } 292 293 static void configure_dual_link_mode(struct intel_encoder *encoder, 294 const struct intel_crtc_state *pipe_config) 295 { 296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 297 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 298 u32 dss_ctl1; 299 300 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 301 dss_ctl1 |= SPLITTER_ENABLE; 302 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 303 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 304 305 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 306 const struct drm_display_mode *adjusted_mode = 307 &pipe_config->hw.adjusted_mode; 308 u32 dss_ctl2; 309 u16 hactive = adjusted_mode->crtc_hdisplay; 310 u16 dl_buffer_depth; 311 312 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 313 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 314 315 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 316 drm_err(&dev_priv->drm, 317 "DL buffer depth exceed max value\n"); 318 319 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 320 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 321 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 322 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 323 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 324 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 325 } else { 326 /* Interleave */ 327 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 328 } 329 330 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 331 } 332 333 /* aka DSI 8X clock */ 334 static int afe_clk(struct intel_encoder *encoder, 335 const struct intel_crtc_state *crtc_state) 336 { 337 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 338 int bpp; 339 340 if (crtc_state->dsc.compression_enable) 341 bpp = crtc_state->dsc.compressed_bpp; 342 else 343 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 344 345 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 346 } 347 348 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 349 const struct intel_crtc_state *crtc_state) 350 { 351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 352 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 353 enum port port; 354 int afe_clk_khz; 355 int theo_word_clk, act_word_clk; 356 u32 esc_clk_div_m, esc_clk_div_m_phy; 357 358 afe_clk_khz = afe_clk(encoder, crtc_state); 359 360 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 361 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 362 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 363 esc_clk_div_m = act_word_clk * 8; 364 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 365 } else { 366 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 367 } 368 369 for_each_dsi_port(port, intel_dsi->ports) { 370 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 371 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 372 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 373 } 374 375 for_each_dsi_port(port, intel_dsi->ports) { 376 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 377 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 378 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 379 } 380 381 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 382 for_each_dsi_port(port, intel_dsi->ports) { 383 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 384 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 385 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 386 } 387 } 388 } 389 390 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 391 struct intel_dsi *intel_dsi) 392 { 393 enum port port; 394 395 for_each_dsi_port(port, intel_dsi->ports) { 396 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 397 intel_dsi->io_wakeref[port] = 398 intel_display_power_get(dev_priv, 399 port == PORT_A ? 400 POWER_DOMAIN_PORT_DDI_A_IO : 401 POWER_DOMAIN_PORT_DDI_B_IO); 402 } 403 } 404 405 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 406 { 407 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 408 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 409 enum port port; 410 u32 tmp; 411 412 for_each_dsi_port(port, intel_dsi->ports) { 413 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 414 tmp |= COMBO_PHY_MODE_DSI; 415 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 416 } 417 418 get_dsi_io_power_domains(dev_priv, intel_dsi); 419 } 420 421 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 422 { 423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 424 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 425 enum phy phy; 426 427 for_each_dsi_phy(phy, intel_dsi->phys) 428 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 429 intel_dsi->lane_count, false); 430 } 431 432 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 433 { 434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 435 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 436 enum phy phy; 437 u32 tmp; 438 int lane; 439 440 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 441 for_each_dsi_phy(phy, intel_dsi->phys) { 442 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 443 tmp &= ~LOADGEN_SELECT; 444 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 445 for (lane = 0; lane <= 3; lane++) { 446 tmp = intel_de_read(dev_priv, 447 ICL_PORT_TX_DW4_LN(lane, phy)); 448 tmp &= ~LOADGEN_SELECT; 449 if (lane != 2) 450 tmp |= LOADGEN_SELECT; 451 intel_de_write(dev_priv, 452 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 453 } 454 } 455 456 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 457 for_each_dsi_phy(phy, intel_dsi->phys) { 458 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 459 tmp &= ~FRC_LATENCY_OPTIM_MASK; 460 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 461 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 462 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 463 tmp &= ~FRC_LATENCY_OPTIM_MASK; 464 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 465 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 466 467 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 468 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) { 469 tmp = intel_de_read(dev_priv, 470 ICL_PORT_PCS_DW1_AUX(phy)); 471 tmp &= ~LATENCY_OPTIM_MASK; 472 tmp |= LATENCY_OPTIM_VAL(0); 473 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 474 tmp); 475 476 tmp = intel_de_read(dev_priv, 477 ICL_PORT_PCS_DW1_LN(0, phy)); 478 tmp &= ~LATENCY_OPTIM_MASK; 479 tmp |= LATENCY_OPTIM_VAL(0x1); 480 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 481 tmp); 482 } 483 } 484 485 } 486 487 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 488 { 489 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 490 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 491 u32 tmp; 492 enum phy phy; 493 494 /* clear common keeper enable bit */ 495 for_each_dsi_phy(phy, intel_dsi->phys) { 496 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 497 tmp &= ~COMMON_KEEPER_EN; 498 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 499 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 500 tmp &= ~COMMON_KEEPER_EN; 501 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 502 } 503 504 /* 505 * Set SUS Clock Config bitfield to 11b 506 * Note: loadgen select program is done 507 * as part of lane phy sequence configuration 508 */ 509 for_each_dsi_phy(phy, intel_dsi->phys) { 510 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 511 tmp |= SUS_CLOCK_CONFIG; 512 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 513 } 514 515 /* Clear training enable to change swing values */ 516 for_each_dsi_phy(phy, intel_dsi->phys) { 517 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 518 tmp &= ~TX_TRAINING_EN; 519 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 520 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 521 tmp &= ~TX_TRAINING_EN; 522 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 523 } 524 525 /* Program swing and de-emphasis */ 526 dsi_program_swing_and_deemphasis(encoder); 527 528 /* Set training enable to trigger update */ 529 for_each_dsi_phy(phy, intel_dsi->phys) { 530 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 531 tmp |= TX_TRAINING_EN; 532 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 533 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 534 tmp |= TX_TRAINING_EN; 535 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 536 } 537 } 538 539 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 540 { 541 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 542 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 543 u32 tmp; 544 enum port port; 545 546 for_each_dsi_port(port, intel_dsi->ports) { 547 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 548 tmp |= DDI_BUF_CTL_ENABLE; 549 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 550 551 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 552 DDI_BUF_IS_IDLE), 553 500)) 554 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 555 port_name(port)); 556 } 557 } 558 559 static void 560 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 561 const struct intel_crtc_state *crtc_state) 562 { 563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 564 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 565 u32 tmp; 566 enum port port; 567 enum phy phy; 568 569 /* Program T-INIT master registers */ 570 for_each_dsi_port(port, intel_dsi->ports) { 571 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 572 tmp &= ~MASTER_INIT_TIMER_MASK; 573 tmp |= intel_dsi->init_count; 574 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 575 } 576 577 /* Program DPHY clock lanes timings */ 578 for_each_dsi_port(port, intel_dsi->ports) { 579 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 580 intel_dsi->dphy_reg); 581 582 /* shadow register inside display core */ 583 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 584 intel_dsi->dphy_reg); 585 } 586 587 /* Program DPHY data lanes timings */ 588 for_each_dsi_port(port, intel_dsi->ports) { 589 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 590 intel_dsi->dphy_data_lane_reg); 591 592 /* shadow register inside display core */ 593 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 594 intel_dsi->dphy_data_lane_reg); 595 } 596 597 /* 598 * If DSI link operating at or below an 800 MHz, 599 * TA_SURE should be override and programmed to 600 * a value '0' inside TA_PARAM_REGISTERS otherwise 601 * leave all fields at HW default values. 602 */ 603 if (DISPLAY_VER(dev_priv) == 11) { 604 if (afe_clk(encoder, crtc_state) <= 800000) { 605 for_each_dsi_port(port, intel_dsi->ports) { 606 tmp = intel_de_read(dev_priv, 607 DPHY_TA_TIMING_PARAM(port)); 608 tmp &= ~TA_SURE_MASK; 609 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 610 intel_de_write(dev_priv, 611 DPHY_TA_TIMING_PARAM(port), 612 tmp); 613 614 /* shadow register inside display core */ 615 tmp = intel_de_read(dev_priv, 616 DSI_TA_TIMING_PARAM(port)); 617 tmp &= ~TA_SURE_MASK; 618 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 619 intel_de_write(dev_priv, 620 DSI_TA_TIMING_PARAM(port), tmp); 621 } 622 } 623 } 624 625 if (IS_JSL_EHL(dev_priv)) { 626 for_each_dsi_phy(phy, intel_dsi->phys) { 627 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 628 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 629 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 630 } 631 } 632 } 633 634 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 635 { 636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 637 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 638 u32 tmp; 639 enum phy phy; 640 641 mutex_lock(&dev_priv->dpll.lock); 642 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 643 for_each_dsi_phy(phy, intel_dsi->phys) 644 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 645 646 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 647 mutex_unlock(&dev_priv->dpll.lock); 648 } 649 650 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 651 { 652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 653 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 654 u32 tmp; 655 enum phy phy; 656 657 mutex_lock(&dev_priv->dpll.lock); 658 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 659 for_each_dsi_phy(phy, intel_dsi->phys) 660 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 661 662 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 663 mutex_unlock(&dev_priv->dpll.lock); 664 } 665 666 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 667 { 668 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 669 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 670 bool clock_enabled = false; 671 enum phy phy; 672 u32 tmp; 673 674 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 675 676 for_each_dsi_phy(phy, intel_dsi->phys) { 677 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 678 clock_enabled = true; 679 } 680 681 return clock_enabled; 682 } 683 684 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 685 const struct intel_crtc_state *crtc_state) 686 { 687 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 688 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 689 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 690 enum phy phy; 691 u32 val; 692 693 mutex_lock(&dev_priv->dpll.lock); 694 695 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 696 for_each_dsi_phy(phy, intel_dsi->phys) { 697 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 698 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 699 } 700 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 701 702 for_each_dsi_phy(phy, intel_dsi->phys) { 703 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 704 } 705 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 706 707 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 708 709 mutex_unlock(&dev_priv->dpll.lock); 710 } 711 712 static void 713 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 714 const struct intel_crtc_state *pipe_config) 715 { 716 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 717 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 718 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 719 enum pipe pipe = crtc->pipe; 720 u32 tmp; 721 enum port port; 722 enum transcoder dsi_trans; 723 724 for_each_dsi_port(port, intel_dsi->ports) { 725 dsi_trans = dsi_port_to_transcoder(port); 726 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 727 728 if (intel_dsi->eotp_pkt) 729 tmp &= ~EOTP_DISABLED; 730 else 731 tmp |= EOTP_DISABLED; 732 733 /* enable link calibration if freq > 1.5Gbps */ 734 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 735 tmp &= ~LINK_CALIBRATION_MASK; 736 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 737 } 738 739 /* configure continuous clock */ 740 tmp &= ~CONTINUOUS_CLK_MASK; 741 if (intel_dsi->clock_stop) 742 tmp |= CLK_ENTER_LP_AFTER_DATA; 743 else 744 tmp |= CLK_HS_CONTINUOUS; 745 746 /* configure buffer threshold limit to minimum */ 747 tmp &= ~PIX_BUF_THRESHOLD_MASK; 748 tmp |= PIX_BUF_THRESHOLD_1_4; 749 750 /* set virtual channel to '0' */ 751 tmp &= ~PIX_VIRT_CHAN_MASK; 752 tmp |= PIX_VIRT_CHAN(0); 753 754 /* program BGR transmission */ 755 if (intel_dsi->bgr_enabled) 756 tmp |= BGR_TRANSMISSION; 757 758 /* select pixel format */ 759 tmp &= ~PIX_FMT_MASK; 760 if (pipe_config->dsc.compression_enable) { 761 tmp |= PIX_FMT_COMPRESSED; 762 } else { 763 switch (intel_dsi->pixel_format) { 764 default: 765 MISSING_CASE(intel_dsi->pixel_format); 766 fallthrough; 767 case MIPI_DSI_FMT_RGB565: 768 tmp |= PIX_FMT_RGB565; 769 break; 770 case MIPI_DSI_FMT_RGB666_PACKED: 771 tmp |= PIX_FMT_RGB666_PACKED; 772 break; 773 case MIPI_DSI_FMT_RGB666: 774 tmp |= PIX_FMT_RGB666_LOOSE; 775 break; 776 case MIPI_DSI_FMT_RGB888: 777 tmp |= PIX_FMT_RGB888; 778 break; 779 } 780 } 781 782 if (DISPLAY_VER(dev_priv) >= 12) { 783 if (is_vid_mode(intel_dsi)) 784 tmp |= BLANKING_PACKET_ENABLE; 785 } 786 787 /* program DSI operation mode */ 788 if (is_vid_mode(intel_dsi)) { 789 tmp &= ~OP_MODE_MASK; 790 switch (intel_dsi->video_mode_format) { 791 default: 792 MISSING_CASE(intel_dsi->video_mode_format); 793 fallthrough; 794 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS: 795 tmp |= VIDEO_MODE_SYNC_EVENT; 796 break; 797 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE: 798 tmp |= VIDEO_MODE_SYNC_PULSE; 799 break; 800 } 801 } else { 802 /* 803 * FIXME: Retrieve this info from VBT. 804 * As per the spec when dsi transcoder is operating 805 * in TE GATE mode, TE comes from GPIO 806 * which is UTIL PIN for DSI 0. 807 * Also this GPIO would not be used for other 808 * purposes is an assumption. 809 */ 810 tmp &= ~OP_MODE_MASK; 811 tmp |= CMD_MODE_TE_GATE; 812 tmp |= TE_SOURCE_GPIO; 813 } 814 815 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 816 } 817 818 /* enable port sync mode if dual link */ 819 if (intel_dsi->dual_link) { 820 for_each_dsi_port(port, intel_dsi->ports) { 821 dsi_trans = dsi_port_to_transcoder(port); 822 tmp = intel_de_read(dev_priv, 823 TRANS_DDI_FUNC_CTL2(dsi_trans)); 824 tmp |= PORT_SYNC_MODE_ENABLE; 825 intel_de_write(dev_priv, 826 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 827 } 828 829 /* configure stream splitting */ 830 configure_dual_link_mode(encoder, pipe_config); 831 } 832 833 for_each_dsi_port(port, intel_dsi->ports) { 834 dsi_trans = dsi_port_to_transcoder(port); 835 836 /* select data lane width */ 837 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 838 tmp &= ~DDI_PORT_WIDTH_MASK; 839 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 840 841 /* select input pipe */ 842 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 843 switch (pipe) { 844 default: 845 MISSING_CASE(pipe); 846 fallthrough; 847 case PIPE_A: 848 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 849 break; 850 case PIPE_B: 851 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 852 break; 853 case PIPE_C: 854 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 855 break; 856 case PIPE_D: 857 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 858 break; 859 } 860 861 /* enable DDI buffer */ 862 tmp |= TRANS_DDI_FUNC_ENABLE; 863 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 864 } 865 866 /* wait for link ready */ 867 for_each_dsi_port(port, intel_dsi->ports) { 868 dsi_trans = dsi_port_to_transcoder(port); 869 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 870 LINK_READY), 2500)) 871 drm_err(&dev_priv->drm, "DSI link not ready\n"); 872 } 873 } 874 875 static void 876 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 877 const struct intel_crtc_state *crtc_state) 878 { 879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 880 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 881 const struct drm_display_mode *adjusted_mode = 882 &crtc_state->hw.adjusted_mode; 883 enum port port; 884 enum transcoder dsi_trans; 885 /* horizontal timings */ 886 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 887 u16 hback_porch; 888 /* vertical timings */ 889 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 890 int mul = 1, div = 1; 891 892 /* 893 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 894 * for slower link speed if DSC is enabled. 895 * 896 * The compression frequency ratio is the ratio between compressed and 897 * non-compressed link speeds, and simplifies down to the ratio between 898 * compressed and non-compressed bpp. 899 */ 900 if (crtc_state->dsc.compression_enable) { 901 mul = crtc_state->dsc.compressed_bpp; 902 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 903 } 904 905 hactive = adjusted_mode->crtc_hdisplay; 906 907 if (is_vid_mode(intel_dsi)) 908 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 909 else 910 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 911 912 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 913 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 914 hsync_size = hsync_end - hsync_start; 915 hback_porch = (adjusted_mode->crtc_htotal - 916 adjusted_mode->crtc_hsync_end); 917 vactive = adjusted_mode->crtc_vdisplay; 918 919 if (is_vid_mode(intel_dsi)) { 920 vtotal = adjusted_mode->crtc_vtotal; 921 } else { 922 int bpp, line_time_us, byte_clk_period_ns; 923 924 if (crtc_state->dsc.compression_enable) 925 bpp = crtc_state->dsc.compressed_bpp; 926 else 927 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 928 929 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 930 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 931 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 932 } 933 vsync_start = adjusted_mode->crtc_vsync_start; 934 vsync_end = adjusted_mode->crtc_vsync_end; 935 vsync_shift = hsync_start - htotal / 2; 936 937 if (intel_dsi->dual_link) { 938 hactive /= 2; 939 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 940 hactive += intel_dsi->pixel_overlap; 941 htotal /= 2; 942 } 943 944 /* minimum hactive as per bspec: 256 pixels */ 945 if (adjusted_mode->crtc_hdisplay < 256) 946 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 947 948 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 949 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 950 drm_err(&dev_priv->drm, 951 "hactive pixels are not multiple of 4\n"); 952 953 /* program TRANS_HTOTAL register */ 954 for_each_dsi_port(port, intel_dsi->ports) { 955 dsi_trans = dsi_port_to_transcoder(port); 956 intel_de_write(dev_priv, HTOTAL(dsi_trans), 957 (hactive - 1) | ((htotal - 1) << 16)); 958 } 959 960 /* TRANS_HSYNC register to be programmed only for video mode */ 961 if (is_vid_mode(intel_dsi)) { 962 if (intel_dsi->video_mode_format == 963 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { 964 /* BSPEC: hsync size should be atleast 16 pixels */ 965 if (hsync_size < 16) 966 drm_err(&dev_priv->drm, 967 "hsync size < 16 pixels\n"); 968 } 969 970 if (hback_porch < 16) 971 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 972 973 if (intel_dsi->dual_link) { 974 hsync_start /= 2; 975 hsync_end /= 2; 976 } 977 978 for_each_dsi_port(port, intel_dsi->ports) { 979 dsi_trans = dsi_port_to_transcoder(port); 980 intel_de_write(dev_priv, HSYNC(dsi_trans), 981 (hsync_start - 1) | ((hsync_end - 1) << 16)); 982 } 983 } 984 985 /* program TRANS_VTOTAL register */ 986 for_each_dsi_port(port, intel_dsi->ports) { 987 dsi_trans = dsi_port_to_transcoder(port); 988 /* 989 * FIXME: Programing this by assuming progressive mode, since 990 * non-interlaced info from VBT is not saved inside 991 * struct drm_display_mode. 992 * For interlace mode: program required pixel minus 2 993 */ 994 intel_de_write(dev_priv, VTOTAL(dsi_trans), 995 (vactive - 1) | ((vtotal - 1) << 16)); 996 } 997 998 if (vsync_end < vsync_start || vsync_end > vtotal) 999 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 1000 1001 if (vsync_start < vactive) 1002 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 1003 1004 /* program TRANS_VSYNC register for video mode only */ 1005 if (is_vid_mode(intel_dsi)) { 1006 for_each_dsi_port(port, intel_dsi->ports) { 1007 dsi_trans = dsi_port_to_transcoder(port); 1008 intel_de_write(dev_priv, VSYNC(dsi_trans), 1009 (vsync_start - 1) | ((vsync_end - 1) << 16)); 1010 } 1011 } 1012 1013 /* 1014 * FIXME: It has to be programmed only for video modes and interlaced 1015 * modes. Put the check condition here once interlaced 1016 * info available as described above. 1017 * program TRANS_VSYNCSHIFT register 1018 */ 1019 if (is_vid_mode(intel_dsi)) { 1020 for_each_dsi_port(port, intel_dsi->ports) { 1021 dsi_trans = dsi_port_to_transcoder(port); 1022 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), 1023 vsync_shift); 1024 } 1025 } 1026 1027 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 1028 if (DISPLAY_VER(dev_priv) >= 12) { 1029 for_each_dsi_port(port, intel_dsi->ports) { 1030 dsi_trans = dsi_port_to_transcoder(port); 1031 intel_de_write(dev_priv, VBLANK(dsi_trans), 1032 (vactive - 1) | ((vtotal - 1) << 16)); 1033 } 1034 } 1035 } 1036 1037 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1038 { 1039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1040 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1041 enum port port; 1042 enum transcoder dsi_trans; 1043 u32 tmp; 1044 1045 for_each_dsi_port(port, intel_dsi->ports) { 1046 dsi_trans = dsi_port_to_transcoder(port); 1047 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1048 tmp |= PIPECONF_ENABLE; 1049 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1050 1051 /* wait for transcoder to be enabled */ 1052 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 1053 I965_PIPECONF_ACTIVE, 10)) 1054 drm_err(&dev_priv->drm, 1055 "DSI transcoder not enabled\n"); 1056 } 1057 } 1058 1059 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1060 const struct intel_crtc_state *crtc_state) 1061 { 1062 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1063 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1064 enum port port; 1065 enum transcoder dsi_trans; 1066 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1067 1068 /* 1069 * escape clock count calculation: 1070 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1071 * UI (nsec) = (10^6)/Bitrate 1072 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1073 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1074 */ 1075 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1076 mul = 8 * 1000000; 1077 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1078 divisor); 1079 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1080 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1081 1082 for_each_dsi_port(port, intel_dsi->ports) { 1083 dsi_trans = dsi_port_to_transcoder(port); 1084 1085 /* program hst_tx_timeout */ 1086 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 1087 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 1088 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 1089 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1090 1091 /* FIXME: DSI_CALIB_TO */ 1092 1093 /* program lp_rx_host timeout */ 1094 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1095 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1096 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1097 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1098 1099 /* FIXME: DSI_PWAIT_TO */ 1100 1101 /* program turn around timeout */ 1102 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1103 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1104 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1105 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1106 } 1107 } 1108 1109 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1110 bool enable) 1111 { 1112 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1113 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1114 u32 tmp; 1115 1116 /* 1117 * used as TE i/p for DSI0, 1118 * for dual link/DSI1 TE is from slave DSI1 1119 * through GPIO. 1120 */ 1121 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1122 return; 1123 1124 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1125 1126 if (enable) { 1127 tmp |= UTIL_PIN_DIRECTION_INPUT; 1128 tmp |= UTIL_PIN_ENABLE; 1129 } else { 1130 tmp &= ~UTIL_PIN_ENABLE; 1131 } 1132 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1133 } 1134 1135 static void 1136 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1137 const struct intel_crtc_state *crtc_state) 1138 { 1139 /* step 4a: power up all lanes of the DDI used by DSI */ 1140 gen11_dsi_power_up_lanes(encoder); 1141 1142 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1143 gen11_dsi_config_phy_lanes_sequence(encoder); 1144 1145 /* step 4c: configure voltage swing and skew */ 1146 gen11_dsi_voltage_swing_program_seq(encoder); 1147 1148 /* enable DDI buffer */ 1149 gen11_dsi_enable_ddi_buffer(encoder); 1150 1151 /* setup D-PHY timings */ 1152 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1153 1154 /* Since transcoder is configured to take events from GPIO */ 1155 gen11_dsi_config_util_pin(encoder, true); 1156 1157 /* step 4h: setup DSI protocol timeouts */ 1158 gen11_dsi_setup_timeouts(encoder, crtc_state); 1159 1160 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1161 gen11_dsi_configure_transcoder(encoder, crtc_state); 1162 1163 /* Step 4l: Gate DDI clocks */ 1164 gen11_dsi_gate_clocks(encoder); 1165 } 1166 1167 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1168 { 1169 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1170 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1171 struct mipi_dsi_device *dsi; 1172 enum port port; 1173 enum transcoder dsi_trans; 1174 u32 tmp; 1175 int ret; 1176 1177 /* set maximum return packet size */ 1178 for_each_dsi_port(port, intel_dsi->ports) { 1179 dsi_trans = dsi_port_to_transcoder(port); 1180 1181 /* 1182 * FIXME: This uses the number of DW's currently in the payload 1183 * receive queue. This is probably not what we want here. 1184 */ 1185 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1186 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1187 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1188 tmp = tmp * 4; 1189 dsi = intel_dsi->dsi_hosts[port]->device; 1190 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1191 if (ret < 0) 1192 drm_err(&dev_priv->drm, 1193 "error setting max return pkt size%d\n", tmp); 1194 } 1195 1196 /* panel power on related mipi dsi vbt sequences */ 1197 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1198 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1199 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1200 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1201 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1202 1203 /* ensure all panel commands dispatched before enabling transcoder */ 1204 wait_for_cmds_dispatched_to_panel(encoder); 1205 } 1206 1207 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1208 struct intel_encoder *encoder, 1209 const struct intel_crtc_state *crtc_state, 1210 const struct drm_connector_state *conn_state) 1211 { 1212 /* step2: enable IO power */ 1213 gen11_dsi_enable_io_power(encoder); 1214 1215 /* step3: enable DSI PLL */ 1216 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1217 } 1218 1219 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1220 struct intel_encoder *encoder, 1221 const struct intel_crtc_state *pipe_config, 1222 const struct drm_connector_state *conn_state) 1223 { 1224 /* step3b */ 1225 gen11_dsi_map_pll(encoder, pipe_config); 1226 1227 /* step4: enable DSI port and DPHY */ 1228 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1229 1230 /* step5: program and powerup panel */ 1231 gen11_dsi_powerup_panel(encoder); 1232 1233 intel_dsc_dsi_pps_write(encoder, pipe_config); 1234 1235 intel_dsc_enable(pipe_config); 1236 1237 /* step6c: configure transcoder timings */ 1238 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1239 } 1240 1241 /* 1242 * Wa_1409054076:icl,jsl,ehl 1243 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1244 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1245 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1246 * it set while DSI is enabled on pipe B 1247 */ 1248 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1249 enum pipe pipe, bool enable) 1250 { 1251 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1252 1253 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1254 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1255 IGNORE_KVMR_PIPE_A, 1256 enable ? IGNORE_KVMR_PIPE_A : 0); 1257 } 1258 1259 /* 1260 * Wa_16012360555:adl-p 1261 * SW will have to program the "LP to HS Wakeup Guardband" 1262 * to account for the repeaters on the HS Request/Ready 1263 * PPI signaling between the Display engine and the DPHY. 1264 */ 1265 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1266 { 1267 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1268 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1269 enum port port; 1270 1271 if (DISPLAY_VER(i915) == 13) { 1272 for_each_dsi_port(port, intel_dsi->ports) 1273 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1274 TGL_DSI_CHKN_LSHS_GB_MASK, 1275 TGL_DSI_CHKN_LSHS_GB(4)); 1276 } 1277 } 1278 1279 static void gen11_dsi_enable(struct intel_atomic_state *state, 1280 struct intel_encoder *encoder, 1281 const struct intel_crtc_state *crtc_state, 1282 const struct drm_connector_state *conn_state) 1283 { 1284 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1285 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 1286 1287 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 1288 1289 /* Wa_1409054076:icl,jsl,ehl */ 1290 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1291 1292 /* Wa_16012360555:adl-p */ 1293 adlp_set_lp_hs_wakeup_gb(encoder); 1294 1295 /* step6d: enable dsi transcoder */ 1296 gen11_dsi_enable_transcoder(encoder); 1297 1298 /* step7: enable backlight */ 1299 intel_backlight_enable(crtc_state, conn_state); 1300 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1301 1302 intel_crtc_vblank_on(crtc_state); 1303 } 1304 1305 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1306 { 1307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1309 enum port port; 1310 enum transcoder dsi_trans; 1311 u32 tmp; 1312 1313 for_each_dsi_port(port, intel_dsi->ports) { 1314 dsi_trans = dsi_port_to_transcoder(port); 1315 1316 /* disable transcoder */ 1317 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1318 tmp &= ~PIPECONF_ENABLE; 1319 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1320 1321 /* wait for transcoder to be disabled */ 1322 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1323 I965_PIPECONF_ACTIVE, 50)) 1324 drm_err(&dev_priv->drm, 1325 "DSI trancoder not disabled\n"); 1326 } 1327 } 1328 1329 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1330 { 1331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1332 1333 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1334 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1335 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1336 1337 /* ensure cmds dispatched to panel */ 1338 wait_for_cmds_dispatched_to_panel(encoder); 1339 } 1340 1341 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1342 { 1343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1344 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1345 enum port port; 1346 enum transcoder dsi_trans; 1347 u32 tmp; 1348 1349 /* disable periodic update mode */ 1350 if (is_cmd_mode(intel_dsi)) { 1351 for_each_dsi_port(port, intel_dsi->ports) { 1352 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); 1353 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; 1354 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); 1355 } 1356 } 1357 1358 /* put dsi link in ULPS */ 1359 for_each_dsi_port(port, intel_dsi->ports) { 1360 dsi_trans = dsi_port_to_transcoder(port); 1361 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1362 tmp |= LINK_ENTER_ULPS; 1363 tmp &= ~LINK_ULPS_TYPE_LP11; 1364 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1365 1366 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1367 LINK_IN_ULPS), 1368 10)) 1369 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1370 } 1371 1372 /* disable ddi function */ 1373 for_each_dsi_port(port, intel_dsi->ports) { 1374 dsi_trans = dsi_port_to_transcoder(port); 1375 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1376 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1377 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1378 } 1379 1380 /* disable port sync mode if dual link */ 1381 if (intel_dsi->dual_link) { 1382 for_each_dsi_port(port, intel_dsi->ports) { 1383 dsi_trans = dsi_port_to_transcoder(port); 1384 tmp = intel_de_read(dev_priv, 1385 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1386 tmp &= ~PORT_SYNC_MODE_ENABLE; 1387 intel_de_write(dev_priv, 1388 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1389 } 1390 } 1391 } 1392 1393 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1394 { 1395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1396 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1397 u32 tmp; 1398 enum port port; 1399 1400 gen11_dsi_ungate_clocks(encoder); 1401 for_each_dsi_port(port, intel_dsi->ports) { 1402 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1403 tmp &= ~DDI_BUF_CTL_ENABLE; 1404 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1405 1406 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1407 DDI_BUF_IS_IDLE), 1408 8)) 1409 drm_err(&dev_priv->drm, 1410 "DDI port:%c buffer not idle\n", 1411 port_name(port)); 1412 } 1413 gen11_dsi_gate_clocks(encoder); 1414 } 1415 1416 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1417 { 1418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1420 enum port port; 1421 u32 tmp; 1422 1423 for_each_dsi_port(port, intel_dsi->ports) { 1424 intel_wakeref_t wakeref; 1425 1426 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1427 intel_display_power_put(dev_priv, 1428 port == PORT_A ? 1429 POWER_DOMAIN_PORT_DDI_A_IO : 1430 POWER_DOMAIN_PORT_DDI_B_IO, 1431 wakeref); 1432 } 1433 1434 /* set mode to DDI */ 1435 for_each_dsi_port(port, intel_dsi->ports) { 1436 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1437 tmp &= ~COMBO_PHY_MODE_DSI; 1438 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1439 } 1440 } 1441 1442 static void gen11_dsi_disable(struct intel_atomic_state *state, 1443 struct intel_encoder *encoder, 1444 const struct intel_crtc_state *old_crtc_state, 1445 const struct drm_connector_state *old_conn_state) 1446 { 1447 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1448 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); 1449 1450 /* step1: turn off backlight */ 1451 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1452 intel_backlight_disable(old_conn_state); 1453 1454 /* step2d,e: disable transcoder and wait */ 1455 gen11_dsi_disable_transcoder(encoder); 1456 1457 /* Wa_1409054076:icl,jsl,ehl */ 1458 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1459 1460 /* step2f,g: powerdown panel */ 1461 gen11_dsi_powerdown_panel(encoder); 1462 1463 /* step2h,i,j: deconfig trancoder */ 1464 gen11_dsi_deconfigure_trancoder(encoder); 1465 1466 /* step3: disable port */ 1467 gen11_dsi_disable_port(encoder); 1468 1469 gen11_dsi_config_util_pin(encoder, false); 1470 1471 /* step4: disable IO power */ 1472 gen11_dsi_disable_io_power(encoder); 1473 } 1474 1475 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1476 struct intel_encoder *encoder, 1477 const struct intel_crtc_state *old_crtc_state, 1478 const struct drm_connector_state *old_conn_state) 1479 { 1480 intel_crtc_vblank_off(old_crtc_state); 1481 1482 intel_dsc_disable(old_crtc_state); 1483 1484 skl_scaler_disable(old_crtc_state); 1485 } 1486 1487 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1488 struct drm_display_mode *mode) 1489 { 1490 /* FIXME: DSC? */ 1491 return intel_dsi_mode_valid(connector, mode); 1492 } 1493 1494 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1495 struct intel_crtc_state *pipe_config) 1496 { 1497 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1498 struct drm_display_mode *adjusted_mode = 1499 &pipe_config->hw.adjusted_mode; 1500 1501 if (pipe_config->dsc.compressed_bpp) { 1502 int div = pipe_config->dsc.compressed_bpp; 1503 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1504 1505 adjusted_mode->crtc_htotal = 1506 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1507 adjusted_mode->crtc_hsync_start = 1508 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1509 adjusted_mode->crtc_hsync_end = 1510 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1511 } 1512 1513 if (intel_dsi->dual_link) { 1514 adjusted_mode->crtc_hdisplay *= 2; 1515 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1516 adjusted_mode->crtc_hdisplay -= 1517 intel_dsi->pixel_overlap; 1518 adjusted_mode->crtc_htotal *= 2; 1519 } 1520 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1521 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1522 1523 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1524 if (intel_dsi->dual_link) { 1525 adjusted_mode->crtc_hsync_start *= 2; 1526 adjusted_mode->crtc_hsync_end *= 2; 1527 } 1528 } 1529 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1530 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1531 } 1532 1533 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1534 { 1535 struct drm_device *dev = intel_dsi->base.base.dev; 1536 struct drm_i915_private *dev_priv = to_i915(dev); 1537 enum transcoder dsi_trans; 1538 u32 val; 1539 1540 if (intel_dsi->ports == BIT(PORT_B)) 1541 dsi_trans = TRANSCODER_DSI_1; 1542 else 1543 dsi_trans = TRANSCODER_DSI_0; 1544 1545 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1546 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1547 } 1548 1549 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1550 struct intel_crtc_state *pipe_config) 1551 { 1552 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1553 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1554 I915_MODE_FLAG_DSI_USE_TE0; 1555 else if (intel_dsi->ports == BIT(PORT_B)) 1556 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1557 else 1558 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1559 } 1560 1561 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1562 struct intel_crtc_state *pipe_config) 1563 { 1564 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1565 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1566 1567 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1568 1569 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1570 if (intel_dsi->dual_link) 1571 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1572 1573 gen11_dsi_get_timings(encoder, pipe_config); 1574 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1575 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1576 1577 /* Get the details on which TE should be enabled */ 1578 if (is_cmd_mode(intel_dsi)) 1579 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1580 1581 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1582 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1583 } 1584 1585 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1586 const struct intel_crtc_state *crtc_state) 1587 { 1588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1589 struct intel_crtc *intel_crtc; 1590 enum pipe pipe; 1591 1592 if (!crtc_state) 1593 return; 1594 1595 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1596 pipe = intel_crtc->pipe; 1597 1598 /* wa verify 1409054076:icl,jsl,ehl */ 1599 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1600 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1601 drm_dbg_kms(&dev_priv->drm, 1602 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1603 encoder->base.base.id, 1604 encoder->base.name); 1605 } 1606 1607 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1608 struct intel_crtc_state *crtc_state) 1609 { 1610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1611 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1612 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1613 bool use_dsc; 1614 int ret; 1615 1616 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1617 if (!use_dsc) 1618 return 0; 1619 1620 if (crtc_state->pipe_bpp < 8 * 3) 1621 return -EINVAL; 1622 1623 /* FIXME: split only when necessary */ 1624 if (crtc_state->dsc.slice_count > 1) 1625 crtc_state->dsc.dsc_split = true; 1626 1627 vdsc_cfg->convert_rgb = true; 1628 1629 /* FIXME: initialize from VBT */ 1630 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1631 1632 ret = intel_dsc_compute_params(crtc_state); 1633 if (ret) 1634 return ret; 1635 1636 /* DSI specific sanity checks on the common code */ 1637 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1638 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1639 drm_WARN_ON(&dev_priv->drm, 1640 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1641 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1642 drm_WARN_ON(&dev_priv->drm, 1643 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1644 1645 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1646 if (ret) 1647 return ret; 1648 1649 crtc_state->dsc.compression_enable = true; 1650 1651 return 0; 1652 } 1653 1654 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1655 struct intel_crtc_state *pipe_config, 1656 struct drm_connector_state *conn_state) 1657 { 1658 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1659 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1660 base); 1661 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1662 struct drm_display_mode *adjusted_mode = 1663 &pipe_config->hw.adjusted_mode; 1664 int ret; 1665 1666 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1667 1668 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1669 if (ret) 1670 return ret; 1671 1672 ret = intel_panel_fitting(pipe_config, conn_state); 1673 if (ret) 1674 return ret; 1675 1676 adjusted_mode->flags = 0; 1677 1678 /* Dual link goes to trancoder DSI'0' */ 1679 if (intel_dsi->ports == BIT(PORT_B)) 1680 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1681 else 1682 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1683 1684 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1685 pipe_config->pipe_bpp = 24; 1686 else 1687 pipe_config->pipe_bpp = 18; 1688 1689 pipe_config->clock_set = true; 1690 1691 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1692 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1693 1694 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1695 1696 /* 1697 * In case of TE GATE cmd mode, we 1698 * receive TE from the slave if 1699 * dual link is enabled 1700 */ 1701 if (is_cmd_mode(intel_dsi)) 1702 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1703 1704 return 0; 1705 } 1706 1707 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1708 struct intel_crtc_state *crtc_state) 1709 { 1710 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1711 1712 get_dsi_io_power_domains(i915, 1713 enc_to_intel_dsi(encoder)); 1714 } 1715 1716 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1717 enum pipe *pipe) 1718 { 1719 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1720 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1721 enum transcoder dsi_trans; 1722 intel_wakeref_t wakeref; 1723 enum port port; 1724 bool ret = false; 1725 u32 tmp; 1726 1727 wakeref = intel_display_power_get_if_enabled(dev_priv, 1728 encoder->power_domain); 1729 if (!wakeref) 1730 return false; 1731 1732 for_each_dsi_port(port, intel_dsi->ports) { 1733 dsi_trans = dsi_port_to_transcoder(port); 1734 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1735 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1736 case TRANS_DDI_EDP_INPUT_A_ON: 1737 *pipe = PIPE_A; 1738 break; 1739 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1740 *pipe = PIPE_B; 1741 break; 1742 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1743 *pipe = PIPE_C; 1744 break; 1745 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1746 *pipe = PIPE_D; 1747 break; 1748 default: 1749 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1750 goto out; 1751 } 1752 1753 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1754 ret = tmp & PIPECONF_ENABLE; 1755 } 1756 out: 1757 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1758 return ret; 1759 } 1760 1761 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1762 struct intel_crtc_state *crtc_state) 1763 { 1764 if (crtc_state->dsc.compression_enable) { 1765 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1766 crtc_state->uapi.mode_changed = true; 1767 1768 return false; 1769 } 1770 1771 return true; 1772 } 1773 1774 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1775 { 1776 intel_encoder_destroy(encoder); 1777 } 1778 1779 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1780 .destroy = gen11_dsi_encoder_destroy, 1781 }; 1782 1783 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1784 .detect = intel_panel_detect, 1785 .late_register = intel_connector_register, 1786 .early_unregister = intel_connector_unregister, 1787 .destroy = intel_connector_destroy, 1788 .fill_modes = drm_helper_probe_single_connector_modes, 1789 .atomic_get_property = intel_digital_connector_atomic_get_property, 1790 .atomic_set_property = intel_digital_connector_atomic_set_property, 1791 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1792 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1793 }; 1794 1795 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1796 .get_modes = intel_dsi_get_modes, 1797 .mode_valid = gen11_dsi_mode_valid, 1798 .atomic_check = intel_digital_connector_atomic_check, 1799 }; 1800 1801 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1802 struct mipi_dsi_device *dsi) 1803 { 1804 return 0; 1805 } 1806 1807 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1808 struct mipi_dsi_device *dsi) 1809 { 1810 return 0; 1811 } 1812 1813 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1814 const struct mipi_dsi_msg *msg) 1815 { 1816 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1817 struct mipi_dsi_packet dsi_pkt; 1818 ssize_t ret; 1819 bool enable_lpdt = false; 1820 1821 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1822 if (ret < 0) 1823 return ret; 1824 1825 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1826 enable_lpdt = true; 1827 1828 /* only long packet contains payload */ 1829 if (mipi_dsi_packet_format_is_long(msg->type)) { 1830 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1831 if (ret < 0) 1832 return ret; 1833 } 1834 1835 /* send packet header */ 1836 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1837 if (ret < 0) 1838 return ret; 1839 1840 //TODO: add payload receive code if needed 1841 1842 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1843 1844 return ret; 1845 } 1846 1847 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1848 .attach = gen11_dsi_host_attach, 1849 .detach = gen11_dsi_host_detach, 1850 .transfer = gen11_dsi_host_transfer, 1851 }; 1852 1853 #define ICL_PREPARE_CNT_MAX 0x7 1854 #define ICL_CLK_ZERO_CNT_MAX 0xf 1855 #define ICL_TRAIL_CNT_MAX 0x7 1856 #define ICL_TCLK_PRE_CNT_MAX 0x3 1857 #define ICL_TCLK_POST_CNT_MAX 0x7 1858 #define ICL_HS_ZERO_CNT_MAX 0xf 1859 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1860 1861 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1862 { 1863 struct drm_device *dev = intel_dsi->base.base.dev; 1864 struct drm_i915_private *dev_priv = to_i915(dev); 1865 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1866 u32 tlpx_ns; 1867 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1868 u32 ths_prepare_ns, tclk_trail_ns; 1869 u32 hs_zero_cnt; 1870 u32 tclk_pre_cnt, tclk_post_cnt; 1871 1872 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1873 1874 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1875 ths_prepare_ns = max(mipi_config->ths_prepare, 1876 mipi_config->tclk_prepare); 1877 1878 /* 1879 * prepare cnt in escape clocks 1880 * this field represents a hexadecimal value with a precision 1881 * of 1.2 – i.e. the most significant bit is the integer 1882 * and the least significant 2 bits are fraction bits. 1883 * so, the field can represent a range of 0.25 to 1.75 1884 */ 1885 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1886 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1887 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1888 prepare_cnt); 1889 prepare_cnt = ICL_PREPARE_CNT_MAX; 1890 } 1891 1892 /* clk zero count in escape clocks */ 1893 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1894 ths_prepare_ns, tlpx_ns); 1895 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1896 drm_dbg_kms(&dev_priv->drm, 1897 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1898 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1899 } 1900 1901 /* trail cnt in escape clocks*/ 1902 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1903 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1904 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1905 trail_cnt); 1906 trail_cnt = ICL_TRAIL_CNT_MAX; 1907 } 1908 1909 /* tclk pre count in escape clocks */ 1910 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1911 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1912 drm_dbg_kms(&dev_priv->drm, 1913 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1914 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1915 } 1916 1917 /* tclk post count in escape clocks */ 1918 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1919 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1920 drm_dbg_kms(&dev_priv->drm, 1921 "tclk_post_cnt out of range (%d)\n", 1922 tclk_post_cnt); 1923 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1924 } 1925 1926 /* hs zero cnt in escape clocks */ 1927 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1928 ths_prepare_ns, tlpx_ns); 1929 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1930 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1931 hs_zero_cnt); 1932 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1933 } 1934 1935 /* hs exit zero cnt in escape clocks */ 1936 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1937 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1938 drm_dbg_kms(&dev_priv->drm, 1939 "exit_zero_cnt out of range (%d)\n", 1940 exit_zero_cnt); 1941 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1942 } 1943 1944 /* clock lane dphy timings */ 1945 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1946 CLK_PREPARE(prepare_cnt) | 1947 CLK_ZERO_OVERRIDE | 1948 CLK_ZERO(clk_zero_cnt) | 1949 CLK_PRE_OVERRIDE | 1950 CLK_PRE(tclk_pre_cnt) | 1951 CLK_POST_OVERRIDE | 1952 CLK_POST(tclk_post_cnt) | 1953 CLK_TRAIL_OVERRIDE | 1954 CLK_TRAIL(trail_cnt)); 1955 1956 /* data lanes dphy timings */ 1957 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1958 HS_PREPARE(prepare_cnt) | 1959 HS_ZERO_OVERRIDE | 1960 HS_ZERO(hs_zero_cnt) | 1961 HS_TRAIL_OVERRIDE | 1962 HS_TRAIL(trail_cnt) | 1963 HS_EXIT_OVERRIDE | 1964 HS_EXIT(exit_zero_cnt)); 1965 1966 intel_dsi_log_params(intel_dsi); 1967 } 1968 1969 static void icl_dsi_add_properties(struct intel_connector *connector) 1970 { 1971 u32 allowed_scalers; 1972 1973 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1974 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1975 BIT(DRM_MODE_SCALE_CENTER); 1976 1977 drm_connector_attach_scaling_mode_property(&connector->base, 1978 allowed_scalers); 1979 1980 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1981 1982 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1983 intel_dsi_get_panel_orientation(connector), 1984 connector->panel.fixed_mode->hdisplay, 1985 connector->panel.fixed_mode->vdisplay); 1986 } 1987 1988 void icl_dsi_init(struct drm_i915_private *dev_priv) 1989 { 1990 struct drm_device *dev = &dev_priv->drm; 1991 struct intel_dsi *intel_dsi; 1992 struct intel_encoder *encoder; 1993 struct intel_connector *intel_connector; 1994 struct drm_connector *connector; 1995 struct drm_display_mode *fixed_mode; 1996 enum port port; 1997 1998 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1999 return; 2000 2001 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 2002 if (!intel_dsi) 2003 return; 2004 2005 intel_connector = intel_connector_alloc(); 2006 if (!intel_connector) { 2007 kfree(intel_dsi); 2008 return; 2009 } 2010 2011 encoder = &intel_dsi->base; 2012 intel_dsi->attached_connector = intel_connector; 2013 connector = &intel_connector->base; 2014 2015 /* register DSI encoder with DRM subsystem */ 2016 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 2017 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 2018 2019 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 2020 encoder->pre_enable = gen11_dsi_pre_enable; 2021 encoder->enable = gen11_dsi_enable; 2022 encoder->disable = gen11_dsi_disable; 2023 encoder->post_disable = gen11_dsi_post_disable; 2024 encoder->port = port; 2025 encoder->get_config = gen11_dsi_get_config; 2026 encoder->sync_state = gen11_dsi_sync_state; 2027 encoder->update_pipe = intel_backlight_update; 2028 encoder->compute_config = gen11_dsi_compute_config; 2029 encoder->get_hw_state = gen11_dsi_get_hw_state; 2030 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 2031 encoder->type = INTEL_OUTPUT_DSI; 2032 encoder->cloneable = 0; 2033 encoder->pipe_mask = ~0; 2034 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2035 encoder->get_power_domains = gen11_dsi_get_power_domains; 2036 encoder->disable_clock = gen11_dsi_gate_clocks; 2037 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2038 2039 /* register DSI connector with DRM subsystem */ 2040 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 2041 DRM_MODE_CONNECTOR_DSI); 2042 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2043 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2044 connector->interlace_allowed = false; 2045 connector->doublescan_allowed = false; 2046 intel_connector->get_hw_state = intel_connector_get_hw_state; 2047 2048 /* attach connector to encoder */ 2049 intel_connector_attach_encoder(intel_connector, encoder); 2050 2051 mutex_lock(&dev->mode_config.mutex); 2052 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 2053 mutex_unlock(&dev->mode_config.mutex); 2054 2055 if (!fixed_mode) { 2056 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2057 goto err; 2058 } 2059 2060 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 2061 intel_backlight_setup(intel_connector, INVALID_PIPE); 2062 2063 if (dev_priv->vbt.dsi.config->dual_link) 2064 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2065 else 2066 intel_dsi->ports = BIT(port); 2067 2068 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 2069 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 2070 2071 for_each_dsi_port(port, intel_dsi->ports) { 2072 struct intel_dsi_host *host; 2073 2074 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2075 if (!host) 2076 goto err; 2077 2078 intel_dsi->dsi_hosts[port] = host; 2079 } 2080 2081 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2082 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2083 goto err; 2084 } 2085 2086 icl_dphy_param_init(intel_dsi); 2087 2088 icl_dsi_add_properties(intel_connector); 2089 return; 2090 2091 err: 2092 drm_connector_cleanup(connector); 2093 drm_encoder_cleanup(&encoder->base); 2094 kfree(intel_dsi); 2095 kfree(intel_connector); 2096 } 2097