xref: /openbmc/linux/arch/arm64/boot/dts/qcom/msm8996.dtsi (revision 25b892b5) 
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8996.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/soc/qcom,apr.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	chosen { };
20
21	clocks {
22		xo_board: xo-board {
23			compatible = "fixed-clock";
24			#clock-cells = <0>;
25			clock-frequency = <19200000>;
26			clock-output-names = "xo_board";
27		};
28
29		sleep_clk: sleep-clk {
30			compatible = "fixed-clock";
31			#clock-cells = <0>;
32			clock-frequency = <32764>;
33			clock-output-names = "sleep_clk";
34		};
35	};
36
37	cpus {
38		#address-cells = <2>;
39		#size-cells = <0>;
40
41		CPU0: cpu@0 {
42			device_type = "cpu";
43			compatible = "qcom,kryo";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			cpu-idle-states = <&CPU_SLEEP_0>;
47			capacity-dmips-mhz = <1024>;
48			clocks = <&kryocc 0>;
49			operating-points-v2 = <&cluster0_opp>;
50			#cooling-cells = <2>;
51			next-level-cache = <&L2_0>;
52			L2_0: l2-cache {
53			      compatible = "cache";
54			      cache-level = <2>;
55			};
56		};
57
58		CPU1: cpu@1 {
59			device_type = "cpu";
60			compatible = "qcom,kryo";
61			reg = <0x0 0x1>;
62			enable-method = "psci";
63			cpu-idle-states = <&CPU_SLEEP_0>;
64			capacity-dmips-mhz = <1024>;
65			clocks = <&kryocc 0>;
66			operating-points-v2 = <&cluster0_opp>;
67			#cooling-cells = <2>;
68			next-level-cache = <&L2_0>;
69		};
70
71		CPU2: cpu@100 {
72			device_type = "cpu";
73			compatible = "qcom,kryo";
74			reg = <0x0 0x100>;
75			enable-method = "psci";
76			cpu-idle-states = <&CPU_SLEEP_0>;
77			capacity-dmips-mhz = <1024>;
78			clocks = <&kryocc 1>;
79			operating-points-v2 = <&cluster1_opp>;
80			#cooling-cells = <2>;
81			next-level-cache = <&L2_1>;
82			L2_1: l2-cache {
83			      compatible = "cache";
84			      cache-level = <2>;
85			};
86		};
87
88		CPU3: cpu@101 {
89			device_type = "cpu";
90			compatible = "qcom,kryo";
91			reg = <0x0 0x101>;
92			enable-method = "psci";
93			cpu-idle-states = <&CPU_SLEEP_0>;
94			capacity-dmips-mhz = <1024>;
95			clocks = <&kryocc 1>;
96			operating-points-v2 = <&cluster1_opp>;
97			#cooling-cells = <2>;
98			next-level-cache = <&L2_1>;
99		};
100
101		cpu-map {
102			cluster0 {
103				core0 {
104					cpu = <&CPU0>;
105				};
106
107				core1 {
108					cpu = <&CPU1>;
109				};
110			};
111
112			cluster1 {
113				core0 {
114					cpu = <&CPU2>;
115				};
116
117				core1 {
118					cpu = <&CPU3>;
119				};
120			};
121		};
122
123		idle-states {
124			entry-method = "psci";
125
126			CPU_SLEEP_0: cpu-sleep-0 {
127				compatible = "arm,idle-state";
128				idle-state-name = "standalone-power-collapse";
129				arm,psci-suspend-param = <0x00000004>;
130				entry-latency-us = <130>;
131				exit-latency-us = <80>;
132				min-residency-us = <300>;
133			};
134		};
135	};
136
137	cluster0_opp: opp_table0 {
138		compatible = "operating-points-v2-kryo-cpu";
139		nvmem-cells = <&speedbin_efuse>;
140		opp-shared;
141
142		/* Nominal fmax for now */
143		opp-307200000 {
144			opp-hz = /bits/ 64 <307200000>;
145			opp-supported-hw = <0x77>;
146			clock-latency-ns = <200000>;
147		};
148		opp-422400000 {
149			opp-hz = /bits/ 64 <422400000>;
150			opp-supported-hw = <0x77>;
151			clock-latency-ns = <200000>;
152		};
153		opp-480000000 {
154			opp-hz = /bits/ 64 <480000000>;
155			opp-supported-hw = <0x77>;
156			clock-latency-ns = <200000>;
157		};
158		opp-556800000 {
159			opp-hz = /bits/ 64 <556800000>;
160			opp-supported-hw = <0x77>;
161			clock-latency-ns = <200000>;
162		};
163		opp-652800000 {
164			opp-hz = /bits/ 64 <652800000>;
165			opp-supported-hw = <0x77>;
166			clock-latency-ns = <200000>;
167		};
168		opp-729600000 {
169			opp-hz = /bits/ 64 <729600000>;
170			opp-supported-hw = <0x77>;
171			clock-latency-ns = <200000>;
172		};
173		opp-844800000 {
174			opp-hz = /bits/ 64 <844800000>;
175			opp-supported-hw = <0x77>;
176			clock-latency-ns = <200000>;
177		};
178		opp-960000000 {
179			opp-hz = /bits/ 64 <960000000>;
180			opp-supported-hw = <0x77>;
181			clock-latency-ns = <200000>;
182		};
183		opp-1036800000 {
184			opp-hz = /bits/ 64 <1036800000>;
185			opp-supported-hw = <0x77>;
186			clock-latency-ns = <200000>;
187		};
188		opp-1113600000 {
189			opp-hz = /bits/ 64 <1113600000>;
190			opp-supported-hw = <0x77>;
191			clock-latency-ns = <200000>;
192		};
193		opp-1190400000 {
194			opp-hz = /bits/ 64 <1190400000>;
195			opp-supported-hw = <0x77>;
196			clock-latency-ns = <200000>;
197		};
198		opp-1228800000 {
199			opp-hz = /bits/ 64 <1228800000>;
200			opp-supported-hw = <0x77>;
201			clock-latency-ns = <200000>;
202		};
203		opp-1324800000 {
204			opp-hz = /bits/ 64 <1324800000>;
205			opp-supported-hw = <0x77>;
206			clock-latency-ns = <200000>;
207		};
208		opp-1401600000 {
209			opp-hz = /bits/ 64 <1401600000>;
210			opp-supported-hw = <0x77>;
211			clock-latency-ns = <200000>;
212		};
213		opp-1478400000 {
214			opp-hz = /bits/ 64 <1478400000>;
215			opp-supported-hw = <0x77>;
216			clock-latency-ns = <200000>;
217		};
218		opp-1593600000 {
219			opp-hz = /bits/ 64 <1593600000>;
220			opp-supported-hw = <0x77>;
221			clock-latency-ns = <200000>;
222		};
223	};
224
225	cluster1_opp: opp_table1 {
226		compatible = "operating-points-v2-kryo-cpu";
227		nvmem-cells = <&speedbin_efuse>;
228		opp-shared;
229
230		/* Nominal fmax for now */
231		opp-307200000 {
232			opp-hz = /bits/ 64 <307200000>;
233			opp-supported-hw = <0x77>;
234			clock-latency-ns = <200000>;
235		};
236		opp-403200000 {
237			opp-hz = /bits/ 64 <403200000>;
238			opp-supported-hw = <0x77>;
239			clock-latency-ns = <200000>;
240		};
241		opp-480000000 {
242			opp-hz = /bits/ 64 <480000000>;
243			opp-supported-hw = <0x77>;
244			clock-latency-ns = <200000>;
245		};
246		opp-556800000 {
247			opp-hz = /bits/ 64 <556800000>;
248			opp-supported-hw = <0x77>;
249			clock-latency-ns = <200000>;
250		};
251		opp-652800000 {
252			opp-hz = /bits/ 64 <652800000>;
253			opp-supported-hw = <0x77>;
254			clock-latency-ns = <200000>;
255		};
256		opp-729600000 {
257			opp-hz = /bits/ 64 <729600000>;
258			opp-supported-hw = <0x77>;
259			clock-latency-ns = <200000>;
260		};
261		opp-806400000 {
262			opp-hz = /bits/ 64 <806400000>;
263			opp-supported-hw = <0x77>;
264			clock-latency-ns = <200000>;
265		};
266		opp-883200000 {
267			opp-hz = /bits/ 64 <883200000>;
268			opp-supported-hw = <0x77>;
269			clock-latency-ns = <200000>;
270		};
271		opp-940800000 {
272			opp-hz = /bits/ 64 <940800000>;
273			opp-supported-hw = <0x77>;
274			clock-latency-ns = <200000>;
275		};
276		opp-1036800000 {
277			opp-hz = /bits/ 64 <1036800000>;
278			opp-supported-hw = <0x77>;
279			clock-latency-ns = <200000>;
280		};
281		opp-1113600000 {
282			opp-hz = /bits/ 64 <1113600000>;
283			opp-supported-hw = <0x77>;
284			clock-latency-ns = <200000>;
285		};
286		opp-1190400000 {
287			opp-hz = /bits/ 64 <1190400000>;
288			opp-supported-hw = <0x77>;
289			clock-latency-ns = <200000>;
290		};
291		opp-1248000000 {
292			opp-hz = /bits/ 64 <1248000000>;
293			opp-supported-hw = <0x77>;
294			clock-latency-ns = <200000>;
295		};
296		opp-1324800000 {
297			opp-hz = /bits/ 64 <1324800000>;
298			opp-supported-hw = <0x77>;
299			clock-latency-ns = <200000>;
300		};
301		opp-1401600000 {
302			opp-hz = /bits/ 64 <1401600000>;
303			opp-supported-hw = <0x77>;
304			clock-latency-ns = <200000>;
305		};
306		opp-1478400000 {
307			opp-hz = /bits/ 64 <1478400000>;
308			opp-supported-hw = <0x77>;
309			clock-latency-ns = <200000>;
310		};
311		opp-1555200000 {
312			opp-hz = /bits/ 64 <1555200000>;
313			opp-supported-hw = <0x77>;
314			clock-latency-ns = <200000>;
315		};
316		opp-1632000000 {
317			opp-hz = /bits/ 64 <1632000000>;
318			opp-supported-hw = <0x77>;
319			clock-latency-ns = <200000>;
320		};
321		opp-1708800000 {
322			opp-hz = /bits/ 64 <1708800000>;
323			opp-supported-hw = <0x77>;
324			clock-latency-ns = <200000>;
325		};
326		opp-1785600000 {
327			opp-hz = /bits/ 64 <1785600000>;
328			opp-supported-hw = <0x77>;
329			clock-latency-ns = <200000>;
330		};
331		opp-1824000000 {
332			opp-hz = /bits/ 64 <1824000000>;
333			opp-supported-hw = <0x77>;
334			clock-latency-ns = <200000>;
335		};
336		opp-1920000000 {
337			opp-hz = /bits/ 64 <1920000000>;
338			opp-supported-hw = <0x77>;
339			clock-latency-ns = <200000>;
340		};
341		opp-1996800000 {
342			opp-hz = /bits/ 64 <1996800000>;
343			opp-supported-hw = <0x77>;
344			clock-latency-ns = <200000>;
345		};
346		opp-2073600000 {
347			opp-hz = /bits/ 64 <2073600000>;
348			opp-supported-hw = <0x77>;
349			clock-latency-ns = <200000>;
350		};
351		opp-2150400000 {
352			opp-hz = /bits/ 64 <2150400000>;
353			opp-supported-hw = <0x77>;
354			clock-latency-ns = <200000>;
355		};
356	};
357
358	firmware {
359		scm {
360			compatible = "qcom,scm-msm8996";
361			qcom,dload-mode = <&tcsr 0x13000>;
362		};
363	};
364
365	tcsr_mutex: hwlock {
366		compatible = "qcom,tcsr-mutex";
367		syscon = <&tcsr_mutex_regs 0 0x1000>;
368		#hwlock-cells = <1>;
369	};
370
371	memory@80000000 {
372		device_type = "memory";
373		/* We expect the bootloader to fill in the reg */
374		reg = <0x0 0x80000000 0x0 0x0>;
375	};
376
377	psci {
378		compatible = "arm,psci-1.0";
379		method = "smc";
380	};
381
382	reserved-memory {
383		#address-cells = <2>;
384		#size-cells = <2>;
385		ranges;
386
387		mba_region: mba@91500000 {
388			reg = <0x0 0x91500000 0x0 0x200000>;
389			no-map;
390		};
391
392		slpi_region: slpi@90b00000 {
393			reg = <0x0 0x90b00000 0x0 0xa00000>;
394			no-map;
395		};
396
397		venus_region: venus@90400000 {
398			reg = <0x0 0x90400000 0x0 0x700000>;
399			no-map;
400		};
401
402		adsp_region: adsp@8ea00000 {
403			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
404			no-map;
405		};
406
407		mpss_region: mpss@88800000 {
408			reg = <0x0 0x88800000 0x0 0x6200000>;
409			no-map;
410		};
411
412		smem_mem: smem-mem@86000000 {
413			reg = <0x0 0x86000000 0x0 0x200000>;
414			no-map;
415		};
416
417		memory@85800000 {
418			reg = <0x0 0x85800000 0x0 0x800000>;
419			no-map;
420		};
421
422		memory@86200000 {
423			reg = <0x0 0x86200000 0x0 0x2600000>;
424			no-map;
425		};
426
427		rmtfs@86700000 {
428			compatible = "qcom,rmtfs-mem";
429
430			size = <0x0 0x200000>;
431			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
432			no-map;
433
434			qcom,client-id = <1>;
435			qcom,vmid = <15>;
436		};
437
438		zap_shader_region: gpu@8f200000 {
439			compatible = "shared-dma-pool";
440			reg = <0x0 0x90b00000 0x0 0xa00000>;
441			no-map;
442		};
443	};
444
445	rpm-glink {
446		compatible = "qcom,glink-rpm";
447
448		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
449
450		qcom,rpm-msg-ram = <&rpm_msg_ram>;
451
452		mboxes = <&apcs_glb 0>;
453
454		rpm_requests: rpm-requests {
455			compatible = "qcom,rpm-msm8996";
456			qcom,glink-channels = "rpm_requests";
457
458			rpmcc: qcom,rpmcc {
459				compatible = "qcom,rpmcc-msm8996";
460				#clock-cells = <1>;
461			};
462
463			rpmpd: power-controller {
464				compatible = "qcom,msm8996-rpmpd";
465				#power-domain-cells = <1>;
466				operating-points-v2 = <&rpmpd_opp_table>;
467
468				rpmpd_opp_table: opp-table {
469					compatible = "operating-points-v2";
470
471					rpmpd_opp1: opp1 {
472						opp-level = <1>;
473					};
474
475					rpmpd_opp2: opp2 {
476						opp-level = <2>;
477					};
478
479					rpmpd_opp3: opp3 {
480						opp-level = <3>;
481					};
482
483					rpmpd_opp4: opp4 {
484						opp-level = <4>;
485					};
486
487					rpmpd_opp5: opp5 {
488						opp-level = <5>;
489					};
490
491					rpmpd_opp6: opp6 {
492						opp-level = <6>;
493					};
494				};
495			};
496		};
497	};
498
499	smem {
500		compatible = "qcom,smem";
501		memory-region = <&smem_mem>;
502		hwlocks = <&tcsr_mutex 3>;
503	};
504
505	smp2p-adsp {
506		compatible = "qcom,smp2p";
507		qcom,smem = <443>, <429>;
508
509		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
510
511		mboxes = <&apcs_glb 10>;
512
513		qcom,local-pid = <0>;
514		qcom,remote-pid = <2>;
515
516		smp2p_adsp_out: master-kernel {
517			qcom,entry-name = "master-kernel";
518			#qcom,smem-state-cells = <1>;
519		};
520
521		smp2p_adsp_in: slave-kernel {
522			qcom,entry-name = "slave-kernel";
523
524			interrupt-controller;
525			#interrupt-cells = <2>;
526		};
527	};
528
529	smp2p-modem {
530		compatible = "qcom,smp2p";
531		qcom,smem = <435>, <428>;
532
533		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
534
535		mboxes = <&apcs_glb 14>;
536
537		qcom,local-pid = <0>;
538		qcom,remote-pid = <1>;
539
540		modem_smp2p_out: master-kernel {
541			qcom,entry-name = "master-kernel";
542			#qcom,smem-state-cells = <1>;
543		};
544
545		modem_smp2p_in: slave-kernel {
546			qcom,entry-name = "slave-kernel";
547
548			interrupt-controller;
549			#interrupt-cells = <2>;
550		};
551	};
552
553	smp2p-slpi {
554		compatible = "qcom,smp2p";
555		qcom,smem = <481>, <430>;
556
557		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
558
559		mboxes = <&apcs_glb 26>;
560
561		qcom,local-pid = <0>;
562		qcom,remote-pid = <3>;
563
564		smp2p_slpi_in: slave-kernel {
565			qcom,entry-name = "slave-kernel";
566			interrupt-controller;
567			#interrupt-cells = <2>;
568		};
569
570		smp2p_slpi_out: master-kernel {
571			qcom,entry-name = "master-kernel";
572			#qcom,smem-state-cells = <1>;
573		};
574	};
575
576	soc: soc {
577		#address-cells = <1>;
578		#size-cells = <1>;
579		ranges = <0 0 0 0xffffffff>;
580		compatible = "simple-bus";
581
582		pcie_phy: phy@34000 {
583			compatible = "qcom,msm8996-qmp-pcie-phy";
584			reg = <0x00034000 0x488>;
585			#clock-cells = <1>;
586			#address-cells = <1>;
587			#size-cells = <1>;
588			ranges;
589
590			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
591				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
592				<&gcc GCC_PCIE_CLKREF_CLK>;
593			clock-names = "aux", "cfg_ahb", "ref";
594
595			resets = <&gcc GCC_PCIE_PHY_BCR>,
596				<&gcc GCC_PCIE_PHY_COM_BCR>,
597				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
598			reset-names = "phy", "common", "cfg";
599			status = "disabled";
600
601			pciephy_0: lane@35000 {
602				reg = <0x00035000 0x130>,
603				      <0x00035200 0x200>,
604				      <0x00035400 0x1dc>;
605				#phy-cells = <0>;
606
607				clock-output-names = "pcie_0_pipe_clk_src";
608				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
609				clock-names = "pipe0";
610				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
611				reset-names = "lane0";
612			};
613
614			pciephy_1: lane@36000 {
615				reg = <0x00036000 0x130>,
616				      <0x00036200 0x200>,
617				      <0x00036400 0x1dc>;
618				#phy-cells = <0>;
619
620				clock-output-names = "pcie_1_pipe_clk_src";
621				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
622				clock-names = "pipe1";
623				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
624				reset-names = "lane1";
625			};
626
627			pciephy_2: lane@37000 {
628				reg = <0x00037000 0x130>,
629				      <0x00037200 0x200>,
630				      <0x00037400 0x1dc>;
631				#phy-cells = <0>;
632
633				clock-output-names = "pcie_2_pipe_clk_src";
634				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
635				clock-names = "pipe2";
636				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
637				reset-names = "lane2";
638			};
639		};
640
641		rpm_msg_ram: memory@68000 {
642			compatible = "qcom,rpm-msg-ram";
643			reg = <0x00068000 0x6000>;
644		};
645
646		qfprom@74000 {
647			compatible = "qcom,qfprom";
648			reg = <0x00074000 0x8ff>;
649			#address-cells = <1>;
650			#size-cells = <1>;
651
652			qusb2p_hstx_trim: hstx_trim@24e {
653				reg = <0x24e 0x2>;
654				bits = <5 4>;
655			};
656
657			qusb2s_hstx_trim: hstx_trim@24f {
658				reg = <0x24f 0x1>;
659				bits = <1 4>;
660			};
661
662			speedbin_efuse: speedbin@133 {
663				reg = <0x133 0x1>;
664				bits = <5 3>;
665			};
666		};
667
668		rng: rng@83000 {
669			compatible = "qcom,prng-ee";
670			reg = <0x00083000 0x1000>;
671			clocks = <&gcc GCC_PRNG_AHB_CLK>;
672			clock-names = "core";
673		};
674
675		gcc: clock-controller@300000 {
676			compatible = "qcom,gcc-msm8996";
677			#clock-cells = <1>;
678			#reset-cells = <1>;
679			#power-domain-cells = <1>;
680			reg = <0x00300000 0x90000>;
681
682			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
683			clock-names = "cxo2";
684		};
685
686		tsens0: thermal-sensor@4a9000 {
687			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
688			reg = <0x004a9000 0x1000>, /* TM */
689			      <0x004a8000 0x1000>; /* SROT */
690			#qcom,sensors = <13>;
691			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
692				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
693			interrupt-names = "uplow", "critical";
694			#thermal-sensor-cells = <1>;
695		};
696
697		tsens1: thermal-sensor@4ad000 {
698			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
699			reg = <0x004ad000 0x1000>, /* TM */
700			      <0x004ac000 0x1000>; /* SROT */
701			#qcom,sensors = <8>;
702			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
703				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
704			interrupt-names = "uplow", "critical";
705			#thermal-sensor-cells = <1>;
706		};
707
708		tcsr_mutex_regs: syscon@740000 {
709			compatible = "syscon";
710			reg = <0x00740000 0x40000>;
711		};
712
713		tcsr: syscon@7a0000 {
714			compatible = "qcom,tcsr-msm8996", "syscon";
715			reg = <0x007a0000 0x18000>;
716		};
717
718		mmcc: clock-controller@8c0000 {
719			compatible = "qcom,mmcc-msm8996";
720			#clock-cells = <1>;
721			#reset-cells = <1>;
722			#power-domain-cells = <1>;
723			reg = <0x008c0000 0x40000>;
724			assigned-clocks = <&mmcc MMPLL9_PLL>,
725					  <&mmcc MMPLL1_PLL>,
726					  <&mmcc MMPLL3_PLL>,
727					  <&mmcc MMPLL4_PLL>,
728					  <&mmcc MMPLL5_PLL>;
729			assigned-clock-rates = <624000000>,
730					       <810000000>,
731					       <980000000>,
732					       <960000000>,
733					       <825000000>;
734		};
735
736		mdss: mdss@900000 {
737			compatible = "qcom,mdss";
738
739			reg = <0x00900000 0x1000>,
740			      <0x009b0000 0x1040>,
741			      <0x009b8000 0x1040>;
742			reg-names = "mdss_phys",
743				    "vbif_phys",
744				    "vbif_nrt_phys";
745
746			power-domains = <&mmcc MDSS_GDSC>;
747			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
748
749			interrupt-controller;
750			#interrupt-cells = <1>;
751
752			clocks = <&mmcc MDSS_AHB_CLK>;
753			clock-names = "iface";
754
755			#address-cells = <1>;
756			#size-cells = <1>;
757			ranges;
758
759			status = "disabled";
760
761			mdp: mdp@901000 {
762				compatible = "qcom,mdp5";
763				reg = <0x00901000 0x90000>;
764				reg-names = "mdp_phys";
765
766				interrupt-parent = <&mdss>;
767				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
768
769				clocks = <&mmcc MDSS_AHB_CLK>,
770					 <&mmcc MDSS_AXI_CLK>,
771					 <&mmcc MDSS_MDP_CLK>,
772					 <&mmcc SMMU_MDP_AXI_CLK>,
773					 <&mmcc MDSS_VSYNC_CLK>;
774				clock-names = "iface",
775					      "bus",
776					      "core",
777					      "iommu",
778					      "vsync";
779
780				iommus = <&mdp_smmu 0>;
781
782				assigned-clocks = <&mmcc MDSS_MDP_CLK>,
783					 <&mmcc MDSS_VSYNC_CLK>;
784				assigned-clock-rates = <300000000>,
785					 <19200000>;
786
787				ports {
788					#address-cells = <1>;
789					#size-cells = <0>;
790
791					port@0 {
792						reg = <0>;
793						mdp5_intf3_out: endpoint {
794							remote-endpoint = <&hdmi_in>;
795						};
796					};
797
798					port@1 {
799						reg = <1>;
800						mdp5_intf1_out: endpoint {
801							remote-endpoint = <&dsi0_in>;
802						};
803					};
804				};
805			};
806
807			dsi0: dsi@994000 {
808				compatible = "qcom,mdss-dsi-ctrl";
809				reg = <0x00994000 0x400>;
810				reg-names = "dsi_ctrl";
811
812				interrupt-parent = <&mdss>;
813				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
814
815				clocks = <&mmcc MDSS_MDP_CLK>,
816					 <&mmcc MDSS_BYTE0_CLK>,
817					 <&mmcc MDSS_AHB_CLK>,
818					 <&mmcc MDSS_AXI_CLK>,
819					 <&mmcc MMSS_MISC_AHB_CLK>,
820					 <&mmcc MDSS_PCLK0_CLK>,
821					 <&mmcc MDSS_ESC0_CLK>;
822				clock-names = "mdp_core",
823					      "byte",
824					      "iface",
825					      "bus",
826					      "core_mmss",
827					      "pixel",
828					      "core";
829
830				phys = <&dsi0_phy>;
831				phy-names = "dsi";
832				status = "disabled";
833
834				#address-cells = <1>;
835				#size-cells = <0>;
836
837				ports {
838					#address-cells = <1>;
839					#size-cells = <0>;
840
841					port@0 {
842						reg = <0>;
843						dsi0_in: endpoint {
844							remote-endpoint = <&mdp5_intf1_out>;
845						};
846					};
847
848					port@1 {
849						reg = <1>;
850						dsi0_out: endpoint {
851						};
852					};
853				};
854			};
855
856			dsi0_phy: dsi-phy@994400 {
857				compatible = "qcom,dsi-phy-14nm";
858				reg = <0x00994400 0x100>,
859				      <0x00994500 0x300>,
860				      <0x00994800 0x188>;
861				reg-names = "dsi_phy",
862					    "dsi_phy_lane",
863					    "dsi_pll";
864
865				#clock-cells = <1>;
866				#phy-cells = <0>;
867
868				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
869				clock-names = "iface", "ref";
870				status = "disabled";
871			};
872
873			hdmi: hdmi-tx@9a0000 {
874				compatible = "qcom,hdmi-tx-8996";
875				reg =	<0x009a0000 0x50c>,
876					<0x00070000 0x6158>,
877					<0x009e0000 0xfff>;
878				reg-names = "core_physical",
879					    "qfprom_physical",
880					    "hdcp_physical";
881
882				interrupt-parent = <&mdss>;
883				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
884
885				clocks = <&mmcc MDSS_MDP_CLK>,
886					 <&mmcc MDSS_AHB_CLK>,
887					 <&mmcc MDSS_HDMI_CLK>,
888					 <&mmcc MDSS_HDMI_AHB_CLK>,
889					 <&mmcc MDSS_EXTPCLK_CLK>;
890				clock-names =
891					"mdp_core",
892					"iface",
893					"core",
894					"alt_iface",
895					"extp";
896
897				phys = <&hdmi_phy>;
898				phy-names = "hdmi_phy";
899				#sound-dai-cells = <1>;
900
901				status = "disabled";
902
903				ports {
904					#address-cells = <1>;
905					#size-cells = <0>;
906
907					port@0 {
908						reg = <0>;
909						hdmi_in: endpoint {
910							remote-endpoint = <&mdp5_intf3_out>;
911						};
912					};
913				};
914			};
915
916			hdmi_phy: hdmi-phy@9a0600 {
917				#phy-cells = <0>;
918				compatible = "qcom,hdmi-phy-8996";
919				reg = <0x009a0600 0x1c4>,
920				      <0x009a0a00 0x124>,
921				      <0x009a0c00 0x124>,
922				      <0x009a0e00 0x124>,
923				      <0x009a1000 0x124>,
924				      <0x009a1200 0x0c8>;
925				reg-names = "hdmi_pll",
926					    "hdmi_tx_l0",
927					    "hdmi_tx_l1",
928					    "hdmi_tx_l2",
929					    "hdmi_tx_l3",
930					    "hdmi_phy";
931
932				clocks = <&mmcc MDSS_AHB_CLK>,
933					 <&gcc GCC_HDMI_CLKREF_CLK>;
934				clock-names = "iface",
935					      "ref";
936
937				status = "disabled";
938			};
939		};
940
941		gpu: gpu@b00000 {
942			compatible = "qcom,adreno-530.2", "qcom,adreno";
943			#stream-id-cells = <16>;
944
945			reg = <0x00b00000 0x3f000>;
946			reg-names = "kgsl_3d0_reg_memory";
947
948			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
949
950			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
951				<&mmcc GPU_AHB_CLK>,
952				<&mmcc GPU_GX_RBBMTIMER_CLK>,
953				<&gcc GCC_BIMC_GFX_CLK>,
954				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
955
956			clock-names = "core",
957				"iface",
958				"rbbmtimer",
959				"mem",
960				"mem_iface";
961
962			power-domains = <&mmcc GPU_GX_GDSC>;
963			iommus = <&adreno_smmu 0>;
964
965			nvmem-cells = <&speedbin_efuse>;
966			nvmem-cell-names = "speed_bin";
967
968			qcom,gpu-quirk-two-pass-use-wfi;
969			qcom,gpu-quirk-fault-detect-mask;
970
971			operating-points-v2 = <&gpu_opp_table>;
972
973			status = "disabled";
974
975			#cooling-cells = <2>;
976
977			gpu_opp_table: opp-table {
978				compatible  ="operating-points-v2";
979
980				/*
981				 * 624Mhz and 560Mhz are only available on speed
982				 * bin (1 << 0). All the rest are available on
983				 * all bins of the hardware
984				 */
985				opp-624000000 {
986					opp-hz = /bits/ 64 <624000000>;
987					opp-supported-hw = <0x01>;
988				};
989				opp-560000000 {
990					opp-hz = /bits/ 64 <560000000>;
991					opp-supported-hw = <0x01>;
992				};
993				opp-510000000 {
994					opp-hz = /bits/ 64 <510000000>;
995					opp-supported-hw = <0xFF>;
996				};
997				opp-401800000 {
998					opp-hz = /bits/ 64 <401800000>;
999					opp-supported-hw = <0xFF>;
1000				};
1001				opp-315000000 {
1002					opp-hz = /bits/ 64 <315000000>;
1003					opp-supported-hw = <0xFF>;
1004				};
1005				opp-214000000 {
1006					opp-hz = /bits/ 64 <214000000>;
1007					opp-supported-hw = <0xFF>;
1008				};
1009				opp-133000000 {
1010					opp-hz = /bits/ 64 <133000000>;
1011					opp-supported-hw = <0xFF>;
1012				};
1013			};
1014
1015			zap-shader {
1016				memory-region = <&zap_shader_region>;
1017			};
1018		};
1019
1020		tlmm: pinctrl@1010000 {
1021			compatible = "qcom,msm8996-pinctrl";
1022			reg = <0x01010000 0x300000>;
1023			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1024			gpio-controller;
1025			gpio-ranges = <&tlmm 0 0 150>;
1026			#gpio-cells = <2>;
1027			interrupt-controller;
1028			#interrupt-cells = <2>;
1029
1030			blsp1_spi1_default: blsp1-spi1-default {
1031				spi {
1032					pins = "gpio0", "gpio1", "gpio3";
1033					function = "blsp_spi1";
1034					drive-strength = <12>;
1035					bias-disable;
1036				};
1037
1038				cs {
1039					pins = "gpio2";
1040					function = "gpio";
1041					drive-strength = <16>;
1042					bias-disable;
1043					output-high;
1044				};
1045			};
1046
1047			blsp1_spi1_sleep: blsp1-spi1-sleep {
1048				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1049				function = "gpio";
1050				drive-strength = <2>;
1051				bias-pull-down;
1052			};
1053
1054			blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1055				pins = "gpio4", "gpio5";
1056				function = "blsp_uart8";
1057				drive-strength = <16>;
1058				bias-disable;
1059			};
1060
1061			blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1062				pins = "gpio4", "gpio5";
1063				function = "gpio";
1064				drive-strength = <2>;
1065				bias-disable;
1066			};
1067
1068			blsp2_i2c2_default: blsp2-i2c2 {
1069				pins = "gpio6", "gpio7";
1070				function = "blsp_i2c8";
1071				drive-strength = <16>;
1072				bias-disable;
1073			};
1074
1075			blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1076				pins = "gpio6", "gpio7";
1077				function = "gpio";
1078				drive-strength = <2>;
1079				bias-disable;
1080			};
1081
1082			cci0_default: cci0-default {
1083				pins = "gpio17", "gpio18";
1084				function = "cci_i2c";
1085				drive-strength = <16>;
1086				bias-disable;
1087			};
1088
1089			camera0_state_on:
1090			camera_rear_default: camera-rear-default {
1091				camera0_mclk: mclk0 {
1092					pins = "gpio13";
1093					function = "cam_mclk";
1094					drive-strength = <16>;
1095					bias-disable;
1096				};
1097
1098				camera0_rst: rst {
1099					pins = "gpio25";
1100					function = "gpio";
1101					drive-strength = <16>;
1102					bias-disable;
1103				};
1104
1105				camera0_pwdn: pwdn {
1106					pins = "gpio26";
1107					function = "gpio";
1108					drive-strength = <16>;
1109					bias-disable;
1110				};
1111			};
1112
1113			cci1_default: cci1-default {
1114				pins = "gpio19", "gpio20";
1115				function = "cci_i2c";
1116				drive-strength = <16>;
1117				bias-disable;
1118			};
1119
1120			camera1_state_on:
1121			camera_board_default: camera-board-default {
1122				mclk1 {
1123					pins = "gpio14";
1124					function = "cam_mclk";
1125					drive-strength = <16>;
1126					bias-disable;
1127				};
1128
1129				pwdn {
1130					pins = "gpio98";
1131					function = "gpio";
1132					drive-strength = <16>;
1133					bias-disable;
1134				};
1135
1136				rst {
1137					pins = "gpio104";
1138					function = "gpio";
1139					drive-strength = <16>;
1140					bias-disable;
1141				};
1142			};
1143
1144			camera2_state_on:
1145			camera_front_default: camera-front-default {
1146				camera2_mclk: mclk2 {
1147					pins = "gpio15";
1148					function = "cam_mclk";
1149					drive-strength = <16>;
1150					bias-disable;
1151				};
1152
1153				camera2_rst: rst {
1154					pins = "gpio23";
1155					function = "gpio";
1156					drive-strength = <16>;
1157					bias-disable;
1158				};
1159
1160				pwdn {
1161					pins = "gpio133";
1162					function = "gpio";
1163					drive-strength = <16>;
1164					bias-disable;
1165				};
1166			};
1167
1168			pcie0_state_on: pcie0-state-on {
1169				perst {
1170					pins = "gpio35";
1171					function = "gpio";
1172					drive-strength = <2>;
1173					bias-pull-down;
1174				};
1175
1176				clkreq {
1177					pins = "gpio36";
1178					function = "pci_e0";
1179					drive-strength = <2>;
1180					bias-pull-up;
1181				};
1182
1183				wake {
1184					pins = "gpio37";
1185					function = "gpio";
1186					drive-strength = <2>;
1187					bias-pull-up;
1188				};
1189			};
1190
1191			pcie0_state_off: pcie0-state-off {
1192				perst {
1193					pins = "gpio35";
1194					function = "gpio";
1195					drive-strength = <2>;
1196					bias-pull-down;
1197				};
1198
1199				clkreq {
1200					pins = "gpio36";
1201					function = "gpio";
1202					drive-strength = <2>;
1203					bias-disable;
1204				};
1205
1206				wake {
1207					pins = "gpio37";
1208					function = "gpio";
1209					drive-strength = <2>;
1210					bias-disable;
1211				};
1212			};
1213
1214			blsp1_uart2_default: blsp1-uart2-default {
1215				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1216				function = "blsp_uart2";
1217				drive-strength = <16>;
1218				bias-disable;
1219			};
1220
1221			blsp1_uart2_sleep: blsp1-uart2-sleep {
1222				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1223				function = "gpio";
1224				drive-strength = <2>;
1225				bias-disable;
1226			};
1227
1228			blsp1_i2c3_default: blsp1-i2c2-default {
1229				pins = "gpio47", "gpio48";
1230				function = "blsp_i2c3";
1231				drive-strength = <16>;
1232				bias-disable = <0>;
1233			};
1234
1235			blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1236				pins = "gpio47", "gpio48";
1237				function = "gpio";
1238				drive-strength = <2>;
1239				bias-disable = <0>;
1240			};
1241
1242			blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1243				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1244				function = "blsp_uart9";
1245				drive-strength = <16>;
1246				bias-disable;
1247			};
1248
1249			blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1250				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1251				function = "blsp_uart9";
1252				drive-strength = <2>;
1253				bias-disable;
1254			};
1255
1256			blsp2_i2c3_default: blsp2-i2c3 {
1257				pins = "gpio51", "gpio52";
1258				function = "blsp_i2c9";
1259				drive-strength = <16>;
1260				bias-disable;
1261			};
1262
1263			blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1264				pins = "gpio51", "gpio52";
1265				function = "gpio";
1266				drive-strength = <2>;
1267				bias-disable;
1268			};
1269
1270			wcd_intr_default: wcd-intr-default{
1271				pins = "gpio54";
1272				function = "gpio";
1273				drive-strength = <2>;
1274				bias-pull-down;
1275				input-enable;
1276			};
1277
1278			blsp2_i2c1_default: blsp2-i2c1 {
1279				pins = "gpio55", "gpio56";
1280				function = "blsp_i2c7";
1281				drive-strength = <16>;
1282				bias-disable;
1283			};
1284
1285			blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1286				pins = "gpio55", "gpio56";
1287				function = "gpio";
1288				drive-strength = <2>;
1289				bias-disable;
1290			};
1291
1292			blsp2_i2c5_default: blsp2-i2c5 {
1293				pins = "gpio60", "gpio61";
1294				function = "blsp_i2c11";
1295				drive-strength = <2>;
1296				bias-disable;
1297			};
1298
1299			/* Sleep state for BLSP2_I2C5 is missing.. */
1300
1301			cdc_reset_active: cdc-reset-active {
1302				pins = "gpio64";
1303				function = "gpio";
1304				drive-strength = <16>;
1305				bias-pull-down;
1306				output-high;
1307			};
1308
1309			cdc_reset_sleep: cdc-reset-sleep {
1310				pins = "gpio64";
1311				function = "gpio";
1312				drive-strength = <16>;
1313				bias-disable;
1314				output-low;
1315			};
1316
1317			blsp2_spi6_default: blsp2-spi5-default {
1318				spi {
1319					pins = "gpio85", "gpio86", "gpio88";
1320					function = "blsp_spi12";
1321					drive-strength = <12>;
1322					bias-disable;
1323				};
1324
1325				cs {
1326					pins = "gpio87";
1327					function = "gpio";
1328					drive-strength = <16>;
1329					bias-disable;
1330					output-high;
1331				};
1332			};
1333
1334			blsp2_spi6_sleep: blsp2-spi5-sleep {
1335				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1336				function = "gpio";
1337				drive-strength = <2>;
1338				bias-pull-down;
1339			};
1340
1341			blsp2_i2c6_default: blsp2-i2c6 {
1342				pins = "gpio87", "gpio88";
1343				function = "blsp_i2c12";
1344				drive-strength = <16>;
1345				bias-disable;
1346			};
1347
1348			blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1349				pins = "gpio87", "gpio88";
1350				function = "gpio";
1351				drive-strength = <2>;
1352				bias-disable;
1353			};
1354
1355			pcie1_state_on: pcie1-state-on {
1356				perst {
1357					pins = "gpio130";
1358					function = "gpio";
1359					drive-strength = <2>;
1360					bias-pull-down;
1361				};
1362
1363				clkreq {
1364					pins = "gpio131";
1365					function = "pci_e1";
1366					drive-strength = <2>;
1367					bias-pull-up;
1368				};
1369
1370				wake {
1371					pins = "gpio132";
1372					function = "gpio";
1373					drive-strength = <2>;
1374					bias-pull-down;
1375				};
1376			};
1377
1378			pcie1_state_off: pcie1-state-off {
1379				/* Perst is missing? */
1380				clkreq {
1381					pins = "gpio131";
1382					function = "gpio";
1383					drive-strength = <2>;
1384					bias-disable;
1385				};
1386
1387				wake {
1388					pins = "gpio132";
1389					function = "gpio";
1390					drive-strength = <2>;
1391					bias-disable;
1392				};
1393			};
1394
1395			pcie2_state_on: pcie2-state-on {
1396				perst {
1397					pins = "gpio114";
1398					function = "gpio";
1399					drive-strength = <2>;
1400					bias-pull-down;
1401				};
1402
1403				clkreq {
1404					pins = "gpio115";
1405					function = "pci_e2";
1406					drive-strength = <2>;
1407					bias-pull-up;
1408				};
1409
1410				wake {
1411					pins = "gpio116";
1412					function = "gpio";
1413					drive-strength = <2>;
1414					bias-pull-down;
1415				};
1416			};
1417
1418			pcie2_state_off: pcie2-state-off {
1419				/* Perst is missing? */
1420				clkreq {
1421					pins = "gpio115";
1422					function = "gpio";
1423					drive-strength = <2>;
1424					bias-disable;
1425				};
1426
1427				wake {
1428					pins = "gpio116";
1429					function = "gpio";
1430					drive-strength = <2>;
1431					bias-disable;
1432				};
1433			};
1434
1435			sdc1_state_on: sdc1-state-on {
1436				clk {
1437					pins = "sdc1_clk";
1438					bias-disable;
1439					drive-strength = <16>;
1440				};
1441
1442				cmd {
1443					pins = "sdc1_cmd";
1444					bias-pull-up;
1445					drive-strength = <10>;
1446				};
1447
1448				data {
1449					pins = "sdc1_data";
1450					bias-pull-up;
1451					drive-strength = <10>;
1452				};
1453
1454				rclk {
1455					pins = "sdc1_rclk";
1456					bias-pull-down;
1457				};
1458			};
1459
1460			sdc1_state_off: sdc1-state-off {
1461				clk {
1462					pins = "sdc1_clk";
1463					bias-disable;
1464					drive-strength = <2>;
1465				};
1466
1467				cmd {
1468					pins = "sdc1_cmd";
1469					bias-pull-up;
1470					drive-strength = <2>;
1471				};
1472
1473				data {
1474					pins = "sdc1_data";
1475					bias-pull-up;
1476					drive-strength = <2>;
1477				};
1478
1479				rclk {
1480					pins = "sdc1_rclk";
1481					bias-pull-down;
1482				};
1483			};
1484
1485			sdc2_state_on: sdc2-clk-on {
1486				clk {
1487					pins = "sdc2_clk";
1488					bias-disable;
1489					drive-strength = <16>;
1490				};
1491
1492				cmd {
1493					pins = "sdc2_cmd";
1494					bias-pull-up;
1495					drive-strength = <10>;
1496				};
1497
1498				data {
1499					pins = "sdc2_data";
1500					bias-pull-up;
1501					drive-strength = <10>;
1502				};
1503			};
1504
1505			sdc2_state_off: sdc2-clk-off {
1506				clk {
1507					pins = "sdc2_clk";
1508					bias-disable;
1509					drive-strength = <2>;
1510				};
1511
1512				cmd {
1513					pins = "sdc2_cmd";
1514					bias-pull-up;
1515					drive-strength = <2>;
1516				};
1517
1518				data {
1519					pins = "sdc2_data";
1520					bias-pull-up;
1521					drive-strength = <2>;
1522				};
1523			};
1524		};
1525
1526		spmi_bus: qcom,spmi@400f000 {
1527			compatible = "qcom,spmi-pmic-arb";
1528			reg = <0x0400f000 0x1000>,
1529			      <0x04400000 0x800000>,
1530			      <0x04c00000 0x800000>,
1531			      <0x05800000 0x200000>,
1532			      <0x0400a000 0x002100>;
1533			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1534			interrupt-names = "periph_irq";
1535			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1536			qcom,ee = <0>;
1537			qcom,channel = <0>;
1538			#address-cells = <2>;
1539			#size-cells = <0>;
1540			interrupt-controller;
1541			#interrupt-cells = <4>;
1542		};
1543
1544		agnoc@0 {
1545			power-domains = <&gcc AGGRE0_NOC_GDSC>;
1546			compatible = "simple-pm-bus";
1547			#address-cells = <1>;
1548			#size-cells = <1>;
1549			ranges;
1550
1551			pcie0: pcie@600000 {
1552				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1553				status = "disabled";
1554				power-domains = <&gcc PCIE0_GDSC>;
1555				bus-range = <0x00 0xff>;
1556				num-lanes = <1>;
1557
1558				reg = <0x00600000 0x2000>,
1559				      <0x0c000000 0xf1d>,
1560				      <0x0c000f20 0xa8>,
1561				      <0x0c100000 0x100000>;
1562				reg-names = "parf", "dbi", "elbi","config";
1563
1564				phys = <&pciephy_0>;
1565				phy-names = "pciephy";
1566
1567				#address-cells = <3>;
1568				#size-cells = <2>;
1569				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1570					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1571
1572				device_type = "pci";
1573
1574				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1575				interrupt-names = "msi";
1576				#interrupt-cells = <1>;
1577				interrupt-map-mask = <0 0 0 0x7>;
1578				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1579						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1580						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1581						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1582
1583				pinctrl-names = "default", "sleep";
1584				pinctrl-0 = <&pcie0_state_on>;
1585				pinctrl-1 = <&pcie0_state_off>;
1586
1587				linux,pci-domain = <0>;
1588
1589				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1590					<&gcc GCC_PCIE_0_AUX_CLK>,
1591					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1592					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1593					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1594
1595				clock-names =  "pipe",
1596						"aux",
1597						"cfg",
1598						"bus_master",
1599						"bus_slave";
1600
1601			};
1602
1603			pcie1: pcie@608000 {
1604				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1605				power-domains = <&gcc PCIE1_GDSC>;
1606				bus-range = <0x00 0xff>;
1607				num-lanes = <1>;
1608
1609				status  = "disabled";
1610
1611				reg = <0x00608000 0x2000>,
1612				      <0x0d000000 0xf1d>,
1613				      <0x0d000f20 0xa8>,
1614				      <0x0d100000 0x100000>;
1615
1616				reg-names = "parf", "dbi", "elbi","config";
1617
1618				phys = <&pciephy_1>;
1619				phy-names = "pciephy";
1620
1621				#address-cells = <3>;
1622				#size-cells = <2>;
1623				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1624					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1625
1626				device_type = "pci";
1627
1628				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1629				interrupt-names = "msi";
1630				#interrupt-cells = <1>;
1631				interrupt-map-mask = <0 0 0 0x7>;
1632				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1633						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1634						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1635						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1636
1637				pinctrl-names = "default", "sleep";
1638				pinctrl-0 = <&pcie1_state_on>;
1639				pinctrl-1 = <&pcie1_state_off>;
1640
1641				linux,pci-domain = <1>;
1642
1643				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1644					<&gcc GCC_PCIE_1_AUX_CLK>,
1645					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1646					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1647					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1648
1649				clock-names =  "pipe",
1650						"aux",
1651						"cfg",
1652						"bus_master",
1653						"bus_slave";
1654			};
1655
1656			pcie2: pcie@610000 {
1657				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1658				power-domains = <&gcc PCIE2_GDSC>;
1659				bus-range = <0x00 0xff>;
1660				num-lanes = <1>;
1661				status = "disabled";
1662				reg = <0x00610000 0x2000>,
1663				      <0x0e000000 0xf1d>,
1664				      <0x0e000f20 0xa8>,
1665				      <0x0e100000 0x100000>;
1666
1667				reg-names = "parf", "dbi", "elbi","config";
1668
1669				phys = <&pciephy_2>;
1670				phy-names = "pciephy";
1671
1672				#address-cells = <3>;
1673				#size-cells = <2>;
1674				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1675					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1676
1677				device_type = "pci";
1678
1679				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1680				interrupt-names = "msi";
1681				#interrupt-cells = <1>;
1682				interrupt-map-mask = <0 0 0 0x7>;
1683				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1684						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1685						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1686						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1687
1688				pinctrl-names = "default", "sleep";
1689				pinctrl-0 = <&pcie2_state_on>;
1690				pinctrl-1 = <&pcie2_state_off>;
1691
1692				linux,pci-domain = <2>;
1693				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1694					<&gcc GCC_PCIE_2_AUX_CLK>,
1695					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1696					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1697					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1698
1699				clock-names =  "pipe",
1700						"aux",
1701						"cfg",
1702						"bus_master",
1703						"bus_slave";
1704			};
1705		};
1706
1707		ufshc: ufshc@624000 {
1708			compatible = "qcom,ufshc";
1709			reg = <0x00624000 0x2500>;
1710			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1711
1712			phys = <&ufsphy_lane>;
1713			phy-names = "ufsphy";
1714
1715			power-domains = <&gcc UFS_GDSC>;
1716
1717			clock-names =
1718				"core_clk_src",
1719				"core_clk",
1720				"bus_clk",
1721				"bus_aggr_clk",
1722				"iface_clk",
1723				"core_clk_unipro_src",
1724				"core_clk_unipro",
1725				"core_clk_ice",
1726				"ref_clk",
1727				"tx_lane0_sync_clk",
1728				"rx_lane0_sync_clk";
1729			clocks =
1730				<&gcc UFS_AXI_CLK_SRC>,
1731				<&gcc GCC_UFS_AXI_CLK>,
1732				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1733				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1734				<&gcc GCC_UFS_AHB_CLK>,
1735				<&gcc UFS_ICE_CORE_CLK_SRC>,
1736				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1737				<&gcc GCC_UFS_ICE_CORE_CLK>,
1738				<&rpmcc RPM_SMD_LN_BB_CLK>,
1739				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1740				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1741			freq-table-hz =
1742				<100000000 200000000>,
1743				<0 0>,
1744				<0 0>,
1745				<0 0>,
1746				<0 0>,
1747				<150000000 300000000>,
1748				<0 0>,
1749				<0 0>,
1750				<0 0>,
1751				<0 0>,
1752				<0 0>;
1753
1754			lanes-per-direction = <1>;
1755			#reset-cells = <1>;
1756			status = "disabled";
1757
1758			ufs_variant {
1759				compatible = "qcom,ufs_variant";
1760			};
1761		};
1762
1763		ufsphy: phy@627000 {
1764			compatible = "qcom,msm8996-qmp-ufs-phy";
1765			reg = <0x00627000 0x1c4>;
1766			#address-cells = <1>;
1767			#size-cells = <1>;
1768			ranges;
1769
1770			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1771			clock-names = "ref";
1772
1773			resets = <&ufshc 0>;
1774			reset-names = "ufsphy";
1775			status = "disabled";
1776
1777			ufsphy_lane: lanes@627400 {
1778				reg = <0x627400 0x12c>,
1779				      <0x627600 0x200>,
1780				      <0x627c00 0x1b4>;
1781				#phy-cells = <0>;
1782			};
1783		};
1784
1785		camss: camss@a00000 {
1786			compatible = "qcom,msm8996-camss";
1787			reg = <0x00a34000 0x1000>,
1788			      <0x00a00030 0x4>,
1789			      <0x00a35000 0x1000>,
1790			      <0x00a00038 0x4>,
1791			      <0x00a36000 0x1000>,
1792			      <0x00a00040 0x4>,
1793			      <0x00a30000 0x100>,
1794			      <0x00a30400 0x100>,
1795			      <0x00a30800 0x100>,
1796			      <0x00a30c00 0x100>,
1797			      <0x00a31000 0x500>,
1798			      <0x00a00020 0x10>,
1799			      <0x00a10000 0x1000>,
1800			      <0x00a14000 0x1000>;
1801			reg-names = "csiphy0",
1802				"csiphy0_clk_mux",
1803				"csiphy1",
1804				"csiphy1_clk_mux",
1805				"csiphy2",
1806				"csiphy2_clk_mux",
1807				"csid0",
1808				"csid1",
1809				"csid2",
1810				"csid3",
1811				"ispif",
1812				"csi_clk_mux",
1813				"vfe0",
1814				"vfe1";
1815			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1816				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1817				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1818				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1819				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1820				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1821				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1822				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1823				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1824				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1825			interrupt-names = "csiphy0",
1826				"csiphy1",
1827				"csiphy2",
1828				"csid0",
1829				"csid1",
1830				"csid2",
1831				"csid3",
1832				"ispif",
1833				"vfe0",
1834				"vfe1";
1835			power-domains = <&mmcc VFE0_GDSC>,
1836					<&mmcc VFE1_GDSC>;
1837			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1838				<&mmcc CAMSS_ISPIF_AHB_CLK>,
1839				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1840				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1841				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1842				<&mmcc CAMSS_CSI0_AHB_CLK>,
1843				<&mmcc CAMSS_CSI0_CLK>,
1844				<&mmcc CAMSS_CSI0PHY_CLK>,
1845				<&mmcc CAMSS_CSI0PIX_CLK>,
1846				<&mmcc CAMSS_CSI0RDI_CLK>,
1847				<&mmcc CAMSS_CSI1_AHB_CLK>,
1848				<&mmcc CAMSS_CSI1_CLK>,
1849				<&mmcc CAMSS_CSI1PHY_CLK>,
1850				<&mmcc CAMSS_CSI1PIX_CLK>,
1851				<&mmcc CAMSS_CSI1RDI_CLK>,
1852				<&mmcc CAMSS_CSI2_AHB_CLK>,
1853				<&mmcc CAMSS_CSI2_CLK>,
1854				<&mmcc CAMSS_CSI2PHY_CLK>,
1855				<&mmcc CAMSS_CSI2PIX_CLK>,
1856				<&mmcc CAMSS_CSI2RDI_CLK>,
1857				<&mmcc CAMSS_CSI3_AHB_CLK>,
1858				<&mmcc CAMSS_CSI3_CLK>,
1859				<&mmcc CAMSS_CSI3PHY_CLK>,
1860				<&mmcc CAMSS_CSI3PIX_CLK>,
1861				<&mmcc CAMSS_CSI3RDI_CLK>,
1862				<&mmcc CAMSS_AHB_CLK>,
1863				<&mmcc CAMSS_VFE0_CLK>,
1864				<&mmcc CAMSS_CSI_VFE0_CLK>,
1865				<&mmcc CAMSS_VFE0_AHB_CLK>,
1866				<&mmcc CAMSS_VFE0_STREAM_CLK>,
1867				<&mmcc CAMSS_VFE1_CLK>,
1868				<&mmcc CAMSS_CSI_VFE1_CLK>,
1869				<&mmcc CAMSS_VFE1_AHB_CLK>,
1870				<&mmcc CAMSS_VFE1_STREAM_CLK>,
1871				<&mmcc CAMSS_VFE_AHB_CLK>,
1872				<&mmcc CAMSS_VFE_AXI_CLK>;
1873			clock-names = "top_ahb",
1874				"ispif_ahb",
1875				"csiphy0_timer",
1876				"csiphy1_timer",
1877				"csiphy2_timer",
1878				"csi0_ahb",
1879				"csi0",
1880				"csi0_phy",
1881				"csi0_pix",
1882				"csi0_rdi",
1883				"csi1_ahb",
1884				"csi1",
1885				"csi1_phy",
1886				"csi1_pix",
1887				"csi1_rdi",
1888				"csi2_ahb",
1889				"csi2",
1890				"csi2_phy",
1891				"csi2_pix",
1892				"csi2_rdi",
1893				"csi3_ahb",
1894				"csi3",
1895				"csi3_phy",
1896				"csi3_pix",
1897				"csi3_rdi",
1898				"ahb",
1899				"vfe0",
1900				"csi_vfe0",
1901				"vfe0_ahb",
1902				"vfe0_stream",
1903				"vfe1",
1904				"csi_vfe1",
1905				"vfe1_ahb",
1906				"vfe1_stream",
1907				"vfe_ahb",
1908				"vfe_axi";
1909			iommus = <&vfe_smmu 0>,
1910				 <&vfe_smmu 1>,
1911				 <&vfe_smmu 2>,
1912				 <&vfe_smmu 3>;
1913			status = "disabled";
1914			ports {
1915				#address-cells = <1>;
1916				#size-cells = <0>;
1917			};
1918		};
1919
1920		cci: cci@a0c000 {
1921			compatible = "qcom,msm8996-cci";
1922			#address-cells = <1>;
1923			#size-cells = <0>;
1924			reg = <0xa0c000 0x1000>;
1925			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1926			power-domains = <&mmcc CAMSS_GDSC>;
1927			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1928				 <&mmcc CAMSS_CCI_AHB_CLK>,
1929				 <&mmcc CAMSS_CCI_CLK>,
1930				 <&mmcc CAMSS_AHB_CLK>;
1931			clock-names = "camss_top_ahb",
1932				      "cci_ahb",
1933				      "cci",
1934				      "camss_ahb";
1935			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1936					  <&mmcc CAMSS_CCI_CLK>;
1937			assigned-clock-rates = <80000000>, <37500000>;
1938			pinctrl-names = "default";
1939			pinctrl-0 = <&cci0_default &cci1_default>;
1940			status = "disabled";
1941
1942			cci_i2c0: i2c-bus@0 {
1943				reg = <0>;
1944				clock-frequency = <400000>;
1945				#address-cells = <1>;
1946				#size-cells = <0>;
1947			};
1948
1949			cci_i2c1: i2c-bus@1 {
1950				reg = <1>;
1951				clock-frequency = <400000>;
1952				#address-cells = <1>;
1953				#size-cells = <0>;
1954			};
1955		};
1956
1957		adreno_smmu: iommu@b40000 {
1958			compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1959			reg = <0x00b40000 0x10000>;
1960
1961			#global-interrupts = <1>;
1962			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1963				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1964				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1965			#iommu-cells = <1>;
1966
1967			clocks = <&mmcc GPU_AHB_CLK>,
1968				 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1969			clock-names = "iface", "bus";
1970
1971			power-domains = <&mmcc GPU_GDSC>;
1972		};
1973
1974		venus: video-codec@c00000 {
1975			compatible = "qcom,msm8996-venus";
1976			reg = <0x00c00000 0xff000>;
1977			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1978			power-domains = <&mmcc VENUS_GDSC>;
1979			clocks = <&mmcc VIDEO_CORE_CLK>,
1980				 <&mmcc VIDEO_AHB_CLK>,
1981				 <&mmcc VIDEO_AXI_CLK>,
1982				 <&mmcc VIDEO_MAXI_CLK>;
1983			clock-names = "core", "iface", "bus", "mbus";
1984			iommus = <&venus_smmu 0x00>,
1985				 <&venus_smmu 0x01>,
1986				 <&venus_smmu 0x0a>,
1987				 <&venus_smmu 0x07>,
1988				 <&venus_smmu 0x0e>,
1989				 <&venus_smmu 0x0f>,
1990				 <&venus_smmu 0x08>,
1991				 <&venus_smmu 0x09>,
1992				 <&venus_smmu 0x0b>,
1993				 <&venus_smmu 0x0c>,
1994				 <&venus_smmu 0x0d>,
1995				 <&venus_smmu 0x10>,
1996				 <&venus_smmu 0x11>,
1997				 <&venus_smmu 0x21>,
1998				 <&venus_smmu 0x28>,
1999				 <&venus_smmu 0x29>,
2000				 <&venus_smmu 0x2b>,
2001				 <&venus_smmu 0x2c>,
2002				 <&venus_smmu 0x2d>,
2003				 <&venus_smmu 0x31>;
2004			memory-region = <&venus_region>;
2005			status = "disabled";
2006
2007			video-decoder {
2008				compatible = "venus-decoder";
2009				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2010				clock-names = "core";
2011				power-domains = <&mmcc VENUS_CORE0_GDSC>;
2012			};
2013
2014			video-encoder {
2015				compatible = "venus-encoder";
2016				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2017				clock-names = "core";
2018				power-domains = <&mmcc VENUS_CORE1_GDSC>;
2019			};
2020		};
2021
2022		mdp_smmu: iommu@d00000 {
2023			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2024			reg = <0x00d00000 0x10000>;
2025
2026			#global-interrupts = <1>;
2027			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2028				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2029				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2030			#iommu-cells = <1>;
2031			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2032				 <&mmcc SMMU_MDP_AXI_CLK>;
2033			clock-names = "iface", "bus";
2034
2035			power-domains = <&mmcc MDSS_GDSC>;
2036		};
2037
2038		venus_smmu: iommu@d40000 {
2039			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2040			reg = <0x00d40000 0x20000>;
2041			#global-interrupts = <1>;
2042			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2043				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2044				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2045				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2046				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2047				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2048				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2049				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2050			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2051			clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2052				 <&mmcc SMMU_VIDEO_AXI_CLK>;
2053			clock-names = "iface", "bus";
2054			#iommu-cells = <1>;
2055			status = "okay";
2056		};
2057
2058		vfe_smmu: iommu@da0000 {
2059			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2060			reg = <0x00da0000 0x10000>;
2061
2062			#global-interrupts = <1>;
2063			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2064				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2065				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2066			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2067			clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2068				 <&mmcc SMMU_VFE_AXI_CLK>;
2069			clock-names = "iface",
2070				      "bus";
2071			#iommu-cells = <1>;
2072		};
2073
2074		lpass_q6_smmu: iommu@1600000 {
2075			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2076			reg = <0x01600000 0x20000>;
2077			#iommu-cells = <1>;
2078			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2079
2080			#global-interrupts = <1>;
2081			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2082		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2083		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2084		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2085		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2086		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2087		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2088		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2089		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2090		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2091		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2092		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2093		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2094
2095			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2096				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2097			clock-names = "iface", "bus";
2098		};
2099
2100		stm@3002000 {
2101			compatible = "arm,coresight-stm", "arm,primecell";
2102			reg = <0x3002000 0x1000>,
2103			      <0x8280000 0x180000>;
2104			reg-names = "stm-base", "stm-stimulus-base";
2105
2106			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2107			clock-names = "apb_pclk", "atclk";
2108
2109			out-ports {
2110				port {
2111					stm_out: endpoint {
2112						remote-endpoint =
2113						  <&funnel0_in>;
2114					};
2115				};
2116			};
2117		};
2118
2119		tpiu@3020000 {
2120			compatible = "arm,coresight-tpiu", "arm,primecell";
2121			reg = <0x3020000 0x1000>;
2122
2123			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2124			clock-names = "apb_pclk", "atclk";
2125
2126			in-ports {
2127				port {
2128					tpiu_in: endpoint {
2129						remote-endpoint =
2130						  <&replicator_out1>;
2131					};
2132				};
2133			};
2134		};
2135
2136		funnel@3021000 {
2137			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2138			reg = <0x3021000 0x1000>;
2139
2140			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2141			clock-names = "apb_pclk", "atclk";
2142
2143			in-ports {
2144				#address-cells = <1>;
2145				#size-cells = <0>;
2146
2147				port@7 {
2148					reg = <7>;
2149					funnel0_in: endpoint {
2150						remote-endpoint =
2151						  <&stm_out>;
2152					};
2153				};
2154			};
2155
2156			out-ports {
2157				port {
2158					funnel0_out: endpoint {
2159						remote-endpoint =
2160						  <&merge_funnel_in0>;
2161					};
2162				};
2163			};
2164		};
2165
2166		funnel@3022000 {
2167			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2168			reg = <0x3022000 0x1000>;
2169
2170			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2171			clock-names = "apb_pclk", "atclk";
2172
2173			in-ports {
2174				#address-cells = <1>;
2175				#size-cells = <0>;
2176
2177				port@6 {
2178					reg = <6>;
2179					funnel1_in: endpoint {
2180						remote-endpoint =
2181						  <&apss_merge_funnel_out>;
2182					};
2183				};
2184			};
2185
2186			out-ports {
2187				port {
2188					funnel1_out: endpoint {
2189						remote-endpoint =
2190						  <&merge_funnel_in1>;
2191					};
2192				};
2193			};
2194		};
2195
2196		funnel@3023000 {
2197			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2198			reg = <0x3023000 0x1000>;
2199
2200			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2201			clock-names = "apb_pclk", "atclk";
2202
2203
2204			out-ports {
2205				port {
2206					funnel2_out: endpoint {
2207						remote-endpoint =
2208						  <&merge_funnel_in2>;
2209					};
2210				};
2211			};
2212		};
2213
2214		funnel@3025000 {
2215			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2216			reg = <0x3025000 0x1000>;
2217
2218			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2219			clock-names = "apb_pclk", "atclk";
2220
2221			in-ports {
2222				#address-cells = <1>;
2223				#size-cells = <0>;
2224
2225				port@0 {
2226					reg = <0>;
2227					merge_funnel_in0: endpoint {
2228						remote-endpoint =
2229						  <&funnel0_out>;
2230					};
2231				};
2232
2233				port@1 {
2234					reg = <1>;
2235					merge_funnel_in1: endpoint {
2236						remote-endpoint =
2237						  <&funnel1_out>;
2238					};
2239				};
2240
2241				port@2 {
2242					reg = <2>;
2243					merge_funnel_in2: endpoint {
2244						remote-endpoint =
2245						  <&funnel2_out>;
2246					};
2247				};
2248			};
2249
2250			out-ports {
2251				port {
2252					merge_funnel_out: endpoint {
2253						remote-endpoint =
2254						  <&etf_in>;
2255					};
2256				};
2257			};
2258		};
2259
2260		replicator@3026000 {
2261			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2262			reg = <0x3026000 0x1000>;
2263
2264			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2265			clock-names = "apb_pclk", "atclk";
2266
2267			in-ports {
2268				port {
2269					replicator_in: endpoint {
2270						remote-endpoint =
2271						  <&etf_out>;
2272					};
2273				};
2274			};
2275
2276			out-ports {
2277				#address-cells = <1>;
2278				#size-cells = <0>;
2279
2280				port@0 {
2281					reg = <0>;
2282					replicator_out0: endpoint {
2283						remote-endpoint =
2284						  <&etr_in>;
2285					};
2286				};
2287
2288				port@1 {
2289					reg = <1>;
2290					replicator_out1: endpoint {
2291						remote-endpoint =
2292						  <&tpiu_in>;
2293					};
2294				};
2295			};
2296		};
2297
2298		etf@3027000 {
2299			compatible = "arm,coresight-tmc", "arm,primecell";
2300			reg = <0x3027000 0x1000>;
2301
2302			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2303			clock-names = "apb_pclk", "atclk";
2304
2305			in-ports {
2306				port {
2307					etf_in: endpoint {
2308						remote-endpoint =
2309						  <&merge_funnel_out>;
2310					};
2311				};
2312			};
2313
2314			out-ports {
2315				port {
2316					etf_out: endpoint {
2317						remote-endpoint =
2318						  <&replicator_in>;
2319					};
2320				};
2321			};
2322		};
2323
2324		etr@3028000 {
2325			compatible = "arm,coresight-tmc", "arm,primecell";
2326			reg = <0x3028000 0x1000>;
2327
2328			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2329			clock-names = "apb_pclk", "atclk";
2330			arm,scatter-gather;
2331
2332			in-ports {
2333				port {
2334					etr_in: endpoint {
2335						remote-endpoint =
2336						  <&replicator_out0>;
2337					};
2338				};
2339			};
2340		};
2341
2342		debug@3810000 {
2343			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2344			reg = <0x3810000 0x1000>;
2345
2346			clocks = <&rpmcc RPM_QDSS_CLK>;
2347			clock-names = "apb_pclk";
2348
2349			cpu = <&CPU0>;
2350		};
2351
2352		etm@3840000 {
2353			compatible = "arm,coresight-etm4x", "arm,primecell";
2354			reg = <0x3840000 0x1000>;
2355
2356			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2357			clock-names = "apb_pclk", "atclk";
2358
2359			cpu = <&CPU0>;
2360
2361			out-ports {
2362				port {
2363					etm0_out: endpoint {
2364						remote-endpoint =
2365						  <&apss_funnel0_in0>;
2366					};
2367				};
2368			};
2369		};
2370
2371		debug@3910000 {
2372			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2373			reg = <0x3910000 0x1000>;
2374
2375			clocks = <&rpmcc RPM_QDSS_CLK>;
2376			clock-names = "apb_pclk";
2377
2378			cpu = <&CPU1>;
2379		};
2380
2381		etm@3940000 {
2382			compatible = "arm,coresight-etm4x", "arm,primecell";
2383			reg = <0x3940000 0x1000>;
2384
2385			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2386			clock-names = "apb_pclk", "atclk";
2387
2388			cpu = <&CPU1>;
2389
2390			out-ports {
2391				port {
2392					etm1_out: endpoint {
2393						remote-endpoint =
2394						  <&apss_funnel0_in1>;
2395					};
2396				};
2397			};
2398		};
2399
2400		funnel@39b0000 { /* APSS Funnel 0 */
2401			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2402			reg = <0x39b0000 0x1000>;
2403
2404			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2405			clock-names = "apb_pclk", "atclk";
2406
2407			in-ports {
2408				#address-cells = <1>;
2409				#size-cells = <0>;
2410
2411				port@0 {
2412					reg = <0>;
2413					apss_funnel0_in0: endpoint {
2414						remote-endpoint = <&etm0_out>;
2415					};
2416				};
2417
2418				port@1 {
2419					reg = <1>;
2420					apss_funnel0_in1: endpoint {
2421						remote-endpoint = <&etm1_out>;
2422					};
2423				};
2424			};
2425
2426			out-ports {
2427				port {
2428					apss_funnel0_out: endpoint {
2429						remote-endpoint =
2430						  <&apss_merge_funnel_in0>;
2431					};
2432				};
2433			};
2434		};
2435
2436		debug@3a10000 {
2437			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2438			reg = <0x3a10000 0x1000>;
2439
2440			clocks = <&rpmcc RPM_QDSS_CLK>;
2441			clock-names = "apb_pclk";
2442
2443			cpu = <&CPU2>;
2444		};
2445
2446		etm@3a40000 {
2447			compatible = "arm,coresight-etm4x", "arm,primecell";
2448			reg = <0x3a40000 0x1000>;
2449
2450			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2451			clock-names = "apb_pclk", "atclk";
2452
2453			cpu = <&CPU2>;
2454
2455			out-ports {
2456				port {
2457					etm2_out: endpoint {
2458						remote-endpoint =
2459						  <&apss_funnel1_in0>;
2460					};
2461				};
2462			};
2463		};
2464
2465		debug@3b10000 {
2466			compatible = "arm,coresight-cpu-debug", "arm,primecell";
2467			reg = <0x3b10000 0x1000>;
2468
2469			clocks = <&rpmcc RPM_QDSS_CLK>;
2470			clock-names = "apb_pclk";
2471
2472			cpu = <&CPU3>;
2473		};
2474
2475		etm@3b40000 {
2476			compatible = "arm,coresight-etm4x", "arm,primecell";
2477			reg = <0x3b40000 0x1000>;
2478
2479			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2480			clock-names = "apb_pclk", "atclk";
2481
2482			cpu = <&CPU3>;
2483
2484			out-ports {
2485				port {
2486					etm3_out: endpoint {
2487						remote-endpoint =
2488						  <&apss_funnel1_in1>;
2489					};
2490				};
2491			};
2492		};
2493
2494		funnel@3bb0000 { /* APSS Funnel 1 */
2495			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2496			reg = <0x3bb0000 0x1000>;
2497
2498			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2499			clock-names = "apb_pclk", "atclk";
2500
2501			in-ports {
2502				#address-cells = <1>;
2503				#size-cells = <0>;
2504
2505				port@0 {
2506					reg = <0>;
2507					apss_funnel1_in0: endpoint {
2508						remote-endpoint = <&etm2_out>;
2509					};
2510				};
2511
2512				port@1 {
2513					reg = <1>;
2514					apss_funnel1_in1: endpoint {
2515						remote-endpoint = <&etm3_out>;
2516					};
2517				};
2518			};
2519
2520			out-ports {
2521				port {
2522					apss_funnel1_out: endpoint {
2523						remote-endpoint =
2524						  <&apss_merge_funnel_in1>;
2525					};
2526				};
2527			};
2528		};
2529
2530		funnel@3bc0000 {
2531			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2532			reg = <0x3bc0000 0x1000>;
2533
2534			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2535			clock-names = "apb_pclk", "atclk";
2536
2537			in-ports {
2538				#address-cells = <1>;
2539				#size-cells = <0>;
2540
2541				port@0 {
2542					reg = <0>;
2543					apss_merge_funnel_in0: endpoint {
2544						remote-endpoint =
2545						  <&apss_funnel0_out>;
2546					};
2547				};
2548
2549				port@1 {
2550					reg = <1>;
2551					apss_merge_funnel_in1: endpoint {
2552						remote-endpoint =
2553						  <&apss_funnel1_out>;
2554					};
2555				};
2556			};
2557
2558			out-ports {
2559				port {
2560					apss_merge_funnel_out: endpoint {
2561						remote-endpoint =
2562						  <&funnel1_in>;
2563					};
2564				};
2565			};
2566		};
2567
2568		kryocc: clock-controller@6400000 {
2569			compatible = "qcom,msm8996-apcc";
2570			reg = <0x06400000 0x90000>;
2571
2572			clock-names = "xo";
2573			clocks = <&xo_board>;
2574
2575			#clock-cells = <1>;
2576		};
2577
2578		usb3: usb@6af8800 {
2579			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2580			reg = <0x06af8800 0x400>;
2581			#address-cells = <1>;
2582			#size-cells = <1>;
2583			ranges;
2584
2585			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2586				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2587			interrupt-names = "hs_phy_irq", "ss_phy_irq";
2588
2589			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2590				<&gcc GCC_USB30_MASTER_CLK>,
2591				<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2592				<&gcc GCC_USB30_MOCK_UTMI_CLK>,
2593				<&gcc GCC_USB30_SLEEP_CLK>,
2594				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2595
2596			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2597					  <&gcc GCC_USB30_MASTER_CLK>;
2598			assigned-clock-rates = <19200000>, <120000000>;
2599
2600			power-domains = <&gcc USB30_GDSC>;
2601			status = "disabled";
2602
2603			usb3_dwc3: dwc3@6a00000 {
2604				compatible = "snps,dwc3";
2605				reg = <0x06a00000 0xcc00>;
2606				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2607				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2608				phy-names = "usb2-phy", "usb3-phy";
2609				snps,dis_u2_susphy_quirk;
2610				snps,dis_enblslpm_quirk;
2611			};
2612		};
2613
2614		usb3phy: phy@7410000 {
2615			compatible = "qcom,msm8996-qmp-usb3-phy";
2616			reg = <0x07410000 0x1c4>;
2617			#clock-cells = <1>;
2618			#address-cells = <1>;
2619			#size-cells = <1>;
2620			ranges;
2621
2622			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2623				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2624				<&gcc GCC_USB3_CLKREF_CLK>;
2625			clock-names = "aux", "cfg_ahb", "ref";
2626
2627			resets = <&gcc GCC_USB3_PHY_BCR>,
2628				<&gcc GCC_USB3PHY_PHY_BCR>;
2629			reset-names = "phy", "common";
2630			status = "disabled";
2631
2632			ssusb_phy_0: lane@7410200 {
2633				reg = <0x07410200 0x200>,
2634				      <0x07410400 0x130>,
2635				      <0x07410600 0x1a8>;
2636				#phy-cells = <0>;
2637
2638				clock-output-names = "usb3_phy_pipe_clk_src";
2639				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2640				clock-names = "pipe0";
2641			};
2642		};
2643
2644		hsusb_phy1: phy@7411000 {
2645			compatible = "qcom,msm8996-qusb2-phy";
2646			reg = <0x07411000 0x180>;
2647			#phy-cells = <0>;
2648
2649			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2650				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
2651			clock-names = "cfg_ahb", "ref";
2652
2653			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2654			nvmem-cells = <&qusb2p_hstx_trim>;
2655			status = "disabled";
2656		};
2657
2658		hsusb_phy2: phy@7412000 {
2659			compatible = "qcom,msm8996-qusb2-phy";
2660			reg = <0x07412000 0x180>;
2661			#phy-cells = <0>;
2662
2663			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2664				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
2665			clock-names = "cfg_ahb", "ref";
2666
2667			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2668			nvmem-cells = <&qusb2s_hstx_trim>;
2669			status = "disabled";
2670		};
2671
2672		sdhc1: sdhci@7464900 {
2673			compatible = "qcom,sdhci-msm-v4";
2674			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2675			reg-names = "hc_mem", "core_mem";
2676
2677			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2678					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2679			interrupt-names = "hc_irq", "pwr_irq";
2680
2681			clock-names = "iface", "core", "xo";
2682			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2683				<&gcc GCC_SDCC1_APPS_CLK>,
2684				<&xo_board>;
2685
2686			pinctrl-names = "default", "sleep";
2687			pinctrl-0 = <&sdc1_state_on>;
2688			pinctrl-1 = <&sdc1_state_off>;
2689
2690			bus-width = <8>;
2691			non-removable;
2692			status = "disabled";
2693		};
2694
2695		sdhc2: sdhci@74a4900 {
2696			compatible = "qcom,sdhci-msm-v4";
2697			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2698			reg-names = "hc_mem", "core_mem";
2699
2700			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2701				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2702			interrupt-names = "hc_irq", "pwr_irq";
2703
2704			clock-names = "iface", "core", "xo";
2705			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2706				<&gcc GCC_SDCC2_APPS_CLK>,
2707				<&xo_board>;
2708
2709			pinctrl-names = "default", "sleep";
2710			pinctrl-0 = <&sdc2_state_on>;
2711			pinctrl-1 = <&sdc2_state_off>;
2712
2713			bus-width = <4>;
2714			status = "disabled";
2715		 };
2716
2717		blsp1_dma: dma-controller@7544000 {
2718			compatible = "qcom,bam-v1.7.0";
2719			reg = <0x07544000 0x2b000>;
2720			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2721			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2722			clock-names = "bam_clk";
2723			qcom,controlled-remotely;
2724			#dma-cells = <1>;
2725			qcom,ee = <0>;
2726		};
2727
2728		blsp1_uart2: serial@7570000 {
2729			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2730			reg = <0x07570000 0x1000>;
2731			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2732			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2733				 <&gcc GCC_BLSP1_AHB_CLK>;
2734			clock-names = "core", "iface";
2735			pinctrl-names = "default", "sleep";
2736			pinctrl-0 = <&blsp1_uart2_default>;
2737			pinctrl-1 = <&blsp1_uart2_sleep>;
2738			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2739			dma-names = "tx", "rx";
2740			status = "disabled";
2741		};
2742
2743		blsp1_spi1: spi@7575000 {
2744			compatible = "qcom,spi-qup-v2.2.1";
2745			reg = <0x07575000 0x600>;
2746			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2747			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2748				 <&gcc GCC_BLSP1_AHB_CLK>;
2749			clock-names = "core", "iface";
2750			pinctrl-names = "default", "sleep";
2751			pinctrl-0 = <&blsp1_spi1_default>;
2752			pinctrl-1 = <&blsp1_spi1_sleep>;
2753			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2754			dma-names = "tx", "rx";
2755			#address-cells = <1>;
2756			#size-cells = <0>;
2757			status = "disabled";
2758		};
2759
2760		blsp1_i2c3: i2c@7577000 {
2761			compatible = "qcom,i2c-qup-v2.2.1";
2762			reg = <0x07577000 0x1000>;
2763			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2764			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2765				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2766			clock-names = "iface", "core";
2767			pinctrl-names = "default", "sleep";
2768			pinctrl-0 = <&blsp1_i2c3_default>;
2769			pinctrl-1 = <&blsp1_i2c3_sleep>;
2770			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2771			dma-names = "tx", "rx";
2772			#address-cells = <1>;
2773			#size-cells = <0>;
2774			status = "disabled";
2775		};
2776
2777		blsp2_dma: dma-controller@7584000 {
2778			compatible = "qcom,bam-v1.7.0";
2779			reg = <0x07584000 0x2b000>;
2780			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2781			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2782			clock-names = "bam_clk";
2783			qcom,controlled-remotely;
2784			#dma-cells = <1>;
2785			qcom,ee = <0>;
2786		};
2787
2788		blsp2_uart2: serial@75b0000 {
2789			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2790			reg = <0x075b0000 0x1000>;
2791			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2792			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2793				 <&gcc GCC_BLSP2_AHB_CLK>;
2794			clock-names = "core", "iface";
2795			status = "disabled";
2796		};
2797
2798		blsp2_uart3: serial@75b1000 {
2799			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2800			reg = <0x075b1000 0x1000>;
2801			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2802			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2803				 <&gcc GCC_BLSP2_AHB_CLK>;
2804			clock-names = "core", "iface";
2805			status = "disabled";
2806		};
2807
2808		blsp2_i2c1: i2c@75b5000 {
2809			compatible = "qcom,i2c-qup-v2.2.1";
2810			reg = <0x075b5000 0x1000>;
2811			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2812			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2813				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2814			clock-names = "iface", "core";
2815			pinctrl-names = "default", "sleep";
2816			pinctrl-0 = <&blsp2_i2c1_default>;
2817			pinctrl-1 = <&blsp2_i2c1_sleep>;
2818			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2819			dma-names = "tx", "rx";
2820			#address-cells = <1>;
2821			#size-cells = <0>;
2822			status = "disabled";
2823		};
2824
2825		blsp2_i2c2: i2c@75b6000 {
2826			compatible = "qcom,i2c-qup-v2.2.1";
2827			reg = <0x075b6000 0x1000>;
2828			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2829			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2830				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2831			clock-names = "iface", "core";
2832			pinctrl-names = "default", "sleep";
2833			pinctrl-0 = <&blsp2_i2c2_default>;
2834			pinctrl-1 = <&blsp2_i2c2_sleep>;
2835			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2836			dma-names = "tx", "rx";
2837			#address-cells = <1>;
2838			#size-cells = <0>;
2839			status = "disabled";
2840		};
2841
2842		blsp2_i2c3: i2c@75b7000 {
2843			compatible = "qcom,i2c-qup-v2.2.1";
2844			reg = <0x075b7000 0x1000>;
2845			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2846			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2847				<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
2848			clock-names = "iface", "core";
2849			clock-frequency = <400000>;
2850			pinctrl-names = "default", "sleep";
2851			pinctrl-0 = <&blsp2_i2c3_default>;
2852			pinctrl-1 = <&blsp2_i2c3_sleep>;
2853			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2854			dma-names = "tx", "rx";
2855			#address-cells = <1>;
2856			#size-cells = <0>;
2857			status = "disabled";
2858		};
2859
2860		blsp2_i2c5: i2c@75b9000 {
2861			compatible = "qcom,i2c-qup-v2.2.1";
2862			reg = <0x75b9000 0x1000>;
2863			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2864			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2865				<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2866			clock-names = "iface", "core";
2867			pinctrl-names = "default";
2868			pinctrl-0 = <&blsp2_i2c5_default>;
2869			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2870			dma-names = "tx", "rx";
2871			#address-cells = <1>;
2872			#size-cells = <0>;
2873			status = "disabled";
2874		};
2875
2876		blsp2_i2c6: i2c@75ba000 {
2877			compatible = "qcom,i2c-qup-v2.2.1";
2878			reg = <0x75ba000 0x1000>;
2879			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2880			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2881				<&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2882			clock-names = "iface", "core";
2883			pinctrl-names = "default", "sleep";
2884			pinctrl-0 = <&blsp2_i2c6_default>;
2885			pinctrl-1 = <&blsp2_i2c6_sleep>;
2886			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2887			dma-names = "tx", "rx";
2888			#address-cells = <1>;
2889			#size-cells = <0>;
2890			status = "disabled";
2891		};
2892
2893		blsp2_spi6: spi@75ba000{
2894			compatible = "qcom,spi-qup-v2.2.1";
2895			reg = <0x075ba000 0x600>;
2896			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2897			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2898				 <&gcc GCC_BLSP2_AHB_CLK>;
2899			clock-names = "core", "iface";
2900			pinctrl-names = "default", "sleep";
2901			pinctrl-0 = <&blsp2_spi6_default>;
2902			pinctrl-1 = <&blsp2_spi6_sleep>;
2903			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2904			dma-names = "tx", "rx";
2905			#address-cells = <1>;
2906			#size-cells = <0>;
2907			status = "disabled";
2908		};
2909
2910		usb2: usb@76f8800 {
2911			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2912			reg = <0x076f8800 0x400>;
2913			#address-cells = <1>;
2914			#size-cells = <1>;
2915			ranges;
2916
2917			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2918				<&gcc GCC_USB20_MASTER_CLK>,
2919				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
2920				<&gcc GCC_USB20_SLEEP_CLK>,
2921				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2922
2923			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2924					  <&gcc GCC_USB20_MASTER_CLK>;
2925			assigned-clock-rates = <19200000>, <60000000>;
2926
2927			power-domains = <&gcc USB30_GDSC>;
2928			qcom,select-utmi-as-pipe-clk;
2929			status = "disabled";
2930
2931			dwc3@7600000 {
2932				compatible = "snps,dwc3";
2933				reg = <0x07600000 0xcc00>;
2934				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2935				phys = <&hsusb_phy2>;
2936				phy-names = "usb2-phy";
2937				maximum-speed = "high-speed";
2938				snps,dis_u2_susphy_quirk;
2939				snps,dis_enblslpm_quirk;
2940			};
2941		};
2942
2943		slimbam: dma-controller@9184000 {
2944			compatible = "qcom,bam-v1.7.0";
2945			qcom,controlled-remotely;
2946			reg = <0x09184000 0x32000>;
2947			num-channels  = <31>;
2948			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2949			#dma-cells = <1>;
2950			qcom,ee = <1>;
2951			qcom,num-ees = <2>;
2952		};
2953
2954		slim_msm: slim@91c0000 {
2955			compatible = "qcom,slim-ngd-v1.5.0";
2956			reg = <0x091c0000 0x2C000>;
2957			reg-names = "ctrl";
2958			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2959			dmas =	<&slimbam 3>, <&slimbam 4>,
2960				<&slimbam 5>, <&slimbam 6>;
2961			dma-names = "rx", "tx", "tx2", "rx2";
2962			#address-cells = <1>;
2963			#size-cells = <0>;
2964			ngd@1 {
2965				reg = <1>;
2966				#address-cells = <1>;
2967				#size-cells = <1>;
2968
2969				tasha_ifd: tas-ifd {
2970					compatible = "slim217,1a0";
2971					reg  = <0 0>;
2972				};
2973
2974				wcd9335: codec@1{
2975					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2976					pinctrl-names = "default";
2977
2978					compatible = "slim217,1a0";
2979					reg  = <1 0>;
2980
2981					interrupt-parent = <&tlmm>;
2982					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2983						     <53 IRQ_TYPE_LEVEL_HIGH>;
2984					interrupt-names  = "intr1", "intr2";
2985					interrupt-controller;
2986					#interrupt-cells = <1>;
2987					reset-gpios = <&tlmm 64 0>;
2988
2989					slim-ifc-dev  = <&tasha_ifd>;
2990
2991					#sound-dai-cells = <1>;
2992				};
2993			};
2994		};
2995
2996		adsp_pil: remoteproc@9300000 {
2997			compatible = "qcom,msm8996-adsp-pil";
2998			reg = <0x09300000 0x80000>;
2999
3000			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3001					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3002					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3003					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3004					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3005			interrupt-names = "wdog", "fatal", "ready",
3006					  "handover", "stop-ack";
3007
3008			clocks = <&xo_board>;
3009			clock-names = "xo";
3010
3011			memory-region = <&adsp_region>;
3012
3013			qcom,smem-states = <&smp2p_adsp_out 0>;
3014			qcom,smem-state-names = "stop";
3015
3016			power-domains = <&rpmpd MSM8996_VDDCX>;
3017			power-domain-names = "cx";
3018
3019			status = "disabled";
3020
3021			smd-edge {
3022				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3023
3024				label = "lpass";
3025				mboxes = <&apcs_glb 8>;
3026				qcom,smd-edge = <1>;
3027				qcom,remote-pid = <2>;
3028				#address-cells = <1>;
3029				#size-cells = <0>;
3030				apr {
3031					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3032					compatible = "qcom,apr-v2";
3033					qcom,smd-channels = "apr_audio_svc";
3034					qcom,apr-domain = <APR_DOMAIN_ADSP>;
3035					#address-cells = <1>;
3036					#size-cells = <0>;
3037
3038					q6core {
3039						reg = <APR_SVC_ADSP_CORE>;
3040						compatible = "qcom,q6core";
3041					};
3042
3043					q6afe: q6afe {
3044						compatible = "qcom,q6afe";
3045						reg = <APR_SVC_AFE>;
3046						q6afedai: dais {
3047							compatible = "qcom,q6afe-dais";
3048							#address-cells = <1>;
3049							#size-cells = <0>;
3050							#sound-dai-cells = <1>;
3051							hdmi@1 {
3052								reg = <1>;
3053							};
3054						};
3055					};
3056
3057					q6asm: q6asm {
3058						compatible = "qcom,q6asm";
3059						reg = <APR_SVC_ASM>;
3060						q6asmdai: dais {
3061							compatible = "qcom,q6asm-dais";
3062							#address-cells = <1>;
3063							#size-cells = <0>;
3064							#sound-dai-cells = <1>;
3065							iommus = <&lpass_q6_smmu 1>;
3066						};
3067					};
3068
3069					q6adm: q6adm {
3070						compatible = "qcom,q6adm";
3071						reg = <APR_SVC_ADM>;
3072						q6routing: routing {
3073							compatible = "qcom,q6adm-routing";
3074							#sound-dai-cells = <0>;
3075						};
3076					};
3077				};
3078
3079			};
3080		};
3081
3082		apcs_glb: mailbox@9820000 {
3083			compatible = "qcom,msm8996-apcs-hmss-global";
3084			reg = <0x09820000 0x1000>;
3085
3086			#mbox-cells = <1>;
3087		};
3088
3089		timer@9840000 {
3090			#address-cells = <1>;
3091			#size-cells = <1>;
3092			ranges;
3093			compatible = "arm,armv7-timer-mem";
3094			reg = <0x09840000 0x1000>;
3095			clock-frequency = <19200000>;
3096
3097			frame@9850000 {
3098				frame-number = <0>;
3099				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3100					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3101				reg = <0x09850000 0x1000>,
3102				      <0x09860000 0x1000>;
3103			};
3104
3105			frame@9870000 {
3106				frame-number = <1>;
3107				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3108				reg = <0x09870000 0x1000>;
3109				status = "disabled";
3110			};
3111
3112			frame@9880000 {
3113				frame-number = <2>;
3114				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3115				reg = <0x09880000 0x1000>;
3116				status = "disabled";
3117			};
3118
3119			frame@9890000 {
3120				frame-number = <3>;
3121				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3122				reg = <0x09890000 0x1000>;
3123				status = "disabled";
3124			};
3125
3126			frame@98a0000 {
3127				frame-number = <4>;
3128				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3129				reg = <0x098a0000 0x1000>;
3130				status = "disabled";
3131			};
3132
3133			frame@98b0000 {
3134				frame-number = <5>;
3135				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3136				reg = <0x098b0000 0x1000>;
3137				status = "disabled";
3138			};
3139
3140			frame@98c0000 {
3141				frame-number = <6>;
3142				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3143				reg = <0x098c0000 0x1000>;
3144				status = "disabled";
3145			};
3146		};
3147
3148		saw3: syscon@9a10000 {
3149			compatible = "syscon";
3150			reg = <0x09a10000 0x1000>;
3151		};
3152
3153		intc: interrupt-controller@9bc0000 {
3154			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3155			#interrupt-cells = <3>;
3156			interrupt-controller;
3157			#redistributor-regions = <1>;
3158			redistributor-stride = <0x0 0x40000>;
3159			reg = <0x09bc0000 0x10000>,
3160			      <0x09c00000 0x100000>;
3161			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3162		};
3163	};
3164
3165	sound: sound {
3166	};
3167
3168	thermal-zones {
3169		cpu0-thermal {
3170			polling-delay-passive = <250>;
3171			polling-delay = <1000>;
3172
3173			thermal-sensors = <&tsens0 3>;
3174
3175			trips {
3176				cpu0_alert0: trip-point0 {
3177					temperature = <75000>;
3178					hysteresis = <2000>;
3179					type = "passive";
3180				};
3181
3182				cpu0_crit: cpu_crit {
3183					temperature = <110000>;
3184					hysteresis = <2000>;
3185					type = "critical";
3186				};
3187			};
3188		};
3189
3190		cpu1-thermal {
3191			polling-delay-passive = <250>;
3192			polling-delay = <1000>;
3193
3194			thermal-sensors = <&tsens0 5>;
3195
3196			trips {
3197				cpu1_alert0: trip-point0 {
3198					temperature = <75000>;
3199					hysteresis = <2000>;
3200					type = "passive";
3201				};
3202
3203				cpu1_crit: cpu_crit {
3204					temperature = <110000>;
3205					hysteresis = <2000>;
3206					type = "critical";
3207				};
3208			};
3209		};
3210
3211		cpu2-thermal {
3212			polling-delay-passive = <250>;
3213			polling-delay = <1000>;
3214
3215			thermal-sensors = <&tsens0 8>;
3216
3217			trips {
3218				cpu2_alert0: trip-point0 {
3219					temperature = <75000>;
3220					hysteresis = <2000>;
3221					type = "passive";
3222				};
3223
3224				cpu2_crit: cpu_crit {
3225					temperature = <110000>;
3226					hysteresis = <2000>;
3227					type = "critical";
3228				};
3229			};
3230		};
3231
3232		cpu3-thermal {
3233			polling-delay-passive = <250>;
3234			polling-delay = <1000>;
3235
3236			thermal-sensors = <&tsens0 10>;
3237
3238			trips {
3239				cpu3_alert0: trip-point0 {
3240					temperature = <75000>;
3241					hysteresis = <2000>;
3242					type = "passive";
3243				};
3244
3245				cpu3_crit: cpu_crit {
3246					temperature = <110000>;
3247					hysteresis = <2000>;
3248					type = "critical";
3249				};
3250			};
3251		};
3252
3253		gpu-thermal-top {
3254			polling-delay-passive = <250>;
3255			polling-delay = <1000>;
3256
3257			thermal-sensors = <&tsens1 6>;
3258
3259			trips {
3260				gpu1_alert0: trip-point0 {
3261					temperature = <90000>;
3262					hysteresis = <2000>;
3263					type = "passive";
3264				};
3265			};
3266
3267			cooling-maps {
3268				map0 {
3269					trip = <&gpu1_alert0>;
3270					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3271				};
3272			};
3273		};
3274
3275		gpu-thermal-bottom {
3276			polling-delay-passive = <250>;
3277			polling-delay = <1000>;
3278
3279			thermal-sensors = <&tsens1 7>;
3280
3281			trips {
3282				gpu2_alert0: trip-point0 {
3283					temperature = <90000>;
3284					hysteresis = <2000>;
3285					type = "passive";
3286				};
3287			};
3288
3289			cooling-maps {
3290				map0 {
3291					trip = <&gpu2_alert0>;
3292					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3293				};
3294			};
3295		};
3296
3297		m4m-thermal {
3298			polling-delay-passive = <250>;
3299			polling-delay = <1000>;
3300
3301			thermal-sensors = <&tsens0 1>;
3302
3303			trips {
3304				m4m_alert0: trip-point0 {
3305					temperature = <90000>;
3306					hysteresis = <2000>;
3307					type = "hot";
3308				};
3309			};
3310		};
3311
3312		l3-or-venus-thermal {
3313			polling-delay-passive = <250>;
3314			polling-delay = <1000>;
3315
3316			thermal-sensors = <&tsens0 2>;
3317
3318			trips {
3319				l3_or_venus_alert0: trip-point0 {
3320					temperature = <90000>;
3321					hysteresis = <2000>;
3322					type = "hot";
3323				};
3324			};
3325		};
3326
3327		cluster0-l2-thermal {
3328			polling-delay-passive = <250>;
3329			polling-delay = <1000>;
3330
3331			thermal-sensors = <&tsens0 7>;
3332
3333			trips {
3334				cluster0_l2_alert0: trip-point0 {
3335					temperature = <90000>;
3336					hysteresis = <2000>;
3337					type = "hot";
3338				};
3339			};
3340		};
3341
3342		cluster1-l2-thermal {
3343			polling-delay-passive = <250>;
3344			polling-delay = <1000>;
3345
3346			thermal-sensors = <&tsens0 12>;
3347
3348			trips {
3349				cluster1_l2_alert0: trip-point0 {
3350					temperature = <90000>;
3351					hysteresis = <2000>;
3352					type = "hot";
3353				};
3354			};
3355		};
3356
3357		camera-thermal {
3358			polling-delay-passive = <250>;
3359			polling-delay = <1000>;
3360
3361			thermal-sensors = <&tsens1 1>;
3362
3363			trips {
3364				camera_alert0: trip-point0 {
3365					temperature = <90000>;
3366					hysteresis = <2000>;
3367					type = "hot";
3368				};
3369			};
3370		};
3371
3372		q6-dsp-thermal {
3373			polling-delay-passive = <250>;
3374			polling-delay = <1000>;
3375
3376			thermal-sensors = <&tsens1 2>;
3377
3378			trips {
3379				q6_dsp_alert0: trip-point0 {
3380					temperature = <90000>;
3381					hysteresis = <2000>;
3382					type = "hot";
3383				};
3384			};
3385		};
3386
3387		mem-thermal {
3388			polling-delay-passive = <250>;
3389			polling-delay = <1000>;
3390
3391			thermal-sensors = <&tsens1 3>;
3392
3393			trips {
3394				mem_alert0: trip-point0 {
3395					temperature = <90000>;
3396					hysteresis = <2000>;
3397					type = "hot";
3398				};
3399			};
3400		};
3401
3402		modemtx-thermal {
3403			polling-delay-passive = <250>;
3404			polling-delay = <1000>;
3405
3406			thermal-sensors = <&tsens1 4>;
3407
3408			trips {
3409				modemtx_alert0: trip-point0 {
3410					temperature = <90000>;
3411					hysteresis = <2000>;
3412					type = "hot";
3413				};
3414			};
3415		};
3416	};
3417
3418	timer {
3419		compatible = "arm,armv8-timer";
3420		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3421			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3422			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3423			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3424	};
3425};
3426