1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 15 #define FW_NLO_INFO_CHECK_SIZE 4 16 17 #define FIFO_PAGE_SIZE_SHIFT 12 18 #define FIFO_PAGE_SIZE 4096 19 #define FIFO_DUMP_ADDR 0x8000 20 21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12 22 #define DLFW_PAGE_SIZE_LEGACY 0x1000 23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2 24 #define DLFW_BLK_SIZE_LEGACY 4 25 #define FW_START_ADDR_LEGACY 0x1000 26 27 #define BCN_LOSS_CNT 10 28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0 29 #define BCN_FILTER_CONNECTION_LOSS 1 30 #define BCN_FILTER_CONNECTED 2 31 #define BCN_FILTER_NOTIFY_BEACON_LOSS 3 32 33 #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10) 34 35 enum rtw_c2h_cmd_id { 36 C2H_CCX_TX_RPT = 0x03, 37 C2H_BT_INFO = 0x09, 38 C2H_BT_MP_INFO = 0x0b, 39 C2H_RA_RPT = 0x0c, 40 C2H_HW_FEATURE_REPORT = 0x19, 41 C2H_WLAN_INFO = 0x27, 42 C2H_WLAN_RFON = 0x32, 43 C2H_BCN_FILTER_NOTIFY = 0x36, 44 C2H_SCAN_RESULT = 0x38, 45 C2H_HW_FEATURE_DUMP = 0xfd, 46 C2H_HALMAC = 0xff, 47 }; 48 49 enum rtw_c2h_cmd_id_ext { 50 C2H_CCX_RPT = 0x0f, 51 }; 52 53 struct rtw_c2h_cmd { 54 u8 id; 55 u8 seq; 56 u8 payload[]; 57 } __packed; 58 59 enum rtw_rsvd_packet_type { 60 RSVD_BEACON, 61 RSVD_DUMMY, 62 RSVD_PS_POLL, 63 RSVD_PROBE_RESP, 64 RSVD_NULL, 65 RSVD_QOS_NULL, 66 RSVD_LPS_PG_DPK, 67 RSVD_LPS_PG_INFO, 68 RSVD_PROBE_REQ, 69 RSVD_NLO_INFO, 70 RSVD_CH_INFO, 71 }; 72 73 enum rtw_fw_rf_type { 74 FW_RF_1T2R = 0, 75 FW_RF_2T4R = 1, 76 FW_RF_2T2R = 2, 77 FW_RF_2T3R = 3, 78 FW_RF_1T1R = 4, 79 FW_RF_2T2R_GREEN = 5, 80 FW_RF_3T3R = 6, 81 FW_RF_3T4R = 7, 82 FW_RF_4T4R = 8, 83 FW_RF_MAX_TYPE = 0xF, 84 }; 85 86 enum rtw_fw_feature { 87 FW_FEATURE_SIG = BIT(0), 88 FW_FEATURE_LPS_C2H = BIT(1), 89 FW_FEATURE_LCLK = BIT(2), 90 FW_FEATURE_PG = BIT(3), 91 FW_FEATURE_BCN_FILTER = BIT(5), 92 FW_FEATURE_NOTIFY_SCAN = BIT(6), 93 FW_FEATURE_MAX = BIT(31), 94 }; 95 96 enum rtw_beacon_filter_offload_mode { 97 BCN_FILTER_OFFLOAD_MODE_0 = 0, 98 BCN_FILTER_OFFLOAD_MODE_1, 99 BCN_FILTER_OFFLOAD_MODE_2, 100 BCN_FILTER_OFFLOAD_MODE_3, 101 102 BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0, 103 }; 104 105 struct rtw_coex_info_req { 106 u8 seq; 107 u8 op_code; 108 u8 para1; 109 u8 para2; 110 u8 para3; 111 }; 112 113 struct rtw_iqk_para { 114 u8 clear; 115 u8 segment_iqk; 116 }; 117 118 struct rtw_lps_pg_dpk_hdr { 119 u16 dpk_path_ok; 120 u8 dpk_txagc[2]; 121 u16 dpk_gs[2]; 122 u32 coef[2][20]; 123 u8 dpk_ch; 124 } __packed; 125 126 struct rtw_lps_pg_info_hdr { 127 u8 macid; 128 u8 mbssid; 129 u8 pattern_count; 130 u8 mu_tab_group_id; 131 u8 sec_cam_count; 132 u8 tx_bu_page_count; 133 u16 rsvd; 134 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; 135 } __packed; 136 137 struct rtw_rsvd_page { 138 /* associated with each vif */ 139 struct list_head vif_list; 140 struct rtw_vif *rtwvif; 141 142 /* associated when build rsvd page */ 143 struct list_head build_list; 144 145 struct sk_buff *skb; 146 enum rtw_rsvd_packet_type type; 147 u8 page; 148 bool add_txdesc; 149 struct cfg80211_ssid *ssid; 150 u16 probe_req_size; 151 }; 152 153 enum rtw_keep_alive_pkt_type { 154 KEEP_ALIVE_NULL_PKT = 0, 155 KEEP_ALIVE_ARP_RSP = 1, 156 }; 157 158 struct rtw_nlo_info_hdr { 159 u8 nlo_count; 160 u8 hidden_ap_count; 161 u8 rsvd1[2]; 162 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE]; 163 u8 rsvd2[8]; 164 u8 ssid_len[16]; 165 u8 chiper[16]; 166 u8 rsvd3[16]; 167 u8 location[8]; 168 } __packed; 169 170 enum rtw_packet_type { 171 RTW_PACKET_PROBE_REQ = 0x00, 172 173 RTW_PACKET_UNDEFINE = 0x7FFFFFFF, 174 }; 175 176 struct rtw_fw_wow_keep_alive_para { 177 bool adopt; 178 u8 pkt_type; 179 u8 period; /* unit: sec */ 180 }; 181 182 struct rtw_fw_wow_disconnect_para { 183 bool adopt; 184 u8 period; /* unit: sec */ 185 u8 retry_count; 186 }; 187 188 struct rtw_ch_switch_option { 189 u8 periodic_option; 190 u32 tsf_high; 191 u32 tsf_low; 192 u8 dest_ch_en; 193 u8 absolute_time_en; 194 u8 dest_ch; 195 u8 normal_period; 196 u8 normal_period_sel; 197 u8 normal_cycle; 198 u8 slow_period; 199 u8 slow_period_sel; 200 u8 nlo_en; 201 }; 202 203 struct rtw_fw_hdr { 204 __le16 signature; 205 u8 category; 206 u8 function; 207 __le16 version; /* 0x04 */ 208 u8 subversion; 209 u8 subindex; 210 __le32 rsvd; /* 0x08 */ 211 __le32 feature; /* 0x0C */ 212 u8 month; /* 0x10 */ 213 u8 day; 214 u8 hour; 215 u8 min; 216 __le16 year; /* 0x14 */ 217 __le16 rsvd3; 218 u8 mem_usage; /* 0x18 */ 219 u8 rsvd4[3]; 220 __le16 h2c_fmt_ver; /* 0x1C */ 221 __le16 rsvd5; 222 __le32 dmem_addr; /* 0x20 */ 223 __le32 dmem_size; 224 __le32 rsvd6; 225 __le32 rsvd7; 226 __le32 imem_size; /* 0x30 */ 227 __le32 emem_size; 228 __le32 emem_addr; 229 __le32 imem_addr; 230 } __packed; 231 232 struct rtw_fw_hdr_legacy { 233 __le16 signature; 234 u8 category; 235 u8 function; 236 __le16 version; /* 0x04 */ 237 u8 subversion1; 238 u8 subversion2; 239 u8 month; /* 0x08 */ 240 u8 day; 241 u8 hour; 242 u8 minute; 243 __le16 size; 244 __le16 rsvd2; 245 __le32 idx; /* 0x10 */ 246 __le32 rsvd3; 247 __le32 rsvd4; /* 0x18 */ 248 __le32 rsvd5; 249 } __packed; 250 251 /* C2H */ 252 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc) 253 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0) 254 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc) 255 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0) 256 257 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) 258 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) 259 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) 260 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) 261 262 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf) 263 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10) 264 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100) 265 266 /* PKT H2C */ 267 #define H2C_PKT_CMD_ID 0xFF 268 #define H2C_PKT_CATEGORY 0x01 269 270 #define H2C_PKT_GENERAL_INFO 0x0D 271 #define H2C_PKT_PHYDM_INFO 0x11 272 #define H2C_PKT_IQK 0x0E 273 274 #define H2C_PKT_CH_SWITCH 0x02 275 #define H2C_PKT_UPDATE_PKT 0x0C 276 277 #define H2C_PKT_CH_SWITCH_LEN 0x20 278 #define H2C_PKT_UPDATE_PKT_LEN 0x4 279 280 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 281 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 282 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 283 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 284 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 285 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 286 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 287 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 288 289 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 290 { 291 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 292 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 293 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 294 } 295 296 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 297 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 298 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 299 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 300 301 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 302 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 303 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 304 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 305 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 306 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 307 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 308 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 309 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 310 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 311 #define IQK_SET_CLEAR(h2c_pkt, value) \ 312 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 313 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 314 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 315 316 #define CHSW_INFO_SET_CH(pkt, value) \ 317 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0)) 318 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \ 319 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8)) 320 #define CHSW_INFO_SET_BW(pkt, value) \ 321 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12)) 322 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \ 323 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16)) 324 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \ 325 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24)) 326 327 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ 328 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0)) 329 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \ 330 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 331 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \ 332 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24)) 333 334 #define CH_SWITCH_SET_START(h2c_pkt, value) \ 335 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 336 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ 337 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 338 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ 339 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 340 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ 341 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3)) 342 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ 343 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 344 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ 345 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 346 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ 347 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 348 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ 349 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 350 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ 351 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8)) 352 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ 353 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14)) 354 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ 355 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16)) 356 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ 357 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22)) 358 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ 359 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24)) 360 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ 361 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0)) 362 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ 363 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0)) 364 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ 365 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0)) 366 367 /* Command H2C */ 368 #define H2C_CMD_RSVD_PAGE 0x0 369 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 370 #define H2C_CMD_SET_PWR_MODE 0x20 371 #define H2C_CMD_LPS_PG_INFO 0x2b 372 #define H2C_CMD_RA_INFO 0x40 373 #define H2C_CMD_RSSI_MONITOR 0x42 374 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56 375 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57 376 #define H2C_CMD_WL_PHY_INFO 0x58 377 #define H2C_CMD_SCAN 0x59 378 379 #define H2C_CMD_COEX_TDMA_TYPE 0x60 380 #define H2C_CMD_QUERY_BT_INFO 0x61 381 #define H2C_CMD_FORCE_BT_TX_POWER 0x62 382 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 383 #define H2C_CMD_WL_CH_INFO 0x66 384 #define H2C_CMD_QUERY_BT_MP_INFO 0x67 385 #define H2C_CMD_BT_WIFI_CONTROL 0x69 386 #define H2C_CMD_WIFI_CALIBRATION 0x6d 387 388 #define H2C_CMD_KEEP_ALIVE 0x03 389 #define H2C_CMD_DISCONNECT_DECISION 0x04 390 #define H2C_CMD_WOWLAN 0x80 391 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81 392 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82 393 #define H2C_CMD_NLO_INFO 0x8C 394 395 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 396 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 397 398 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 399 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 400 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 401 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 402 403 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \ 404 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8)) 405 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \ 406 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18)) 407 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \ 408 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 409 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \ 410 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 411 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \ 412 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 413 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \ 414 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 415 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \ 416 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16)) 417 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \ 418 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17)) 419 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \ 420 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21)) 421 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \ 422 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 423 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \ 424 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0)) 425 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \ 426 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4)) 427 428 #define SET_SCAN_START(h2c_pkt, value) \ 429 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 430 431 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 432 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 433 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 434 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 435 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 436 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 437 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 438 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 439 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 440 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 441 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 442 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 443 #define LPS_PG_INFO_LOC(h2c_pkt, value) \ 444 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 445 #define LPS_PG_DPK_LOC(h2c_pkt, value) \ 446 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 447 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ 448 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 449 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \ 450 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 451 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 452 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 453 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 454 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 455 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 456 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 457 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 458 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 459 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 460 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 461 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 462 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 463 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 464 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 465 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 466 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 467 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 468 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 469 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 470 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 471 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 472 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 473 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 474 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 475 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 476 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 477 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 478 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 479 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 480 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 481 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 482 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 483 #define SET_QUERY_BT_INFO(h2c_pkt, value) \ 484 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 485 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ 486 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 487 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ 488 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 489 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ 490 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 491 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ 492 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 493 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ 494 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 495 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ 496 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 497 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ 498 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 499 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ 500 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 501 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ 502 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 503 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ 504 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 505 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ 506 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 507 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ 508 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 509 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ 510 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 511 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ 512 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 513 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ 514 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 515 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ 516 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 517 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ 518 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 519 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ 520 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 521 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ 522 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 523 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ 524 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 525 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ 526 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 527 528 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \ 529 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 530 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \ 531 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 532 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \ 533 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 534 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ 535 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 536 537 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \ 538 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 539 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \ 540 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 541 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \ 542 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 543 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \ 544 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 545 546 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \ 547 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 548 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \ 549 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 550 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \ 551 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 552 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \ 553 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11)) 554 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \ 555 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14)) 556 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \ 557 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15)) 558 559 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \ 560 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 561 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \ 562 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12)) 563 564 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \ 565 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 566 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \ 567 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 568 569 #define SET_NLO_FUN_EN(h2c_pkt, value) \ 570 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 571 #define SET_NLO_PS_32K(h2c_pkt, value) \ 572 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 573 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \ 574 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 575 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \ 576 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 577 578 #define GET_FW_DUMP_LEN(_header) \ 579 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0)) 580 #define GET_FW_DUMP_SEQ(_header) \ 581 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16)) 582 #define GET_FW_DUMP_MORE(_header) \ 583 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23)) 584 #define GET_FW_DUMP_VERSION(_header) \ 585 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24)) 586 #define GET_FW_DUMP_TLV_TYPE(_header) \ 587 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0)) 588 #define GET_FW_DUMP_TLV_LEN(_header) \ 589 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16)) 590 #define GET_FW_DUMP_TLV_VAL(_header) \ 591 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0)) 592 593 #define RFK_SET_INFORM_START(h2c_pkt, value) \ 594 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 595 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 596 { 597 u32 pkt_offset; 598 599 pkt_offset = *((u32 *)skb->cb); 600 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 601 } 602 603 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw, 604 enum rtw_fw_feature feature) 605 { 606 return !!(fw->feature & feature); 607 } 608 609 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, 610 struct sk_buff *skb); 611 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 612 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 613 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 614 615 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 616 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start); 617 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 618 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); 619 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); 620 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); 621 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, 622 struct rtw_coex_info_req *req); 623 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); 624 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); 625 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, 626 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); 627 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); 628 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 629 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 630 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 631 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev); 632 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect, 633 struct ieee80211_vif *vif); 634 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 635 u8 *buf, u32 size); 636 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev, 637 struct rtw_vif *rtwvif); 638 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev, 639 struct rtw_vif *rtwvif); 640 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev, 641 struct rtw_vif *rtwvif); 642 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev, 643 struct rtw_vif *rtwvif); 644 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev); 645 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 646 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 647 u32 offset, u32 size, u32 *buf); 648 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 649 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 650 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable); 651 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable); 652 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev, 653 u8 pairwise_key_enc, 654 u8 group_key_enc); 655 656 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable); 657 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev, 658 struct cfg80211_ssid *ssid); 659 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable); 660 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c); 661 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev); 662 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size, 663 u32 *buffer); 664 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 665 #endif 666