1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 2 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 /* Copyright (c) 2008-2019, IBM Corporation */ 5 6 #include <linux/errno.h> 7 #include <linux/types.h> 8 #include <linux/uaccess.h> 9 #include <linux/vmalloc.h> 10 #include <linux/xarray.h> 11 #include <net/addrconf.h> 12 13 #include <rdma/iw_cm.h> 14 #include <rdma/ib_verbs.h> 15 #include <rdma/ib_user_verbs.h> 16 #include <rdma/uverbs_ioctl.h> 17 18 #include "siw.h" 19 #include "siw_verbs.h" 20 #include "siw_mem.h" 21 22 static int ib_qp_state_to_siw_qp_state[IB_QPS_ERR + 1] = { 23 [IB_QPS_RESET] = SIW_QP_STATE_IDLE, 24 [IB_QPS_INIT] = SIW_QP_STATE_IDLE, 25 [IB_QPS_RTR] = SIW_QP_STATE_RTR, 26 [IB_QPS_RTS] = SIW_QP_STATE_RTS, 27 [IB_QPS_SQD] = SIW_QP_STATE_CLOSING, 28 [IB_QPS_SQE] = SIW_QP_STATE_TERMINATE, 29 [IB_QPS_ERR] = SIW_QP_STATE_ERROR 30 }; 31 32 static char ib_qp_state_to_string[IB_QPS_ERR + 1][sizeof("RESET")] = { 33 [IB_QPS_RESET] = "RESET", [IB_QPS_INIT] = "INIT", [IB_QPS_RTR] = "RTR", 34 [IB_QPS_RTS] = "RTS", [IB_QPS_SQD] = "SQD", [IB_QPS_SQE] = "SQE", 35 [IB_QPS_ERR] = "ERR" 36 }; 37 38 void siw_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 39 { 40 struct siw_user_mmap_entry *entry = to_siw_mmap_entry(rdma_entry); 41 42 kfree(entry); 43 } 44 45 int siw_mmap(struct ib_ucontext *ctx, struct vm_area_struct *vma) 46 { 47 struct siw_ucontext *uctx = to_siw_ctx(ctx); 48 size_t size = vma->vm_end - vma->vm_start; 49 struct rdma_user_mmap_entry *rdma_entry; 50 struct siw_user_mmap_entry *entry; 51 int rv = -EINVAL; 52 53 /* 54 * Must be page aligned 55 */ 56 if (vma->vm_start & (PAGE_SIZE - 1)) { 57 pr_warn("siw: mmap not page aligned\n"); 58 return -EINVAL; 59 } 60 rdma_entry = rdma_user_mmap_entry_get(&uctx->base_ucontext, vma); 61 if (!rdma_entry) { 62 siw_dbg(&uctx->sdev->base_dev, "mmap lookup failed: %lu, %#zx\n", 63 vma->vm_pgoff, size); 64 return -EINVAL; 65 } 66 entry = to_siw_mmap_entry(rdma_entry); 67 68 rv = remap_vmalloc_range(vma, entry->address, 0); 69 if (rv) { 70 pr_warn("remap_vmalloc_range failed: %lu, %zu\n", vma->vm_pgoff, 71 size); 72 goto out; 73 } 74 out: 75 rdma_user_mmap_entry_put(rdma_entry); 76 77 return rv; 78 } 79 80 int siw_alloc_ucontext(struct ib_ucontext *base_ctx, struct ib_udata *udata) 81 { 82 struct siw_device *sdev = to_siw_dev(base_ctx->device); 83 struct siw_ucontext *ctx = to_siw_ctx(base_ctx); 84 struct siw_uresp_alloc_ctx uresp = {}; 85 int rv; 86 87 if (atomic_inc_return(&sdev->num_ctx) > SIW_MAX_CONTEXT) { 88 rv = -ENOMEM; 89 goto err_out; 90 } 91 ctx->sdev = sdev; 92 93 uresp.dev_id = sdev->vendor_part_id; 94 95 if (udata->outlen < sizeof(uresp)) { 96 rv = -EINVAL; 97 goto err_out; 98 } 99 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 100 if (rv) 101 goto err_out; 102 103 siw_dbg(base_ctx->device, "success. now %d context(s)\n", 104 atomic_read(&sdev->num_ctx)); 105 106 return 0; 107 108 err_out: 109 atomic_dec(&sdev->num_ctx); 110 siw_dbg(base_ctx->device, "failure %d. now %d context(s)\n", rv, 111 atomic_read(&sdev->num_ctx)); 112 113 return rv; 114 } 115 116 void siw_dealloc_ucontext(struct ib_ucontext *base_ctx) 117 { 118 struct siw_ucontext *uctx = to_siw_ctx(base_ctx); 119 120 atomic_dec(&uctx->sdev->num_ctx); 121 } 122 123 int siw_query_device(struct ib_device *base_dev, struct ib_device_attr *attr, 124 struct ib_udata *udata) 125 { 126 struct siw_device *sdev = to_siw_dev(base_dev); 127 128 if (udata->inlen || udata->outlen) 129 return -EINVAL; 130 131 memset(attr, 0, sizeof(*attr)); 132 133 /* Revisit atomic caps if RFC 7306 gets supported */ 134 attr->atomic_cap = 0; 135 attr->device_cap_flags = IB_DEVICE_MEM_MGT_EXTENSIONS; 136 attr->kernel_cap_flags = IBK_ALLOW_USER_UNREG; 137 attr->max_cq = sdev->attrs.max_cq; 138 attr->max_cqe = sdev->attrs.max_cqe; 139 attr->max_fast_reg_page_list_len = SIW_MAX_SGE_PBL; 140 attr->max_mr = sdev->attrs.max_mr; 141 attr->max_mw = sdev->attrs.max_mw; 142 attr->max_mr_size = ~0ull; 143 attr->max_pd = sdev->attrs.max_pd; 144 attr->max_qp = sdev->attrs.max_qp; 145 attr->max_qp_init_rd_atom = sdev->attrs.max_ird; 146 attr->max_qp_rd_atom = sdev->attrs.max_ord; 147 attr->max_qp_wr = sdev->attrs.max_qp_wr; 148 attr->max_recv_sge = sdev->attrs.max_sge; 149 attr->max_res_rd_atom = sdev->attrs.max_qp * sdev->attrs.max_ird; 150 attr->max_send_sge = sdev->attrs.max_sge; 151 attr->max_sge_rd = sdev->attrs.max_sge_rd; 152 attr->max_srq = sdev->attrs.max_srq; 153 attr->max_srq_sge = sdev->attrs.max_srq_sge; 154 attr->max_srq_wr = sdev->attrs.max_srq_wr; 155 attr->page_size_cap = PAGE_SIZE; 156 attr->vendor_id = SIW_VENDOR_ID; 157 attr->vendor_part_id = sdev->vendor_part_id; 158 159 addrconf_addr_eui48((u8 *)&attr->sys_image_guid, 160 sdev->netdev->dev_addr); 161 162 return 0; 163 } 164 165 int siw_query_port(struct ib_device *base_dev, u32 port, 166 struct ib_port_attr *attr) 167 { 168 struct siw_device *sdev = to_siw_dev(base_dev); 169 int rv; 170 171 memset(attr, 0, sizeof(*attr)); 172 173 rv = ib_get_eth_speed(base_dev, port, &attr->active_speed, 174 &attr->active_width); 175 attr->gid_tbl_len = 1; 176 attr->max_msg_sz = -1; 177 attr->max_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu); 178 attr->active_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu); 179 attr->phys_state = sdev->state == IB_PORT_ACTIVE ? 180 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED; 181 attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_DEVICE_MGMT_SUP; 182 attr->state = sdev->state; 183 /* 184 * All zero 185 * 186 * attr->lid = 0; 187 * attr->bad_pkey_cntr = 0; 188 * attr->qkey_viol_cntr = 0; 189 * attr->sm_lid = 0; 190 * attr->lmc = 0; 191 * attr->max_vl_num = 0; 192 * attr->sm_sl = 0; 193 * attr->subnet_timeout = 0; 194 * attr->init_type_repy = 0; 195 */ 196 return rv; 197 } 198 199 int siw_get_port_immutable(struct ib_device *base_dev, u32 port, 200 struct ib_port_immutable *port_immutable) 201 { 202 struct ib_port_attr attr; 203 int rv = siw_query_port(base_dev, port, &attr); 204 205 if (rv) 206 return rv; 207 208 port_immutable->gid_tbl_len = attr.gid_tbl_len; 209 port_immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 210 211 return 0; 212 } 213 214 int siw_query_gid(struct ib_device *base_dev, u32 port, int idx, 215 union ib_gid *gid) 216 { 217 struct siw_device *sdev = to_siw_dev(base_dev); 218 219 /* subnet_prefix == interface_id == 0; */ 220 memset(gid, 0, sizeof(*gid)); 221 memcpy(&gid->raw[0], sdev->netdev->dev_addr, 6); 222 223 return 0; 224 } 225 226 int siw_alloc_pd(struct ib_pd *pd, struct ib_udata *udata) 227 { 228 struct siw_device *sdev = to_siw_dev(pd->device); 229 230 if (atomic_inc_return(&sdev->num_pd) > SIW_MAX_PD) { 231 atomic_dec(&sdev->num_pd); 232 return -ENOMEM; 233 } 234 siw_dbg_pd(pd, "now %d PD's(s)\n", atomic_read(&sdev->num_pd)); 235 236 return 0; 237 } 238 239 int siw_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 240 { 241 struct siw_device *sdev = to_siw_dev(pd->device); 242 243 siw_dbg_pd(pd, "free PD\n"); 244 atomic_dec(&sdev->num_pd); 245 return 0; 246 } 247 248 void siw_qp_get_ref(struct ib_qp *base_qp) 249 { 250 siw_qp_get(to_siw_qp(base_qp)); 251 } 252 253 void siw_qp_put_ref(struct ib_qp *base_qp) 254 { 255 siw_qp_put(to_siw_qp(base_qp)); 256 } 257 258 static struct rdma_user_mmap_entry * 259 siw_mmap_entry_insert(struct siw_ucontext *uctx, 260 void *address, size_t length, 261 u64 *offset) 262 { 263 struct siw_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL); 264 int rv; 265 266 *offset = SIW_INVAL_UOBJ_KEY; 267 if (!entry) 268 return NULL; 269 270 entry->address = address; 271 272 rv = rdma_user_mmap_entry_insert(&uctx->base_ucontext, 273 &entry->rdma_entry, 274 length); 275 if (rv) { 276 kfree(entry); 277 return NULL; 278 } 279 280 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 281 282 return &entry->rdma_entry; 283 } 284 285 /* 286 * siw_create_qp() 287 * 288 * Create QP of requested size on given device. 289 * 290 * @qp: Queue pait 291 * @attrs: Initial QP attributes. 292 * @udata: used to provide QP ID, SQ and RQ size back to user. 293 */ 294 295 int siw_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attrs, 296 struct ib_udata *udata) 297 { 298 struct ib_pd *pd = ibqp->pd; 299 struct siw_qp *qp = to_siw_qp(ibqp); 300 struct ib_device *base_dev = pd->device; 301 struct siw_device *sdev = to_siw_dev(base_dev); 302 struct siw_ucontext *uctx = 303 rdma_udata_to_drv_context(udata, struct siw_ucontext, 304 base_ucontext); 305 unsigned long flags; 306 int num_sqe, num_rqe, rv = 0; 307 size_t length; 308 309 siw_dbg(base_dev, "create new QP\n"); 310 311 if (attrs->create_flags) 312 return -EOPNOTSUPP; 313 314 if (atomic_inc_return(&sdev->num_qp) > SIW_MAX_QP) { 315 siw_dbg(base_dev, "too many QP's\n"); 316 rv = -ENOMEM; 317 goto err_atomic; 318 } 319 if (attrs->qp_type != IB_QPT_RC) { 320 siw_dbg(base_dev, "only RC QP's supported\n"); 321 rv = -EOPNOTSUPP; 322 goto err_atomic; 323 } 324 if ((attrs->cap.max_send_wr > SIW_MAX_QP_WR) || 325 (attrs->cap.max_recv_wr > SIW_MAX_QP_WR) || 326 (attrs->cap.max_send_sge > SIW_MAX_SGE) || 327 (attrs->cap.max_recv_sge > SIW_MAX_SGE)) { 328 siw_dbg(base_dev, "QP size error\n"); 329 rv = -EINVAL; 330 goto err_atomic; 331 } 332 if (attrs->cap.max_inline_data > SIW_MAX_INLINE) { 333 siw_dbg(base_dev, "max inline send: %d > %d\n", 334 attrs->cap.max_inline_data, (int)SIW_MAX_INLINE); 335 rv = -EINVAL; 336 goto err_atomic; 337 } 338 /* 339 * NOTE: we allow for zero element SQ and RQ WQE's SGL's 340 * but not for a QP unable to hold any WQE (SQ + RQ) 341 */ 342 if (attrs->cap.max_send_wr + attrs->cap.max_recv_wr == 0) { 343 siw_dbg(base_dev, "QP must have send or receive queue\n"); 344 rv = -EINVAL; 345 goto err_atomic; 346 } 347 348 if (!attrs->send_cq || (!attrs->recv_cq && !attrs->srq)) { 349 siw_dbg(base_dev, "send CQ or receive CQ invalid\n"); 350 rv = -EINVAL; 351 goto err_atomic; 352 } 353 354 init_rwsem(&qp->state_lock); 355 spin_lock_init(&qp->sq_lock); 356 spin_lock_init(&qp->rq_lock); 357 spin_lock_init(&qp->orq_lock); 358 359 rv = siw_qp_add(sdev, qp); 360 if (rv) 361 goto err_atomic; 362 363 num_sqe = attrs->cap.max_send_wr; 364 num_rqe = attrs->cap.max_recv_wr; 365 366 /* All queue indices are derived from modulo operations 367 * on a free running 'get' (consumer) and 'put' (producer) 368 * unsigned counter. Having queue sizes at power of two 369 * avoids handling counter wrap around. 370 */ 371 if (num_sqe) 372 num_sqe = roundup_pow_of_two(num_sqe); 373 else { 374 /* Zero sized SQ is not supported */ 375 rv = -EINVAL; 376 goto err_out_xa; 377 } 378 if (num_rqe) 379 num_rqe = roundup_pow_of_two(num_rqe); 380 381 if (udata) 382 qp->sendq = vmalloc_user(num_sqe * sizeof(struct siw_sqe)); 383 else 384 qp->sendq = vzalloc(num_sqe * sizeof(struct siw_sqe)); 385 386 if (qp->sendq == NULL) { 387 rv = -ENOMEM; 388 goto err_out_xa; 389 } 390 if (attrs->sq_sig_type != IB_SIGNAL_REQ_WR) { 391 if (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) 392 qp->attrs.flags |= SIW_SIGNAL_ALL_WR; 393 else { 394 rv = -EINVAL; 395 goto err_out_xa; 396 } 397 } 398 qp->pd = pd; 399 qp->scq = to_siw_cq(attrs->send_cq); 400 qp->rcq = to_siw_cq(attrs->recv_cq); 401 402 if (attrs->srq) { 403 /* 404 * SRQ support. 405 * Verbs 6.3.7: ignore RQ size, if SRQ present 406 * Verbs 6.3.5: do not check PD of SRQ against PD of QP 407 */ 408 qp->srq = to_siw_srq(attrs->srq); 409 qp->attrs.rq_size = 0; 410 siw_dbg(base_dev, "QP [%u]: SRQ attached\n", 411 qp->base_qp.qp_num); 412 } else if (num_rqe) { 413 if (udata) 414 qp->recvq = 415 vmalloc_user(num_rqe * sizeof(struct siw_rqe)); 416 else 417 qp->recvq = vzalloc(num_rqe * sizeof(struct siw_rqe)); 418 419 if (qp->recvq == NULL) { 420 rv = -ENOMEM; 421 goto err_out_xa; 422 } 423 qp->attrs.rq_size = num_rqe; 424 } 425 qp->attrs.sq_size = num_sqe; 426 qp->attrs.sq_max_sges = attrs->cap.max_send_sge; 427 qp->attrs.rq_max_sges = attrs->cap.max_recv_sge; 428 429 /* Make those two tunables fixed for now. */ 430 qp->tx_ctx.gso_seg_limit = 1; 431 qp->tx_ctx.zcopy_tx = zcopy_tx; 432 433 qp->attrs.state = SIW_QP_STATE_IDLE; 434 435 if (udata) { 436 struct siw_uresp_create_qp uresp = {}; 437 438 uresp.num_sqe = num_sqe; 439 uresp.num_rqe = num_rqe; 440 uresp.qp_id = qp_id(qp); 441 442 if (qp->sendq) { 443 length = num_sqe * sizeof(struct siw_sqe); 444 qp->sq_entry = 445 siw_mmap_entry_insert(uctx, qp->sendq, 446 length, &uresp.sq_key); 447 if (!qp->sq_entry) { 448 rv = -ENOMEM; 449 goto err_out_xa; 450 } 451 } 452 453 if (qp->recvq) { 454 length = num_rqe * sizeof(struct siw_rqe); 455 qp->rq_entry = 456 siw_mmap_entry_insert(uctx, qp->recvq, 457 length, &uresp.rq_key); 458 if (!qp->rq_entry) { 459 uresp.sq_key = SIW_INVAL_UOBJ_KEY; 460 rv = -ENOMEM; 461 goto err_out_xa; 462 } 463 } 464 465 if (udata->outlen < sizeof(uresp)) { 466 rv = -EINVAL; 467 goto err_out_xa; 468 } 469 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 470 if (rv) 471 goto err_out_xa; 472 } 473 qp->tx_cpu = siw_get_tx_cpu(sdev); 474 if (qp->tx_cpu < 0) { 475 rv = -EINVAL; 476 goto err_out_xa; 477 } 478 INIT_LIST_HEAD(&qp->devq); 479 spin_lock_irqsave(&sdev->lock, flags); 480 list_add_tail(&qp->devq, &sdev->qp_list); 481 spin_unlock_irqrestore(&sdev->lock, flags); 482 483 init_completion(&qp->qp_free); 484 485 return 0; 486 487 err_out_xa: 488 xa_erase(&sdev->qp_xa, qp_id(qp)); 489 if (uctx) { 490 rdma_user_mmap_entry_remove(qp->sq_entry); 491 rdma_user_mmap_entry_remove(qp->rq_entry); 492 } 493 vfree(qp->sendq); 494 vfree(qp->recvq); 495 496 err_atomic: 497 atomic_dec(&sdev->num_qp); 498 return rv; 499 } 500 501 /* 502 * Minimum siw_query_qp() verb interface. 503 * 504 * @qp_attr_mask is not used but all available information is provided 505 */ 506 int siw_query_qp(struct ib_qp *base_qp, struct ib_qp_attr *qp_attr, 507 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 508 { 509 struct siw_qp *qp; 510 struct siw_device *sdev; 511 512 if (base_qp && qp_attr && qp_init_attr) { 513 qp = to_siw_qp(base_qp); 514 sdev = to_siw_dev(base_qp->device); 515 } else { 516 return -EINVAL; 517 } 518 qp_attr->cap.max_inline_data = SIW_MAX_INLINE; 519 qp_attr->cap.max_send_wr = qp->attrs.sq_size; 520 qp_attr->cap.max_send_sge = qp->attrs.sq_max_sges; 521 qp_attr->cap.max_recv_wr = qp->attrs.rq_size; 522 qp_attr->cap.max_recv_sge = qp->attrs.rq_max_sges; 523 qp_attr->path_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu); 524 qp_attr->max_rd_atomic = qp->attrs.irq_size; 525 qp_attr->max_dest_rd_atomic = qp->attrs.orq_size; 526 527 qp_attr->qp_access_flags = IB_ACCESS_LOCAL_WRITE | 528 IB_ACCESS_REMOTE_WRITE | 529 IB_ACCESS_REMOTE_READ; 530 531 qp_init_attr->qp_type = base_qp->qp_type; 532 qp_init_attr->send_cq = base_qp->send_cq; 533 qp_init_attr->recv_cq = base_qp->recv_cq; 534 qp_init_attr->srq = base_qp->srq; 535 536 qp_init_attr->cap = qp_attr->cap; 537 538 return 0; 539 } 540 541 int siw_verbs_modify_qp(struct ib_qp *base_qp, struct ib_qp_attr *attr, 542 int attr_mask, struct ib_udata *udata) 543 { 544 struct siw_qp_attrs new_attrs; 545 enum siw_qp_attr_mask siw_attr_mask = 0; 546 struct siw_qp *qp = to_siw_qp(base_qp); 547 int rv = 0; 548 549 if (!attr_mask) 550 return 0; 551 552 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 553 return -EOPNOTSUPP; 554 555 memset(&new_attrs, 0, sizeof(new_attrs)); 556 557 if (attr_mask & IB_QP_ACCESS_FLAGS) { 558 siw_attr_mask = SIW_QP_ATTR_ACCESS_FLAGS; 559 560 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 561 new_attrs.flags |= SIW_RDMA_READ_ENABLED; 562 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 563 new_attrs.flags |= SIW_RDMA_WRITE_ENABLED; 564 if (attr->qp_access_flags & IB_ACCESS_MW_BIND) 565 new_attrs.flags |= SIW_RDMA_BIND_ENABLED; 566 } 567 if (attr_mask & IB_QP_STATE) { 568 siw_dbg_qp(qp, "desired IB QP state: %s\n", 569 ib_qp_state_to_string[attr->qp_state]); 570 571 new_attrs.state = ib_qp_state_to_siw_qp_state[attr->qp_state]; 572 573 if (new_attrs.state > SIW_QP_STATE_RTS) 574 qp->tx_ctx.tx_suspend = 1; 575 576 siw_attr_mask |= SIW_QP_ATTR_STATE; 577 } 578 if (!siw_attr_mask) 579 goto out; 580 581 down_write(&qp->state_lock); 582 583 rv = siw_qp_modify(qp, &new_attrs, siw_attr_mask); 584 585 up_write(&qp->state_lock); 586 out: 587 return rv; 588 } 589 590 int siw_destroy_qp(struct ib_qp *base_qp, struct ib_udata *udata) 591 { 592 struct siw_qp *qp = to_siw_qp(base_qp); 593 struct siw_ucontext *uctx = 594 rdma_udata_to_drv_context(udata, struct siw_ucontext, 595 base_ucontext); 596 struct siw_qp_attrs qp_attrs; 597 598 siw_dbg_qp(qp, "state %d\n", qp->attrs.state); 599 600 /* 601 * Mark QP as in process of destruction to prevent from 602 * any async callbacks to RDMA core 603 */ 604 qp->attrs.flags |= SIW_QP_IN_DESTROY; 605 qp->rx_stream.rx_suspend = 1; 606 607 if (uctx) { 608 rdma_user_mmap_entry_remove(qp->sq_entry); 609 rdma_user_mmap_entry_remove(qp->rq_entry); 610 } 611 612 down_write(&qp->state_lock); 613 614 qp_attrs.state = SIW_QP_STATE_ERROR; 615 siw_qp_modify(qp, &qp_attrs, SIW_QP_ATTR_STATE); 616 617 if (qp->cep) { 618 siw_cep_put(qp->cep); 619 qp->cep = NULL; 620 } 621 up_write(&qp->state_lock); 622 623 kfree(qp->tx_ctx.mpa_crc_hd); 624 kfree(qp->rx_stream.mpa_crc_hd); 625 626 qp->scq = qp->rcq = NULL; 627 628 siw_qp_put(qp); 629 wait_for_completion(&qp->qp_free); 630 631 return 0; 632 } 633 634 /* 635 * siw_copy_inline_sgl() 636 * 637 * Prepare sgl of inlined data for sending. For userland callers 638 * function checks if given buffer addresses and len's are within 639 * process context bounds. 640 * Data from all provided sge's are copied together into the wqe, 641 * referenced by a single sge. 642 */ 643 static int siw_copy_inline_sgl(const struct ib_send_wr *core_wr, 644 struct siw_sqe *sqe) 645 { 646 struct ib_sge *core_sge = core_wr->sg_list; 647 void *kbuf = &sqe->sge[1]; 648 int num_sge = core_wr->num_sge, bytes = 0; 649 650 sqe->sge[0].laddr = (uintptr_t)kbuf; 651 sqe->sge[0].lkey = 0; 652 653 while (num_sge--) { 654 if (!core_sge->length) { 655 core_sge++; 656 continue; 657 } 658 bytes += core_sge->length; 659 if (bytes > SIW_MAX_INLINE) { 660 bytes = -EINVAL; 661 break; 662 } 663 memcpy(kbuf, (void *)(uintptr_t)core_sge->addr, 664 core_sge->length); 665 666 kbuf += core_sge->length; 667 core_sge++; 668 } 669 sqe->sge[0].length = max(bytes, 0); 670 sqe->num_sge = bytes > 0 ? 1 : 0; 671 672 return bytes; 673 } 674 675 /* Complete SQ WR's without processing */ 676 static int siw_sq_flush_wr(struct siw_qp *qp, const struct ib_send_wr *wr, 677 const struct ib_send_wr **bad_wr) 678 { 679 struct siw_sqe sqe = {}; 680 int rv = 0; 681 682 while (wr) { 683 sqe.id = wr->wr_id; 684 sqe.opcode = wr->opcode; 685 rv = siw_sqe_complete(qp, &sqe, 0, SIW_WC_WR_FLUSH_ERR); 686 if (rv) { 687 if (bad_wr) 688 *bad_wr = wr; 689 break; 690 } 691 wr = wr->next; 692 } 693 return rv; 694 } 695 696 /* Complete RQ WR's without processing */ 697 static int siw_rq_flush_wr(struct siw_qp *qp, const struct ib_recv_wr *wr, 698 const struct ib_recv_wr **bad_wr) 699 { 700 struct siw_rqe rqe = {}; 701 int rv = 0; 702 703 while (wr) { 704 rqe.id = wr->wr_id; 705 rv = siw_rqe_complete(qp, &rqe, 0, 0, SIW_WC_WR_FLUSH_ERR); 706 if (rv) { 707 if (bad_wr) 708 *bad_wr = wr; 709 break; 710 } 711 wr = wr->next; 712 } 713 return rv; 714 } 715 716 /* 717 * siw_post_send() 718 * 719 * Post a list of S-WR's to a SQ. 720 * 721 * @base_qp: Base QP contained in siw QP 722 * @wr: Null terminated list of user WR's 723 * @bad_wr: Points to failing WR in case of synchronous failure. 724 */ 725 int siw_post_send(struct ib_qp *base_qp, const struct ib_send_wr *wr, 726 const struct ib_send_wr **bad_wr) 727 { 728 struct siw_qp *qp = to_siw_qp(base_qp); 729 struct siw_wqe *wqe = tx_wqe(qp); 730 731 unsigned long flags; 732 int rv = 0; 733 734 if (wr && !rdma_is_kernel_res(&qp->base_qp.res)) { 735 siw_dbg_qp(qp, "wr must be empty for user mapped sq\n"); 736 *bad_wr = wr; 737 return -EINVAL; 738 } 739 740 /* 741 * Try to acquire QP state lock. Must be non-blocking 742 * to accommodate kernel clients needs. 743 */ 744 if (!down_read_trylock(&qp->state_lock)) { 745 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 746 /* 747 * ERROR state is final, so we can be sure 748 * this state will not change as long as the QP 749 * exists. 750 * 751 * This handles an ib_drain_sq() call with 752 * a concurrent request to set the QP state 753 * to ERROR. 754 */ 755 rv = siw_sq_flush_wr(qp, wr, bad_wr); 756 } else { 757 siw_dbg_qp(qp, "QP locked, state %d\n", 758 qp->attrs.state); 759 *bad_wr = wr; 760 rv = -ENOTCONN; 761 } 762 return rv; 763 } 764 if (unlikely(qp->attrs.state != SIW_QP_STATE_RTS)) { 765 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 766 /* 767 * Immediately flush this WR to CQ, if QP 768 * is in ERROR state. SQ is guaranteed to 769 * be empty, so WR complets in-order. 770 * 771 * Typically triggered by ib_drain_sq(). 772 */ 773 rv = siw_sq_flush_wr(qp, wr, bad_wr); 774 } else { 775 siw_dbg_qp(qp, "QP out of state %d\n", 776 qp->attrs.state); 777 *bad_wr = wr; 778 rv = -ENOTCONN; 779 } 780 up_read(&qp->state_lock); 781 return rv; 782 } 783 spin_lock_irqsave(&qp->sq_lock, flags); 784 785 while (wr) { 786 u32 idx = qp->sq_put % qp->attrs.sq_size; 787 struct siw_sqe *sqe = &qp->sendq[idx]; 788 789 if (sqe->flags) { 790 siw_dbg_qp(qp, "sq full\n"); 791 rv = -ENOMEM; 792 break; 793 } 794 if (wr->num_sge > qp->attrs.sq_max_sges) { 795 siw_dbg_qp(qp, "too many sge's: %d\n", wr->num_sge); 796 rv = -EINVAL; 797 break; 798 } 799 sqe->id = wr->wr_id; 800 801 if ((wr->send_flags & IB_SEND_SIGNALED) || 802 (qp->attrs.flags & SIW_SIGNAL_ALL_WR)) 803 sqe->flags |= SIW_WQE_SIGNALLED; 804 805 if (wr->send_flags & IB_SEND_FENCE) 806 sqe->flags |= SIW_WQE_READ_FENCE; 807 808 switch (wr->opcode) { 809 case IB_WR_SEND: 810 case IB_WR_SEND_WITH_INV: 811 if (wr->send_flags & IB_SEND_SOLICITED) 812 sqe->flags |= SIW_WQE_SOLICITED; 813 814 if (!(wr->send_flags & IB_SEND_INLINE)) { 815 siw_copy_sgl(wr->sg_list, sqe->sge, 816 wr->num_sge); 817 sqe->num_sge = wr->num_sge; 818 } else { 819 rv = siw_copy_inline_sgl(wr, sqe); 820 if (rv <= 0) { 821 rv = -EINVAL; 822 break; 823 } 824 sqe->flags |= SIW_WQE_INLINE; 825 sqe->num_sge = 1; 826 } 827 if (wr->opcode == IB_WR_SEND) 828 sqe->opcode = SIW_OP_SEND; 829 else { 830 sqe->opcode = SIW_OP_SEND_REMOTE_INV; 831 sqe->rkey = wr->ex.invalidate_rkey; 832 } 833 break; 834 835 case IB_WR_RDMA_READ_WITH_INV: 836 case IB_WR_RDMA_READ: 837 /* 838 * iWarp restricts RREAD sink to SGL containing 839 * 1 SGE only. we could relax to SGL with multiple 840 * elements referring the SAME ltag or even sending 841 * a private per-rreq tag referring to a checked 842 * local sgl with MULTIPLE ltag's. 843 */ 844 if (unlikely(wr->num_sge != 1)) { 845 rv = -EINVAL; 846 break; 847 } 848 siw_copy_sgl(wr->sg_list, &sqe->sge[0], 1); 849 /* 850 * NOTE: zero length RREAD is allowed! 851 */ 852 sqe->raddr = rdma_wr(wr)->remote_addr; 853 sqe->rkey = rdma_wr(wr)->rkey; 854 sqe->num_sge = 1; 855 856 if (wr->opcode == IB_WR_RDMA_READ) 857 sqe->opcode = SIW_OP_READ; 858 else 859 sqe->opcode = SIW_OP_READ_LOCAL_INV; 860 break; 861 862 case IB_WR_RDMA_WRITE: 863 if (!(wr->send_flags & IB_SEND_INLINE)) { 864 siw_copy_sgl(wr->sg_list, &sqe->sge[0], 865 wr->num_sge); 866 sqe->num_sge = wr->num_sge; 867 } else { 868 rv = siw_copy_inline_sgl(wr, sqe); 869 if (unlikely(rv < 0)) { 870 rv = -EINVAL; 871 break; 872 } 873 sqe->flags |= SIW_WQE_INLINE; 874 sqe->num_sge = 1; 875 } 876 sqe->raddr = rdma_wr(wr)->remote_addr; 877 sqe->rkey = rdma_wr(wr)->rkey; 878 sqe->opcode = SIW_OP_WRITE; 879 break; 880 881 case IB_WR_REG_MR: 882 sqe->base_mr = (uintptr_t)reg_wr(wr)->mr; 883 sqe->rkey = reg_wr(wr)->key; 884 sqe->access = reg_wr(wr)->access & IWARP_ACCESS_MASK; 885 sqe->opcode = SIW_OP_REG_MR; 886 break; 887 888 case IB_WR_LOCAL_INV: 889 sqe->rkey = wr->ex.invalidate_rkey; 890 sqe->opcode = SIW_OP_INVAL_STAG; 891 break; 892 893 default: 894 siw_dbg_qp(qp, "ib wr type %d unsupported\n", 895 wr->opcode); 896 rv = -EINVAL; 897 break; 898 } 899 siw_dbg_qp(qp, "opcode %d, flags 0x%x, wr_id 0x%pK\n", 900 sqe->opcode, sqe->flags, 901 (void *)(uintptr_t)sqe->id); 902 903 if (unlikely(rv < 0)) 904 break; 905 906 /* make SQE only valid after completely written */ 907 smp_wmb(); 908 sqe->flags |= SIW_WQE_VALID; 909 910 qp->sq_put++; 911 wr = wr->next; 912 } 913 914 /* 915 * Send directly if SQ processing is not in progress. 916 * Eventual immediate errors (rv < 0) do not affect the involved 917 * RI resources (Verbs, 8.3.1) and thus do not prevent from SQ 918 * processing, if new work is already pending. But rv must be passed 919 * to caller. 920 */ 921 if (wqe->wr_status != SIW_WR_IDLE) { 922 spin_unlock_irqrestore(&qp->sq_lock, flags); 923 goto skip_direct_sending; 924 } 925 rv = siw_activate_tx(qp); 926 spin_unlock_irqrestore(&qp->sq_lock, flags); 927 928 if (rv <= 0) 929 goto skip_direct_sending; 930 931 if (rdma_is_kernel_res(&qp->base_qp.res)) { 932 rv = siw_sq_start(qp); 933 } else { 934 qp->tx_ctx.in_syscall = 1; 935 936 if (siw_qp_sq_process(qp) != 0 && !(qp->tx_ctx.tx_suspend)) 937 siw_qp_cm_drop(qp, 0); 938 939 qp->tx_ctx.in_syscall = 0; 940 } 941 skip_direct_sending: 942 943 up_read(&qp->state_lock); 944 945 if (rv >= 0) 946 return 0; 947 /* 948 * Immediate error 949 */ 950 siw_dbg_qp(qp, "error %d\n", rv); 951 952 *bad_wr = wr; 953 return rv; 954 } 955 956 /* 957 * siw_post_receive() 958 * 959 * Post a list of R-WR's to a RQ. 960 * 961 * @base_qp: Base QP contained in siw QP 962 * @wr: Null terminated list of user WR's 963 * @bad_wr: Points to failing WR in case of synchronous failure. 964 */ 965 int siw_post_receive(struct ib_qp *base_qp, const struct ib_recv_wr *wr, 966 const struct ib_recv_wr **bad_wr) 967 { 968 struct siw_qp *qp = to_siw_qp(base_qp); 969 unsigned long flags; 970 int rv = 0; 971 972 if (qp->srq || qp->attrs.rq_size == 0) { 973 *bad_wr = wr; 974 return -EINVAL; 975 } 976 if (!rdma_is_kernel_res(&qp->base_qp.res)) { 977 siw_dbg_qp(qp, "no kernel post_recv for user mapped rq\n"); 978 *bad_wr = wr; 979 return -EINVAL; 980 } 981 982 /* 983 * Try to acquire QP state lock. Must be non-blocking 984 * to accommodate kernel clients needs. 985 */ 986 if (!down_read_trylock(&qp->state_lock)) { 987 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 988 /* 989 * ERROR state is final, so we can be sure 990 * this state will not change as long as the QP 991 * exists. 992 * 993 * This handles an ib_drain_rq() call with 994 * a concurrent request to set the QP state 995 * to ERROR. 996 */ 997 rv = siw_rq_flush_wr(qp, wr, bad_wr); 998 } else { 999 siw_dbg_qp(qp, "QP locked, state %d\n", 1000 qp->attrs.state); 1001 *bad_wr = wr; 1002 rv = -ENOTCONN; 1003 } 1004 return rv; 1005 } 1006 if (qp->attrs.state > SIW_QP_STATE_RTS) { 1007 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 1008 /* 1009 * Immediately flush this WR to CQ, if QP 1010 * is in ERROR state. RQ is guaranteed to 1011 * be empty, so WR complets in-order. 1012 * 1013 * Typically triggered by ib_drain_rq(). 1014 */ 1015 rv = siw_rq_flush_wr(qp, wr, bad_wr); 1016 } else { 1017 siw_dbg_qp(qp, "QP out of state %d\n", 1018 qp->attrs.state); 1019 *bad_wr = wr; 1020 rv = -ENOTCONN; 1021 } 1022 up_read(&qp->state_lock); 1023 return rv; 1024 } 1025 /* 1026 * Serialize potentially multiple producers. 1027 * Not needed for single threaded consumer side. 1028 */ 1029 spin_lock_irqsave(&qp->rq_lock, flags); 1030 1031 while (wr) { 1032 u32 idx = qp->rq_put % qp->attrs.rq_size; 1033 struct siw_rqe *rqe = &qp->recvq[idx]; 1034 1035 if (rqe->flags) { 1036 siw_dbg_qp(qp, "RQ full\n"); 1037 rv = -ENOMEM; 1038 break; 1039 } 1040 if (wr->num_sge > qp->attrs.rq_max_sges) { 1041 siw_dbg_qp(qp, "too many sge's: %d\n", wr->num_sge); 1042 rv = -EINVAL; 1043 break; 1044 } 1045 rqe->id = wr->wr_id; 1046 rqe->num_sge = wr->num_sge; 1047 siw_copy_sgl(wr->sg_list, rqe->sge, wr->num_sge); 1048 1049 /* make sure RQE is completely written before valid */ 1050 smp_wmb(); 1051 1052 rqe->flags = SIW_WQE_VALID; 1053 1054 qp->rq_put++; 1055 wr = wr->next; 1056 } 1057 spin_unlock_irqrestore(&qp->rq_lock, flags); 1058 1059 up_read(&qp->state_lock); 1060 1061 if (rv < 0) { 1062 siw_dbg_qp(qp, "error %d\n", rv); 1063 *bad_wr = wr; 1064 } 1065 return rv > 0 ? 0 : rv; 1066 } 1067 1068 int siw_destroy_cq(struct ib_cq *base_cq, struct ib_udata *udata) 1069 { 1070 struct siw_cq *cq = to_siw_cq(base_cq); 1071 struct siw_device *sdev = to_siw_dev(base_cq->device); 1072 struct siw_ucontext *ctx = 1073 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1074 base_ucontext); 1075 1076 siw_dbg_cq(cq, "free CQ resources\n"); 1077 1078 siw_cq_flush(cq); 1079 1080 if (ctx) 1081 rdma_user_mmap_entry_remove(cq->cq_entry); 1082 1083 atomic_dec(&sdev->num_cq); 1084 1085 vfree(cq->queue); 1086 return 0; 1087 } 1088 1089 /* 1090 * siw_create_cq() 1091 * 1092 * Populate CQ of requested size 1093 * 1094 * @base_cq: CQ as allocated by RDMA midlayer 1095 * @attr: Initial CQ attributes 1096 * @udata: relates to user context 1097 */ 1098 1099 int siw_create_cq(struct ib_cq *base_cq, const struct ib_cq_init_attr *attr, 1100 struct ib_udata *udata) 1101 { 1102 struct siw_device *sdev = to_siw_dev(base_cq->device); 1103 struct siw_cq *cq = to_siw_cq(base_cq); 1104 int rv, size = attr->cqe; 1105 1106 if (attr->flags) 1107 return -EOPNOTSUPP; 1108 1109 if (atomic_inc_return(&sdev->num_cq) > SIW_MAX_CQ) { 1110 siw_dbg(base_cq->device, "too many CQ's\n"); 1111 rv = -ENOMEM; 1112 goto err_out; 1113 } 1114 if (size < 1 || size > sdev->attrs.max_cqe) { 1115 siw_dbg(base_cq->device, "CQ size error: %d\n", size); 1116 rv = -EINVAL; 1117 goto err_out; 1118 } 1119 size = roundup_pow_of_two(size); 1120 cq->base_cq.cqe = size; 1121 cq->num_cqe = size; 1122 1123 if (udata) 1124 cq->queue = vmalloc_user(size * sizeof(struct siw_cqe) + 1125 sizeof(struct siw_cq_ctrl)); 1126 else 1127 cq->queue = vzalloc(size * sizeof(struct siw_cqe) + 1128 sizeof(struct siw_cq_ctrl)); 1129 1130 if (cq->queue == NULL) { 1131 rv = -ENOMEM; 1132 goto err_out; 1133 } 1134 get_random_bytes(&cq->id, 4); 1135 siw_dbg(base_cq->device, "new CQ [%u]\n", cq->id); 1136 1137 spin_lock_init(&cq->lock); 1138 1139 cq->notify = (struct siw_cq_ctrl *)&cq->queue[size]; 1140 1141 if (udata) { 1142 struct siw_uresp_create_cq uresp = {}; 1143 struct siw_ucontext *ctx = 1144 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1145 base_ucontext); 1146 size_t length = size * sizeof(struct siw_cqe) + 1147 sizeof(struct siw_cq_ctrl); 1148 1149 cq->cq_entry = 1150 siw_mmap_entry_insert(ctx, cq->queue, 1151 length, &uresp.cq_key); 1152 if (!cq->cq_entry) { 1153 rv = -ENOMEM; 1154 goto err_out; 1155 } 1156 1157 uresp.cq_id = cq->id; 1158 uresp.num_cqe = size; 1159 1160 if (udata->outlen < sizeof(uresp)) { 1161 rv = -EINVAL; 1162 goto err_out; 1163 } 1164 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1165 if (rv) 1166 goto err_out; 1167 } 1168 return 0; 1169 1170 err_out: 1171 siw_dbg(base_cq->device, "CQ creation failed: %d", rv); 1172 1173 if (cq->queue) { 1174 struct siw_ucontext *ctx = 1175 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1176 base_ucontext); 1177 if (ctx) 1178 rdma_user_mmap_entry_remove(cq->cq_entry); 1179 vfree(cq->queue); 1180 } 1181 atomic_dec(&sdev->num_cq); 1182 1183 return rv; 1184 } 1185 1186 /* 1187 * siw_poll_cq() 1188 * 1189 * Reap CQ entries if available and copy work completion status into 1190 * array of WC's provided by caller. Returns number of reaped CQE's. 1191 * 1192 * @base_cq: Base CQ contained in siw CQ. 1193 * @num_cqe: Maximum number of CQE's to reap. 1194 * @wc: Array of work completions to be filled by siw. 1195 */ 1196 int siw_poll_cq(struct ib_cq *base_cq, int num_cqe, struct ib_wc *wc) 1197 { 1198 struct siw_cq *cq = to_siw_cq(base_cq); 1199 int i; 1200 1201 for (i = 0; i < num_cqe; i++) { 1202 if (!siw_reap_cqe(cq, wc)) 1203 break; 1204 wc++; 1205 } 1206 return i; 1207 } 1208 1209 /* 1210 * siw_req_notify_cq() 1211 * 1212 * Request notification for new CQE's added to that CQ. 1213 * Defined flags: 1214 * o SIW_CQ_NOTIFY_SOLICITED lets siw trigger a notification 1215 * event if a WQE with notification flag set enters the CQ 1216 * o SIW_CQ_NOTIFY_NEXT_COMP lets siw trigger a notification 1217 * event if a WQE enters the CQ. 1218 * o IB_CQ_REPORT_MISSED_EVENTS: return value will provide the 1219 * number of not reaped CQE's regardless of its notification 1220 * type and current or new CQ notification settings. 1221 * 1222 * @base_cq: Base CQ contained in siw CQ. 1223 * @flags: Requested notification flags. 1224 */ 1225 int siw_req_notify_cq(struct ib_cq *base_cq, enum ib_cq_notify_flags flags) 1226 { 1227 struct siw_cq *cq = to_siw_cq(base_cq); 1228 1229 siw_dbg_cq(cq, "flags: 0x%02x\n", flags); 1230 1231 if ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED) 1232 /* 1233 * Enable CQ event for next solicited completion. 1234 * and make it visible to all associated producers. 1235 */ 1236 smp_store_mb(cq->notify->flags, SIW_NOTIFY_SOLICITED); 1237 else 1238 /* 1239 * Enable CQ event for any signalled completion. 1240 * and make it visible to all associated producers. 1241 */ 1242 smp_store_mb(cq->notify->flags, SIW_NOTIFY_ALL); 1243 1244 if (flags & IB_CQ_REPORT_MISSED_EVENTS) 1245 return cq->cq_put - cq->cq_get; 1246 1247 return 0; 1248 } 1249 1250 /* 1251 * siw_dereg_mr() 1252 * 1253 * Release Memory Region. 1254 * 1255 * @base_mr: Base MR contained in siw MR. 1256 * @udata: points to user context, unused. 1257 */ 1258 int siw_dereg_mr(struct ib_mr *base_mr, struct ib_udata *udata) 1259 { 1260 struct siw_mr *mr = to_siw_mr(base_mr); 1261 struct siw_device *sdev = to_siw_dev(base_mr->device); 1262 1263 siw_dbg_mem(mr->mem, "deregister MR\n"); 1264 1265 atomic_dec(&sdev->num_mr); 1266 1267 siw_mr_drop_mem(mr); 1268 kfree_rcu(mr, rcu); 1269 1270 return 0; 1271 } 1272 1273 /* 1274 * siw_reg_user_mr() 1275 * 1276 * Register Memory Region. 1277 * 1278 * @pd: Protection Domain 1279 * @start: starting address of MR (virtual address) 1280 * @len: len of MR 1281 * @rnic_va: not used by siw 1282 * @rights: MR access rights 1283 * @udata: user buffer to communicate STag and Key. 1284 */ 1285 struct ib_mr *siw_reg_user_mr(struct ib_pd *pd, u64 start, u64 len, 1286 u64 rnic_va, int rights, struct ib_udata *udata) 1287 { 1288 struct siw_mr *mr = NULL; 1289 struct siw_umem *umem = NULL; 1290 struct siw_ureq_reg_mr ureq; 1291 struct siw_device *sdev = to_siw_dev(pd->device); 1292 1293 unsigned long mem_limit = rlimit(RLIMIT_MEMLOCK); 1294 int rv; 1295 1296 siw_dbg_pd(pd, "start: 0x%pK, va: 0x%pK, len: %llu\n", 1297 (void *)(uintptr_t)start, (void *)(uintptr_t)rnic_va, 1298 (unsigned long long)len); 1299 1300 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1301 siw_dbg_pd(pd, "too many mr's\n"); 1302 rv = -ENOMEM; 1303 goto err_out; 1304 } 1305 if (!len) { 1306 rv = -EINVAL; 1307 goto err_out; 1308 } 1309 if (mem_limit != RLIM_INFINITY) { 1310 unsigned long num_pages = 1311 (PAGE_ALIGN(len + (start & ~PAGE_MASK))) >> PAGE_SHIFT; 1312 mem_limit >>= PAGE_SHIFT; 1313 1314 if (num_pages > mem_limit - current->mm->locked_vm) { 1315 siw_dbg_pd(pd, "pages req %lu, max %lu, lock %lu\n", 1316 num_pages, mem_limit, 1317 current->mm->locked_vm); 1318 rv = -ENOMEM; 1319 goto err_out; 1320 } 1321 } 1322 umem = siw_umem_get(start, len, ib_access_writable(rights)); 1323 if (IS_ERR(umem)) { 1324 rv = PTR_ERR(umem); 1325 siw_dbg_pd(pd, "getting user memory failed: %d\n", rv); 1326 umem = NULL; 1327 goto err_out; 1328 } 1329 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1330 if (!mr) { 1331 rv = -ENOMEM; 1332 goto err_out; 1333 } 1334 rv = siw_mr_add_mem(mr, pd, umem, start, len, rights); 1335 if (rv) 1336 goto err_out; 1337 1338 if (udata) { 1339 struct siw_uresp_reg_mr uresp = {}; 1340 struct siw_mem *mem = mr->mem; 1341 1342 if (udata->inlen < sizeof(ureq)) { 1343 rv = -EINVAL; 1344 goto err_out; 1345 } 1346 rv = ib_copy_from_udata(&ureq, udata, sizeof(ureq)); 1347 if (rv) 1348 goto err_out; 1349 1350 mr->base_mr.lkey |= ureq.stag_key; 1351 mr->base_mr.rkey |= ureq.stag_key; 1352 mem->stag |= ureq.stag_key; 1353 uresp.stag = mem->stag; 1354 1355 if (udata->outlen < sizeof(uresp)) { 1356 rv = -EINVAL; 1357 goto err_out; 1358 } 1359 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1360 if (rv) 1361 goto err_out; 1362 } 1363 mr->mem->stag_valid = 1; 1364 1365 return &mr->base_mr; 1366 1367 err_out: 1368 atomic_dec(&sdev->num_mr); 1369 if (mr) { 1370 if (mr->mem) 1371 siw_mr_drop_mem(mr); 1372 kfree_rcu(mr, rcu); 1373 } else { 1374 if (umem) 1375 siw_umem_release(umem, false); 1376 } 1377 return ERR_PTR(rv); 1378 } 1379 1380 struct ib_mr *siw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1381 u32 max_sge) 1382 { 1383 struct siw_device *sdev = to_siw_dev(pd->device); 1384 struct siw_mr *mr = NULL; 1385 struct siw_pbl *pbl = NULL; 1386 int rv; 1387 1388 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1389 siw_dbg_pd(pd, "too many mr's\n"); 1390 rv = -ENOMEM; 1391 goto err_out; 1392 } 1393 if (mr_type != IB_MR_TYPE_MEM_REG) { 1394 siw_dbg_pd(pd, "mr type %d unsupported\n", mr_type); 1395 rv = -EOPNOTSUPP; 1396 goto err_out; 1397 } 1398 if (max_sge > SIW_MAX_SGE_PBL) { 1399 siw_dbg_pd(pd, "too many sge's: %d\n", max_sge); 1400 rv = -ENOMEM; 1401 goto err_out; 1402 } 1403 pbl = siw_pbl_alloc(max_sge); 1404 if (IS_ERR(pbl)) { 1405 rv = PTR_ERR(pbl); 1406 siw_dbg_pd(pd, "pbl allocation failed: %d\n", rv); 1407 pbl = NULL; 1408 goto err_out; 1409 } 1410 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1411 if (!mr) { 1412 rv = -ENOMEM; 1413 goto err_out; 1414 } 1415 rv = siw_mr_add_mem(mr, pd, pbl, 0, max_sge * PAGE_SIZE, 0); 1416 if (rv) 1417 goto err_out; 1418 1419 mr->mem->is_pbl = 1; 1420 1421 siw_dbg_pd(pd, "[MEM %u]: success\n", mr->mem->stag); 1422 1423 return &mr->base_mr; 1424 1425 err_out: 1426 atomic_dec(&sdev->num_mr); 1427 1428 if (!mr) { 1429 kfree(pbl); 1430 } else { 1431 if (mr->mem) 1432 siw_mr_drop_mem(mr); 1433 kfree_rcu(mr, rcu); 1434 } 1435 siw_dbg_pd(pd, "failed: %d\n", rv); 1436 1437 return ERR_PTR(rv); 1438 } 1439 1440 /* Just used to count number of pages being mapped */ 1441 static int siw_set_pbl_page(struct ib_mr *base_mr, u64 buf_addr) 1442 { 1443 return 0; 1444 } 1445 1446 int siw_map_mr_sg(struct ib_mr *base_mr, struct scatterlist *sl, int num_sle, 1447 unsigned int *sg_off) 1448 { 1449 struct scatterlist *slp; 1450 struct siw_mr *mr = to_siw_mr(base_mr); 1451 struct siw_mem *mem = mr->mem; 1452 struct siw_pbl *pbl = mem->pbl; 1453 struct siw_pble *pble; 1454 unsigned long pbl_size; 1455 int i, rv; 1456 1457 if (!pbl) { 1458 siw_dbg_mem(mem, "no PBL allocated\n"); 1459 return -EINVAL; 1460 } 1461 pble = pbl->pbe; 1462 1463 if (pbl->max_buf < num_sle) { 1464 siw_dbg_mem(mem, "too many SGE's: %d > %d\n", 1465 mem->pbl->max_buf, num_sle); 1466 return -ENOMEM; 1467 } 1468 for_each_sg(sl, slp, num_sle, i) { 1469 if (sg_dma_len(slp) == 0) { 1470 siw_dbg_mem(mem, "empty SGE\n"); 1471 return -EINVAL; 1472 } 1473 if (i == 0) { 1474 pble->addr = sg_dma_address(slp); 1475 pble->size = sg_dma_len(slp); 1476 pble->pbl_off = 0; 1477 pbl_size = pble->size; 1478 pbl->num_buf = 1; 1479 } else { 1480 /* Merge PBL entries if adjacent */ 1481 if (pble->addr + pble->size == sg_dma_address(slp)) { 1482 pble->size += sg_dma_len(slp); 1483 } else { 1484 pble++; 1485 pbl->num_buf++; 1486 pble->addr = sg_dma_address(slp); 1487 pble->size = sg_dma_len(slp); 1488 pble->pbl_off = pbl_size; 1489 } 1490 pbl_size += sg_dma_len(slp); 1491 } 1492 siw_dbg_mem(mem, 1493 "sge[%d], size %u, addr 0x%p, total %lu\n", 1494 i, pble->size, (void *)(uintptr_t)pble->addr, 1495 pbl_size); 1496 } 1497 rv = ib_sg_to_pages(base_mr, sl, num_sle, sg_off, siw_set_pbl_page); 1498 if (rv > 0) { 1499 mem->len = base_mr->length; 1500 mem->va = base_mr->iova; 1501 siw_dbg_mem(mem, 1502 "%llu bytes, start 0x%pK, %u SLE to %u entries\n", 1503 mem->len, (void *)(uintptr_t)mem->va, num_sle, 1504 pbl->num_buf); 1505 } 1506 return rv; 1507 } 1508 1509 /* 1510 * siw_get_dma_mr() 1511 * 1512 * Create a (empty) DMA memory region, where no umem is attached. 1513 */ 1514 struct ib_mr *siw_get_dma_mr(struct ib_pd *pd, int rights) 1515 { 1516 struct siw_device *sdev = to_siw_dev(pd->device); 1517 struct siw_mr *mr = NULL; 1518 int rv; 1519 1520 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1521 siw_dbg_pd(pd, "too many mr's\n"); 1522 rv = -ENOMEM; 1523 goto err_out; 1524 } 1525 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1526 if (!mr) { 1527 rv = -ENOMEM; 1528 goto err_out; 1529 } 1530 rv = siw_mr_add_mem(mr, pd, NULL, 0, ULONG_MAX, rights); 1531 if (rv) 1532 goto err_out; 1533 1534 mr->mem->stag_valid = 1; 1535 1536 siw_dbg_pd(pd, "[MEM %u]: success\n", mr->mem->stag); 1537 1538 return &mr->base_mr; 1539 1540 err_out: 1541 if (rv) 1542 kfree(mr); 1543 1544 atomic_dec(&sdev->num_mr); 1545 1546 return ERR_PTR(rv); 1547 } 1548 1549 /* 1550 * siw_create_srq() 1551 * 1552 * Create Shared Receive Queue of attributes @init_attrs 1553 * within protection domain given by @pd. 1554 * 1555 * @base_srq: Base SRQ contained in siw SRQ. 1556 * @init_attrs: SRQ init attributes. 1557 * @udata: points to user context 1558 */ 1559 int siw_create_srq(struct ib_srq *base_srq, 1560 struct ib_srq_init_attr *init_attrs, struct ib_udata *udata) 1561 { 1562 struct siw_srq *srq = to_siw_srq(base_srq); 1563 struct ib_srq_attr *attrs = &init_attrs->attr; 1564 struct siw_device *sdev = to_siw_dev(base_srq->device); 1565 struct siw_ucontext *ctx = 1566 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1567 base_ucontext); 1568 int rv; 1569 1570 if (init_attrs->srq_type != IB_SRQT_BASIC) 1571 return -EOPNOTSUPP; 1572 1573 if (atomic_inc_return(&sdev->num_srq) > SIW_MAX_SRQ) { 1574 siw_dbg_pd(base_srq->pd, "too many SRQ's\n"); 1575 rv = -ENOMEM; 1576 goto err_out; 1577 } 1578 if (attrs->max_wr == 0 || attrs->max_wr > SIW_MAX_SRQ_WR || 1579 attrs->max_sge > SIW_MAX_SGE || attrs->srq_limit > attrs->max_wr) { 1580 rv = -EINVAL; 1581 goto err_out; 1582 } 1583 srq->max_sge = attrs->max_sge; 1584 srq->num_rqe = roundup_pow_of_two(attrs->max_wr); 1585 srq->limit = attrs->srq_limit; 1586 if (srq->limit) 1587 srq->armed = true; 1588 1589 srq->is_kernel_res = !udata; 1590 1591 if (udata) 1592 srq->recvq = 1593 vmalloc_user(srq->num_rqe * sizeof(struct siw_rqe)); 1594 else 1595 srq->recvq = vzalloc(srq->num_rqe * sizeof(struct siw_rqe)); 1596 1597 if (srq->recvq == NULL) { 1598 rv = -ENOMEM; 1599 goto err_out; 1600 } 1601 if (udata) { 1602 struct siw_uresp_create_srq uresp = {}; 1603 size_t length = srq->num_rqe * sizeof(struct siw_rqe); 1604 1605 srq->srq_entry = 1606 siw_mmap_entry_insert(ctx, srq->recvq, 1607 length, &uresp.srq_key); 1608 if (!srq->srq_entry) { 1609 rv = -ENOMEM; 1610 goto err_out; 1611 } 1612 1613 uresp.num_rqe = srq->num_rqe; 1614 1615 if (udata->outlen < sizeof(uresp)) { 1616 rv = -EINVAL; 1617 goto err_out; 1618 } 1619 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1620 if (rv) 1621 goto err_out; 1622 } 1623 spin_lock_init(&srq->lock); 1624 1625 siw_dbg_pd(base_srq->pd, "[SRQ]: success\n"); 1626 1627 return 0; 1628 1629 err_out: 1630 if (srq->recvq) { 1631 if (ctx) 1632 rdma_user_mmap_entry_remove(srq->srq_entry); 1633 vfree(srq->recvq); 1634 } 1635 atomic_dec(&sdev->num_srq); 1636 1637 return rv; 1638 } 1639 1640 /* 1641 * siw_modify_srq() 1642 * 1643 * Modify SRQ. The caller may resize SRQ and/or set/reset notification 1644 * limit and (re)arm IB_EVENT_SRQ_LIMIT_REACHED notification. 1645 * 1646 * NOTE: it is unclear if RDMA core allows for changing the MAX_SGE 1647 * parameter. siw_modify_srq() does not check the attrs->max_sge param. 1648 */ 1649 int siw_modify_srq(struct ib_srq *base_srq, struct ib_srq_attr *attrs, 1650 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata) 1651 { 1652 struct siw_srq *srq = to_siw_srq(base_srq); 1653 unsigned long flags; 1654 int rv = 0; 1655 1656 spin_lock_irqsave(&srq->lock, flags); 1657 1658 if (attr_mask & IB_SRQ_MAX_WR) { 1659 /* resize request not yet supported */ 1660 rv = -EOPNOTSUPP; 1661 goto out; 1662 } 1663 if (attr_mask & IB_SRQ_LIMIT) { 1664 if (attrs->srq_limit) { 1665 if (unlikely(attrs->srq_limit > srq->num_rqe)) { 1666 rv = -EINVAL; 1667 goto out; 1668 } 1669 srq->armed = true; 1670 } else { 1671 srq->armed = false; 1672 } 1673 srq->limit = attrs->srq_limit; 1674 } 1675 out: 1676 spin_unlock_irqrestore(&srq->lock, flags); 1677 1678 return rv; 1679 } 1680 1681 /* 1682 * siw_query_srq() 1683 * 1684 * Query SRQ attributes. 1685 */ 1686 int siw_query_srq(struct ib_srq *base_srq, struct ib_srq_attr *attrs) 1687 { 1688 struct siw_srq *srq = to_siw_srq(base_srq); 1689 unsigned long flags; 1690 1691 spin_lock_irqsave(&srq->lock, flags); 1692 1693 attrs->max_wr = srq->num_rqe; 1694 attrs->max_sge = srq->max_sge; 1695 attrs->srq_limit = srq->limit; 1696 1697 spin_unlock_irqrestore(&srq->lock, flags); 1698 1699 return 0; 1700 } 1701 1702 /* 1703 * siw_destroy_srq() 1704 * 1705 * Destroy SRQ. 1706 * It is assumed that the SRQ is not referenced by any 1707 * QP anymore - the code trusts the RDMA core environment to keep track 1708 * of QP references. 1709 */ 1710 int siw_destroy_srq(struct ib_srq *base_srq, struct ib_udata *udata) 1711 { 1712 struct siw_srq *srq = to_siw_srq(base_srq); 1713 struct siw_device *sdev = to_siw_dev(base_srq->device); 1714 struct siw_ucontext *ctx = 1715 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1716 base_ucontext); 1717 1718 if (ctx) 1719 rdma_user_mmap_entry_remove(srq->srq_entry); 1720 vfree(srq->recvq); 1721 atomic_dec(&sdev->num_srq); 1722 return 0; 1723 } 1724 1725 /* 1726 * siw_post_srq_recv() 1727 * 1728 * Post a list of receive queue elements to SRQ. 1729 * NOTE: The function does not check or lock a certain SRQ state 1730 * during the post operation. The code simply trusts the 1731 * RDMA core environment. 1732 * 1733 * @base_srq: Base SRQ contained in siw SRQ 1734 * @wr: List of R-WR's 1735 * @bad_wr: Updated to failing WR if posting fails. 1736 */ 1737 int siw_post_srq_recv(struct ib_srq *base_srq, const struct ib_recv_wr *wr, 1738 const struct ib_recv_wr **bad_wr) 1739 { 1740 struct siw_srq *srq = to_siw_srq(base_srq); 1741 unsigned long flags; 1742 int rv = 0; 1743 1744 if (unlikely(!srq->is_kernel_res)) { 1745 siw_dbg_pd(base_srq->pd, 1746 "[SRQ]: no kernel post_recv for mapped srq\n"); 1747 rv = -EINVAL; 1748 goto out; 1749 } 1750 /* 1751 * Serialize potentially multiple producers. 1752 * Also needed to serialize potentially multiple 1753 * consumers. 1754 */ 1755 spin_lock_irqsave(&srq->lock, flags); 1756 1757 while (wr) { 1758 u32 idx = srq->rq_put % srq->num_rqe; 1759 struct siw_rqe *rqe = &srq->recvq[idx]; 1760 1761 if (rqe->flags) { 1762 siw_dbg_pd(base_srq->pd, "SRQ full\n"); 1763 rv = -ENOMEM; 1764 break; 1765 } 1766 if (unlikely(wr->num_sge > srq->max_sge)) { 1767 siw_dbg_pd(base_srq->pd, 1768 "[SRQ]: too many sge's: %d\n", wr->num_sge); 1769 rv = -EINVAL; 1770 break; 1771 } 1772 rqe->id = wr->wr_id; 1773 rqe->num_sge = wr->num_sge; 1774 siw_copy_sgl(wr->sg_list, rqe->sge, wr->num_sge); 1775 1776 /* Make sure S-RQE is completely written before valid */ 1777 smp_wmb(); 1778 1779 rqe->flags = SIW_WQE_VALID; 1780 1781 srq->rq_put++; 1782 wr = wr->next; 1783 } 1784 spin_unlock_irqrestore(&srq->lock, flags); 1785 out: 1786 if (unlikely(rv < 0)) { 1787 siw_dbg_pd(base_srq->pd, "[SRQ]: error %d\n", rv); 1788 *bad_wr = wr; 1789 } 1790 return rv; 1791 } 1792 1793 void siw_qp_event(struct siw_qp *qp, enum ib_event_type etype) 1794 { 1795 struct ib_event event; 1796 struct ib_qp *base_qp = &qp->base_qp; 1797 1798 /* 1799 * Do not report asynchronous errors on QP which gets 1800 * destroyed via verbs interface (siw_destroy_qp()) 1801 */ 1802 if (qp->attrs.flags & SIW_QP_IN_DESTROY) 1803 return; 1804 1805 event.event = etype; 1806 event.device = base_qp->device; 1807 event.element.qp = base_qp; 1808 1809 if (base_qp->event_handler) { 1810 siw_dbg_qp(qp, "reporting event %d\n", etype); 1811 base_qp->event_handler(&event, base_qp->qp_context); 1812 } 1813 } 1814 1815 void siw_cq_event(struct siw_cq *cq, enum ib_event_type etype) 1816 { 1817 struct ib_event event; 1818 struct ib_cq *base_cq = &cq->base_cq; 1819 1820 event.event = etype; 1821 event.device = base_cq->device; 1822 event.element.cq = base_cq; 1823 1824 if (base_cq->event_handler) { 1825 siw_dbg_cq(cq, "reporting CQ event %d\n", etype); 1826 base_cq->event_handler(&event, base_cq->cq_context); 1827 } 1828 } 1829 1830 void siw_srq_event(struct siw_srq *srq, enum ib_event_type etype) 1831 { 1832 struct ib_event event; 1833 struct ib_srq *base_srq = &srq->base_srq; 1834 1835 event.event = etype; 1836 event.device = base_srq->device; 1837 event.element.srq = base_srq; 1838 1839 if (base_srq->event_handler) { 1840 siw_dbg_pd(srq->base_srq.pd, 1841 "reporting SRQ event %d\n", etype); 1842 base_srq->event_handler(&event, base_srq->srq_context); 1843 } 1844 } 1845 1846 void siw_port_event(struct siw_device *sdev, u32 port, enum ib_event_type etype) 1847 { 1848 struct ib_event event; 1849 1850 event.event = etype; 1851 event.device = &sdev->base_dev; 1852 event.element.port_num = port; 1853 1854 siw_dbg(&sdev->base_dev, "reporting port event %d\n", etype); 1855 1856 ib_dispatch_event(&event); 1857 } 1858