1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_FIVE 0x40a00000 42 #define FLOAT_SIX 0x40c00000 43 #define FLOAT_EIGHT 0x41000000 44 #define FLOAT_MINUS_5 0xc0a00000 45 46 #define UNSOL_TAG_DSP 0x16 47 48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 50 51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 54 55 #define MASTERCONTROL 0x80 56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 58 59 #define WIDGET_CHIP_CTRL 0x15 60 #define WIDGET_DSP_CTRL 0x16 61 62 #define MEM_CONNID_MICIN1 3 63 #define MEM_CONNID_MICIN2 5 64 #define MEM_CONNID_MICOUT1 12 65 #define MEM_CONNID_MICOUT2 14 66 #define MEM_CONNID_WUH 10 67 #define MEM_CONNID_DSP 16 68 #define MEM_CONNID_DMIC 100 69 70 #define SCP_SET 0 71 #define SCP_GET 1 72 73 #define EFX_FILE "ctefx.bin" 74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 75 #define R3DI_EFX_FILE "ctefx-r3di.bin" 76 77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78 MODULE_FIRMWARE(EFX_FILE); 79 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 80 MODULE_FIRMWARE(R3DI_EFX_FILE); 81 #endif 82 83 static const char *const dirstr[2] = { "Playback", "Capture" }; 84 85 #define NUM_OF_OUTPUTS 2 86 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 87 enum { 88 SPEAKER_OUT, 89 HEADPHONE_OUT, 90 }; 91 92 enum { 93 DIGITAL_MIC, 94 LINE_MIC_IN 95 }; 96 97 /* Strings for Input Source Enum Control */ 98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 99 #define IN_SRC_NUM_OF_INPUTS 3 100 enum { 101 REAR_MIC, 102 REAR_LINE_IN, 103 FRONT_MIC, 104 }; 105 106 enum { 107 #define VNODE_START_NID 0x80 108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 109 VNID_MIC, 110 VNID_HP_SEL, 111 VNID_AMIC1_SEL, 112 VNID_HP_ASEL, 113 VNID_AMIC1_ASEL, 114 VNODE_END_NID, 115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 116 117 #define EFFECT_START_NID 0x90 118 #define OUT_EFFECT_START_NID EFFECT_START_NID 119 SURROUND = OUT_EFFECT_START_NID, 120 CRYSTALIZER, 121 DIALOG_PLUS, 122 SMART_VOLUME, 123 X_BASS, 124 EQUALIZER, 125 OUT_EFFECT_END_NID, 126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 127 128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 129 ECHO_CANCELLATION = IN_EFFECT_START_NID, 130 VOICE_FOCUS, 131 MIC_SVM, 132 NOISE_REDUCTION, 133 IN_EFFECT_END_NID, 134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 135 136 VOICEFX = IN_EFFECT_END_NID, 137 PLAY_ENHANCEMENT, 138 CRYSTAL_VOICE, 139 EFFECT_END_NID, 140 OUTPUT_SOURCE_ENUM, 141 INPUT_SOURCE_ENUM, 142 XBASS_XOVER, 143 EQ_PRESET_ENUM, 144 SMART_VOLUME_ENUM, 145 MIC_BOOST_ENUM, 146 AE5_HEADPHONE_GAIN_ENUM, 147 AE5_SOUND_FILTER_ENUM, 148 ZXR_HEADPHONE_GAIN, 149 SPEAKER_CHANNEL_CFG_ENUM, 150 SPEAKER_FULL_RANGE_FRONT, 151 SPEAKER_FULL_RANGE_REAR, 152 BASS_REDIRECTION, 153 BASS_REDIRECTION_XOVER, 154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 155 }; 156 157 /* Effects values size*/ 158 #define EFFECT_VALS_MAX_COUNT 12 159 160 /* 161 * Default values for the effect slider controls, they are in order of their 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 163 * X-bass. 164 */ 165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 166 /* Amount of effect level sliders for ca0132_alt controls. */ 167 #define EFFECT_LEVEL_SLIDERS 5 168 169 /* Latency introduced by DSP blocks in milliseconds. */ 170 #define DSP_CAPTURE_INIT_LATENCY 0 171 #define DSP_CRYSTAL_VOICE_LATENCY 124 172 #define DSP_PLAYBACK_INIT_LATENCY 13 173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 174 #define DSP_SPEAKER_OUT_LATENCY 7 175 176 struct ct_effect { 177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 178 hda_nid_t nid; 179 int mid; /*effect module ID*/ 180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 181 int direct; /* 0:output; 1:input*/ 182 int params; /* number of default non-on/off params */ 183 /*effect default values, 1st is on/off. */ 184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 185 }; 186 187 #define EFX_DIR_OUT 0 188 #define EFX_DIR_IN 1 189 190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 191 { .name = "Surround", 192 .nid = SURROUND, 193 .mid = 0x96, 194 .reqs = {0, 1}, 195 .direct = EFX_DIR_OUT, 196 .params = 1, 197 .def_vals = {0x3F800000, 0x3F2B851F} 198 }, 199 { .name = "Crystalizer", 200 .nid = CRYSTALIZER, 201 .mid = 0x96, 202 .reqs = {7, 8}, 203 .direct = EFX_DIR_OUT, 204 .params = 1, 205 .def_vals = {0x3F800000, 0x3F266666} 206 }, 207 { .name = "Dialog Plus", 208 .nid = DIALOG_PLUS, 209 .mid = 0x96, 210 .reqs = {2, 3}, 211 .direct = EFX_DIR_OUT, 212 .params = 1, 213 .def_vals = {0x00000000, 0x3F000000} 214 }, 215 { .name = "Smart Volume", 216 .nid = SMART_VOLUME, 217 .mid = 0x96, 218 .reqs = {4, 5, 6}, 219 .direct = EFX_DIR_OUT, 220 .params = 2, 221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 222 }, 223 { .name = "X-Bass", 224 .nid = X_BASS, 225 .mid = 0x96, 226 .reqs = {24, 23, 25}, 227 .direct = EFX_DIR_OUT, 228 .params = 2, 229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 230 }, 231 { .name = "Equalizer", 232 .nid = EQUALIZER, 233 .mid = 0x96, 234 .reqs = {9, 10, 11, 12, 13, 14, 235 15, 16, 17, 18, 19, 20}, 236 .direct = EFX_DIR_OUT, 237 .params = 11, 238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000} 241 }, 242 { .name = "Echo Cancellation", 243 .nid = ECHO_CANCELLATION, 244 .mid = 0x95, 245 .reqs = {0, 1, 2, 3}, 246 .direct = EFX_DIR_IN, 247 .params = 3, 248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 249 }, 250 { .name = "Voice Focus", 251 .nid = VOICE_FOCUS, 252 .mid = 0x95, 253 .reqs = {6, 7, 8, 9}, 254 .direct = EFX_DIR_IN, 255 .params = 3, 256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 257 }, 258 { .name = "Mic SVM", 259 .nid = MIC_SVM, 260 .mid = 0x95, 261 .reqs = {44, 45}, 262 .direct = EFX_DIR_IN, 263 .params = 1, 264 .def_vals = {0x00000000, 0x3F3D70A4} 265 }, 266 { .name = "Noise Reduction", 267 .nid = NOISE_REDUCTION, 268 .mid = 0x95, 269 .reqs = {4, 5}, 270 .direct = EFX_DIR_IN, 271 .params = 1, 272 .def_vals = {0x3F800000, 0x3F000000} 273 }, 274 { .name = "VoiceFX", 275 .nid = VOICEFX, 276 .mid = 0x95, 277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 278 .direct = EFX_DIR_IN, 279 .params = 8, 280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 282 0x00000000} 283 } 284 }; 285 286 /* Tuning controls */ 287 #ifdef ENABLE_TUNING_CONTROLS 288 289 enum { 290 #define TUNING_CTL_START_NID 0xC0 291 WEDGE_ANGLE = TUNING_CTL_START_NID, 292 SVM_LEVEL, 293 EQUALIZER_BAND_0, 294 EQUALIZER_BAND_1, 295 EQUALIZER_BAND_2, 296 EQUALIZER_BAND_3, 297 EQUALIZER_BAND_4, 298 EQUALIZER_BAND_5, 299 EQUALIZER_BAND_6, 300 EQUALIZER_BAND_7, 301 EQUALIZER_BAND_8, 302 EQUALIZER_BAND_9, 303 TUNING_CTL_END_NID 304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 305 }; 306 307 struct ct_tuning_ctl { 308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 309 hda_nid_t parent_nid; 310 hda_nid_t nid; 311 int mid; /*effect module ID*/ 312 int req; /*effect module request*/ 313 int direct; /* 0:output; 1:input*/ 314 unsigned int def_val;/*effect default values*/ 315 }; 316 317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 318 { .name = "Wedge Angle", 319 .parent_nid = VOICE_FOCUS, 320 .nid = WEDGE_ANGLE, 321 .mid = 0x95, 322 .req = 8, 323 .direct = EFX_DIR_IN, 324 .def_val = 0x41F00000 325 }, 326 { .name = "SVM Level", 327 .parent_nid = MIC_SVM, 328 .nid = SVM_LEVEL, 329 .mid = 0x95, 330 .req = 45, 331 .direct = EFX_DIR_IN, 332 .def_val = 0x3F3D70A4 333 }, 334 { .name = "EQ Band0", 335 .parent_nid = EQUALIZER, 336 .nid = EQUALIZER_BAND_0, 337 .mid = 0x96, 338 .req = 11, 339 .direct = EFX_DIR_OUT, 340 .def_val = 0x00000000 341 }, 342 { .name = "EQ Band1", 343 .parent_nid = EQUALIZER, 344 .nid = EQUALIZER_BAND_1, 345 .mid = 0x96, 346 .req = 12, 347 .direct = EFX_DIR_OUT, 348 .def_val = 0x00000000 349 }, 350 { .name = "EQ Band2", 351 .parent_nid = EQUALIZER, 352 .nid = EQUALIZER_BAND_2, 353 .mid = 0x96, 354 .req = 13, 355 .direct = EFX_DIR_OUT, 356 .def_val = 0x00000000 357 }, 358 { .name = "EQ Band3", 359 .parent_nid = EQUALIZER, 360 .nid = EQUALIZER_BAND_3, 361 .mid = 0x96, 362 .req = 14, 363 .direct = EFX_DIR_OUT, 364 .def_val = 0x00000000 365 }, 366 { .name = "EQ Band4", 367 .parent_nid = EQUALIZER, 368 .nid = EQUALIZER_BAND_4, 369 .mid = 0x96, 370 .req = 15, 371 .direct = EFX_DIR_OUT, 372 .def_val = 0x00000000 373 }, 374 { .name = "EQ Band5", 375 .parent_nid = EQUALIZER, 376 .nid = EQUALIZER_BAND_5, 377 .mid = 0x96, 378 .req = 16, 379 .direct = EFX_DIR_OUT, 380 .def_val = 0x00000000 381 }, 382 { .name = "EQ Band6", 383 .parent_nid = EQUALIZER, 384 .nid = EQUALIZER_BAND_6, 385 .mid = 0x96, 386 .req = 17, 387 .direct = EFX_DIR_OUT, 388 .def_val = 0x00000000 389 }, 390 { .name = "EQ Band7", 391 .parent_nid = EQUALIZER, 392 .nid = EQUALIZER_BAND_7, 393 .mid = 0x96, 394 .req = 18, 395 .direct = EFX_DIR_OUT, 396 .def_val = 0x00000000 397 }, 398 { .name = "EQ Band8", 399 .parent_nid = EQUALIZER, 400 .nid = EQUALIZER_BAND_8, 401 .mid = 0x96, 402 .req = 19, 403 .direct = EFX_DIR_OUT, 404 .def_val = 0x00000000 405 }, 406 { .name = "EQ Band9", 407 .parent_nid = EQUALIZER, 408 .nid = EQUALIZER_BAND_9, 409 .mid = 0x96, 410 .req = 20, 411 .direct = EFX_DIR_OUT, 412 .def_val = 0x00000000 413 } 414 }; 415 #endif 416 417 /* Voice FX Presets */ 418 #define VOICEFX_MAX_PARAM_COUNT 9 419 420 struct ct_voicefx { 421 char *name; 422 hda_nid_t nid; 423 int mid; 424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 425 }; 426 427 struct ct_voicefx_preset { 428 char *name; /*preset name*/ 429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 430 }; 431 432 static const struct ct_voicefx ca0132_voicefx = { 433 .name = "VoiceFX Capture Switch", 434 .nid = VOICEFX, 435 .mid = 0x95, 436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 437 }; 438 439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 440 { .name = "Neutral", 441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 442 0x44FA0000, 0x3F800000, 0x3F800000, 443 0x3F800000, 0x00000000, 0x00000000 } 444 }, 445 { .name = "Female2Male", 446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 447 0x44FA0000, 0x3F19999A, 0x3F866666, 448 0x3F800000, 0x00000000, 0x00000000 } 449 }, 450 { .name = "Male2Female", 451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 452 0x450AC000, 0x4017AE14, 0x3F6B851F, 453 0x3F800000, 0x00000000, 0x00000000 } 454 }, 455 { .name = "ScrappyKid", 456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 457 0x44FA0000, 0x40400000, 0x3F28F5C3, 458 0x3F800000, 0x00000000, 0x00000000 } 459 }, 460 { .name = "Elderly", 461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 462 0x44E10000, 0x3FB33333, 0x3FB9999A, 463 0x3F800000, 0x3E3A2E43, 0x00000000 } 464 }, 465 { .name = "Orc", 466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 467 0x45098000, 0x3F266666, 0x3FC00000, 468 0x3F800000, 0x00000000, 0x00000000 } 469 }, 470 { .name = "Elf", 471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 472 0x45193000, 0x3F8E147B, 0x3F75C28F, 473 0x3F800000, 0x00000000, 0x00000000 } 474 }, 475 { .name = "Dwarf", 476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 477 0x45007000, 0x3F451EB8, 0x3F7851EC, 478 0x3F800000, 0x00000000, 0x00000000 } 479 }, 480 { .name = "AlienBrute", 481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 482 0x451F6000, 0x3F266666, 0x3FA7D945, 483 0x3F800000, 0x3CF5C28F, 0x00000000 } 484 }, 485 { .name = "Robot", 486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 487 0x44FA0000, 0x3FB2718B, 0x3F800000, 488 0xBC07010E, 0x00000000, 0x00000000 } 489 }, 490 { .name = "Marine", 491 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 493 0x3F0A3D71, 0x00000000, 0x00000000 } 494 }, 495 { .name = "Emo", 496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 497 0x44FA0000, 0x3F800000, 0x3F800000, 498 0x3E4CCCCD, 0x00000000, 0x00000000 } 499 }, 500 { .name = "DeepVoice", 501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 503 0x3F800000, 0x00000000, 0x00000000 } 504 }, 505 { .name = "Munchkin", 506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 507 0x44FA0000, 0x3F800000, 0x3F1A043C, 508 0x3F800000, 0x00000000, 0x00000000 } 509 } 510 }; 511 512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 513 514 #define EQ_PRESET_MAX_PARAM_COUNT 11 515 516 struct ct_eq { 517 char *name; 518 hda_nid_t nid; 519 int mid; 520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 521 }; 522 523 struct ct_eq_preset { 524 char *name; /*preset name*/ 525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 526 }; 527 528 static const struct ct_eq ca0132_alt_eq_enum = { 529 .name = "FX: Equalizer Preset Switch", 530 .nid = EQ_PRESET_ENUM, 531 .mid = 0x96, 532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 533 }; 534 535 536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 537 { .name = "Flat", 538 .vals = { 0x00000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000 } 542 }, 543 { .name = "Acoustic", 544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 545 0x40000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x40000000, 547 0x40000000, 0x40000000 } 548 }, 549 { .name = "Classical", 550 .vals = { 0x00000000, 0x00000000, 0x40C00000, 551 0x40C00000, 0x40466666, 0x00000000, 552 0x00000000, 0x00000000, 0x00000000, 553 0x40466666, 0x40466666 } 554 }, 555 { .name = "Country", 556 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 558 0x00000000, 0x00000000, 0x40000000, 559 0x40466666, 0x40800000 } 560 }, 561 { .name = "Dance", 562 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 563 0x40466666, 0x40866666, 0xBF99999A, 564 0xBF99999A, 0x00000000, 0x00000000, 565 0x40800000, 0x40800000 } 566 }, 567 { .name = "Jazz", 568 .vals = { 0x00000000, 0x00000000, 0x00000000, 569 0x3F8CCCCD, 0x40800000, 0x40800000, 570 0x40800000, 0x00000000, 0x3F8CCCCD, 571 0x40466666, 0x40466666 } 572 }, 573 { .name = "New Age", 574 .vals = { 0x00000000, 0x00000000, 0x40000000, 575 0x40000000, 0x00000000, 0x00000000, 576 0x00000000, 0x3F8CCCCD, 0x40000000, 577 0x40000000, 0x40000000 } 578 }, 579 { .name = "Pop", 580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 581 0x40000000, 0x40000000, 0x00000000, 582 0xBF99999A, 0xBF99999A, 0x00000000, 583 0x40466666, 0x40C00000 } 584 }, 585 { .name = "Rock", 586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 587 0x3F8CCCCD, 0x40000000, 0xBF99999A, 588 0xBF99999A, 0x00000000, 0x00000000, 589 0x40800000, 0x40800000 } 590 }, 591 { .name = "Vocal", 592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 593 0xBF99999A, 0x00000000, 0x40466666, 594 0x40800000, 0x40466666, 0x00000000, 595 0x00000000, 0x3F8CCCCD } 596 } 597 }; 598 599 /* 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 601 * set as not being full range, and bass redirection is enabled, all 602 * frequencies below the crossover frequency are redirected to the LFE 603 * channel. If the surround configuration has no LFE channel, this can't be 604 * enabled. X-Bass must be disabled when using these. 605 */ 606 enum speaker_range_reqs { 607 SPEAKER_BASS_REDIRECT = 0x15, 608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 609 /* Between 0x16-0x1a are the X-Bass reqs. */ 610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 615 }; 616 617 /* 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to 619 * module ID 0x96, the output effects module. 620 */ 621 enum speaker_tuning_reqs { 622 /* 623 * Currently, this value is always set to 0.0f. However, on Windows, 624 * when selecting certain headphone profiles on the new Sound Blaster 625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 626 * sent. This gets the speaker EQ address area, which is then used to 627 * send over (presumably) an equalizer profile for the specific 628 * headphone setup. It is sent using the same method the DSP 629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 630 * file exists in linux firmware tree but goes unused. It would also 631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 633 * set to 1.0f. 634 */ 635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 645 /* 646 * Inversion is used when setting headphone virtualization to line 647 * out. Not sure why this is, but it's the only place it's ever used. 648 */ 649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 651 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 652 SPEAKER_TUNING_LFE_INVERT = 0x2c, 653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 657 /* Delay is used when setting surround speaker distance in Windows. */ 658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 660 SPEAKER_TUNING_CENTER_DELAY = 0x33, 661 SPEAKER_TUNING_LFE_DELAY = 0x34, 662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 666 /* Of these two, only mute seems to ever be used. */ 667 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 668 SPEAKER_TUNING_MUTE = 0x3a, 669 }; 670 671 /* Surround output channel count configuration structures. */ 672 #define SPEAKER_CHANNEL_CFG_COUNT 5 673 enum { 674 SPEAKER_CHANNELS_2_0, 675 SPEAKER_CHANNELS_2_1, 676 SPEAKER_CHANNELS_4_0, 677 SPEAKER_CHANNELS_4_1, 678 SPEAKER_CHANNELS_5_1, 679 }; 680 681 struct ca0132_alt_speaker_channel_cfg { 682 char *name; 683 unsigned int val; 684 }; 685 686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 687 { .name = "2.0", 688 .val = FLOAT_ONE 689 }, 690 { .name = "2.1", 691 .val = FLOAT_TWO 692 }, 693 { .name = "4.0", 694 .val = FLOAT_FIVE 695 }, 696 { .name = "4.1", 697 .val = FLOAT_SIX 698 }, 699 { .name = "5.1", 700 .val = FLOAT_EIGHT 701 } 702 }; 703 704 /* 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 706 * and I don't know what the third req is, but it's always zero. I assume it's 707 * some sort of update or set command to tell the DSP there's new volume info. 708 */ 709 #define DSP_VOL_OUT 0 710 #define DSP_VOL_IN 1 711 712 struct ct_dsp_volume_ctl { 713 hda_nid_t vnid; 714 int mid; /* module ID*/ 715 unsigned int reqs[3]; /* scp req ID */ 716 }; 717 718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 719 { .vnid = VNID_SPK, 720 .mid = 0x32, 721 .reqs = {3, 4, 2} 722 }, 723 { .vnid = VNID_MIC, 724 .mid = 0x37, 725 .reqs = {2, 3, 1} 726 } 727 }; 728 729 /* Values for ca0113_mmio_command_set for selecting output. */ 730 #define AE_CA0113_OUT_SET_COMMANDS 6 731 struct ae_ca0113_output_set { 732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 735 }; 736 737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 740 /* Speakers. */ 741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 742 /* Headphones. */ 743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 744 }; 745 746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 749 /* Speakers. */ 750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 751 /* Headphones. */ 752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 753 }; 754 755 /* ae5 ca0113 command sequences to set headphone gain levels. */ 756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 757 struct ae5_headphone_gain_set { 758 char *name; 759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 760 }; 761 762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 763 { .name = "Low (16-31", 764 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 765 }, 766 { .name = "Medium (32-149", 767 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 768 }, 769 { .name = "High (150-600", 770 .vals = { 0xff, 0xff, 0xff, 0x7f } 771 } 772 }; 773 774 struct ae5_filter_set { 775 char *name; 776 unsigned int val; 777 }; 778 779 static const struct ae5_filter_set ae5_filter_presets[] = { 780 { .name = "Slow Roll Off", 781 .val = 0xa0 782 }, 783 { .name = "Minimum Phase", 784 .val = 0xc0 785 }, 786 { .name = "Fast Roll Off", 787 .val = 0x80 788 } 789 }; 790 791 /* 792 * Data structures for storing audio router remapping data. These are used to 793 * remap a currently active streams ports. 794 */ 795 struct chipio_stream_remap_data { 796 unsigned int stream_id; 797 unsigned int count; 798 799 unsigned int offset[16]; 800 unsigned int value[16]; 801 }; 802 803 static const struct chipio_stream_remap_data stream_remap_data[] = { 804 { .stream_id = 0x14, 805 .count = 0x04, 806 .offset = { 0x00, 0x04, 0x08, 0x0c }, 807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, 808 }, 809 { .stream_id = 0x0c, 810 .count = 0x0c, 811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 812 0x20, 0x24, 0x28, 0x2c }, 813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, 816 }, 817 { .stream_id = 0x0c, 818 .count = 0x08, 819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, 820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, 822 } 823 }; 824 825 enum hda_cmd_vendor_io { 826 /* for DspIO node */ 827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 829 830 VENDOR_DSPIO_STATUS = 0xF01, 831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 833 VENDOR_DSPIO_DSP_INIT = 0x703, 834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 836 837 /* for ChipIO node */ 838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 841 VENDOR_CHIPIO_DATA_LOW = 0x300, 842 VENDOR_CHIPIO_DATA_HIGH = 0x400, 843 844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 846 847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 848 VENDOR_CHIPIO_STATUS = 0xF01, 849 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 851 852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 857 858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 860 861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 865 VENDOR_CHIPIO_FLAG_SET = 0x70F, 866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 867 VENDOR_CHIPIO_PARAM_SET = 0x710, 868 VENDOR_CHIPIO_PARAM_GET = 0xF10, 869 870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 874 875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 879 880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 886 887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 888 }; 889 890 /* 891 * Control flag IDs 892 */ 893 enum control_flag_id { 894 /* Connection manager stream setup is bypassed/enabled */ 895 CONTROL_FLAG_C_MGR = 0, 896 /* DSP DMA is bypassed/enabled */ 897 CONTROL_FLAG_DMA = 1, 898 /* 8051 'idle' mode is disabled/enabled */ 899 CONTROL_FLAG_IDLE_ENABLE = 2, 900 /* Tracker for the SPDIF-in path is bypassed/enabled */ 901 CONTROL_FLAG_TRACKER = 3, 902 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 903 CONTROL_FLAG_SPDIF2OUT = 4, 904 /* Digital Microphone is disabled/enabled */ 905 CONTROL_FLAG_DMIC = 5, 906 /* ADC_B rate is 48 kHz/96 kHz */ 907 CONTROL_FLAG_ADC_B_96KHZ = 6, 908 /* ADC_C rate is 48 kHz/96 kHz */ 909 CONTROL_FLAG_ADC_C_96KHZ = 7, 910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 911 CONTROL_FLAG_DAC_96KHZ = 8, 912 /* DSP rate is 48 kHz/96 kHz */ 913 CONTROL_FLAG_DSP_96KHZ = 9, 914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 917 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 919 CONTROL_FLAG_DECODE_LOOP = 12, 920 /* De-emphasis filter on DAC-1 disabled/enabled */ 921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 922 /* De-emphasis filter on DAC-2 disabled/enabled */ 923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 924 /* De-emphasis filter on DAC-3 disabled/enabled */ 925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 926 /* High-pass filter on ADC_B disabled/enabled */ 927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 928 /* High-pass filter on ADC_C disabled/enabled */ 929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 930 /* Common mode on Port_A disabled/enabled */ 931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 932 /* Common mode on Port_D disabled/enabled */ 933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 938 /* ASI rate is 48kHz/96kHz */ 939 CONTROL_FLAG_ASI_96KHZ = 22, 940 /* DAC power settings able to control attached ports no/yes */ 941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 942 /* Clock Stop OK reporting is disabled/enabled */ 943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 944 /* Number of control flags */ 945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 946 }; 947 948 /* 949 * Control parameter IDs 950 */ 951 enum control_param_id { 952 /* 0: None, 1: Mic1In*/ 953 CONTROL_PARAM_VIP_SOURCE = 1, 954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 955 CONTROL_PARAM_SPDIF1_SOURCE = 2, 956 /* Port A output stage gain setting to use when 16 Ohm output 957 * impedance is selected*/ 958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 959 /* Port D output stage gain setting to use when 16 Ohm output 960 * impedance is selected*/ 961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 962 963 /* 964 * This control param name was found in the 8051 memory, and makes 965 * sense given the fact the AE-5 uses it and has the ASI flag set. 966 */ 967 CONTROL_PARAM_ASI = 23, 968 969 /* Stream Control */ 970 971 /* Select stream with the given ID */ 972 CONTROL_PARAM_STREAM_ID = 24, 973 /* Source connection point for the selected stream */ 974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 975 /* Destination connection point for the selected stream */ 976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 977 /* Number of audio channels in the selected stream */ 978 CONTROL_PARAM_STREAMS_CHANNELS = 27, 979 /*Enable control for the selected stream */ 980 CONTROL_PARAM_STREAM_CONTROL = 28, 981 982 /* Connection Point Control */ 983 984 /* Select connection point with the given ID */ 985 CONTROL_PARAM_CONN_POINT_ID = 29, 986 /* Connection point sample rate */ 987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 988 989 /* Node Control */ 990 991 /* Select HDA node with the given ID */ 992 CONTROL_PARAM_NODE_ID = 31 993 }; 994 995 /* 996 * Dsp Io Status codes 997 */ 998 enum hda_vendor_status_dspio { 999 /* Success */ 1000 VENDOR_STATUS_DSPIO_OK = 0x00, 1001 /* Busy, unable to accept new command, the host must retry */ 1002 VENDOR_STATUS_DSPIO_BUSY = 0x01, 1003 /* SCP command queue is full */ 1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 1005 /* SCP response queue is empty */ 1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 1007 }; 1008 1009 /* 1010 * Chip Io Status codes 1011 */ 1012 enum hda_vendor_status_chipio { 1013 /* Success */ 1014 VENDOR_STATUS_CHIPIO_OK = 0x00, 1015 /* Busy, unable to accept new command, the host must retry */ 1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01 1017 }; 1018 1019 /* 1020 * CA0132 sample rate 1021 */ 1022 enum ca0132_sample_rate { 1023 SR_6_000 = 0x00, 1024 SR_8_000 = 0x01, 1025 SR_9_600 = 0x02, 1026 SR_11_025 = 0x03, 1027 SR_16_000 = 0x04, 1028 SR_22_050 = 0x05, 1029 SR_24_000 = 0x06, 1030 SR_32_000 = 0x07, 1031 SR_44_100 = 0x08, 1032 SR_48_000 = 0x09, 1033 SR_88_200 = 0x0A, 1034 SR_96_000 = 0x0B, 1035 SR_144_000 = 0x0C, 1036 SR_176_400 = 0x0D, 1037 SR_192_000 = 0x0E, 1038 SR_384_000 = 0x0F, 1039 1040 SR_COUNT = 0x10, 1041 1042 SR_RATE_UNKNOWN = 0x1F 1043 }; 1044 1045 enum dsp_download_state { 1046 DSP_DOWNLOAD_FAILED = -1, 1047 DSP_DOWNLOAD_INIT = 0, 1048 DSP_DOWNLOADING = 1, 1049 DSP_DOWNLOADED = 2 1050 }; 1051 1052 /* retrieve parameters from hda format */ 1053 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1057 1058 /* 1059 * CA0132 specific 1060 */ 1061 1062 struct ca0132_spec { 1063 const struct snd_kcontrol_new *mixers[5]; 1064 unsigned int num_mixers; 1065 const struct hda_verb *base_init_verbs; 1066 const struct hda_verb *base_exit_verbs; 1067 const struct hda_verb *chip_init_verbs; 1068 const struct hda_verb *desktop_init_verbs; 1069 struct hda_verb *spec_init_verbs; 1070 struct auto_pin_cfg autocfg; 1071 1072 /* Nodes configurations */ 1073 struct hda_multi_out multiout; 1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1076 unsigned int num_outputs; 1077 hda_nid_t input_pins[AUTO_PIN_LAST]; 1078 hda_nid_t adcs[AUTO_PIN_LAST]; 1079 hda_nid_t dig_out; 1080 hda_nid_t dig_in; 1081 unsigned int num_inputs; 1082 hda_nid_t shared_mic_nid; 1083 hda_nid_t shared_out_nid; 1084 hda_nid_t unsol_tag_hp; 1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1086 hda_nid_t unsol_tag_amic1; 1087 1088 /* chip access */ 1089 struct mutex chipio_mutex; /* chip access mutex */ 1090 u32 curr_chip_addx; 1091 1092 /* DSP download related */ 1093 enum dsp_download_state dsp_state; 1094 unsigned int dsp_stream_id; 1095 unsigned int wait_scp; 1096 unsigned int wait_scp_header; 1097 unsigned int wait_num_data; 1098 unsigned int scp_resp_header; 1099 unsigned int scp_resp_data[4]; 1100 unsigned int scp_resp_count; 1101 bool startup_check_entered; 1102 bool dsp_reload; 1103 1104 /* mixer and effects related */ 1105 unsigned char dmic_ctl; 1106 int cur_out_type; 1107 int cur_mic_type; 1108 long vnode_lvol[VNODES_COUNT]; 1109 long vnode_rvol[VNODES_COUNT]; 1110 long vnode_lswitch[VNODES_COUNT]; 1111 long vnode_rswitch[VNODES_COUNT]; 1112 long effects_switch[EFFECTS_COUNT]; 1113 long voicefx_val; 1114 long cur_mic_boost; 1115 /* ca0132_alt control related values */ 1116 unsigned char in_enum_val; 1117 unsigned char out_enum_val; 1118 unsigned char channel_cfg_val; 1119 unsigned char speaker_range_val[2]; 1120 unsigned char mic_boost_enum_val; 1121 unsigned char smart_volume_setting; 1122 unsigned char bass_redirection_val; 1123 long bass_redirect_xover_freq; 1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1125 long xbass_xover_freq; 1126 long eq_preset_val; 1127 unsigned int tlv[4]; 1128 struct hda_vmaster_mute_hook vmaster_mute; 1129 /* AE-5 Control values */ 1130 unsigned char ae5_headphone_gain_val; 1131 unsigned char ae5_filter_val; 1132 /* ZxR Control Values */ 1133 unsigned char zxr_gain_set; 1134 1135 struct hda_codec *codec; 1136 struct delayed_work unsol_hp_work; 1137 int quirk; 1138 1139 #ifdef ENABLE_TUNING_CONTROLS 1140 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1141 #endif 1142 /* 1143 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1144 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1145 * things. 1146 */ 1147 bool use_pci_mmio; 1148 void __iomem *mem_base; 1149 1150 /* 1151 * Whether or not to use the alt functions like alt_select_out, 1152 * alt_select_in, etc. Only used on desktop codecs for now, because of 1153 * surround sound support. 1154 */ 1155 bool use_alt_functions; 1156 1157 /* 1158 * Whether or not to use alt controls: volume effect sliders, EQ 1159 * presets, smart volume presets, and new control names with FX prefix. 1160 * Renames PlayEnhancement and CrystalVoice too. 1161 */ 1162 bool use_alt_controls; 1163 }; 1164 1165 /* 1166 * CA0132 quirks table 1167 */ 1168 enum { 1169 QUIRK_NONE, 1170 QUIRK_ALIENWARE, 1171 QUIRK_ALIENWARE_M17XR4, 1172 QUIRK_SBZ, 1173 QUIRK_ZXR, 1174 QUIRK_ZXR_DBPRO, 1175 QUIRK_R3DI, 1176 QUIRK_R3D, 1177 QUIRK_AE5, 1178 QUIRK_AE7, 1179 }; 1180 1181 #ifdef CONFIG_PCI 1182 #define ca0132_quirk(spec) ((spec)->quirk) 1183 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1184 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1185 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1186 #else 1187 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1188 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1189 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1190 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1191 #endif 1192 1193 static const struct hda_pintbl alienware_pincfgs[] = { 1194 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1195 { 0x0c, 0x411111f0 }, /* N/A */ 1196 { 0x0d, 0x411111f0 }, /* N/A */ 1197 { 0x0e, 0x411111f0 }, /* N/A */ 1198 { 0x0f, 0x0321101f }, /* HP */ 1199 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1200 { 0x11, 0x03a11021 }, /* Mic */ 1201 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1202 { 0x13, 0x411111f0 }, /* N/A */ 1203 { 0x18, 0x411111f0 }, /* N/A */ 1204 {} 1205 }; 1206 1207 /* Sound Blaster Z pin configs taken from Windows Driver */ 1208 static const struct hda_pintbl sbz_pincfgs[] = { 1209 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1210 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1211 { 0x0d, 0x014510f0 }, /* Digital Out */ 1212 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1213 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1214 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1215 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1216 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1217 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1218 { 0x18, 0x50d000f0 }, /* N/A */ 1219 {} 1220 }; 1221 1222 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1223 static const struct hda_pintbl zxr_pincfgs[] = { 1224 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1225 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1226 { 0x0d, 0x014510f0 }, /* Digital Out */ 1227 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1228 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1229 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1230 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1231 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1232 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1233 { 0x18, 0x50d000f0 }, /* N/A */ 1234 {} 1235 }; 1236 1237 /* Recon3D pin configs taken from Windows Driver */ 1238 static const struct hda_pintbl r3d_pincfgs[] = { 1239 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1240 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1241 { 0x0d, 0x014510f0 }, /* Digital Out */ 1242 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1243 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1244 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1245 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1246 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1247 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1248 { 0x18, 0x50d000f0 }, /* N/A */ 1249 {} 1250 }; 1251 1252 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1253 static const struct hda_pintbl ae5_pincfgs[] = { 1254 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1255 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1256 { 0x0d, 0x014510f0 }, /* Digital Out */ 1257 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1258 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1259 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1260 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1261 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1262 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1263 { 0x18, 0x50d000f0 }, /* N/A */ 1264 {} 1265 }; 1266 1267 /* Recon3D integrated pin configs taken from Windows Driver */ 1268 static const struct hda_pintbl r3di_pincfgs[] = { 1269 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1270 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1271 { 0x0d, 0x014510f0 }, /* Digital Out */ 1272 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1273 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1274 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1275 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1276 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1277 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1278 { 0x18, 0x500000f0 }, /* N/A */ 1279 {} 1280 }; 1281 1282 static const struct hda_pintbl ae7_pincfgs[] = { 1283 { 0x0b, 0x01017010 }, 1284 { 0x0c, 0x014510f0 }, 1285 { 0x0d, 0x414510f0 }, 1286 { 0x0e, 0x01c520f0 }, 1287 { 0x0f, 0x01017114 }, 1288 { 0x10, 0x01017011 }, 1289 { 0x11, 0x018170ff }, 1290 { 0x12, 0x01a170f0 }, 1291 { 0x13, 0x908700f0 }, 1292 { 0x18, 0x500000f0 }, 1293 {} 1294 }; 1295 1296 static const struct snd_pci_quirk ca0132_quirks[] = { 1297 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1298 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1299 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1300 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1301 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1302 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1303 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1304 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1305 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1306 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1307 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1308 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), 1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), 1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1315 {} 1316 }; 1317 1318 /* Output selection quirk info structures. */ 1319 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1320 #define MAX_QUIRK_SCP_SET_VALS 2 1321 struct ca0132_alt_out_set_info { 1322 unsigned int dac2port; /* ParamID 0x0d value. */ 1323 1324 bool has_hda_gpio; 1325 char hda_gpio_pin; 1326 char hda_gpio_set; 1327 1328 unsigned int mmio_gpio_count; 1329 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1330 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1331 1332 unsigned int scp_cmds_count; 1333 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1334 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1335 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1336 1337 bool has_chipio_write; 1338 unsigned int chipio_write_addr; 1339 unsigned int chipio_write_data; 1340 }; 1341 1342 struct ca0132_alt_out_set_quirk_data { 1343 int quirk_id; 1344 1345 bool has_headphone_gain; 1346 bool is_ae_series; 1347 1348 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1349 }; 1350 1351 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1352 { .quirk_id = QUIRK_R3DI, 1353 .has_headphone_gain = false, 1354 .is_ae_series = false, 1355 .out_set_info = { 1356 /* Speakers. */ 1357 { .dac2port = 0x24, 1358 .has_hda_gpio = true, 1359 .hda_gpio_pin = 2, 1360 .hda_gpio_set = 1, 1361 .mmio_gpio_count = 0, 1362 .scp_cmds_count = 0, 1363 .has_chipio_write = false, 1364 }, 1365 /* Headphones. */ 1366 { .dac2port = 0x21, 1367 .has_hda_gpio = true, 1368 .hda_gpio_pin = 2, 1369 .hda_gpio_set = 0, 1370 .mmio_gpio_count = 0, 1371 .scp_cmds_count = 0, 1372 .has_chipio_write = false, 1373 } }, 1374 }, 1375 { .quirk_id = QUIRK_R3D, 1376 .has_headphone_gain = false, 1377 .is_ae_series = false, 1378 .out_set_info = { 1379 /* Speakers. */ 1380 { .dac2port = 0x24, 1381 .has_hda_gpio = false, 1382 .mmio_gpio_count = 1, 1383 .mmio_gpio_pin = { 1 }, 1384 .mmio_gpio_set = { 1 }, 1385 .scp_cmds_count = 0, 1386 .has_chipio_write = false, 1387 }, 1388 /* Headphones. */ 1389 { .dac2port = 0x21, 1390 .has_hda_gpio = false, 1391 .mmio_gpio_count = 1, 1392 .mmio_gpio_pin = { 1 }, 1393 .mmio_gpio_set = { 0 }, 1394 .scp_cmds_count = 0, 1395 .has_chipio_write = false, 1396 } }, 1397 }, 1398 { .quirk_id = QUIRK_SBZ, 1399 .has_headphone_gain = false, 1400 .is_ae_series = false, 1401 .out_set_info = { 1402 /* Speakers. */ 1403 { .dac2port = 0x18, 1404 .has_hda_gpio = false, 1405 .mmio_gpio_count = 3, 1406 .mmio_gpio_pin = { 7, 4, 1 }, 1407 .mmio_gpio_set = { 0, 1, 1 }, 1408 .scp_cmds_count = 0, 1409 .has_chipio_write = false, }, 1410 /* Headphones. */ 1411 { .dac2port = 0x12, 1412 .has_hda_gpio = false, 1413 .mmio_gpio_count = 3, 1414 .mmio_gpio_pin = { 7, 4, 1 }, 1415 .mmio_gpio_set = { 1, 1, 0 }, 1416 .scp_cmds_count = 0, 1417 .has_chipio_write = false, 1418 } }, 1419 }, 1420 { .quirk_id = QUIRK_ZXR, 1421 .has_headphone_gain = true, 1422 .is_ae_series = false, 1423 .out_set_info = { 1424 /* Speakers. */ 1425 { .dac2port = 0x24, 1426 .has_hda_gpio = false, 1427 .mmio_gpio_count = 3, 1428 .mmio_gpio_pin = { 2, 3, 5 }, 1429 .mmio_gpio_set = { 1, 1, 0 }, 1430 .scp_cmds_count = 0, 1431 .has_chipio_write = false, 1432 }, 1433 /* Headphones. */ 1434 { .dac2port = 0x21, 1435 .has_hda_gpio = false, 1436 .mmio_gpio_count = 3, 1437 .mmio_gpio_pin = { 2, 3, 5 }, 1438 .mmio_gpio_set = { 0, 1, 1 }, 1439 .scp_cmds_count = 0, 1440 .has_chipio_write = false, 1441 } }, 1442 }, 1443 { .quirk_id = QUIRK_AE5, 1444 .has_headphone_gain = true, 1445 .is_ae_series = true, 1446 .out_set_info = { 1447 /* Speakers. */ 1448 { .dac2port = 0xa4, 1449 .has_hda_gpio = false, 1450 .mmio_gpio_count = 0, 1451 .scp_cmds_count = 2, 1452 .scp_cmd_mid = { 0x96, 0x96 }, 1453 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1454 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1455 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1456 .has_chipio_write = true, 1457 .chipio_write_addr = 0x0018b03c, 1458 .chipio_write_data = 0x00000012 1459 }, 1460 /* Headphones. */ 1461 { .dac2port = 0xa1, 1462 .has_hda_gpio = false, 1463 .mmio_gpio_count = 0, 1464 .scp_cmds_count = 2, 1465 .scp_cmd_mid = { 0x96, 0x96 }, 1466 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1467 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1468 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1469 .has_chipio_write = true, 1470 .chipio_write_addr = 0x0018b03c, 1471 .chipio_write_data = 0x00000012 1472 } }, 1473 }, 1474 { .quirk_id = QUIRK_AE7, 1475 .has_headphone_gain = true, 1476 .is_ae_series = true, 1477 .out_set_info = { 1478 /* Speakers. */ 1479 { .dac2port = 0x58, 1480 .has_hda_gpio = false, 1481 .mmio_gpio_count = 1, 1482 .mmio_gpio_pin = { 0 }, 1483 .mmio_gpio_set = { 1 }, 1484 .scp_cmds_count = 2, 1485 .scp_cmd_mid = { 0x96, 0x96 }, 1486 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1487 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1488 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1489 .has_chipio_write = true, 1490 .chipio_write_addr = 0x0018b03c, 1491 .chipio_write_data = 0x00000000 1492 }, 1493 /* Headphones. */ 1494 { .dac2port = 0x58, 1495 .has_hda_gpio = false, 1496 .mmio_gpio_count = 1, 1497 .mmio_gpio_pin = { 0 }, 1498 .mmio_gpio_set = { 1 }, 1499 .scp_cmds_count = 2, 1500 .scp_cmd_mid = { 0x96, 0x96 }, 1501 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1502 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1503 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1504 .has_chipio_write = true, 1505 .chipio_write_addr = 0x0018b03c, 1506 .chipio_write_data = 0x00000010 1507 } }, 1508 } 1509 }; 1510 1511 /* 1512 * CA0132 codec access 1513 */ 1514 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1515 unsigned int verb, unsigned int parm, unsigned int *res) 1516 { 1517 unsigned int response; 1518 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1519 *res = response; 1520 1521 return ((response == -1) ? -1 : 0); 1522 } 1523 1524 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1525 unsigned short converter_format, unsigned int *res) 1526 { 1527 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1528 converter_format & 0xffff, res); 1529 } 1530 1531 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1532 hda_nid_t nid, unsigned char stream, 1533 unsigned char channel, unsigned int *res) 1534 { 1535 unsigned char converter_stream_channel = 0; 1536 1537 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1538 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1539 converter_stream_channel, res); 1540 } 1541 1542 /* Chip access helper function */ 1543 static int chipio_send(struct hda_codec *codec, 1544 unsigned int reg, 1545 unsigned int data) 1546 { 1547 unsigned int res; 1548 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1549 1550 /* send bits of data specified by reg */ 1551 do { 1552 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1553 reg, data); 1554 if (res == VENDOR_STATUS_CHIPIO_OK) 1555 return 0; 1556 msleep(20); 1557 } while (time_before(jiffies, timeout)); 1558 1559 return -EIO; 1560 } 1561 1562 /* 1563 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1564 */ 1565 static int chipio_write_address(struct hda_codec *codec, 1566 unsigned int chip_addx) 1567 { 1568 struct ca0132_spec *spec = codec->spec; 1569 int res; 1570 1571 if (spec->curr_chip_addx == chip_addx) 1572 return 0; 1573 1574 /* send low 16 bits of the address */ 1575 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1576 chip_addx & 0xffff); 1577 1578 if (res != -EIO) { 1579 /* send high 16 bits of the address */ 1580 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1581 chip_addx >> 16); 1582 } 1583 1584 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1585 1586 return res; 1587 } 1588 1589 /* 1590 * Write data through the vendor widget -- NOT protected by the Mutex! 1591 */ 1592 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1593 { 1594 struct ca0132_spec *spec = codec->spec; 1595 int res; 1596 1597 /* send low 16 bits of the data */ 1598 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1599 1600 if (res != -EIO) { 1601 /* send high 16 bits of the data */ 1602 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1603 data >> 16); 1604 } 1605 1606 /*If no error encountered, automatically increment the address 1607 as per chip behaviour*/ 1608 spec->curr_chip_addx = (res != -EIO) ? 1609 (spec->curr_chip_addx + 4) : ~0U; 1610 return res; 1611 } 1612 1613 /* 1614 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1615 */ 1616 static int chipio_write_data_multiple(struct hda_codec *codec, 1617 const u32 *data, 1618 unsigned int count) 1619 { 1620 int status = 0; 1621 1622 if (data == NULL) { 1623 codec_dbg(codec, "chipio_write_data null ptr\n"); 1624 return -EINVAL; 1625 } 1626 1627 while ((count-- != 0) && (status == 0)) 1628 status = chipio_write_data(codec, *data++); 1629 1630 return status; 1631 } 1632 1633 1634 /* 1635 * Read data through the vendor widget -- NOT protected by the Mutex! 1636 */ 1637 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1638 { 1639 struct ca0132_spec *spec = codec->spec; 1640 int res; 1641 1642 /* post read */ 1643 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1644 1645 if (res != -EIO) { 1646 /* read status */ 1647 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1648 } 1649 1650 if (res != -EIO) { 1651 /* read data */ 1652 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1653 VENDOR_CHIPIO_HIC_READ_DATA, 1654 0); 1655 } 1656 1657 /*If no error encountered, automatically increment the address 1658 as per chip behaviour*/ 1659 spec->curr_chip_addx = (res != -EIO) ? 1660 (spec->curr_chip_addx + 4) : ~0U; 1661 return res; 1662 } 1663 1664 /* 1665 * Write given value to the given address through the chip I/O widget. 1666 * protected by the Mutex 1667 */ 1668 static int chipio_write(struct hda_codec *codec, 1669 unsigned int chip_addx, const unsigned int data) 1670 { 1671 struct ca0132_spec *spec = codec->spec; 1672 int err; 1673 1674 mutex_lock(&spec->chipio_mutex); 1675 1676 /* write the address, and if successful proceed to write data */ 1677 err = chipio_write_address(codec, chip_addx); 1678 if (err < 0) 1679 goto exit; 1680 1681 err = chipio_write_data(codec, data); 1682 if (err < 0) 1683 goto exit; 1684 1685 exit: 1686 mutex_unlock(&spec->chipio_mutex); 1687 return err; 1688 } 1689 1690 /* 1691 * Write given value to the given address through the chip I/O widget. 1692 * not protected by the Mutex 1693 */ 1694 static int chipio_write_no_mutex(struct hda_codec *codec, 1695 unsigned int chip_addx, const unsigned int data) 1696 { 1697 int err; 1698 1699 1700 /* write the address, and if successful proceed to write data */ 1701 err = chipio_write_address(codec, chip_addx); 1702 if (err < 0) 1703 goto exit; 1704 1705 err = chipio_write_data(codec, data); 1706 if (err < 0) 1707 goto exit; 1708 1709 exit: 1710 return err; 1711 } 1712 1713 /* 1714 * Write multiple values to the given address through the chip I/O widget. 1715 * protected by the Mutex 1716 */ 1717 static int chipio_write_multiple(struct hda_codec *codec, 1718 u32 chip_addx, 1719 const u32 *data, 1720 unsigned int count) 1721 { 1722 struct ca0132_spec *spec = codec->spec; 1723 int status; 1724 1725 mutex_lock(&spec->chipio_mutex); 1726 status = chipio_write_address(codec, chip_addx); 1727 if (status < 0) 1728 goto error; 1729 1730 status = chipio_write_data_multiple(codec, data, count); 1731 error: 1732 mutex_unlock(&spec->chipio_mutex); 1733 1734 return status; 1735 } 1736 1737 /* 1738 * Read the given address through the chip I/O widget 1739 * protected by the Mutex 1740 */ 1741 static int chipio_read(struct hda_codec *codec, 1742 unsigned int chip_addx, unsigned int *data) 1743 { 1744 struct ca0132_spec *spec = codec->spec; 1745 int err; 1746 1747 mutex_lock(&spec->chipio_mutex); 1748 1749 /* write the address, and if successful proceed to write data */ 1750 err = chipio_write_address(codec, chip_addx); 1751 if (err < 0) 1752 goto exit; 1753 1754 err = chipio_read_data(codec, data); 1755 if (err < 0) 1756 goto exit; 1757 1758 exit: 1759 mutex_unlock(&spec->chipio_mutex); 1760 return err; 1761 } 1762 1763 /* 1764 * Set chip control flags through the chip I/O widget. 1765 */ 1766 static void chipio_set_control_flag(struct hda_codec *codec, 1767 enum control_flag_id flag_id, 1768 bool flag_state) 1769 { 1770 unsigned int val; 1771 unsigned int flag_bit; 1772 1773 flag_bit = (flag_state ? 1 : 0); 1774 val = (flag_bit << 7) | (flag_id); 1775 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1776 VENDOR_CHIPIO_FLAG_SET, val); 1777 } 1778 1779 /* 1780 * Set chip parameters through the chip I/O widget. 1781 */ 1782 static void chipio_set_control_param(struct hda_codec *codec, 1783 enum control_param_id param_id, int param_val) 1784 { 1785 struct ca0132_spec *spec = codec->spec; 1786 int val; 1787 1788 if ((param_id < 32) && (param_val < 8)) { 1789 val = (param_val << 5) | (param_id); 1790 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1791 VENDOR_CHIPIO_PARAM_SET, val); 1792 } else { 1793 mutex_lock(&spec->chipio_mutex); 1794 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1795 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1796 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1797 param_id); 1798 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1799 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1800 param_val); 1801 } 1802 mutex_unlock(&spec->chipio_mutex); 1803 } 1804 } 1805 1806 /* 1807 * Set chip parameters through the chip I/O widget. NO MUTEX. 1808 */ 1809 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1810 enum control_param_id param_id, int param_val) 1811 { 1812 int val; 1813 1814 if ((param_id < 32) && (param_val < 8)) { 1815 val = (param_val << 5) | (param_id); 1816 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1817 VENDOR_CHIPIO_PARAM_SET, val); 1818 } else { 1819 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1820 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1821 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1822 param_id); 1823 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1824 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1825 param_val); 1826 } 1827 } 1828 } 1829 /* 1830 * Connect stream to a source point, and then connect 1831 * that source point to a destination point. 1832 */ 1833 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1834 int streamid, int source_point, int dest_point) 1835 { 1836 chipio_set_control_param_no_mutex(codec, 1837 CONTROL_PARAM_STREAM_ID, streamid); 1838 chipio_set_control_param_no_mutex(codec, 1839 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1840 chipio_set_control_param_no_mutex(codec, 1841 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1842 } 1843 1844 /* 1845 * Set number of channels in the selected stream. 1846 */ 1847 static void chipio_set_stream_channels(struct hda_codec *codec, 1848 int streamid, unsigned int channels) 1849 { 1850 chipio_set_control_param_no_mutex(codec, 1851 CONTROL_PARAM_STREAM_ID, streamid); 1852 chipio_set_control_param_no_mutex(codec, 1853 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1854 } 1855 1856 /* 1857 * Enable/Disable audio stream. 1858 */ 1859 static void chipio_set_stream_control(struct hda_codec *codec, 1860 int streamid, int enable) 1861 { 1862 chipio_set_control_param_no_mutex(codec, 1863 CONTROL_PARAM_STREAM_ID, streamid); 1864 chipio_set_control_param_no_mutex(codec, 1865 CONTROL_PARAM_STREAM_CONTROL, enable); 1866 } 1867 1868 /* 1869 * Get ChipIO audio stream's status. 1870 */ 1871 static void chipio_get_stream_control(struct hda_codec *codec, 1872 int streamid, unsigned int *enable) 1873 { 1874 chipio_set_control_param_no_mutex(codec, 1875 CONTROL_PARAM_STREAM_ID, streamid); 1876 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1877 VENDOR_CHIPIO_PARAM_GET, 1878 CONTROL_PARAM_STREAM_CONTROL); 1879 } 1880 1881 /* 1882 * Set sampling rate of the connection point. NO MUTEX. 1883 */ 1884 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1885 int connid, enum ca0132_sample_rate rate) 1886 { 1887 chipio_set_control_param_no_mutex(codec, 1888 CONTROL_PARAM_CONN_POINT_ID, connid); 1889 chipio_set_control_param_no_mutex(codec, 1890 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1891 } 1892 1893 /* 1894 * Set sampling rate of the connection point. 1895 */ 1896 static void chipio_set_conn_rate(struct hda_codec *codec, 1897 int connid, enum ca0132_sample_rate rate) 1898 { 1899 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1900 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1901 rate); 1902 } 1903 1904 /* 1905 * Writes to the 8051's internal address space directly instead of indirectly, 1906 * giving access to the special function registers located at addresses 1907 * 0x80-0xFF. 1908 */ 1909 static void chipio_8051_write_direct(struct hda_codec *codec, 1910 unsigned int addr, unsigned int data) 1911 { 1912 unsigned int verb; 1913 1914 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1915 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1916 } 1917 1918 /* 1919 * Writes to the 8051's exram, which has 16-bits of address space. 1920 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. 1921 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by 1922 * setting the pmem bank selection SFR. 1923 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff 1924 * being writable. 1925 */ 1926 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) 1927 { 1928 unsigned int tmp; 1929 1930 /* Lower 8-bits. */ 1931 tmp = addr & 0xff; 1932 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1933 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); 1934 1935 /* Upper 8-bits. */ 1936 tmp = (addr >> 8) & 0xff; 1937 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1938 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); 1939 } 1940 1941 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) 1942 { 1943 /* 8-bits of data. */ 1944 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1945 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); 1946 } 1947 1948 static unsigned int chipio_8051_get_data(struct hda_codec *codec) 1949 { 1950 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1951 VENDOR_CHIPIO_8051_DATA_READ, 0); 1952 } 1953 1954 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ 1955 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) 1956 { 1957 /* 8-bits of data. */ 1958 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1959 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); 1960 } 1961 1962 static void chipio_8051_write_exram(struct hda_codec *codec, 1963 unsigned int addr, unsigned int data) 1964 { 1965 struct ca0132_spec *spec = codec->spec; 1966 1967 mutex_lock(&spec->chipio_mutex); 1968 1969 chipio_8051_set_address(codec, addr); 1970 chipio_8051_set_data(codec, data); 1971 1972 mutex_unlock(&spec->chipio_mutex); 1973 } 1974 1975 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, 1976 unsigned int addr, unsigned int data) 1977 { 1978 chipio_8051_set_address(codec, addr); 1979 chipio_8051_set_data(codec, data); 1980 } 1981 1982 /* Readback data from the 8051's exram. No mutex. */ 1983 static void chipio_8051_read_exram(struct hda_codec *codec, 1984 unsigned int addr, unsigned int *data) 1985 { 1986 chipio_8051_set_address(codec, addr); 1987 *data = chipio_8051_get_data(codec); 1988 } 1989 1990 static void chipio_8051_write_pll_pmu(struct hda_codec *codec, 1991 unsigned int addr, unsigned int data) 1992 { 1993 struct ca0132_spec *spec = codec->spec; 1994 1995 mutex_lock(&spec->chipio_mutex); 1996 1997 chipio_8051_set_address(codec, addr & 0xff); 1998 chipio_8051_set_data_pll(codec, data); 1999 2000 mutex_unlock(&spec->chipio_mutex); 2001 } 2002 2003 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, 2004 unsigned int addr, unsigned int data) 2005 { 2006 chipio_8051_set_address(codec, addr & 0xff); 2007 chipio_8051_set_data_pll(codec, data); 2008 } 2009 2010 /* 2011 * Enable clocks. 2012 */ 2013 static void chipio_enable_clocks(struct hda_codec *codec) 2014 { 2015 struct ca0132_spec *spec = codec->spec; 2016 2017 mutex_lock(&spec->chipio_mutex); 2018 2019 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); 2020 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); 2021 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); 2022 2023 mutex_unlock(&spec->chipio_mutex); 2024 } 2025 2026 /* 2027 * CA0132 DSP IO stuffs 2028 */ 2029 static int dspio_send(struct hda_codec *codec, unsigned int reg, 2030 unsigned int data) 2031 { 2032 int res; 2033 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2034 2035 /* send bits of data specified by reg to dsp */ 2036 do { 2037 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 2038 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 2039 return res; 2040 msleep(20); 2041 } while (time_before(jiffies, timeout)); 2042 2043 return -EIO; 2044 } 2045 2046 /* 2047 * Wait for DSP to be ready for commands 2048 */ 2049 static void dspio_write_wait(struct hda_codec *codec) 2050 { 2051 int status; 2052 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2053 2054 do { 2055 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2056 VENDOR_DSPIO_STATUS, 0); 2057 if ((status == VENDOR_STATUS_DSPIO_OK) || 2058 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 2059 break; 2060 msleep(1); 2061 } while (time_before(jiffies, timeout)); 2062 } 2063 2064 /* 2065 * Write SCP data to DSP 2066 */ 2067 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 2068 { 2069 struct ca0132_spec *spec = codec->spec; 2070 int status; 2071 2072 dspio_write_wait(codec); 2073 2074 mutex_lock(&spec->chipio_mutex); 2075 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 2076 scp_data & 0xffff); 2077 if (status < 0) 2078 goto error; 2079 2080 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 2081 scp_data >> 16); 2082 if (status < 0) 2083 goto error; 2084 2085 /* OK, now check if the write itself has executed*/ 2086 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2087 VENDOR_DSPIO_STATUS, 0); 2088 error: 2089 mutex_unlock(&spec->chipio_mutex); 2090 2091 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 2092 -EIO : 0; 2093 } 2094 2095 /* 2096 * Write multiple SCP data to DSP 2097 */ 2098 static int dspio_write_multiple(struct hda_codec *codec, 2099 unsigned int *buffer, unsigned int size) 2100 { 2101 int status = 0; 2102 unsigned int count; 2103 2104 if (buffer == NULL) 2105 return -EINVAL; 2106 2107 count = 0; 2108 while (count < size) { 2109 status = dspio_write(codec, *buffer++); 2110 if (status != 0) 2111 break; 2112 count++; 2113 } 2114 2115 return status; 2116 } 2117 2118 static int dspio_read(struct hda_codec *codec, unsigned int *data) 2119 { 2120 int status; 2121 2122 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 2123 if (status == -EIO) 2124 return status; 2125 2126 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 2127 if (status == -EIO || 2128 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 2129 return -EIO; 2130 2131 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2132 VENDOR_DSPIO_SCP_READ_DATA, 0); 2133 2134 return 0; 2135 } 2136 2137 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2138 unsigned int *buf_size, unsigned int size_count) 2139 { 2140 int status = 0; 2141 unsigned int size = *buf_size; 2142 unsigned int count; 2143 unsigned int skip_count; 2144 unsigned int dummy; 2145 2146 if (buffer == NULL) 2147 return -1; 2148 2149 count = 0; 2150 while (count < size && count < size_count) { 2151 status = dspio_read(codec, buffer++); 2152 if (status != 0) 2153 break; 2154 count++; 2155 } 2156 2157 skip_count = count; 2158 if (status == 0) { 2159 while (skip_count < size) { 2160 status = dspio_read(codec, &dummy); 2161 if (status != 0) 2162 break; 2163 skip_count++; 2164 } 2165 } 2166 *buf_size = count; 2167 2168 return status; 2169 } 2170 2171 /* 2172 * Construct the SCP header using corresponding fields 2173 */ 2174 static inline unsigned int 2175 make_scp_header(unsigned int target_id, unsigned int source_id, 2176 unsigned int get_flag, unsigned int req, 2177 unsigned int device_flag, unsigned int resp_flag, 2178 unsigned int error_flag, unsigned int data_size) 2179 { 2180 unsigned int header = 0; 2181 2182 header = (data_size & 0x1f) << 27; 2183 header |= (error_flag & 0x01) << 26; 2184 header |= (resp_flag & 0x01) << 25; 2185 header |= (device_flag & 0x01) << 24; 2186 header |= (req & 0x7f) << 17; 2187 header |= (get_flag & 0x01) << 16; 2188 header |= (source_id & 0xff) << 8; 2189 header |= target_id & 0xff; 2190 2191 return header; 2192 } 2193 2194 /* 2195 * Extract corresponding fields from SCP header 2196 */ 2197 static inline void 2198 extract_scp_header(unsigned int header, 2199 unsigned int *target_id, unsigned int *source_id, 2200 unsigned int *get_flag, unsigned int *req, 2201 unsigned int *device_flag, unsigned int *resp_flag, 2202 unsigned int *error_flag, unsigned int *data_size) 2203 { 2204 if (data_size) 2205 *data_size = (header >> 27) & 0x1f; 2206 if (error_flag) 2207 *error_flag = (header >> 26) & 0x01; 2208 if (resp_flag) 2209 *resp_flag = (header >> 25) & 0x01; 2210 if (device_flag) 2211 *device_flag = (header >> 24) & 0x01; 2212 if (req) 2213 *req = (header >> 17) & 0x7f; 2214 if (get_flag) 2215 *get_flag = (header >> 16) & 0x01; 2216 if (source_id) 2217 *source_id = (header >> 8) & 0xff; 2218 if (target_id) 2219 *target_id = header & 0xff; 2220 } 2221 2222 #define SCP_MAX_DATA_WORDS (16) 2223 2224 /* Structure to contain any SCP message */ 2225 struct scp_msg { 2226 unsigned int hdr; 2227 unsigned int data[SCP_MAX_DATA_WORDS]; 2228 }; 2229 2230 static void dspio_clear_response_queue(struct hda_codec *codec) 2231 { 2232 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2233 unsigned int dummy = 0; 2234 int status; 2235 2236 /* clear all from the response queue */ 2237 do { 2238 status = dspio_read(codec, &dummy); 2239 } while (status == 0 && time_before(jiffies, timeout)); 2240 } 2241 2242 static int dspio_get_response_data(struct hda_codec *codec) 2243 { 2244 struct ca0132_spec *spec = codec->spec; 2245 unsigned int data = 0; 2246 unsigned int count; 2247 2248 if (dspio_read(codec, &data) < 0) 2249 return -EIO; 2250 2251 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2252 spec->scp_resp_header = data; 2253 spec->scp_resp_count = data >> 27; 2254 count = spec->wait_num_data; 2255 dspio_read_multiple(codec, spec->scp_resp_data, 2256 &spec->scp_resp_count, count); 2257 return 0; 2258 } 2259 2260 return -EIO; 2261 } 2262 2263 /* 2264 * Send SCP message to DSP 2265 */ 2266 static int dspio_send_scp_message(struct hda_codec *codec, 2267 unsigned char *send_buf, 2268 unsigned int send_buf_size, 2269 unsigned char *return_buf, 2270 unsigned int return_buf_size, 2271 unsigned int *bytes_returned) 2272 { 2273 struct ca0132_spec *spec = codec->spec; 2274 int status; 2275 unsigned int scp_send_size = 0; 2276 unsigned int total_size; 2277 bool waiting_for_resp = false; 2278 unsigned int header; 2279 struct scp_msg *ret_msg; 2280 unsigned int resp_src_id, resp_target_id; 2281 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2282 2283 if (bytes_returned) 2284 *bytes_returned = 0; 2285 2286 /* get scp header from buffer */ 2287 header = *((unsigned int *)send_buf); 2288 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2289 &device_flag, NULL, NULL, &data_size); 2290 scp_send_size = data_size + 1; 2291 total_size = (scp_send_size * 4); 2292 2293 if (send_buf_size < total_size) 2294 return -EINVAL; 2295 2296 if (get_flag || device_flag) { 2297 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2298 return -EINVAL; 2299 2300 spec->wait_scp_header = *((unsigned int *)send_buf); 2301 2302 /* swap source id with target id */ 2303 resp_target_id = src_id; 2304 resp_src_id = target_id; 2305 spec->wait_scp_header &= 0xffff0000; 2306 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2307 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2308 spec->wait_scp = 1; 2309 waiting_for_resp = true; 2310 } 2311 2312 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2313 scp_send_size); 2314 if (status < 0) { 2315 spec->wait_scp = 0; 2316 return status; 2317 } 2318 2319 if (waiting_for_resp) { 2320 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2321 memset(return_buf, 0, return_buf_size); 2322 do { 2323 msleep(20); 2324 } while (spec->wait_scp && time_before(jiffies, timeout)); 2325 waiting_for_resp = false; 2326 if (!spec->wait_scp) { 2327 ret_msg = (struct scp_msg *)return_buf; 2328 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2329 memcpy(&ret_msg->data, spec->scp_resp_data, 2330 spec->wait_num_data); 2331 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2332 status = 0; 2333 } else { 2334 status = -EIO; 2335 } 2336 spec->wait_scp = 0; 2337 } 2338 2339 return status; 2340 } 2341 2342 /** 2343 * dspio_scp - Prepare and send the SCP message to DSP 2344 * @codec: the HDA codec 2345 * @mod_id: ID of the DSP module to send the command 2346 * @src_id: ID of the source 2347 * @req: ID of request to send to the DSP module 2348 * @dir: SET or GET 2349 * @data: pointer to the data to send with the request, request specific 2350 * @len: length of the data, in bytes 2351 * @reply: point to the buffer to hold data returned for a reply 2352 * @reply_len: length of the reply buffer returned from GET 2353 * 2354 * Returns zero or a negative error code. 2355 */ 2356 static int dspio_scp(struct hda_codec *codec, 2357 int mod_id, int src_id, int req, int dir, const void *data, 2358 unsigned int len, void *reply, unsigned int *reply_len) 2359 { 2360 int status = 0; 2361 struct scp_msg scp_send, scp_reply; 2362 unsigned int ret_bytes, send_size, ret_size; 2363 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2364 unsigned int reply_data_size; 2365 2366 memset(&scp_send, 0, sizeof(scp_send)); 2367 memset(&scp_reply, 0, sizeof(scp_reply)); 2368 2369 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2370 return -EINVAL; 2371 2372 if (dir == SCP_GET && reply == NULL) { 2373 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2374 return -EINVAL; 2375 } 2376 2377 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2378 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2379 return -EINVAL; 2380 } 2381 2382 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2383 0, 0, 0, len/sizeof(unsigned int)); 2384 if (data != NULL && len > 0) { 2385 len = min((unsigned int)(sizeof(scp_send.data)), len); 2386 memcpy(scp_send.data, data, len); 2387 } 2388 2389 ret_bytes = 0; 2390 send_size = sizeof(unsigned int) + len; 2391 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2392 send_size, (unsigned char *)&scp_reply, 2393 sizeof(scp_reply), &ret_bytes); 2394 2395 if (status < 0) { 2396 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2397 return status; 2398 } 2399 2400 /* extract send and reply headers members */ 2401 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2402 NULL, NULL, NULL, NULL, NULL); 2403 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2404 &reply_resp_flag, &reply_error_flag, 2405 &reply_data_size); 2406 2407 if (!send_get_flag) 2408 return 0; 2409 2410 if (reply_resp_flag && !reply_error_flag) { 2411 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2412 / sizeof(unsigned int); 2413 2414 if (*reply_len < ret_size*sizeof(unsigned int)) { 2415 codec_dbg(codec, "reply too long for buf\n"); 2416 return -EINVAL; 2417 } else if (ret_size != reply_data_size) { 2418 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2419 return -EINVAL; 2420 } else if (!reply) { 2421 codec_dbg(codec, "NULL reply\n"); 2422 return -EINVAL; 2423 } else { 2424 *reply_len = ret_size*sizeof(unsigned int); 2425 memcpy(reply, scp_reply.data, *reply_len); 2426 } 2427 } else { 2428 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2429 return -EIO; 2430 } 2431 2432 return status; 2433 } 2434 2435 /* 2436 * Set DSP parameters 2437 */ 2438 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2439 int src_id, int req, const void *data, unsigned int len) 2440 { 2441 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2442 NULL); 2443 } 2444 2445 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2446 int req, const unsigned int data) 2447 { 2448 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2449 sizeof(unsigned int)); 2450 } 2451 2452 /* 2453 * Allocate a DSP DMA channel via an SCP message 2454 */ 2455 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2456 { 2457 int status = 0; 2458 unsigned int size = sizeof(*dma_chan); 2459 2460 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2461 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2462 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2463 dma_chan, &size); 2464 2465 if (status < 0) { 2466 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2467 return status; 2468 } 2469 2470 if ((*dma_chan + 1) == 0) { 2471 codec_dbg(codec, "no free dma channels to allocate\n"); 2472 return -EBUSY; 2473 } 2474 2475 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2476 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2477 2478 return status; 2479 } 2480 2481 /* 2482 * Free a DSP DMA via an SCP message 2483 */ 2484 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2485 { 2486 int status = 0; 2487 unsigned int dummy = 0; 2488 2489 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2490 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2491 2492 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2493 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2494 sizeof(dma_chan), NULL, &dummy); 2495 2496 if (status < 0) { 2497 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2498 return status; 2499 } 2500 2501 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2502 2503 return status; 2504 } 2505 2506 /* 2507 * (Re)start the DSP 2508 */ 2509 static int dsp_set_run_state(struct hda_codec *codec) 2510 { 2511 unsigned int dbg_ctrl_reg; 2512 unsigned int halt_state; 2513 int err; 2514 2515 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2516 if (err < 0) 2517 return err; 2518 2519 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2520 DSP_DBGCNTL_STATE_LOBIT; 2521 2522 if (halt_state != 0) { 2523 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2524 DSP_DBGCNTL_SS_MASK); 2525 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2526 dbg_ctrl_reg); 2527 if (err < 0) 2528 return err; 2529 2530 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2531 DSP_DBGCNTL_EXEC_MASK; 2532 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2533 dbg_ctrl_reg); 2534 if (err < 0) 2535 return err; 2536 } 2537 2538 return 0; 2539 } 2540 2541 /* 2542 * Reset the DSP 2543 */ 2544 static int dsp_reset(struct hda_codec *codec) 2545 { 2546 unsigned int res; 2547 int retry = 20; 2548 2549 codec_dbg(codec, "dsp_reset\n"); 2550 do { 2551 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2552 retry--; 2553 } while (res == -EIO && retry); 2554 2555 if (!retry) { 2556 codec_dbg(codec, "dsp_reset timeout\n"); 2557 return -EIO; 2558 } 2559 2560 return 0; 2561 } 2562 2563 /* 2564 * Convert chip address to DSP address 2565 */ 2566 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2567 bool *code, bool *yram) 2568 { 2569 *code = *yram = false; 2570 2571 if (UC_RANGE(chip_addx, 1)) { 2572 *code = true; 2573 return UC_OFF(chip_addx); 2574 } else if (X_RANGE_ALL(chip_addx, 1)) { 2575 return X_OFF(chip_addx); 2576 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2577 *yram = true; 2578 return Y_OFF(chip_addx); 2579 } 2580 2581 return INVALID_CHIP_ADDRESS; 2582 } 2583 2584 /* 2585 * Check if the DSP DMA is active 2586 */ 2587 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2588 { 2589 unsigned int dma_chnlstart_reg; 2590 2591 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2592 2593 return ((dma_chnlstart_reg & (1 << 2594 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2595 } 2596 2597 static int dsp_dma_setup_common(struct hda_codec *codec, 2598 unsigned int chip_addx, 2599 unsigned int dma_chan, 2600 unsigned int port_map_mask, 2601 bool ovly) 2602 { 2603 int status = 0; 2604 unsigned int chnl_prop; 2605 unsigned int dsp_addx; 2606 unsigned int active; 2607 bool code, yram; 2608 2609 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2610 2611 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2612 codec_dbg(codec, "dma chan num invalid\n"); 2613 return -EINVAL; 2614 } 2615 2616 if (dsp_is_dma_active(codec, dma_chan)) { 2617 codec_dbg(codec, "dma already active\n"); 2618 return -EBUSY; 2619 } 2620 2621 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2622 2623 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2624 codec_dbg(codec, "invalid chip addr\n"); 2625 return -ENXIO; 2626 } 2627 2628 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2629 active = 0; 2630 2631 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2632 2633 if (ovly) { 2634 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2635 &chnl_prop); 2636 2637 if (status < 0) { 2638 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2639 return status; 2640 } 2641 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2642 } 2643 2644 if (!code) 2645 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2646 else 2647 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2648 2649 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2650 2651 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2652 if (status < 0) { 2653 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2654 return status; 2655 } 2656 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2657 2658 if (ovly) { 2659 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2660 &active); 2661 2662 if (status < 0) { 2663 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2664 return status; 2665 } 2666 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2667 } 2668 2669 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2670 DSPDMAC_ACTIVE_AAR_MASK; 2671 2672 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2673 if (status < 0) { 2674 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2675 return status; 2676 } 2677 2678 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2679 2680 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2681 port_map_mask); 2682 if (status < 0) { 2683 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2684 return status; 2685 } 2686 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2687 2688 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2689 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2690 if (status < 0) { 2691 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2692 return status; 2693 } 2694 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2695 2696 codec_dbg(codec, 2697 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2698 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2699 chip_addx, dsp_addx, dma_chan, 2700 port_map_mask, chnl_prop, active); 2701 2702 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2703 2704 return 0; 2705 } 2706 2707 /* 2708 * Setup the DSP DMA per-transfer-specific registers 2709 */ 2710 static int dsp_dma_setup(struct hda_codec *codec, 2711 unsigned int chip_addx, 2712 unsigned int count, 2713 unsigned int dma_chan) 2714 { 2715 int status = 0; 2716 bool code, yram; 2717 unsigned int dsp_addx; 2718 unsigned int addr_field; 2719 unsigned int incr_field; 2720 unsigned int base_cnt; 2721 unsigned int cur_cnt; 2722 unsigned int dma_cfg = 0; 2723 unsigned int adr_ofs = 0; 2724 unsigned int xfr_cnt = 0; 2725 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2726 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2727 2728 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2729 2730 if (count > max_dma_count) { 2731 codec_dbg(codec, "count too big\n"); 2732 return -EINVAL; 2733 } 2734 2735 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2736 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2737 codec_dbg(codec, "invalid chip addr\n"); 2738 return -ENXIO; 2739 } 2740 2741 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2742 2743 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2744 incr_field = 0; 2745 2746 if (!code) { 2747 addr_field <<= 1; 2748 if (yram) 2749 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2750 2751 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2752 } 2753 2754 dma_cfg = addr_field + incr_field; 2755 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2756 dma_cfg); 2757 if (status < 0) { 2758 codec_dbg(codec, "write DMACFG Reg fail\n"); 2759 return status; 2760 } 2761 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2762 2763 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2764 (code ? 0 : 1)); 2765 2766 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2767 adr_ofs); 2768 if (status < 0) { 2769 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2770 return status; 2771 } 2772 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2773 2774 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2775 2776 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2777 2778 xfr_cnt = base_cnt | cur_cnt; 2779 2780 status = chipio_write(codec, 2781 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2782 if (status < 0) { 2783 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2784 return status; 2785 } 2786 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2787 2788 codec_dbg(codec, 2789 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2790 "ADROFS=0x%x, XFRCNT=0x%x\n", 2791 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2792 2793 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2794 2795 return 0; 2796 } 2797 2798 /* 2799 * Start the DSP DMA 2800 */ 2801 static int dsp_dma_start(struct hda_codec *codec, 2802 unsigned int dma_chan, bool ovly) 2803 { 2804 unsigned int reg = 0; 2805 int status = 0; 2806 2807 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2808 2809 if (ovly) { 2810 status = chipio_read(codec, 2811 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2812 2813 if (status < 0) { 2814 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2815 return status; 2816 } 2817 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2818 2819 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2820 DSPDMAC_CHNLSTART_DIS_MASK); 2821 } 2822 2823 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2824 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2825 if (status < 0) { 2826 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2827 return status; 2828 } 2829 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2830 2831 return status; 2832 } 2833 2834 /* 2835 * Stop the DSP DMA 2836 */ 2837 static int dsp_dma_stop(struct hda_codec *codec, 2838 unsigned int dma_chan, bool ovly) 2839 { 2840 unsigned int reg = 0; 2841 int status = 0; 2842 2843 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2844 2845 if (ovly) { 2846 status = chipio_read(codec, 2847 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2848 2849 if (status < 0) { 2850 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2851 return status; 2852 } 2853 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2854 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2855 DSPDMAC_CHNLSTART_DIS_MASK); 2856 } 2857 2858 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2859 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2860 if (status < 0) { 2861 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2862 return status; 2863 } 2864 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2865 2866 return status; 2867 } 2868 2869 /** 2870 * dsp_allocate_router_ports - Allocate router ports 2871 * 2872 * @codec: the HDA codec 2873 * @num_chans: number of channels in the stream 2874 * @ports_per_channel: number of ports per channel 2875 * @start_device: start device 2876 * @port_map: pointer to the port list to hold the allocated ports 2877 * 2878 * Returns zero or a negative error code. 2879 */ 2880 static int dsp_allocate_router_ports(struct hda_codec *codec, 2881 unsigned int num_chans, 2882 unsigned int ports_per_channel, 2883 unsigned int start_device, 2884 unsigned int *port_map) 2885 { 2886 int status = 0; 2887 int res; 2888 u8 val; 2889 2890 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2891 if (status < 0) 2892 return status; 2893 2894 val = start_device << 6; 2895 val |= (ports_per_channel - 1) << 4; 2896 val |= num_chans - 1; 2897 2898 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2899 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2900 val); 2901 2902 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2903 VENDOR_CHIPIO_PORT_ALLOC_SET, 2904 MEM_CONNID_DSP); 2905 2906 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2907 if (status < 0) 2908 return status; 2909 2910 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2911 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2912 2913 *port_map = res; 2914 2915 return (res < 0) ? res : 0; 2916 } 2917 2918 /* 2919 * Free router ports 2920 */ 2921 static int dsp_free_router_ports(struct hda_codec *codec) 2922 { 2923 int status = 0; 2924 2925 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2926 if (status < 0) 2927 return status; 2928 2929 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2930 VENDOR_CHIPIO_PORT_FREE_SET, 2931 MEM_CONNID_DSP); 2932 2933 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2934 2935 return status; 2936 } 2937 2938 /* 2939 * Allocate DSP ports for the download stream 2940 */ 2941 static int dsp_allocate_ports(struct hda_codec *codec, 2942 unsigned int num_chans, 2943 unsigned int rate_multi, unsigned int *port_map) 2944 { 2945 int status; 2946 2947 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2948 2949 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2950 codec_dbg(codec, "bad rate multiple\n"); 2951 return -EINVAL; 2952 } 2953 2954 status = dsp_allocate_router_ports(codec, num_chans, 2955 rate_multi, 0, port_map); 2956 2957 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2958 2959 return status; 2960 } 2961 2962 static int dsp_allocate_ports_format(struct hda_codec *codec, 2963 const unsigned short fmt, 2964 unsigned int *port_map) 2965 { 2966 unsigned int num_chans; 2967 2968 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2969 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2970 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2971 2972 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2973 codec_dbg(codec, "bad rate multiple\n"); 2974 return -EINVAL; 2975 } 2976 2977 num_chans = get_hdafmt_chs(fmt) + 1; 2978 2979 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2980 } 2981 2982 /* 2983 * free DSP ports 2984 */ 2985 static int dsp_free_ports(struct hda_codec *codec) 2986 { 2987 int status; 2988 2989 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2990 2991 status = dsp_free_router_ports(codec); 2992 if (status < 0) { 2993 codec_dbg(codec, "free router ports fail\n"); 2994 return status; 2995 } 2996 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2997 2998 return status; 2999 } 3000 3001 /* 3002 * HDA DMA engine stuffs for DSP code download 3003 */ 3004 struct dma_engine { 3005 struct hda_codec *codec; 3006 unsigned short m_converter_format; 3007 struct snd_dma_buffer *dmab; 3008 unsigned int buf_size; 3009 }; 3010 3011 3012 enum dma_state { 3013 DMA_STATE_STOP = 0, 3014 DMA_STATE_RUN = 1 3015 }; 3016 3017 static int dma_convert_to_hda_format(struct hda_codec *codec, 3018 unsigned int sample_rate, 3019 unsigned short channels, 3020 unsigned short *hda_format) 3021 { 3022 unsigned int format_val; 3023 3024 format_val = snd_hdac_calc_stream_format(sample_rate, 3025 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 3026 3027 if (hda_format) 3028 *hda_format = (unsigned short)format_val; 3029 3030 return 0; 3031 } 3032 3033 /* 3034 * Reset DMA for DSP download 3035 */ 3036 static int dma_reset(struct dma_engine *dma) 3037 { 3038 struct hda_codec *codec = dma->codec; 3039 struct ca0132_spec *spec = codec->spec; 3040 int status; 3041 3042 if (dma->dmab->area) 3043 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 3044 3045 status = snd_hda_codec_load_dsp_prepare(codec, 3046 dma->m_converter_format, 3047 dma->buf_size, 3048 dma->dmab); 3049 if (status < 0) 3050 return status; 3051 spec->dsp_stream_id = status; 3052 return 0; 3053 } 3054 3055 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 3056 { 3057 bool cmd; 3058 3059 switch (state) { 3060 case DMA_STATE_STOP: 3061 cmd = false; 3062 break; 3063 case DMA_STATE_RUN: 3064 cmd = true; 3065 break; 3066 default: 3067 return 0; 3068 } 3069 3070 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 3071 return 0; 3072 } 3073 3074 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 3075 { 3076 return dma->dmab->bytes; 3077 } 3078 3079 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 3080 { 3081 return dma->dmab->area; 3082 } 3083 3084 static int dma_xfer(struct dma_engine *dma, 3085 const unsigned int *data, 3086 unsigned int count) 3087 { 3088 memcpy(dma->dmab->area, data, count); 3089 return 0; 3090 } 3091 3092 static void dma_get_converter_format( 3093 struct dma_engine *dma, 3094 unsigned short *format) 3095 { 3096 if (format) 3097 *format = dma->m_converter_format; 3098 } 3099 3100 static unsigned int dma_get_stream_id(struct dma_engine *dma) 3101 { 3102 struct ca0132_spec *spec = dma->codec->spec; 3103 3104 return spec->dsp_stream_id; 3105 } 3106 3107 struct dsp_image_seg { 3108 u32 magic; 3109 u32 chip_addr; 3110 u32 count; 3111 u32 data[]; 3112 }; 3113 3114 static const u32 g_magic_value = 0x4c46584d; 3115 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 3116 3117 static bool is_valid(const struct dsp_image_seg *p) 3118 { 3119 return p->magic == g_magic_value; 3120 } 3121 3122 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3123 { 3124 return g_chip_addr_magic_value == p->chip_addr; 3125 } 3126 3127 static bool is_last(const struct dsp_image_seg *p) 3128 { 3129 return p->count == 0; 3130 } 3131 3132 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3133 { 3134 return struct_size(p, data, p->count); 3135 } 3136 3137 static const struct dsp_image_seg *get_next_seg_ptr( 3138 const struct dsp_image_seg *p) 3139 { 3140 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3141 } 3142 3143 /* 3144 * CA0132 chip DSP transfer stuffs. For DSP download. 3145 */ 3146 #define INVALID_DMA_CHANNEL (~0U) 3147 3148 /* 3149 * Program a list of address/data pairs via the ChipIO widget. 3150 * The segment data is in the format of successive pairs of words. 3151 * These are repeated as indicated by the segment's count field. 3152 */ 3153 static int dspxfr_hci_write(struct hda_codec *codec, 3154 const struct dsp_image_seg *fls) 3155 { 3156 int status; 3157 const u32 *data; 3158 unsigned int count; 3159 3160 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3161 codec_dbg(codec, "hci_write invalid params\n"); 3162 return -EINVAL; 3163 } 3164 3165 count = fls->count; 3166 data = (u32 *)(fls->data); 3167 while (count >= 2) { 3168 status = chipio_write(codec, data[0], data[1]); 3169 if (status < 0) { 3170 codec_dbg(codec, "hci_write chipio failed\n"); 3171 return status; 3172 } 3173 count -= 2; 3174 data += 2; 3175 } 3176 return 0; 3177 } 3178 3179 /** 3180 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. 3181 * 3182 * @codec: the HDA codec 3183 * @fls: pointer to a fast load image 3184 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3185 * no relocation 3186 * @dma_engine: pointer to DMA engine to be used for DSP download 3187 * @dma_chan: The number of DMA channels used for DSP download 3188 * @port_map_mask: port mapping 3189 * @ovly: TRUE if overlay format is required 3190 * 3191 * Returns zero or a negative error code. 3192 */ 3193 static int dspxfr_one_seg(struct hda_codec *codec, 3194 const struct dsp_image_seg *fls, 3195 unsigned int reloc, 3196 struct dma_engine *dma_engine, 3197 unsigned int dma_chan, 3198 unsigned int port_map_mask, 3199 bool ovly) 3200 { 3201 int status = 0; 3202 bool comm_dma_setup_done = false; 3203 const unsigned int *data; 3204 unsigned int chip_addx; 3205 unsigned int words_to_write; 3206 unsigned int buffer_size_words; 3207 unsigned char *buffer_addx; 3208 unsigned short hda_format; 3209 unsigned int sample_rate_div; 3210 unsigned int sample_rate_mul; 3211 unsigned int num_chans; 3212 unsigned int hda_frame_size_words; 3213 unsigned int remainder_words; 3214 const u32 *data_remainder; 3215 u32 chip_addx_remainder; 3216 unsigned int run_size_words; 3217 const struct dsp_image_seg *hci_write = NULL; 3218 unsigned long timeout; 3219 bool dma_active; 3220 3221 if (fls == NULL) 3222 return -EINVAL; 3223 if (is_hci_prog_list_seg(fls)) { 3224 hci_write = fls; 3225 fls = get_next_seg_ptr(fls); 3226 } 3227 3228 if (hci_write && (!fls || is_last(fls))) { 3229 codec_dbg(codec, "hci_write\n"); 3230 return dspxfr_hci_write(codec, hci_write); 3231 } 3232 3233 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3234 codec_dbg(codec, "Invalid Params\n"); 3235 return -EINVAL; 3236 } 3237 3238 data = fls->data; 3239 chip_addx = fls->chip_addr; 3240 words_to_write = fls->count; 3241 3242 if (!words_to_write) 3243 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3244 if (reloc) 3245 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3246 3247 if (!UC_RANGE(chip_addx, words_to_write) && 3248 !X_RANGE_ALL(chip_addx, words_to_write) && 3249 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3250 codec_dbg(codec, "Invalid chip_addx Params\n"); 3251 return -EINVAL; 3252 } 3253 3254 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3255 sizeof(u32); 3256 3257 buffer_addx = dma_get_buffer_addr(dma_engine); 3258 3259 if (buffer_addx == NULL) { 3260 codec_dbg(codec, "dma_engine buffer NULL\n"); 3261 return -EINVAL; 3262 } 3263 3264 dma_get_converter_format(dma_engine, &hda_format); 3265 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3266 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3267 num_chans = get_hdafmt_chs(hda_format) + 1; 3268 3269 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3270 (num_chans * sample_rate_mul / sample_rate_div)); 3271 3272 if (hda_frame_size_words == 0) { 3273 codec_dbg(codec, "frmsz zero\n"); 3274 return -EINVAL; 3275 } 3276 3277 buffer_size_words = min(buffer_size_words, 3278 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3279 65536 : 32768)); 3280 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3281 codec_dbg(codec, 3282 "chpadr=0x%08x frmsz=%u nchan=%u " 3283 "rate_mul=%u div=%u bufsz=%u\n", 3284 chip_addx, hda_frame_size_words, num_chans, 3285 sample_rate_mul, sample_rate_div, buffer_size_words); 3286 3287 if (buffer_size_words < hda_frame_size_words) { 3288 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3289 return -EINVAL; 3290 } 3291 3292 remainder_words = words_to_write % hda_frame_size_words; 3293 data_remainder = data; 3294 chip_addx_remainder = chip_addx; 3295 3296 data += remainder_words; 3297 chip_addx += remainder_words*sizeof(u32); 3298 words_to_write -= remainder_words; 3299 3300 while (words_to_write != 0) { 3301 run_size_words = min(buffer_size_words, words_to_write); 3302 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3303 words_to_write, run_size_words, remainder_words); 3304 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3305 if (!comm_dma_setup_done) { 3306 status = dsp_dma_stop(codec, dma_chan, ovly); 3307 if (status < 0) 3308 return status; 3309 status = dsp_dma_setup_common(codec, chip_addx, 3310 dma_chan, port_map_mask, ovly); 3311 if (status < 0) 3312 return status; 3313 comm_dma_setup_done = true; 3314 } 3315 3316 status = dsp_dma_setup(codec, chip_addx, 3317 run_size_words, dma_chan); 3318 if (status < 0) 3319 return status; 3320 status = dsp_dma_start(codec, dma_chan, ovly); 3321 if (status < 0) 3322 return status; 3323 if (!dsp_is_dma_active(codec, dma_chan)) { 3324 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3325 return -EIO; 3326 } 3327 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3328 if (status < 0) 3329 return status; 3330 if (remainder_words != 0) { 3331 status = chipio_write_multiple(codec, 3332 chip_addx_remainder, 3333 data_remainder, 3334 remainder_words); 3335 if (status < 0) 3336 return status; 3337 remainder_words = 0; 3338 } 3339 if (hci_write) { 3340 status = dspxfr_hci_write(codec, hci_write); 3341 if (status < 0) 3342 return status; 3343 hci_write = NULL; 3344 } 3345 3346 timeout = jiffies + msecs_to_jiffies(2000); 3347 do { 3348 dma_active = dsp_is_dma_active(codec, dma_chan); 3349 if (!dma_active) 3350 break; 3351 msleep(20); 3352 } while (time_before(jiffies, timeout)); 3353 if (dma_active) 3354 break; 3355 3356 codec_dbg(codec, "+++++ DMA complete\n"); 3357 dma_set_state(dma_engine, DMA_STATE_STOP); 3358 status = dma_reset(dma_engine); 3359 3360 if (status < 0) 3361 return status; 3362 3363 data += run_size_words; 3364 chip_addx += run_size_words*sizeof(u32); 3365 words_to_write -= run_size_words; 3366 } 3367 3368 if (remainder_words != 0) { 3369 status = chipio_write_multiple(codec, chip_addx_remainder, 3370 data_remainder, remainder_words); 3371 } 3372 3373 return status; 3374 } 3375 3376 /** 3377 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories 3378 * 3379 * @codec: the HDA codec 3380 * @fls_data: pointer to a fast load image 3381 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3382 * no relocation 3383 * @sample_rate: sampling rate of the stream used for DSP download 3384 * @channels: channels of the stream used for DSP download 3385 * @ovly: TRUE if overlay format is required 3386 * 3387 * Returns zero or a negative error code. 3388 */ 3389 static int dspxfr_image(struct hda_codec *codec, 3390 const struct dsp_image_seg *fls_data, 3391 unsigned int reloc, 3392 unsigned int sample_rate, 3393 unsigned short channels, 3394 bool ovly) 3395 { 3396 struct ca0132_spec *spec = codec->spec; 3397 int status; 3398 unsigned short hda_format = 0; 3399 unsigned int response; 3400 unsigned char stream_id = 0; 3401 struct dma_engine *dma_engine; 3402 unsigned int dma_chan; 3403 unsigned int port_map_mask; 3404 3405 if (fls_data == NULL) 3406 return -EINVAL; 3407 3408 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3409 if (!dma_engine) 3410 return -ENOMEM; 3411 3412 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3413 if (!dma_engine->dmab) { 3414 kfree(dma_engine); 3415 return -ENOMEM; 3416 } 3417 3418 dma_engine->codec = codec; 3419 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3420 dma_engine->m_converter_format = hda_format; 3421 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3422 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3423 3424 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3425 3426 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3427 hda_format, &response); 3428 3429 if (status < 0) { 3430 codec_dbg(codec, "set converter format fail\n"); 3431 goto exit; 3432 } 3433 3434 status = snd_hda_codec_load_dsp_prepare(codec, 3435 dma_engine->m_converter_format, 3436 dma_engine->buf_size, 3437 dma_engine->dmab); 3438 if (status < 0) 3439 goto exit; 3440 spec->dsp_stream_id = status; 3441 3442 if (ovly) { 3443 status = dspio_alloc_dma_chan(codec, &dma_chan); 3444 if (status < 0) { 3445 codec_dbg(codec, "alloc dmachan fail\n"); 3446 dma_chan = INVALID_DMA_CHANNEL; 3447 goto exit; 3448 } 3449 } 3450 3451 port_map_mask = 0; 3452 status = dsp_allocate_ports_format(codec, hda_format, 3453 &port_map_mask); 3454 if (status < 0) { 3455 codec_dbg(codec, "alloc ports fail\n"); 3456 goto exit; 3457 } 3458 3459 stream_id = dma_get_stream_id(dma_engine); 3460 status = codec_set_converter_stream_channel(codec, 3461 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3462 if (status < 0) { 3463 codec_dbg(codec, "set stream chan fail\n"); 3464 goto exit; 3465 } 3466 3467 while ((fls_data != NULL) && !is_last(fls_data)) { 3468 if (!is_valid(fls_data)) { 3469 codec_dbg(codec, "FLS check fail\n"); 3470 status = -EINVAL; 3471 goto exit; 3472 } 3473 status = dspxfr_one_seg(codec, fls_data, reloc, 3474 dma_engine, dma_chan, 3475 port_map_mask, ovly); 3476 if (status < 0) 3477 break; 3478 3479 if (is_hci_prog_list_seg(fls_data)) 3480 fls_data = get_next_seg_ptr(fls_data); 3481 3482 if ((fls_data != NULL) && !is_last(fls_data)) 3483 fls_data = get_next_seg_ptr(fls_data); 3484 } 3485 3486 if (port_map_mask != 0) 3487 status = dsp_free_ports(codec); 3488 3489 if (status < 0) 3490 goto exit; 3491 3492 status = codec_set_converter_stream_channel(codec, 3493 WIDGET_CHIP_CTRL, 0, 0, &response); 3494 3495 exit: 3496 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3497 dspio_free_dma_chan(codec, dma_chan); 3498 3499 if (dma_engine->dmab->area) 3500 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3501 kfree(dma_engine->dmab); 3502 kfree(dma_engine); 3503 3504 return status; 3505 } 3506 3507 /* 3508 * CA0132 DSP download stuffs. 3509 */ 3510 static void dspload_post_setup(struct hda_codec *codec) 3511 { 3512 struct ca0132_spec *spec = codec->spec; 3513 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3514 if (!ca0132_use_alt_functions(spec)) { 3515 /*set DSP speaker to 2.0 configuration*/ 3516 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3517 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3518 3519 /*update write pointer*/ 3520 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3521 } 3522 } 3523 3524 /** 3525 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3526 * 3527 * @codec: the HDA codec 3528 * @fls: pointer to a fast load image 3529 * @ovly: TRUE if overlay format is required 3530 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3531 * no relocation 3532 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3533 * @router_chans: number of audio router channels to be allocated (0 means use 3534 * internal defaults; max is 32) 3535 * 3536 * Download DSP from a DSP Image Fast Load structure. This structure is a 3537 * linear, non-constant sized element array of structures, each of which 3538 * contain the count of the data to be loaded, the data itself, and the 3539 * corresponding starting chip address of the starting data location. 3540 * Returns zero or a negative error code. 3541 */ 3542 static int dspload_image(struct hda_codec *codec, 3543 const struct dsp_image_seg *fls, 3544 bool ovly, 3545 unsigned int reloc, 3546 bool autostart, 3547 int router_chans) 3548 { 3549 int status = 0; 3550 unsigned int sample_rate; 3551 unsigned short channels; 3552 3553 codec_dbg(codec, "---- dspload_image begin ------\n"); 3554 if (router_chans == 0) { 3555 if (!ovly) 3556 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3557 else 3558 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3559 } 3560 3561 sample_rate = 48000; 3562 channels = (unsigned short)router_chans; 3563 3564 while (channels > 16) { 3565 sample_rate *= 2; 3566 channels /= 2; 3567 } 3568 3569 do { 3570 codec_dbg(codec, "Ready to program DMA\n"); 3571 if (!ovly) 3572 status = dsp_reset(codec); 3573 3574 if (status < 0) 3575 break; 3576 3577 codec_dbg(codec, "dsp_reset() complete\n"); 3578 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3579 ovly); 3580 3581 if (status < 0) 3582 break; 3583 3584 codec_dbg(codec, "dspxfr_image() complete\n"); 3585 if (autostart && !ovly) { 3586 dspload_post_setup(codec); 3587 status = dsp_set_run_state(codec); 3588 } 3589 3590 codec_dbg(codec, "LOAD FINISHED\n"); 3591 } while (0); 3592 3593 return status; 3594 } 3595 3596 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3597 static bool dspload_is_loaded(struct hda_codec *codec) 3598 { 3599 unsigned int data = 0; 3600 int status = 0; 3601 3602 status = chipio_read(codec, 0x40004, &data); 3603 if ((status < 0) || (data != 1)) 3604 return false; 3605 3606 return true; 3607 } 3608 #else 3609 #define dspload_is_loaded(codec) false 3610 #endif 3611 3612 static bool dspload_wait_loaded(struct hda_codec *codec) 3613 { 3614 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3615 3616 do { 3617 if (dspload_is_loaded(codec)) { 3618 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3619 return true; 3620 } 3621 msleep(20); 3622 } while (time_before(jiffies, timeout)); 3623 3624 codec_err(codec, "ca0132 failed to download DSP\n"); 3625 return false; 3626 } 3627 3628 /* 3629 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3630 * based cards, and has a second mmio region, region2, that's used for special 3631 * commands. 3632 */ 3633 3634 /* 3635 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3636 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3637 * The first eight bits are just the number of the pin. So far, I've only seen 3638 * this number go to 7. 3639 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3640 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3641 * then off to send that bit. 3642 */ 3643 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3644 bool enable) 3645 { 3646 struct ca0132_spec *spec = codec->spec; 3647 unsigned short gpio_data; 3648 3649 gpio_data = gpio_pin & 0xF; 3650 gpio_data |= ((enable << 8) & 0x100); 3651 3652 writew(gpio_data, spec->mem_base + 0x320); 3653 } 3654 3655 /* 3656 * Special pci region2 commands that are only used by the AE-5. They follow 3657 * a set format, and require reads at certain points to seemingly 'clear' 3658 * the response data. My first tests didn't do these reads, and would cause 3659 * the card to get locked up until the memory was read. These commands 3660 * seem to work with three distinct values that I've taken to calling group, 3661 * target-id, and value. 3662 */ 3663 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3664 unsigned int target, unsigned int value) 3665 { 3666 struct ca0132_spec *spec = codec->spec; 3667 unsigned int write_val; 3668 3669 writel(0x0000007e, spec->mem_base + 0x210); 3670 readl(spec->mem_base + 0x210); 3671 writel(0x0000005a, spec->mem_base + 0x210); 3672 readl(spec->mem_base + 0x210); 3673 readl(spec->mem_base + 0x210); 3674 3675 writel(0x00800005, spec->mem_base + 0x20c); 3676 writel(group, spec->mem_base + 0x804); 3677 3678 writel(0x00800005, spec->mem_base + 0x20c); 3679 write_val = (target & 0xff); 3680 write_val |= (value << 8); 3681 3682 3683 writel(write_val, spec->mem_base + 0x204); 3684 /* 3685 * Need delay here or else it goes too fast and works inconsistently. 3686 */ 3687 msleep(20); 3688 3689 readl(spec->mem_base + 0x860); 3690 readl(spec->mem_base + 0x854); 3691 readl(spec->mem_base + 0x840); 3692 3693 writel(0x00800004, spec->mem_base + 0x20c); 3694 writel(0x00000000, spec->mem_base + 0x210); 3695 readl(spec->mem_base + 0x210); 3696 readl(spec->mem_base + 0x210); 3697 } 3698 3699 /* 3700 * This second type of command is used for setting the sound filter type. 3701 */ 3702 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3703 unsigned int group, unsigned int target, unsigned int value) 3704 { 3705 struct ca0132_spec *spec = codec->spec; 3706 unsigned int write_val; 3707 3708 writel(0x0000007e, spec->mem_base + 0x210); 3709 readl(spec->mem_base + 0x210); 3710 writel(0x0000005a, spec->mem_base + 0x210); 3711 readl(spec->mem_base + 0x210); 3712 readl(spec->mem_base + 0x210); 3713 3714 writel(0x00800003, spec->mem_base + 0x20c); 3715 writel(group, spec->mem_base + 0x804); 3716 3717 writel(0x00800005, spec->mem_base + 0x20c); 3718 write_val = (target & 0xff); 3719 write_val |= (value << 8); 3720 3721 3722 writel(write_val, spec->mem_base + 0x204); 3723 msleep(20); 3724 readl(spec->mem_base + 0x860); 3725 readl(spec->mem_base + 0x854); 3726 readl(spec->mem_base + 0x840); 3727 3728 writel(0x00800004, spec->mem_base + 0x20c); 3729 writel(0x00000000, spec->mem_base + 0x210); 3730 readl(spec->mem_base + 0x210); 3731 readl(spec->mem_base + 0x210); 3732 } 3733 3734 /* 3735 * Setup GPIO for the other variants of Core3D. 3736 */ 3737 3738 /* 3739 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3740 * the card shows as having no GPIO pins. 3741 */ 3742 static void ca0132_gpio_init(struct hda_codec *codec) 3743 { 3744 struct ca0132_spec *spec = codec->spec; 3745 3746 switch (ca0132_quirk(spec)) { 3747 case QUIRK_SBZ: 3748 case QUIRK_AE5: 3749 case QUIRK_AE7: 3750 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3751 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3752 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3753 break; 3754 case QUIRK_R3DI: 3755 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3756 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3757 break; 3758 default: 3759 break; 3760 } 3761 3762 } 3763 3764 /* Sets the GPIO for audio output. */ 3765 static void ca0132_gpio_setup(struct hda_codec *codec) 3766 { 3767 struct ca0132_spec *spec = codec->spec; 3768 3769 switch (ca0132_quirk(spec)) { 3770 case QUIRK_SBZ: 3771 snd_hda_codec_write(codec, 0x01, 0, 3772 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3773 snd_hda_codec_write(codec, 0x01, 0, 3774 AC_VERB_SET_GPIO_MASK, 0x07); 3775 snd_hda_codec_write(codec, 0x01, 0, 3776 AC_VERB_SET_GPIO_DATA, 0x04); 3777 snd_hda_codec_write(codec, 0x01, 0, 3778 AC_VERB_SET_GPIO_DATA, 0x06); 3779 break; 3780 case QUIRK_R3DI: 3781 snd_hda_codec_write(codec, 0x01, 0, 3782 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3783 snd_hda_codec_write(codec, 0x01, 0, 3784 AC_VERB_SET_GPIO_MASK, 0x1F); 3785 snd_hda_codec_write(codec, 0x01, 0, 3786 AC_VERB_SET_GPIO_DATA, 0x0C); 3787 break; 3788 default: 3789 break; 3790 } 3791 } 3792 3793 /* 3794 * GPIO control functions for the Recon3D integrated. 3795 */ 3796 3797 enum r3di_gpio_bit { 3798 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3799 R3DI_MIC_SELECT_BIT = 1, 3800 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3801 R3DI_OUT_SELECT_BIT = 2, 3802 /* 3803 * I dunno what this actually does, but it stays on until the dsp 3804 * is downloaded. 3805 */ 3806 R3DI_GPIO_DSP_DOWNLOADING = 3, 3807 /* 3808 * Same as above, no clue what it does, but it comes on after the dsp 3809 * is downloaded. 3810 */ 3811 R3DI_GPIO_DSP_DOWNLOADED = 4 3812 }; 3813 3814 enum r3di_mic_select { 3815 /* Set GPIO bit 1 to 0 for rear mic */ 3816 R3DI_REAR_MIC = 0, 3817 /* Set GPIO bit 1 to 1 for front microphone*/ 3818 R3DI_FRONT_MIC = 1 3819 }; 3820 3821 enum r3di_out_select { 3822 /* Set GPIO bit 2 to 0 for headphone */ 3823 R3DI_HEADPHONE_OUT = 0, 3824 /* Set GPIO bit 2 to 1 for speaker */ 3825 R3DI_LINE_OUT = 1 3826 }; 3827 enum r3di_dsp_status { 3828 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3829 R3DI_DSP_DOWNLOADING = 0, 3830 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3831 R3DI_DSP_DOWNLOADED = 1 3832 }; 3833 3834 3835 static void r3di_gpio_mic_set(struct hda_codec *codec, 3836 enum r3di_mic_select cur_mic) 3837 { 3838 unsigned int cur_gpio; 3839 3840 /* Get the current GPIO Data setup */ 3841 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3842 3843 switch (cur_mic) { 3844 case R3DI_REAR_MIC: 3845 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3846 break; 3847 case R3DI_FRONT_MIC: 3848 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3849 break; 3850 } 3851 snd_hda_codec_write(codec, codec->core.afg, 0, 3852 AC_VERB_SET_GPIO_DATA, cur_gpio); 3853 } 3854 3855 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3856 enum r3di_dsp_status dsp_status) 3857 { 3858 unsigned int cur_gpio; 3859 3860 /* Get the current GPIO Data setup */ 3861 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3862 3863 switch (dsp_status) { 3864 case R3DI_DSP_DOWNLOADING: 3865 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3866 snd_hda_codec_write(codec, codec->core.afg, 0, 3867 AC_VERB_SET_GPIO_DATA, cur_gpio); 3868 break; 3869 case R3DI_DSP_DOWNLOADED: 3870 /* Set DOWNLOADING bit to 0. */ 3871 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3872 3873 snd_hda_codec_write(codec, codec->core.afg, 0, 3874 AC_VERB_SET_GPIO_DATA, cur_gpio); 3875 3876 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3877 break; 3878 } 3879 3880 snd_hda_codec_write(codec, codec->core.afg, 0, 3881 AC_VERB_SET_GPIO_DATA, cur_gpio); 3882 } 3883 3884 /* 3885 * PCM callbacks 3886 */ 3887 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3888 struct hda_codec *codec, 3889 unsigned int stream_tag, 3890 unsigned int format, 3891 struct snd_pcm_substream *substream) 3892 { 3893 struct ca0132_spec *spec = codec->spec; 3894 3895 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3896 3897 return 0; 3898 } 3899 3900 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3901 struct hda_codec *codec, 3902 struct snd_pcm_substream *substream) 3903 { 3904 struct ca0132_spec *spec = codec->spec; 3905 3906 if (spec->dsp_state == DSP_DOWNLOADING) 3907 return 0; 3908 3909 /*If Playback effects are on, allow stream some time to flush 3910 *effects tail*/ 3911 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3912 msleep(50); 3913 3914 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3915 3916 return 0; 3917 } 3918 3919 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3920 struct hda_codec *codec, 3921 struct snd_pcm_substream *substream) 3922 { 3923 struct ca0132_spec *spec = codec->spec; 3924 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3925 struct snd_pcm_runtime *runtime = substream->runtime; 3926 3927 if (spec->dsp_state != DSP_DOWNLOADED) 3928 return 0; 3929 3930 /* Add latency if playback enhancement and either effect is enabled. */ 3931 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3932 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3933 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3934 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3935 } 3936 3937 /* Applying Speaker EQ adds latency as well. */ 3938 if (spec->cur_out_type == SPEAKER_OUT) 3939 latency += DSP_SPEAKER_OUT_LATENCY; 3940 3941 return (latency * runtime->rate) / 1000; 3942 } 3943 3944 /* 3945 * Digital out 3946 */ 3947 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3948 struct hda_codec *codec, 3949 struct snd_pcm_substream *substream) 3950 { 3951 struct ca0132_spec *spec = codec->spec; 3952 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3953 } 3954 3955 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3956 struct hda_codec *codec, 3957 unsigned int stream_tag, 3958 unsigned int format, 3959 struct snd_pcm_substream *substream) 3960 { 3961 struct ca0132_spec *spec = codec->spec; 3962 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3963 stream_tag, format, substream); 3964 } 3965 3966 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3967 struct hda_codec *codec, 3968 struct snd_pcm_substream *substream) 3969 { 3970 struct ca0132_spec *spec = codec->spec; 3971 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3972 } 3973 3974 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3975 struct hda_codec *codec, 3976 struct snd_pcm_substream *substream) 3977 { 3978 struct ca0132_spec *spec = codec->spec; 3979 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3980 } 3981 3982 /* 3983 * Analog capture 3984 */ 3985 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3986 struct hda_codec *codec, 3987 unsigned int stream_tag, 3988 unsigned int format, 3989 struct snd_pcm_substream *substream) 3990 { 3991 snd_hda_codec_setup_stream(codec, hinfo->nid, 3992 stream_tag, 0, format); 3993 3994 return 0; 3995 } 3996 3997 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3998 struct hda_codec *codec, 3999 struct snd_pcm_substream *substream) 4000 { 4001 struct ca0132_spec *spec = codec->spec; 4002 4003 if (spec->dsp_state == DSP_DOWNLOADING) 4004 return 0; 4005 4006 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 4007 return 0; 4008 } 4009 4010 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 4011 struct hda_codec *codec, 4012 struct snd_pcm_substream *substream) 4013 { 4014 struct ca0132_spec *spec = codec->spec; 4015 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 4016 struct snd_pcm_runtime *runtime = substream->runtime; 4017 4018 if (spec->dsp_state != DSP_DOWNLOADED) 4019 return 0; 4020 4021 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4022 latency += DSP_CRYSTAL_VOICE_LATENCY; 4023 4024 return (latency * runtime->rate) / 1000; 4025 } 4026 4027 /* 4028 * Controls stuffs. 4029 */ 4030 4031 /* 4032 * Mixer controls helpers. 4033 */ 4034 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4035 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4036 .name = xname, \ 4037 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4038 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4039 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4040 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4041 .info = ca0132_volume_info, \ 4042 .get = ca0132_volume_get, \ 4043 .put = ca0132_volume_put, \ 4044 .tlv = { .c = ca0132_volume_tlv }, \ 4045 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4046 4047 /* 4048 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 4049 * volume put, which is used for setting the DSP volume. This was done because 4050 * the ca0132 functions were taking too much time and causing lag. 4051 */ 4052 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4053 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4054 .name = xname, \ 4055 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4056 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4057 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4058 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4059 .info = snd_hda_mixer_amp_volume_info, \ 4060 .get = snd_hda_mixer_amp_volume_get, \ 4061 .put = ca0132_alt_volume_put, \ 4062 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 4063 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4064 4065 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 4066 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4067 .name = xname, \ 4068 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4069 .info = snd_hda_mixer_amp_switch_info, \ 4070 .get = ca0132_switch_get, \ 4071 .put = ca0132_switch_put, \ 4072 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4073 4074 /* stereo */ 4075 #define CA0132_CODEC_VOL(xname, nid, dir) \ 4076 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 4077 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 4078 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 4079 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 4080 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 4081 4082 /* lookup tables */ 4083 /* 4084 * Lookup table with decibel values for the DSP. When volume is changed in 4085 * Windows, the DSP is also sent the dB value in floating point. In Windows, 4086 * these values have decimal points, probably because the Windows driver 4087 * actually uses floating point. We can't here, so I made a lookup table of 4088 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 4089 * DAC's, and 9 is the maximum. 4090 */ 4091 static const unsigned int float_vol_db_lookup[] = { 4092 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 4093 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 4094 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 4095 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 4096 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 4097 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 4098 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 4099 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 4100 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 4101 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 4102 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 4103 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4104 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4105 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4106 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4107 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4108 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 4109 }; 4110 4111 /* 4112 * This table counts from float 0 to 1 in increments of .01, which is 4113 * useful for a few different sliders. 4114 */ 4115 static const unsigned int float_zero_to_one_lookup[] = { 4116 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4117 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4118 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4119 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4120 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4121 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4122 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4123 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4124 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4125 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4126 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4127 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4128 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4129 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4130 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4131 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4132 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4133 }; 4134 4135 /* 4136 * This table counts from float 10 to 1000, which is the range of the x-bass 4137 * crossover slider in Windows. 4138 */ 4139 static const unsigned int float_xbass_xover_lookup[] = { 4140 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4141 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4142 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4143 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4144 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4145 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4146 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4147 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4148 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4149 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4150 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4151 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4152 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4153 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4154 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4155 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4156 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4157 }; 4158 4159 /* The following are for tuning of products */ 4160 #ifdef ENABLE_TUNING_CONTROLS 4161 4162 static const unsigned int voice_focus_vals_lookup[] = { 4163 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4164 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4165 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4166 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4167 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4168 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4169 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4170 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4171 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4172 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4173 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4174 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4175 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4176 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4177 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4178 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4179 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4180 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4181 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4182 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4183 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4184 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4185 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4186 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4187 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4188 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4189 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4190 }; 4191 4192 static const unsigned int mic_svm_vals_lookup[] = { 4193 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4194 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4195 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4196 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4197 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4198 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4199 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4200 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4201 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4202 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4203 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4204 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4205 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4206 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4207 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4208 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4209 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4210 }; 4211 4212 static const unsigned int equalizer_vals_lookup[] = { 4213 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4214 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4215 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4216 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4217 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4218 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4219 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4220 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4221 0x41C00000 4222 }; 4223 4224 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4225 const unsigned int *lookup, int idx) 4226 { 4227 int i = 0; 4228 4229 for (i = 0; i < TUNING_CTLS_COUNT; i++) 4230 if (nid == ca0132_tuning_ctls[i].nid) 4231 goto found; 4232 4233 return -EINVAL; 4234 found: 4235 snd_hda_power_up(codec); 4236 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4237 ca0132_tuning_ctls[i].req, 4238 &(lookup[idx]), sizeof(unsigned int)); 4239 snd_hda_power_down(codec); 4240 4241 return 1; 4242 } 4243 4244 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4245 struct snd_ctl_elem_value *ucontrol) 4246 { 4247 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4248 struct ca0132_spec *spec = codec->spec; 4249 hda_nid_t nid = get_amp_nid(kcontrol); 4250 long *valp = ucontrol->value.integer.value; 4251 int idx = nid - TUNING_CTL_START_NID; 4252 4253 *valp = spec->cur_ctl_vals[idx]; 4254 return 0; 4255 } 4256 4257 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4258 struct snd_ctl_elem_info *uinfo) 4259 { 4260 int chs = get_amp_channels(kcontrol); 4261 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4262 uinfo->count = chs == 3 ? 2 : 1; 4263 uinfo->value.integer.min = 20; 4264 uinfo->value.integer.max = 180; 4265 uinfo->value.integer.step = 1; 4266 4267 return 0; 4268 } 4269 4270 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4271 struct snd_ctl_elem_value *ucontrol) 4272 { 4273 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4274 struct ca0132_spec *spec = codec->spec; 4275 hda_nid_t nid = get_amp_nid(kcontrol); 4276 long *valp = ucontrol->value.integer.value; 4277 int idx; 4278 4279 idx = nid - TUNING_CTL_START_NID; 4280 /* any change? */ 4281 if (spec->cur_ctl_vals[idx] == *valp) 4282 return 0; 4283 4284 spec->cur_ctl_vals[idx] = *valp; 4285 4286 idx = *valp - 20; 4287 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4288 4289 return 1; 4290 } 4291 4292 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4293 struct snd_ctl_elem_info *uinfo) 4294 { 4295 int chs = get_amp_channels(kcontrol); 4296 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4297 uinfo->count = chs == 3 ? 2 : 1; 4298 uinfo->value.integer.min = 0; 4299 uinfo->value.integer.max = 100; 4300 uinfo->value.integer.step = 1; 4301 4302 return 0; 4303 } 4304 4305 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4306 struct snd_ctl_elem_value *ucontrol) 4307 { 4308 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4309 struct ca0132_spec *spec = codec->spec; 4310 hda_nid_t nid = get_amp_nid(kcontrol); 4311 long *valp = ucontrol->value.integer.value; 4312 int idx; 4313 4314 idx = nid - TUNING_CTL_START_NID; 4315 /* any change? */ 4316 if (spec->cur_ctl_vals[idx] == *valp) 4317 return 0; 4318 4319 spec->cur_ctl_vals[idx] = *valp; 4320 4321 idx = *valp; 4322 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4323 4324 return 0; 4325 } 4326 4327 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4328 struct snd_ctl_elem_info *uinfo) 4329 { 4330 int chs = get_amp_channels(kcontrol); 4331 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4332 uinfo->count = chs == 3 ? 2 : 1; 4333 uinfo->value.integer.min = 0; 4334 uinfo->value.integer.max = 48; 4335 uinfo->value.integer.step = 1; 4336 4337 return 0; 4338 } 4339 4340 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4341 struct snd_ctl_elem_value *ucontrol) 4342 { 4343 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4344 struct ca0132_spec *spec = codec->spec; 4345 hda_nid_t nid = get_amp_nid(kcontrol); 4346 long *valp = ucontrol->value.integer.value; 4347 int idx; 4348 4349 idx = nid - TUNING_CTL_START_NID; 4350 /* any change? */ 4351 if (spec->cur_ctl_vals[idx] == *valp) 4352 return 0; 4353 4354 spec->cur_ctl_vals[idx] = *valp; 4355 4356 idx = *valp; 4357 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4358 4359 return 1; 4360 } 4361 4362 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4363 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4364 4365 static int add_tuning_control(struct hda_codec *codec, 4366 hda_nid_t pnid, hda_nid_t nid, 4367 const char *name, int dir) 4368 { 4369 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4370 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4371 struct snd_kcontrol_new knew = 4372 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4373 4374 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4375 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4376 knew.tlv.c = 0; 4377 knew.tlv.p = 0; 4378 switch (pnid) { 4379 case VOICE_FOCUS: 4380 knew.info = voice_focus_ctl_info; 4381 knew.get = tuning_ctl_get; 4382 knew.put = voice_focus_ctl_put; 4383 knew.tlv.p = voice_focus_db_scale; 4384 break; 4385 case MIC_SVM: 4386 knew.info = mic_svm_ctl_info; 4387 knew.get = tuning_ctl_get; 4388 knew.put = mic_svm_ctl_put; 4389 break; 4390 case EQUALIZER: 4391 knew.info = equalizer_ctl_info; 4392 knew.get = tuning_ctl_get; 4393 knew.put = equalizer_ctl_put; 4394 knew.tlv.p = eq_db_scale; 4395 break; 4396 default: 4397 return 0; 4398 } 4399 knew.private_value = 4400 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4401 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4402 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4403 } 4404 4405 static int add_tuning_ctls(struct hda_codec *codec) 4406 { 4407 int i; 4408 int err; 4409 4410 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4411 err = add_tuning_control(codec, 4412 ca0132_tuning_ctls[i].parent_nid, 4413 ca0132_tuning_ctls[i].nid, 4414 ca0132_tuning_ctls[i].name, 4415 ca0132_tuning_ctls[i].direct); 4416 if (err < 0) 4417 return err; 4418 } 4419 4420 return 0; 4421 } 4422 4423 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4424 { 4425 struct ca0132_spec *spec = codec->spec; 4426 int i; 4427 4428 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4429 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4430 /* SVM level defaults to 0.74. */ 4431 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4432 4433 /* EQ defaults to 0dB. */ 4434 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4435 spec->cur_ctl_vals[i] = 24; 4436 } 4437 #endif /*ENABLE_TUNING_CONTROLS*/ 4438 4439 /* 4440 * Select the active output. 4441 * If autodetect is enabled, output will be selected based on jack detection. 4442 * If jack inserted, headphone will be selected, else built-in speakers 4443 * If autodetect is disabled, output will be selected based on selection. 4444 */ 4445 static int ca0132_select_out(struct hda_codec *codec) 4446 { 4447 struct ca0132_spec *spec = codec->spec; 4448 unsigned int pin_ctl; 4449 int jack_present; 4450 int auto_jack; 4451 unsigned int tmp; 4452 int err; 4453 4454 codec_dbg(codec, "ca0132_select_out\n"); 4455 4456 snd_hda_power_up_pm(codec); 4457 4458 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4459 4460 if (auto_jack) 4461 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4462 else 4463 jack_present = 4464 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4465 4466 if (jack_present) 4467 spec->cur_out_type = HEADPHONE_OUT; 4468 else 4469 spec->cur_out_type = SPEAKER_OUT; 4470 4471 if (spec->cur_out_type == SPEAKER_OUT) { 4472 codec_dbg(codec, "ca0132_select_out speaker\n"); 4473 /*speaker out config*/ 4474 tmp = FLOAT_ONE; 4475 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4476 if (err < 0) 4477 goto exit; 4478 /*enable speaker EQ*/ 4479 tmp = FLOAT_ONE; 4480 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4481 if (err < 0) 4482 goto exit; 4483 4484 /* Setup EAPD */ 4485 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4486 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4487 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4488 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4489 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4490 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4491 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4492 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4493 4494 /* disable headphone node */ 4495 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4496 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4497 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4498 pin_ctl & ~PIN_HP); 4499 /* enable speaker node */ 4500 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4501 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4502 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4503 pin_ctl | PIN_OUT); 4504 } else { 4505 codec_dbg(codec, "ca0132_select_out hp\n"); 4506 /*headphone out config*/ 4507 tmp = FLOAT_ZERO; 4508 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4509 if (err < 0) 4510 goto exit; 4511 /*disable speaker EQ*/ 4512 tmp = FLOAT_ZERO; 4513 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4514 if (err < 0) 4515 goto exit; 4516 4517 /* Setup EAPD */ 4518 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4519 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4520 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4521 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4522 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4523 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4524 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4525 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4526 4527 /* disable speaker*/ 4528 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4529 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4530 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4531 pin_ctl & ~PIN_HP); 4532 /* enable headphone*/ 4533 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4534 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4535 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4536 pin_ctl | PIN_HP); 4537 } 4538 4539 exit: 4540 snd_hda_power_down_pm(codec); 4541 4542 return err < 0 ? err : 0; 4543 } 4544 4545 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4546 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4547 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4548 4549 static void ae5_mmio_select_out(struct hda_codec *codec) 4550 { 4551 struct ca0132_spec *spec = codec->spec; 4552 const struct ae_ca0113_output_set *out_cmds; 4553 unsigned int i; 4554 4555 if (ca0132_quirk(spec) == QUIRK_AE5) 4556 out_cmds = &ae5_ca0113_output_presets; 4557 else 4558 out_cmds = &ae7_ca0113_output_presets; 4559 4560 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4561 ca0113_mmio_command_set(codec, out_cmds->group[i], 4562 out_cmds->target[i], 4563 out_cmds->vals[spec->cur_out_type][i]); 4564 } 4565 4566 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4567 { 4568 struct ca0132_spec *spec = codec->spec; 4569 int quirk = ca0132_quirk(spec); 4570 unsigned int tmp; 4571 int err; 4572 4573 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4574 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4575 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4576 return 0; 4577 4578 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4579 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4580 err = dspio_set_uint_param(codec, 0x96, 4581 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4582 if (err < 0) 4583 return err; 4584 4585 /* When setting full-range rear, both rear and center/lfe are set. */ 4586 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4587 err = dspio_set_uint_param(codec, 0x96, 4588 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4589 if (err < 0) 4590 return err; 4591 4592 err = dspio_set_uint_param(codec, 0x96, 4593 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4594 if (err < 0) 4595 return err; 4596 4597 /* 4598 * Only the AE series cards set this value when setting full-range, 4599 * and it's always 1.0f. 4600 */ 4601 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4602 err = dspio_set_uint_param(codec, 0x96, 4603 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4604 if (err < 0) 4605 return err; 4606 } 4607 4608 return 0; 4609 } 4610 4611 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4612 bool val) 4613 { 4614 struct ca0132_spec *spec = codec->spec; 4615 unsigned int tmp; 4616 int err; 4617 4618 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4619 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4620 tmp = FLOAT_ONE; 4621 else 4622 tmp = FLOAT_ZERO; 4623 4624 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4625 if (err < 0) 4626 return err; 4627 4628 /* If it is enabled, make sure to set the crossover frequency. */ 4629 if (tmp) { 4630 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4631 err = dspio_set_uint_param(codec, 0x96, 4632 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4633 if (err < 0) 4634 return err; 4635 } 4636 4637 return 0; 4638 } 4639 4640 /* 4641 * These are the commands needed to setup output on each of the different card 4642 * types. 4643 */ 4644 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4645 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4646 { 4647 struct ca0132_spec *spec = codec->spec; 4648 int quirk = ca0132_quirk(spec); 4649 unsigned int i; 4650 4651 *quirk_data = NULL; 4652 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4653 if (quirk_out_set_data[i].quirk_id == quirk) { 4654 *quirk_data = &quirk_out_set_data[i]; 4655 return; 4656 } 4657 } 4658 } 4659 4660 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4661 { 4662 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4663 const struct ca0132_alt_out_set_info *out_info; 4664 struct ca0132_spec *spec = codec->spec; 4665 unsigned int i, gpio_data; 4666 int err; 4667 4668 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4669 if (!quirk_data) 4670 return 0; 4671 4672 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4673 if (quirk_data->is_ae_series) 4674 ae5_mmio_select_out(codec); 4675 4676 if (out_info->has_hda_gpio) { 4677 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4678 AC_VERB_GET_GPIO_DATA, 0); 4679 4680 if (out_info->hda_gpio_set) 4681 gpio_data |= (1 << out_info->hda_gpio_pin); 4682 else 4683 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4684 4685 snd_hda_codec_write(codec, codec->core.afg, 0, 4686 AC_VERB_SET_GPIO_DATA, gpio_data); 4687 } 4688 4689 if (out_info->mmio_gpio_count) { 4690 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4691 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4692 out_info->mmio_gpio_set[i]); 4693 } 4694 } 4695 4696 if (out_info->scp_cmds_count) { 4697 for (i = 0; i < out_info->scp_cmds_count; i++) { 4698 err = dspio_set_uint_param(codec, 4699 out_info->scp_cmd_mid[i], 4700 out_info->scp_cmd_req[i], 4701 out_info->scp_cmd_val[i]); 4702 if (err < 0) 4703 return err; 4704 } 4705 } 4706 4707 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4708 4709 if (out_info->has_chipio_write) { 4710 chipio_write(codec, out_info->chipio_write_addr, 4711 out_info->chipio_write_data); 4712 } 4713 4714 if (quirk_data->has_headphone_gain) { 4715 if (spec->cur_out_type != HEADPHONE_OUT) { 4716 if (quirk_data->is_ae_series) 4717 ae5_headphone_gain_set(codec, 2); 4718 else 4719 zxr_headphone_gain_set(codec, 0); 4720 } else { 4721 if (quirk_data->is_ae_series) 4722 ae5_headphone_gain_set(codec, 4723 spec->ae5_headphone_gain_val); 4724 else 4725 zxr_headphone_gain_set(codec, 4726 spec->zxr_gain_set); 4727 } 4728 } 4729 4730 return 0; 4731 } 4732 4733 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4734 bool out_enable, bool hp_enable) 4735 { 4736 unsigned int pin_ctl; 4737 4738 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4739 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4740 4741 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4742 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4743 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4744 } 4745 4746 /* 4747 * This function behaves similarly to the ca0132_select_out funciton above, 4748 * except with a few differences. It adds the ability to select the current 4749 * output with an enumerated control "output source" if the auto detect 4750 * mute switch is set to off. If the auto detect mute switch is enabled, it 4751 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4752 * It also adds the ability to auto-detect the front headphone port. 4753 */ 4754 static int ca0132_alt_select_out(struct hda_codec *codec) 4755 { 4756 struct ca0132_spec *spec = codec->spec; 4757 unsigned int tmp, outfx_set; 4758 int jack_present; 4759 int auto_jack; 4760 int err; 4761 /* Default Headphone is rear headphone */ 4762 hda_nid_t headphone_nid = spec->out_pins[1]; 4763 4764 codec_dbg(codec, "%s\n", __func__); 4765 4766 snd_hda_power_up_pm(codec); 4767 4768 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4769 4770 /* 4771 * If headphone rear or front is plugged in, set to headphone. 4772 * If neither is plugged in, set to rear line out. Only if 4773 * hp/speaker auto detect is enabled. 4774 */ 4775 if (auto_jack) { 4776 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4777 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4778 4779 if (jack_present) 4780 spec->cur_out_type = HEADPHONE_OUT; 4781 else 4782 spec->cur_out_type = SPEAKER_OUT; 4783 } else 4784 spec->cur_out_type = spec->out_enum_val; 4785 4786 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4787 4788 /* Begin DSP output switch, mute DSP volume. */ 4789 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4790 if (err < 0) 4791 goto exit; 4792 4793 if (ca0132_alt_select_out_quirk_set(codec) < 0) 4794 goto exit; 4795 4796 switch (spec->cur_out_type) { 4797 case SPEAKER_OUT: 4798 codec_dbg(codec, "%s speaker\n", __func__); 4799 4800 /* Enable EAPD */ 4801 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4802 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4803 4804 /* Disable headphone node. */ 4805 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4806 /* Set front L-R to output. */ 4807 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4808 /* Set Center/LFE to output. */ 4809 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4810 /* Set rear surround to output. */ 4811 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4812 4813 /* 4814 * Without PlayEnhancement being enabled, if we've got a 2.0 4815 * setup, set it to floating point eight to disable any DSP 4816 * processing effects. 4817 */ 4818 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4819 tmp = FLOAT_EIGHT; 4820 else 4821 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4822 4823 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4824 if (err < 0) 4825 goto exit; 4826 4827 break; 4828 case HEADPHONE_OUT: 4829 codec_dbg(codec, "%s hp\n", __func__); 4830 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4831 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4832 4833 /* Disable all speaker nodes. */ 4834 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4835 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4836 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4837 4838 /* enable headphone, either front or rear */ 4839 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4840 headphone_nid = spec->out_pins[2]; 4841 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4842 headphone_nid = spec->out_pins[1]; 4843 4844 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4845 4846 if (outfx_set) 4847 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4848 else 4849 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4850 4851 if (err < 0) 4852 goto exit; 4853 break; 4854 } 4855 /* 4856 * If output effects are enabled, set the X-Bass effect value again to 4857 * make sure that it's properly enabled/disabled for speaker 4858 * configurations with an LFE channel. 4859 */ 4860 if (outfx_set) 4861 ca0132_effects_set(codec, X_BASS, 4862 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4863 4864 /* Set speaker EQ bypass attenuation to 0. */ 4865 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4866 if (err < 0) 4867 goto exit; 4868 4869 /* 4870 * Although unused on all cards but the AE series, this is always set 4871 * to zero when setting the output. 4872 */ 4873 err = dspio_set_uint_param(codec, 0x96, 4874 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4875 if (err < 0) 4876 goto exit; 4877 4878 if (spec->cur_out_type == SPEAKER_OUT) 4879 err = ca0132_alt_surround_set_bass_redirection(codec, 4880 spec->bass_redirection_val); 4881 else 4882 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4883 4884 /* Unmute DSP now that we're done with output selection. */ 4885 err = dspio_set_uint_param(codec, 0x96, 4886 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4887 if (err < 0) 4888 goto exit; 4889 4890 if (spec->cur_out_type == SPEAKER_OUT) { 4891 err = ca0132_alt_set_full_range_speaker(codec); 4892 if (err < 0) 4893 goto exit; 4894 } 4895 4896 exit: 4897 snd_hda_power_down_pm(codec); 4898 4899 return err < 0 ? err : 0; 4900 } 4901 4902 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4903 { 4904 struct ca0132_spec *spec = container_of( 4905 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4906 struct hda_jack_tbl *jack; 4907 4908 if (ca0132_use_alt_functions(spec)) 4909 ca0132_alt_select_out(spec->codec); 4910 else 4911 ca0132_select_out(spec->codec); 4912 4913 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4914 if (jack) { 4915 jack->block_report = 0; 4916 snd_hda_jack_report_sync(spec->codec); 4917 } 4918 } 4919 4920 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4921 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4922 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4923 static int stop_mic1(struct hda_codec *codec); 4924 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4925 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4926 4927 /* 4928 * Select the active VIP source 4929 */ 4930 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4931 { 4932 struct ca0132_spec *spec = codec->spec; 4933 unsigned int tmp; 4934 4935 if (spec->dsp_state != DSP_DOWNLOADED) 4936 return 0; 4937 4938 /* if CrystalVoice if off, vipsource should be 0 */ 4939 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4940 (val == 0)) { 4941 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4942 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4943 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4944 if (spec->cur_mic_type == DIGITAL_MIC) 4945 tmp = FLOAT_TWO; 4946 else 4947 tmp = FLOAT_ONE; 4948 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4949 tmp = FLOAT_ZERO; 4950 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4951 } else { 4952 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4953 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4954 if (spec->cur_mic_type == DIGITAL_MIC) 4955 tmp = FLOAT_TWO; 4956 else 4957 tmp = FLOAT_ONE; 4958 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4959 tmp = FLOAT_ONE; 4960 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4961 msleep(20); 4962 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4963 } 4964 4965 return 1; 4966 } 4967 4968 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4969 { 4970 struct ca0132_spec *spec = codec->spec; 4971 unsigned int tmp; 4972 4973 if (spec->dsp_state != DSP_DOWNLOADED) 4974 return 0; 4975 4976 codec_dbg(codec, "%s\n", __func__); 4977 4978 chipio_set_stream_control(codec, 0x03, 0); 4979 chipio_set_stream_control(codec, 0x04, 0); 4980 4981 /* if CrystalVoice is off, vipsource should be 0 */ 4982 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4983 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4984 codec_dbg(codec, "%s: off.", __func__); 4985 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4986 4987 tmp = FLOAT_ZERO; 4988 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4989 4990 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4991 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4992 if (ca0132_quirk(spec) == QUIRK_R3DI) 4993 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4994 4995 4996 if (spec->in_enum_val == REAR_LINE_IN) 4997 tmp = FLOAT_ZERO; 4998 else { 4999 if (ca0132_quirk(spec) == QUIRK_SBZ) 5000 tmp = FLOAT_THREE; 5001 else 5002 tmp = FLOAT_ONE; 5003 } 5004 5005 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5006 5007 } else { 5008 codec_dbg(codec, "%s: on.", __func__); 5009 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 5010 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 5011 if (ca0132_quirk(spec) == QUIRK_R3DI) 5012 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 5013 5014 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 5015 tmp = FLOAT_TWO; 5016 else 5017 tmp = FLOAT_ONE; 5018 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5019 5020 tmp = FLOAT_ONE; 5021 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5022 5023 msleep(20); 5024 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 5025 } 5026 5027 chipio_set_stream_control(codec, 0x03, 1); 5028 chipio_set_stream_control(codec, 0x04, 1); 5029 5030 return 1; 5031 } 5032 5033 /* 5034 * Select the active microphone. 5035 * If autodetect is enabled, mic will be selected based on jack detection. 5036 * If jack inserted, ext.mic will be selected, else built-in mic 5037 * If autodetect is disabled, mic will be selected based on selection. 5038 */ 5039 static int ca0132_select_mic(struct hda_codec *codec) 5040 { 5041 struct ca0132_spec *spec = codec->spec; 5042 int jack_present; 5043 int auto_jack; 5044 5045 codec_dbg(codec, "ca0132_select_mic\n"); 5046 5047 snd_hda_power_up_pm(codec); 5048 5049 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5050 5051 if (auto_jack) 5052 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 5053 else 5054 jack_present = 5055 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 5056 5057 if (jack_present) 5058 spec->cur_mic_type = LINE_MIC_IN; 5059 else 5060 spec->cur_mic_type = DIGITAL_MIC; 5061 5062 if (spec->cur_mic_type == DIGITAL_MIC) { 5063 /* enable digital Mic */ 5064 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 5065 ca0132_set_dmic(codec, 1); 5066 ca0132_mic_boost_set(codec, 0); 5067 /* set voice focus */ 5068 ca0132_effects_set(codec, VOICE_FOCUS, 5069 spec->effects_switch 5070 [VOICE_FOCUS - EFFECT_START_NID]); 5071 } else { 5072 /* disable digital Mic */ 5073 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 5074 ca0132_set_dmic(codec, 0); 5075 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 5076 /* disable voice focus */ 5077 ca0132_effects_set(codec, VOICE_FOCUS, 0); 5078 } 5079 5080 snd_hda_power_down_pm(codec); 5081 5082 return 0; 5083 } 5084 5085 /* 5086 * Select the active input. 5087 * Mic detection isn't used, because it's kind of pointless on the SBZ. 5088 * The front mic has no jack-detection, so the only way to switch to it 5089 * is to do it manually in alsamixer. 5090 */ 5091 static int ca0132_alt_select_in(struct hda_codec *codec) 5092 { 5093 struct ca0132_spec *spec = codec->spec; 5094 unsigned int tmp; 5095 5096 codec_dbg(codec, "%s\n", __func__); 5097 5098 snd_hda_power_up_pm(codec); 5099 5100 chipio_set_stream_control(codec, 0x03, 0); 5101 chipio_set_stream_control(codec, 0x04, 0); 5102 5103 spec->cur_mic_type = spec->in_enum_val; 5104 5105 switch (spec->cur_mic_type) { 5106 case REAR_MIC: 5107 switch (ca0132_quirk(spec)) { 5108 case QUIRK_SBZ: 5109 case QUIRK_R3D: 5110 ca0113_mmio_gpio_set(codec, 0, false); 5111 tmp = FLOAT_THREE; 5112 break; 5113 case QUIRK_ZXR: 5114 tmp = FLOAT_THREE; 5115 break; 5116 case QUIRK_R3DI: 5117 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5118 tmp = FLOAT_ONE; 5119 break; 5120 case QUIRK_AE5: 5121 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5122 tmp = FLOAT_THREE; 5123 break; 5124 case QUIRK_AE7: 5125 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5126 tmp = FLOAT_THREE; 5127 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5128 SR_96_000); 5129 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5130 SR_96_000); 5131 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5132 break; 5133 default: 5134 tmp = FLOAT_ONE; 5135 break; 5136 } 5137 5138 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5139 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5140 if (ca0132_quirk(spec) == QUIRK_R3DI) 5141 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5142 5143 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5144 5145 chipio_set_stream_control(codec, 0x03, 1); 5146 chipio_set_stream_control(codec, 0x04, 1); 5147 switch (ca0132_quirk(spec)) { 5148 case QUIRK_SBZ: 5149 chipio_write(codec, 0x18B098, 0x0000000C); 5150 chipio_write(codec, 0x18B09C, 0x0000000C); 5151 break; 5152 case QUIRK_ZXR: 5153 chipio_write(codec, 0x18B098, 0x0000000C); 5154 chipio_write(codec, 0x18B09C, 0x000000CC); 5155 break; 5156 case QUIRK_AE5: 5157 chipio_write(codec, 0x18B098, 0x0000000C); 5158 chipio_write(codec, 0x18B09C, 0x0000004C); 5159 break; 5160 default: 5161 break; 5162 } 5163 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5164 break; 5165 case REAR_LINE_IN: 5166 ca0132_mic_boost_set(codec, 0); 5167 switch (ca0132_quirk(spec)) { 5168 case QUIRK_SBZ: 5169 case QUIRK_R3D: 5170 ca0113_mmio_gpio_set(codec, 0, false); 5171 break; 5172 case QUIRK_R3DI: 5173 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5174 break; 5175 case QUIRK_AE5: 5176 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5177 break; 5178 case QUIRK_AE7: 5179 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5180 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5181 SR_96_000); 5182 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5183 SR_96_000); 5184 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5185 break; 5186 default: 5187 break; 5188 } 5189 5190 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5191 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5192 if (ca0132_quirk(spec) == QUIRK_R3DI) 5193 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5194 5195 if (ca0132_quirk(spec) == QUIRK_AE7) 5196 tmp = FLOAT_THREE; 5197 else 5198 tmp = FLOAT_ZERO; 5199 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5200 5201 switch (ca0132_quirk(spec)) { 5202 case QUIRK_SBZ: 5203 case QUIRK_AE5: 5204 chipio_write(codec, 0x18B098, 0x00000000); 5205 chipio_write(codec, 0x18B09C, 0x00000000); 5206 break; 5207 default: 5208 break; 5209 } 5210 chipio_set_stream_control(codec, 0x03, 1); 5211 chipio_set_stream_control(codec, 0x04, 1); 5212 break; 5213 case FRONT_MIC: 5214 switch (ca0132_quirk(spec)) { 5215 case QUIRK_SBZ: 5216 case QUIRK_R3D: 5217 ca0113_mmio_gpio_set(codec, 0, true); 5218 ca0113_mmio_gpio_set(codec, 5, false); 5219 tmp = FLOAT_THREE; 5220 break; 5221 case QUIRK_R3DI: 5222 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5223 tmp = FLOAT_ONE; 5224 break; 5225 case QUIRK_AE5: 5226 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5227 tmp = FLOAT_THREE; 5228 break; 5229 default: 5230 tmp = FLOAT_ONE; 5231 break; 5232 } 5233 5234 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5235 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5236 if (ca0132_quirk(spec) == QUIRK_R3DI) 5237 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5238 5239 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5240 5241 chipio_set_stream_control(codec, 0x03, 1); 5242 chipio_set_stream_control(codec, 0x04, 1); 5243 5244 switch (ca0132_quirk(spec)) { 5245 case QUIRK_SBZ: 5246 chipio_write(codec, 0x18B098, 0x0000000C); 5247 chipio_write(codec, 0x18B09C, 0x000000CC); 5248 break; 5249 case QUIRK_AE5: 5250 chipio_write(codec, 0x18B098, 0x0000000C); 5251 chipio_write(codec, 0x18B09C, 0x0000004C); 5252 break; 5253 default: 5254 break; 5255 } 5256 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5257 break; 5258 } 5259 ca0132_cvoice_switch_set(codec); 5260 5261 snd_hda_power_down_pm(codec); 5262 return 0; 5263 } 5264 5265 /* 5266 * Check if VNODE settings take effect immediately. 5267 */ 5268 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5269 hda_nid_t vnid, 5270 hda_nid_t *shared_nid) 5271 { 5272 struct ca0132_spec *spec = codec->spec; 5273 hda_nid_t nid; 5274 5275 switch (vnid) { 5276 case VNID_SPK: 5277 nid = spec->shared_out_nid; 5278 break; 5279 case VNID_MIC: 5280 nid = spec->shared_mic_nid; 5281 break; 5282 default: 5283 return false; 5284 } 5285 5286 if (shared_nid) 5287 *shared_nid = nid; 5288 5289 return true; 5290 } 5291 5292 /* 5293 * The following functions are control change helpers. 5294 * They return 0 if no changed. Return 1 if changed. 5295 */ 5296 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5297 { 5298 struct ca0132_spec *spec = codec->spec; 5299 unsigned int tmp; 5300 5301 /* based on CrystalVoice state to enable VoiceFX. */ 5302 if (enable) { 5303 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5304 FLOAT_ONE : FLOAT_ZERO; 5305 } else { 5306 tmp = FLOAT_ZERO; 5307 } 5308 5309 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5310 ca0132_voicefx.reqs[0], tmp); 5311 5312 return 1; 5313 } 5314 5315 /* 5316 * Set the effects parameters 5317 */ 5318 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5319 { 5320 struct ca0132_spec *spec = codec->spec; 5321 unsigned int on, tmp, channel_cfg; 5322 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5323 int err = 0; 5324 int idx = nid - EFFECT_START_NID; 5325 5326 if ((idx < 0) || (idx >= num_fx)) 5327 return 0; /* no changed */ 5328 5329 /* for out effect, qualify with PE */ 5330 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5331 /* if PE if off, turn off out effects. */ 5332 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5333 val = 0; 5334 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5335 channel_cfg = spec->channel_cfg_val; 5336 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5337 channel_cfg != SPEAKER_CHANNELS_4_0) 5338 val = 0; 5339 } 5340 } 5341 5342 /* for in effect, qualify with CrystalVoice */ 5343 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5344 /* if CrystalVoice if off, turn off in effects. */ 5345 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5346 val = 0; 5347 5348 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5349 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5350 val = 0; 5351 5352 /* If Voice Focus on SBZ, set to two channel. */ 5353 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5354 && (spec->cur_mic_type != REAR_LINE_IN)) { 5355 if (spec->effects_switch[CRYSTAL_VOICE - 5356 EFFECT_START_NID]) { 5357 5358 if (spec->effects_switch[VOICE_FOCUS - 5359 EFFECT_START_NID]) { 5360 tmp = FLOAT_TWO; 5361 val = 1; 5362 } else 5363 tmp = FLOAT_ONE; 5364 5365 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5366 } 5367 } 5368 /* 5369 * For SBZ noise reduction, there's an extra command 5370 * to module ID 0x47. No clue why. 5371 */ 5372 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5373 && (spec->cur_mic_type != REAR_LINE_IN)) { 5374 if (spec->effects_switch[CRYSTAL_VOICE - 5375 EFFECT_START_NID]) { 5376 if (spec->effects_switch[NOISE_REDUCTION - 5377 EFFECT_START_NID]) 5378 tmp = FLOAT_ONE; 5379 else 5380 tmp = FLOAT_ZERO; 5381 } else 5382 tmp = FLOAT_ZERO; 5383 5384 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5385 } 5386 5387 /* If rear line in disable effects. */ 5388 if (ca0132_use_alt_functions(spec) && 5389 spec->in_enum_val == REAR_LINE_IN) 5390 val = 0; 5391 } 5392 5393 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5394 nid, val); 5395 5396 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5397 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5398 ca0132_effects[idx].reqs[0], on); 5399 5400 if (err < 0) 5401 return 0; /* no changed */ 5402 5403 return 1; 5404 } 5405 5406 /* 5407 * Turn on/off Playback Enhancements 5408 */ 5409 static int ca0132_pe_switch_set(struct hda_codec *codec) 5410 { 5411 struct ca0132_spec *spec = codec->spec; 5412 hda_nid_t nid; 5413 int i, ret = 0; 5414 5415 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5416 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5417 5418 if (ca0132_use_alt_functions(spec)) 5419 ca0132_alt_select_out(codec); 5420 5421 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5422 nid = OUT_EFFECT_START_NID; 5423 /* PE affects all out effects */ 5424 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5425 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5426 5427 return ret; 5428 } 5429 5430 /* Check if Mic1 is streaming, if so, stop streaming */ 5431 static int stop_mic1(struct hda_codec *codec) 5432 { 5433 struct ca0132_spec *spec = codec->spec; 5434 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5435 AC_VERB_GET_CONV, 0); 5436 if (oldval != 0) 5437 snd_hda_codec_write(codec, spec->adcs[0], 0, 5438 AC_VERB_SET_CHANNEL_STREAMID, 5439 0); 5440 return oldval; 5441 } 5442 5443 /* Resume Mic1 streaming if it was stopped. */ 5444 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5445 { 5446 struct ca0132_spec *spec = codec->spec; 5447 /* Restore the previous stream and channel */ 5448 if (oldval != 0) 5449 snd_hda_codec_write(codec, spec->adcs[0], 0, 5450 AC_VERB_SET_CHANNEL_STREAMID, 5451 oldval); 5452 } 5453 5454 /* 5455 * Turn on/off CrystalVoice 5456 */ 5457 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5458 { 5459 struct ca0132_spec *spec = codec->spec; 5460 hda_nid_t nid; 5461 int i, ret = 0; 5462 unsigned int oldval; 5463 5464 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5465 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5466 5467 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5468 nid = IN_EFFECT_START_NID; 5469 /* CrystalVoice affects all in effects */ 5470 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5471 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5472 5473 /* including VoiceFX */ 5474 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5475 5476 /* set correct vipsource */ 5477 oldval = stop_mic1(codec); 5478 if (ca0132_use_alt_functions(spec)) 5479 ret |= ca0132_alt_set_vipsource(codec, 1); 5480 else 5481 ret |= ca0132_set_vipsource(codec, 1); 5482 resume_mic1(codec, oldval); 5483 return ret; 5484 } 5485 5486 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5487 { 5488 struct ca0132_spec *spec = codec->spec; 5489 int ret = 0; 5490 5491 if (val) /* on */ 5492 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5493 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5494 else /* off */ 5495 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5496 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5497 5498 return ret; 5499 } 5500 5501 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5502 { 5503 struct ca0132_spec *spec = codec->spec; 5504 int ret = 0; 5505 5506 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5507 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5508 return ret; 5509 } 5510 5511 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5512 { 5513 unsigned int i; 5514 5515 for (i = 0; i < 4; i++) 5516 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5517 ae5_headphone_gain_presets[val].vals[i]); 5518 return 0; 5519 } 5520 5521 /* 5522 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5523 * amplifier to handle a 600 ohm load. 5524 */ 5525 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5526 { 5527 ca0113_mmio_gpio_set(codec, 1, val); 5528 5529 return 0; 5530 } 5531 5532 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5533 struct snd_ctl_elem_value *ucontrol) 5534 { 5535 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5536 hda_nid_t nid = get_amp_nid(kcontrol); 5537 hda_nid_t shared_nid = 0; 5538 bool effective; 5539 int ret = 0; 5540 struct ca0132_spec *spec = codec->spec; 5541 int auto_jack; 5542 5543 if (nid == VNID_HP_SEL) { 5544 auto_jack = 5545 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5546 if (!auto_jack) { 5547 if (ca0132_use_alt_functions(spec)) 5548 ca0132_alt_select_out(codec); 5549 else 5550 ca0132_select_out(codec); 5551 } 5552 return 1; 5553 } 5554 5555 if (nid == VNID_AMIC1_SEL) { 5556 auto_jack = 5557 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5558 if (!auto_jack) 5559 ca0132_select_mic(codec); 5560 return 1; 5561 } 5562 5563 if (nid == VNID_HP_ASEL) { 5564 if (ca0132_use_alt_functions(spec)) 5565 ca0132_alt_select_out(codec); 5566 else 5567 ca0132_select_out(codec); 5568 return 1; 5569 } 5570 5571 if (nid == VNID_AMIC1_ASEL) { 5572 ca0132_select_mic(codec); 5573 return 1; 5574 } 5575 5576 /* if effective conditions, then update hw immediately. */ 5577 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5578 if (effective) { 5579 int dir = get_amp_direction(kcontrol); 5580 int ch = get_amp_channels(kcontrol); 5581 unsigned long pval; 5582 5583 mutex_lock(&codec->control_mutex); 5584 pval = kcontrol->private_value; 5585 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5586 0, dir); 5587 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5588 kcontrol->private_value = pval; 5589 mutex_unlock(&codec->control_mutex); 5590 } 5591 5592 return ret; 5593 } 5594 /* End of control change helpers. */ 5595 5596 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5597 long idx) 5598 { 5599 snd_hda_power_up(codec); 5600 5601 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5602 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5603 5604 snd_hda_power_down(codec); 5605 } 5606 5607 /* 5608 * Below I've added controls to mess with the effect levels, I've only enabled 5609 * them on the Sound Blaster Z, but they would probably also work on the 5610 * Chromebook. I figured they were probably tuned specifically for it, and left 5611 * out for a reason. 5612 */ 5613 5614 /* Sets DSP effect level from the sliders above the controls */ 5615 5616 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5617 const unsigned int *lookup, int idx) 5618 { 5619 int i = 0; 5620 unsigned int y; 5621 /* 5622 * For X_BASS, req 2 is actually crossover freq instead of 5623 * effect level 5624 */ 5625 if (nid == X_BASS) 5626 y = 2; 5627 else 5628 y = 1; 5629 5630 snd_hda_power_up(codec); 5631 if (nid == XBASS_XOVER) { 5632 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5633 if (ca0132_effects[i].nid == X_BASS) 5634 break; 5635 5636 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5637 ca0132_effects[i].reqs[1], 5638 &(lookup[idx - 1]), sizeof(unsigned int)); 5639 } else { 5640 /* Find the actual effect structure */ 5641 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5642 if (nid == ca0132_effects[i].nid) 5643 break; 5644 5645 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5646 ca0132_effects[i].reqs[y], 5647 &(lookup[idx]), sizeof(unsigned int)); 5648 } 5649 5650 snd_hda_power_down(codec); 5651 5652 return 0; 5653 } 5654 5655 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5656 struct snd_ctl_elem_value *ucontrol) 5657 { 5658 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5659 struct ca0132_spec *spec = codec->spec; 5660 long *valp = ucontrol->value.integer.value; 5661 hda_nid_t nid = get_amp_nid(kcontrol); 5662 5663 if (nid == BASS_REDIRECTION_XOVER) 5664 *valp = spec->bass_redirect_xover_freq; 5665 else 5666 *valp = spec->xbass_xover_freq; 5667 5668 return 0; 5669 } 5670 5671 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5672 struct snd_ctl_elem_value *ucontrol) 5673 { 5674 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5675 struct ca0132_spec *spec = codec->spec; 5676 hda_nid_t nid = get_amp_nid(kcontrol); 5677 long *valp = ucontrol->value.integer.value; 5678 int idx = nid - OUT_EFFECT_START_NID; 5679 5680 *valp = spec->fx_ctl_val[idx]; 5681 return 0; 5682 } 5683 5684 /* 5685 * The X-bass crossover starts at 10hz, so the min is 1. The 5686 * frequency is set in multiples of 10. 5687 */ 5688 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5689 struct snd_ctl_elem_info *uinfo) 5690 { 5691 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5692 uinfo->count = 1; 5693 uinfo->value.integer.min = 1; 5694 uinfo->value.integer.max = 100; 5695 uinfo->value.integer.step = 1; 5696 5697 return 0; 5698 } 5699 5700 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5701 struct snd_ctl_elem_info *uinfo) 5702 { 5703 int chs = get_amp_channels(kcontrol); 5704 5705 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5706 uinfo->count = chs == 3 ? 2 : 1; 5707 uinfo->value.integer.min = 0; 5708 uinfo->value.integer.max = 100; 5709 uinfo->value.integer.step = 1; 5710 5711 return 0; 5712 } 5713 5714 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5715 struct snd_ctl_elem_value *ucontrol) 5716 { 5717 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5718 struct ca0132_spec *spec = codec->spec; 5719 hda_nid_t nid = get_amp_nid(kcontrol); 5720 long *valp = ucontrol->value.integer.value; 5721 long *cur_val; 5722 int idx; 5723 5724 if (nid == BASS_REDIRECTION_XOVER) 5725 cur_val = &spec->bass_redirect_xover_freq; 5726 else 5727 cur_val = &spec->xbass_xover_freq; 5728 5729 /* any change? */ 5730 if (*cur_val == *valp) 5731 return 0; 5732 5733 *cur_val = *valp; 5734 5735 idx = *valp; 5736 if (nid == BASS_REDIRECTION_XOVER) 5737 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5738 else 5739 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5740 5741 return 0; 5742 } 5743 5744 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5745 struct snd_ctl_elem_value *ucontrol) 5746 { 5747 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5748 struct ca0132_spec *spec = codec->spec; 5749 hda_nid_t nid = get_amp_nid(kcontrol); 5750 long *valp = ucontrol->value.integer.value; 5751 int idx; 5752 5753 idx = nid - EFFECT_START_NID; 5754 /* any change? */ 5755 if (spec->fx_ctl_val[idx] == *valp) 5756 return 0; 5757 5758 spec->fx_ctl_val[idx] = *valp; 5759 5760 idx = *valp; 5761 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5762 5763 return 0; 5764 } 5765 5766 5767 /* 5768 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5769 * only has off or full 30 dB, and didn't like making a volume slider that has 5770 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5771 */ 5772 #define MIC_BOOST_NUM_OF_STEPS 4 5773 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5774 5775 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5776 struct snd_ctl_elem_info *uinfo) 5777 { 5778 char *sfx = "dB"; 5779 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5780 5781 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5782 uinfo->count = 1; 5783 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5784 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5785 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5786 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5787 strcpy(uinfo->value.enumerated.name, namestr); 5788 return 0; 5789 } 5790 5791 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5792 struct snd_ctl_elem_value *ucontrol) 5793 { 5794 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5795 struct ca0132_spec *spec = codec->spec; 5796 5797 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5798 return 0; 5799 } 5800 5801 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5802 struct snd_ctl_elem_value *ucontrol) 5803 { 5804 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5805 struct ca0132_spec *spec = codec->spec; 5806 int sel = ucontrol->value.enumerated.item[0]; 5807 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5808 5809 if (sel >= items) 5810 return 0; 5811 5812 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5813 sel); 5814 5815 spec->mic_boost_enum_val = sel; 5816 5817 if (spec->in_enum_val != REAR_LINE_IN) 5818 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5819 5820 return 1; 5821 } 5822 5823 /* 5824 * Sound BlasterX AE-5 Headphone Gain Controls. 5825 */ 5826 #define AE5_HEADPHONE_GAIN_MAX 3 5827 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5828 struct snd_ctl_elem_info *uinfo) 5829 { 5830 char *sfx = " Ohms)"; 5831 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5832 5833 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5834 uinfo->count = 1; 5835 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5836 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5837 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5838 sprintf(namestr, "%s %s", 5839 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5840 sfx); 5841 strcpy(uinfo->value.enumerated.name, namestr); 5842 return 0; 5843 } 5844 5845 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5846 struct snd_ctl_elem_value *ucontrol) 5847 { 5848 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5849 struct ca0132_spec *spec = codec->spec; 5850 5851 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5852 return 0; 5853 } 5854 5855 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5856 struct snd_ctl_elem_value *ucontrol) 5857 { 5858 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5859 struct ca0132_spec *spec = codec->spec; 5860 int sel = ucontrol->value.enumerated.item[0]; 5861 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5862 5863 if (sel >= items) 5864 return 0; 5865 5866 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5867 sel); 5868 5869 spec->ae5_headphone_gain_val = sel; 5870 5871 if (spec->out_enum_val == HEADPHONE_OUT) 5872 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5873 5874 return 1; 5875 } 5876 5877 /* 5878 * Sound BlasterX AE-5 sound filter enumerated control. 5879 */ 5880 #define AE5_SOUND_FILTER_MAX 3 5881 5882 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5883 struct snd_ctl_elem_info *uinfo) 5884 { 5885 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5886 5887 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5888 uinfo->count = 1; 5889 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5890 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5891 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5892 sprintf(namestr, "%s", 5893 ae5_filter_presets[uinfo->value.enumerated.item].name); 5894 strcpy(uinfo->value.enumerated.name, namestr); 5895 return 0; 5896 } 5897 5898 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5899 struct snd_ctl_elem_value *ucontrol) 5900 { 5901 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5902 struct ca0132_spec *spec = codec->spec; 5903 5904 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5905 return 0; 5906 } 5907 5908 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5909 struct snd_ctl_elem_value *ucontrol) 5910 { 5911 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5912 struct ca0132_spec *spec = codec->spec; 5913 int sel = ucontrol->value.enumerated.item[0]; 5914 unsigned int items = AE5_SOUND_FILTER_MAX; 5915 5916 if (sel >= items) 5917 return 0; 5918 5919 codec_dbg(codec, "ae5_sound_filter: %s\n", 5920 ae5_filter_presets[sel].name); 5921 5922 spec->ae5_filter_val = sel; 5923 5924 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5925 ae5_filter_presets[sel].val); 5926 5927 return 1; 5928 } 5929 5930 /* 5931 * Input Select Control for alternative ca0132 codecs. This exists because 5932 * front microphone has no auto-detect, and we need a way to set the rear 5933 * as line-in 5934 */ 5935 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5936 struct snd_ctl_elem_info *uinfo) 5937 { 5938 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5939 uinfo->count = 1; 5940 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5941 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5942 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5943 strcpy(uinfo->value.enumerated.name, 5944 in_src_str[uinfo->value.enumerated.item]); 5945 return 0; 5946 } 5947 5948 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5949 struct snd_ctl_elem_value *ucontrol) 5950 { 5951 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5952 struct ca0132_spec *spec = codec->spec; 5953 5954 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5955 return 0; 5956 } 5957 5958 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5959 struct snd_ctl_elem_value *ucontrol) 5960 { 5961 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5962 struct ca0132_spec *spec = codec->spec; 5963 int sel = ucontrol->value.enumerated.item[0]; 5964 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5965 5966 /* 5967 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5968 * line-in. 5969 */ 5970 if (ca0132_quirk(spec) == QUIRK_AE7) 5971 items = 2; 5972 5973 if (sel >= items) 5974 return 0; 5975 5976 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5977 sel, in_src_str[sel]); 5978 5979 spec->in_enum_val = sel; 5980 5981 ca0132_alt_select_in(codec); 5982 5983 return 1; 5984 } 5985 5986 /* Sound Blaster Z Output Select Control */ 5987 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5988 struct snd_ctl_elem_info *uinfo) 5989 { 5990 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5991 uinfo->count = 1; 5992 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5993 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5994 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5995 strcpy(uinfo->value.enumerated.name, 5996 out_type_str[uinfo->value.enumerated.item]); 5997 return 0; 5998 } 5999 6000 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 6001 struct snd_ctl_elem_value *ucontrol) 6002 { 6003 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6004 struct ca0132_spec *spec = codec->spec; 6005 6006 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 6007 return 0; 6008 } 6009 6010 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 6011 struct snd_ctl_elem_value *ucontrol) 6012 { 6013 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6014 struct ca0132_spec *spec = codec->spec; 6015 int sel = ucontrol->value.enumerated.item[0]; 6016 unsigned int items = NUM_OF_OUTPUTS; 6017 unsigned int auto_jack; 6018 6019 if (sel >= items) 6020 return 0; 6021 6022 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 6023 sel, out_type_str[sel]); 6024 6025 spec->out_enum_val = sel; 6026 6027 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 6028 6029 if (!auto_jack) 6030 ca0132_alt_select_out(codec); 6031 6032 return 1; 6033 } 6034 6035 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 6036 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 6037 struct snd_ctl_elem_info *uinfo) 6038 { 6039 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6040 6041 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6042 uinfo->count = 1; 6043 uinfo->value.enumerated.items = items; 6044 if (uinfo->value.enumerated.item >= items) 6045 uinfo->value.enumerated.item = items - 1; 6046 strcpy(uinfo->value.enumerated.name, 6047 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 6048 return 0; 6049 } 6050 6051 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 6052 struct snd_ctl_elem_value *ucontrol) 6053 { 6054 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6055 struct ca0132_spec *spec = codec->spec; 6056 6057 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 6058 return 0; 6059 } 6060 6061 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 6062 struct snd_ctl_elem_value *ucontrol) 6063 { 6064 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6065 struct ca0132_spec *spec = codec->spec; 6066 int sel = ucontrol->value.enumerated.item[0]; 6067 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6068 6069 if (sel >= items) 6070 return 0; 6071 6072 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 6073 sel, speaker_channel_cfgs[sel].name); 6074 6075 spec->channel_cfg_val = sel; 6076 6077 if (spec->out_enum_val == SPEAKER_OUT) 6078 ca0132_alt_select_out(codec); 6079 6080 return 1; 6081 } 6082 6083 /* 6084 * Smart Volume output setting control. Three different settings, Normal, 6085 * which takes the value from the smart volume slider. The two others, loud 6086 * and night, disregard the slider value and have uneditable values. 6087 */ 6088 #define NUM_OF_SVM_SETTINGS 3 6089 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 6090 6091 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 6092 struct snd_ctl_elem_info *uinfo) 6093 { 6094 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6095 uinfo->count = 1; 6096 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 6097 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 6098 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 6099 strcpy(uinfo->value.enumerated.name, 6100 out_svm_set_enum_str[uinfo->value.enumerated.item]); 6101 return 0; 6102 } 6103 6104 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 6105 struct snd_ctl_elem_value *ucontrol) 6106 { 6107 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6108 struct ca0132_spec *spec = codec->spec; 6109 6110 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 6111 return 0; 6112 } 6113 6114 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 6115 struct snd_ctl_elem_value *ucontrol) 6116 { 6117 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6118 struct ca0132_spec *spec = codec->spec; 6119 int sel = ucontrol->value.enumerated.item[0]; 6120 unsigned int items = NUM_OF_SVM_SETTINGS; 6121 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6122 unsigned int tmp; 6123 6124 if (sel >= items) 6125 return 0; 6126 6127 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6128 sel, out_svm_set_enum_str[sel]); 6129 6130 spec->smart_volume_setting = sel; 6131 6132 switch (sel) { 6133 case 0: 6134 tmp = FLOAT_ZERO; 6135 break; 6136 case 1: 6137 tmp = FLOAT_ONE; 6138 break; 6139 case 2: 6140 tmp = FLOAT_TWO; 6141 break; 6142 default: 6143 tmp = FLOAT_ZERO; 6144 break; 6145 } 6146 /* Req 2 is the Smart Volume Setting req. */ 6147 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6148 ca0132_effects[idx].reqs[2], tmp); 6149 return 1; 6150 } 6151 6152 /* Sound Blaster Z EQ preset controls */ 6153 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6154 struct snd_ctl_elem_info *uinfo) 6155 { 6156 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6157 6158 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6159 uinfo->count = 1; 6160 uinfo->value.enumerated.items = items; 6161 if (uinfo->value.enumerated.item >= items) 6162 uinfo->value.enumerated.item = items - 1; 6163 strcpy(uinfo->value.enumerated.name, 6164 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6165 return 0; 6166 } 6167 6168 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6169 struct snd_ctl_elem_value *ucontrol) 6170 { 6171 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6172 struct ca0132_spec *spec = codec->spec; 6173 6174 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6175 return 0; 6176 } 6177 6178 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6179 struct snd_ctl_elem_value *ucontrol) 6180 { 6181 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6182 struct ca0132_spec *spec = codec->spec; 6183 int i, err = 0; 6184 int sel = ucontrol->value.enumerated.item[0]; 6185 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6186 6187 if (sel >= items) 6188 return 0; 6189 6190 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6191 ca0132_alt_eq_presets[sel].name); 6192 /* 6193 * Idx 0 is default. 6194 * Default needs to qualify with CrystalVoice state. 6195 */ 6196 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6197 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6198 ca0132_alt_eq_enum.reqs[i], 6199 ca0132_alt_eq_presets[sel].vals[i]); 6200 if (err < 0) 6201 break; 6202 } 6203 6204 if (err >= 0) 6205 spec->eq_preset_val = sel; 6206 6207 return 1; 6208 } 6209 6210 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6211 struct snd_ctl_elem_info *uinfo) 6212 { 6213 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6214 6215 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6216 uinfo->count = 1; 6217 uinfo->value.enumerated.items = items; 6218 if (uinfo->value.enumerated.item >= items) 6219 uinfo->value.enumerated.item = items - 1; 6220 strcpy(uinfo->value.enumerated.name, 6221 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6222 return 0; 6223 } 6224 6225 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6226 struct snd_ctl_elem_value *ucontrol) 6227 { 6228 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6229 struct ca0132_spec *spec = codec->spec; 6230 6231 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6232 return 0; 6233 } 6234 6235 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6236 struct snd_ctl_elem_value *ucontrol) 6237 { 6238 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6239 struct ca0132_spec *spec = codec->spec; 6240 int i, err = 0; 6241 int sel = ucontrol->value.enumerated.item[0]; 6242 6243 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6244 return 0; 6245 6246 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6247 sel, ca0132_voicefx_presets[sel].name); 6248 6249 /* 6250 * Idx 0 is default. 6251 * Default needs to qualify with CrystalVoice state. 6252 */ 6253 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6254 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6255 ca0132_voicefx.reqs[i], 6256 ca0132_voicefx_presets[sel].vals[i]); 6257 if (err < 0) 6258 break; 6259 } 6260 6261 if (err >= 0) { 6262 spec->voicefx_val = sel; 6263 /* enable voice fx */ 6264 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6265 } 6266 6267 return 1; 6268 } 6269 6270 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6271 struct snd_ctl_elem_value *ucontrol) 6272 { 6273 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6274 struct ca0132_spec *spec = codec->spec; 6275 hda_nid_t nid = get_amp_nid(kcontrol); 6276 int ch = get_amp_channels(kcontrol); 6277 long *valp = ucontrol->value.integer.value; 6278 6279 /* vnode */ 6280 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6281 if (ch & 1) { 6282 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6283 valp++; 6284 } 6285 if (ch & 2) { 6286 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6287 valp++; 6288 } 6289 return 0; 6290 } 6291 6292 /* effects, include PE and CrystalVoice */ 6293 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6294 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6295 return 0; 6296 } 6297 6298 /* mic boost */ 6299 if (nid == spec->input_pins[0]) { 6300 *valp = spec->cur_mic_boost; 6301 return 0; 6302 } 6303 6304 if (nid == ZXR_HEADPHONE_GAIN) { 6305 *valp = spec->zxr_gain_set; 6306 return 0; 6307 } 6308 6309 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6310 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6311 return 0; 6312 } 6313 6314 if (nid == BASS_REDIRECTION) { 6315 *valp = spec->bass_redirection_val; 6316 return 0; 6317 } 6318 6319 return 0; 6320 } 6321 6322 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6323 struct snd_ctl_elem_value *ucontrol) 6324 { 6325 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6326 struct ca0132_spec *spec = codec->spec; 6327 hda_nid_t nid = get_amp_nid(kcontrol); 6328 int ch = get_amp_channels(kcontrol); 6329 long *valp = ucontrol->value.integer.value; 6330 int changed = 1; 6331 6332 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6333 nid, *valp); 6334 6335 snd_hda_power_up(codec); 6336 /* vnode */ 6337 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6338 if (ch & 1) { 6339 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6340 valp++; 6341 } 6342 if (ch & 2) { 6343 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6344 valp++; 6345 } 6346 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 6347 goto exit; 6348 } 6349 6350 /* PE */ 6351 if (nid == PLAY_ENHANCEMENT) { 6352 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6353 changed = ca0132_pe_switch_set(codec); 6354 goto exit; 6355 } 6356 6357 /* CrystalVoice */ 6358 if (nid == CRYSTAL_VOICE) { 6359 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6360 changed = ca0132_cvoice_switch_set(codec); 6361 goto exit; 6362 } 6363 6364 /* out and in effects */ 6365 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6366 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6367 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6368 changed = ca0132_effects_set(codec, nid, *valp); 6369 goto exit; 6370 } 6371 6372 /* mic boost */ 6373 if (nid == spec->input_pins[0]) { 6374 spec->cur_mic_boost = *valp; 6375 if (ca0132_use_alt_functions(spec)) { 6376 if (spec->in_enum_val != REAR_LINE_IN) 6377 changed = ca0132_mic_boost_set(codec, *valp); 6378 } else { 6379 /* Mic boost does not apply to Digital Mic */ 6380 if (spec->cur_mic_type != DIGITAL_MIC) 6381 changed = ca0132_mic_boost_set(codec, *valp); 6382 } 6383 6384 goto exit; 6385 } 6386 6387 if (nid == ZXR_HEADPHONE_GAIN) { 6388 spec->zxr_gain_set = *valp; 6389 if (spec->cur_out_type == HEADPHONE_OUT) 6390 changed = zxr_headphone_gain_set(codec, *valp); 6391 else 6392 changed = 0; 6393 6394 goto exit; 6395 } 6396 6397 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6398 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6399 if (spec->cur_out_type == SPEAKER_OUT) 6400 ca0132_alt_set_full_range_speaker(codec); 6401 6402 changed = 0; 6403 } 6404 6405 if (nid == BASS_REDIRECTION) { 6406 spec->bass_redirection_val = *valp; 6407 if (spec->cur_out_type == SPEAKER_OUT) 6408 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6409 6410 changed = 0; 6411 } 6412 6413 exit: 6414 snd_hda_power_down(codec); 6415 return changed; 6416 } 6417 6418 /* 6419 * Volume related 6420 */ 6421 /* 6422 * Sets the internal DSP decibel level to match the DAC for output, and the 6423 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6424 * all alternative codecs set DSP playback volume. 6425 */ 6426 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6427 { 6428 struct ca0132_spec *spec = codec->spec; 6429 unsigned int dsp_dir; 6430 unsigned int lookup_val; 6431 6432 if (nid == VNID_SPK) 6433 dsp_dir = DSP_VOL_OUT; 6434 else 6435 dsp_dir = DSP_VOL_IN; 6436 6437 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6438 6439 dspio_set_uint_param(codec, 6440 ca0132_alt_vol_ctls[dsp_dir].mid, 6441 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6442 float_vol_db_lookup[lookup_val]); 6443 6444 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6445 6446 dspio_set_uint_param(codec, 6447 ca0132_alt_vol_ctls[dsp_dir].mid, 6448 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6449 float_vol_db_lookup[lookup_val]); 6450 6451 dspio_set_uint_param(codec, 6452 ca0132_alt_vol_ctls[dsp_dir].mid, 6453 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6454 } 6455 6456 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6457 struct snd_ctl_elem_info *uinfo) 6458 { 6459 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6460 struct ca0132_spec *spec = codec->spec; 6461 hda_nid_t nid = get_amp_nid(kcontrol); 6462 int ch = get_amp_channels(kcontrol); 6463 int dir = get_amp_direction(kcontrol); 6464 unsigned long pval; 6465 int err; 6466 6467 switch (nid) { 6468 case VNID_SPK: 6469 /* follow shared_out info */ 6470 nid = spec->shared_out_nid; 6471 mutex_lock(&codec->control_mutex); 6472 pval = kcontrol->private_value; 6473 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6474 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6475 kcontrol->private_value = pval; 6476 mutex_unlock(&codec->control_mutex); 6477 break; 6478 case VNID_MIC: 6479 /* follow shared_mic info */ 6480 nid = spec->shared_mic_nid; 6481 mutex_lock(&codec->control_mutex); 6482 pval = kcontrol->private_value; 6483 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6484 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6485 kcontrol->private_value = pval; 6486 mutex_unlock(&codec->control_mutex); 6487 break; 6488 default: 6489 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6490 } 6491 return err; 6492 } 6493 6494 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6495 struct snd_ctl_elem_value *ucontrol) 6496 { 6497 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6498 struct ca0132_spec *spec = codec->spec; 6499 hda_nid_t nid = get_amp_nid(kcontrol); 6500 int ch = get_amp_channels(kcontrol); 6501 long *valp = ucontrol->value.integer.value; 6502 6503 /* store the left and right volume */ 6504 if (ch & 1) { 6505 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6506 valp++; 6507 } 6508 if (ch & 2) { 6509 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6510 valp++; 6511 } 6512 return 0; 6513 } 6514 6515 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6516 struct snd_ctl_elem_value *ucontrol) 6517 { 6518 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6519 struct ca0132_spec *spec = codec->spec; 6520 hda_nid_t nid = get_amp_nid(kcontrol); 6521 int ch = get_amp_channels(kcontrol); 6522 long *valp = ucontrol->value.integer.value; 6523 hda_nid_t shared_nid = 0; 6524 bool effective; 6525 int changed = 1; 6526 6527 /* store the left and right volume */ 6528 if (ch & 1) { 6529 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6530 valp++; 6531 } 6532 if (ch & 2) { 6533 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6534 valp++; 6535 } 6536 6537 /* if effective conditions, then update hw immediately. */ 6538 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6539 if (effective) { 6540 int dir = get_amp_direction(kcontrol); 6541 unsigned long pval; 6542 6543 snd_hda_power_up(codec); 6544 mutex_lock(&codec->control_mutex); 6545 pval = kcontrol->private_value; 6546 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6547 0, dir); 6548 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6549 kcontrol->private_value = pval; 6550 mutex_unlock(&codec->control_mutex); 6551 snd_hda_power_down(codec); 6552 } 6553 6554 return changed; 6555 } 6556 6557 /* 6558 * This function is the same as the one above, because using an if statement 6559 * inside of the above volume control for the DSP volume would cause too much 6560 * lag. This is a lot more smooth. 6561 */ 6562 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6563 struct snd_ctl_elem_value *ucontrol) 6564 { 6565 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6566 struct ca0132_spec *spec = codec->spec; 6567 hda_nid_t nid = get_amp_nid(kcontrol); 6568 int ch = get_amp_channels(kcontrol); 6569 long *valp = ucontrol->value.integer.value; 6570 hda_nid_t vnid = 0; 6571 int changed; 6572 6573 switch (nid) { 6574 case 0x02: 6575 vnid = VNID_SPK; 6576 break; 6577 case 0x07: 6578 vnid = VNID_MIC; 6579 break; 6580 } 6581 6582 /* store the left and right volume */ 6583 if (ch & 1) { 6584 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6585 valp++; 6586 } 6587 if (ch & 2) { 6588 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6589 valp++; 6590 } 6591 6592 snd_hda_power_up(codec); 6593 ca0132_alt_dsp_volume_put(codec, vnid); 6594 mutex_lock(&codec->control_mutex); 6595 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6596 mutex_unlock(&codec->control_mutex); 6597 snd_hda_power_down(codec); 6598 6599 return changed; 6600 } 6601 6602 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6603 unsigned int size, unsigned int __user *tlv) 6604 { 6605 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6606 struct ca0132_spec *spec = codec->spec; 6607 hda_nid_t nid = get_amp_nid(kcontrol); 6608 int ch = get_amp_channels(kcontrol); 6609 int dir = get_amp_direction(kcontrol); 6610 unsigned long pval; 6611 int err; 6612 6613 switch (nid) { 6614 case VNID_SPK: 6615 /* follow shared_out tlv */ 6616 nid = spec->shared_out_nid; 6617 mutex_lock(&codec->control_mutex); 6618 pval = kcontrol->private_value; 6619 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6620 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6621 kcontrol->private_value = pval; 6622 mutex_unlock(&codec->control_mutex); 6623 break; 6624 case VNID_MIC: 6625 /* follow shared_mic tlv */ 6626 nid = spec->shared_mic_nid; 6627 mutex_lock(&codec->control_mutex); 6628 pval = kcontrol->private_value; 6629 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6630 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6631 kcontrol->private_value = pval; 6632 mutex_unlock(&codec->control_mutex); 6633 break; 6634 default: 6635 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6636 } 6637 return err; 6638 } 6639 6640 /* Add volume slider control for effect level */ 6641 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6642 const char *pfx, int dir) 6643 { 6644 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6645 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6646 struct snd_kcontrol_new knew = 6647 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6648 6649 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6650 6651 knew.tlv.c = NULL; 6652 6653 switch (nid) { 6654 case XBASS_XOVER: 6655 knew.info = ca0132_alt_xbass_xover_slider_info; 6656 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6657 knew.put = ca0132_alt_xbass_xover_slider_put; 6658 break; 6659 default: 6660 knew.info = ca0132_alt_effect_slider_info; 6661 knew.get = ca0132_alt_slider_ctl_get; 6662 knew.put = ca0132_alt_effect_slider_put; 6663 knew.private_value = 6664 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6665 break; 6666 } 6667 6668 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6669 } 6670 6671 /* 6672 * Added FX: prefix for the alternative codecs, because otherwise the surround 6673 * effect would conflict with the Surround sound volume control. Also seems more 6674 * clear as to what the switches do. Left alone for others. 6675 */ 6676 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6677 const char *pfx, int dir) 6678 { 6679 struct ca0132_spec *spec = codec->spec; 6680 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6681 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6682 struct snd_kcontrol_new knew = 6683 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6684 /* If using alt_controls, add FX: prefix. But, don't add FX: 6685 * prefix to OutFX or InFX enable controls. 6686 */ 6687 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6688 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6689 else 6690 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6691 6692 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6693 } 6694 6695 static int add_voicefx(struct hda_codec *codec) 6696 { 6697 struct snd_kcontrol_new knew = 6698 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6699 VOICEFX, 1, 0, HDA_INPUT); 6700 knew.info = ca0132_voicefx_info; 6701 knew.get = ca0132_voicefx_get; 6702 knew.put = ca0132_voicefx_put; 6703 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6704 } 6705 6706 /* Create the EQ Preset control */ 6707 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6708 { 6709 struct snd_kcontrol_new knew = 6710 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6711 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6712 knew.info = ca0132_alt_eq_preset_info; 6713 knew.get = ca0132_alt_eq_preset_get; 6714 knew.put = ca0132_alt_eq_preset_put; 6715 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6716 snd_ctl_new1(&knew, codec)); 6717 } 6718 6719 /* 6720 * Add enumerated control for the three different settings of the smart volume 6721 * output effect. Normal just uses the slider value, and loud and night are 6722 * their own things that ignore that value. 6723 */ 6724 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6725 { 6726 struct snd_kcontrol_new knew = 6727 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6728 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6729 knew.info = ca0132_alt_svm_setting_info; 6730 knew.get = ca0132_alt_svm_setting_get; 6731 knew.put = ca0132_alt_svm_setting_put; 6732 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6733 snd_ctl_new1(&knew, codec)); 6734 6735 } 6736 6737 /* 6738 * Create an Output Select enumerated control for codecs with surround 6739 * out capabilities. 6740 */ 6741 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6742 { 6743 struct snd_kcontrol_new knew = 6744 HDA_CODEC_MUTE_MONO("Output Select", 6745 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6746 knew.info = ca0132_alt_output_select_get_info; 6747 knew.get = ca0132_alt_output_select_get; 6748 knew.put = ca0132_alt_output_select_put; 6749 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6750 snd_ctl_new1(&knew, codec)); 6751 } 6752 6753 /* 6754 * Add a control for selecting channel count on speaker output. Setting this 6755 * allows the DSP to do bass redirection and channel upmixing on surround 6756 * configurations. 6757 */ 6758 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6759 { 6760 struct snd_kcontrol_new knew = 6761 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6762 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6763 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6764 knew.get = ca0132_alt_speaker_channel_cfg_get; 6765 knew.put = ca0132_alt_speaker_channel_cfg_put; 6766 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6767 snd_ctl_new1(&knew, codec)); 6768 } 6769 6770 /* 6771 * Full range front stereo and rear surround switches. When these are set to 6772 * full range, the lower frequencies from these channels are no longer 6773 * redirected to the LFE channel. 6774 */ 6775 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6776 { 6777 struct snd_kcontrol_new knew = 6778 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6779 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6780 6781 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6782 snd_ctl_new1(&knew, codec)); 6783 } 6784 6785 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6786 { 6787 struct snd_kcontrol_new knew = 6788 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6789 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6790 6791 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6792 snd_ctl_new1(&knew, codec)); 6793 } 6794 6795 /* 6796 * Bass redirection redirects audio below the crossover frequency to the LFE 6797 * channel on speakers that are set as not being full-range. On configurations 6798 * without an LFE channel, it does nothing. Bass redirection seems to be the 6799 * replacement for X-Bass on configurations with an LFE channel. 6800 */ 6801 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6802 { 6803 const char *namestr = "Bass Redirection Crossover"; 6804 struct snd_kcontrol_new knew = 6805 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6806 HDA_OUTPUT); 6807 6808 knew.tlv.c = NULL; 6809 knew.info = ca0132_alt_xbass_xover_slider_info; 6810 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6811 knew.put = ca0132_alt_xbass_xover_slider_put; 6812 6813 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6814 snd_ctl_new1(&knew, codec)); 6815 } 6816 6817 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6818 { 6819 const char *namestr = "Bass Redirection"; 6820 struct snd_kcontrol_new knew = 6821 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6822 HDA_OUTPUT); 6823 6824 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6825 snd_ctl_new1(&knew, codec)); 6826 } 6827 6828 /* 6829 * Create an Input Source enumerated control for the alternate ca0132 codecs 6830 * because the front microphone has no auto-detect, and Line-in has to be set 6831 * somehow. 6832 */ 6833 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6834 { 6835 struct snd_kcontrol_new knew = 6836 HDA_CODEC_MUTE_MONO("Input Source", 6837 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6838 knew.info = ca0132_alt_input_source_info; 6839 knew.get = ca0132_alt_input_source_get; 6840 knew.put = ca0132_alt_input_source_put; 6841 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6842 snd_ctl_new1(&knew, codec)); 6843 } 6844 6845 /* 6846 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6847 * more control than the original mic boost, which is either full 30dB or off. 6848 */ 6849 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6850 { 6851 struct snd_kcontrol_new knew = 6852 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6853 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6854 knew.info = ca0132_alt_mic_boost_info; 6855 knew.get = ca0132_alt_mic_boost_get; 6856 knew.put = ca0132_alt_mic_boost_put; 6857 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6858 snd_ctl_new1(&knew, codec)); 6859 6860 } 6861 6862 /* 6863 * Add headphone gain enumerated control for the AE-5. This switches between 6864 * three modes, low, medium, and high. When non-headphone outputs are selected, 6865 * it is automatically set to high. This is the same behavior as Windows. 6866 */ 6867 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6868 { 6869 struct snd_kcontrol_new knew = 6870 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6871 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6872 knew.info = ae5_headphone_gain_info; 6873 knew.get = ae5_headphone_gain_get; 6874 knew.put = ae5_headphone_gain_put; 6875 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6876 snd_ctl_new1(&knew, codec)); 6877 } 6878 6879 /* 6880 * Add sound filter enumerated control for the AE-5. This adds three different 6881 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6882 * read into it, it changes the DAC's interpolation filter. 6883 */ 6884 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6885 { 6886 struct snd_kcontrol_new knew = 6887 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6888 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6889 knew.info = ae5_sound_filter_info; 6890 knew.get = ae5_sound_filter_get; 6891 knew.put = ae5_sound_filter_put; 6892 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6893 snd_ctl_new1(&knew, codec)); 6894 } 6895 6896 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6897 { 6898 struct snd_kcontrol_new knew = 6899 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6900 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6901 6902 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6903 snd_ctl_new1(&knew, codec)); 6904 } 6905 6906 /* 6907 * Need to create follower controls for the alternate codecs that have surround 6908 * capabilities. 6909 */ 6910 static const char * const ca0132_alt_follower_pfxs[] = { 6911 "Front", "Surround", "Center", "LFE", NULL, 6912 }; 6913 6914 /* 6915 * Also need special channel map, because the default one is incorrect. 6916 * I think this has to do with the pin for rear surround being 0x11, 6917 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6918 */ 6919 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6920 { .channels = 2, 6921 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6922 { .channels = 4, 6923 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6924 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6925 { .channels = 6, 6926 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6927 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6928 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6929 { } 6930 }; 6931 6932 /* Add the correct chmap for streams with 6 channels. */ 6933 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6934 { 6935 int err = 0; 6936 struct hda_pcm *pcm; 6937 6938 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6939 struct hda_pcm_stream *hinfo = 6940 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6941 struct snd_pcm_chmap *chmap; 6942 const struct snd_pcm_chmap_elem *elem; 6943 6944 elem = ca0132_alt_chmaps; 6945 if (hinfo->channels_max == 6) { 6946 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6947 SNDRV_PCM_STREAM_PLAYBACK, 6948 elem, hinfo->channels_max, 0, &chmap); 6949 if (err < 0) 6950 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6951 } 6952 } 6953 } 6954 6955 /* 6956 * When changing Node IDs for Mixer Controls below, make sure to update 6957 * Node IDs in ca0132_config() as well. 6958 */ 6959 static const struct snd_kcontrol_new ca0132_mixer[] = { 6960 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6961 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6962 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6963 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6964 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6965 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6966 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6967 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6968 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6969 0x12, 1, HDA_INPUT), 6970 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6971 VNID_HP_SEL, 1, HDA_OUTPUT), 6972 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6973 VNID_AMIC1_SEL, 1, HDA_INPUT), 6974 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6975 VNID_HP_ASEL, 1, HDA_OUTPUT), 6976 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6977 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6978 { } /* end */ 6979 }; 6980 6981 /* 6982 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6983 * surround controls. Also sets both the Front Playback and Capture Volume 6984 * controls to alt so they set the DSP's decibel level. 6985 */ 6986 static const struct snd_kcontrol_new desktop_mixer[] = { 6987 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6988 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6989 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6990 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6991 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6992 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6993 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6994 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6995 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6996 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6997 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6998 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6999 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7000 VNID_HP_ASEL, 1, HDA_OUTPUT), 7001 { } /* end */ 7002 }; 7003 7004 /* 7005 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 7006 * because it doesn't set decibel levels for the DSP for capture. 7007 */ 7008 static const struct snd_kcontrol_new r3di_mixer[] = { 7009 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 7010 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 7011 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 7012 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 7013 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7014 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7015 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7016 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7017 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 7018 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7019 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7020 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7021 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7022 VNID_HP_ASEL, 1, HDA_OUTPUT), 7023 { } /* end */ 7024 }; 7025 7026 static int ca0132_build_controls(struct hda_codec *codec) 7027 { 7028 struct ca0132_spec *spec = codec->spec; 7029 int i, num_fx, num_sliders; 7030 int err = 0; 7031 7032 /* Add Mixer controls */ 7033 for (i = 0; i < spec->num_mixers; i++) { 7034 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 7035 if (err < 0) 7036 return err; 7037 } 7038 /* Setup vmaster with surround followers for desktop ca0132 devices */ 7039 if (ca0132_use_alt_functions(spec)) { 7040 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 7041 spec->tlv); 7042 snd_hda_add_vmaster(codec, "Master Playback Volume", 7043 spec->tlv, ca0132_alt_follower_pfxs, 7044 "Playback Volume", 0); 7045 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 7046 NULL, ca0132_alt_follower_pfxs, 7047 "Playback Switch", 7048 true, 0, &spec->vmaster_mute.sw_kctl); 7049 if (err < 0) 7050 return err; 7051 } 7052 7053 /* Add in and out effects controls. 7054 * VoiceFX, PE and CrystalVoice are added separately. 7055 */ 7056 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7057 for (i = 0; i < num_fx; i++) { 7058 /* Desktop cards break if Echo Cancellation is used. */ 7059 if (ca0132_use_pci_mmio(spec)) { 7060 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 7061 OUT_EFFECTS_COUNT)) 7062 continue; 7063 } 7064 7065 err = add_fx_switch(codec, ca0132_effects[i].nid, 7066 ca0132_effects[i].name, 7067 ca0132_effects[i].direct); 7068 if (err < 0) 7069 return err; 7070 } 7071 /* 7072 * If codec has use_alt_controls set to true, add effect level sliders, 7073 * EQ presets, and Smart Volume presets. Also, change names to add FX 7074 * prefix, and change PlayEnhancement and CrystalVoice to match. 7075 */ 7076 if (ca0132_use_alt_controls(spec)) { 7077 err = ca0132_alt_add_svm_enum(codec); 7078 if (err < 0) 7079 return err; 7080 7081 err = add_ca0132_alt_eq_presets(codec); 7082 if (err < 0) 7083 return err; 7084 7085 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7086 "Enable OutFX", 0); 7087 if (err < 0) 7088 return err; 7089 7090 err = add_fx_switch(codec, CRYSTAL_VOICE, 7091 "Enable InFX", 1); 7092 if (err < 0) 7093 return err; 7094 7095 num_sliders = OUT_EFFECTS_COUNT - 1; 7096 for (i = 0; i < num_sliders; i++) { 7097 err = ca0132_alt_add_effect_slider(codec, 7098 ca0132_effects[i].nid, 7099 ca0132_effects[i].name, 7100 ca0132_effects[i].direct); 7101 if (err < 0) 7102 return err; 7103 } 7104 7105 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 7106 "X-Bass Crossover", EFX_DIR_OUT); 7107 7108 if (err < 0) 7109 return err; 7110 } else { 7111 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7112 "PlayEnhancement", 0); 7113 if (err < 0) 7114 return err; 7115 7116 err = add_fx_switch(codec, CRYSTAL_VOICE, 7117 "CrystalVoice", 1); 7118 if (err < 0) 7119 return err; 7120 } 7121 err = add_voicefx(codec); 7122 if (err < 0) 7123 return err; 7124 7125 /* 7126 * If the codec uses alt_functions, you need the enumerated controls 7127 * to select the new outputs and inputs, plus add the new mic boost 7128 * setting control. 7129 */ 7130 if (ca0132_use_alt_functions(spec)) { 7131 err = ca0132_alt_add_output_enum(codec); 7132 if (err < 0) 7133 return err; 7134 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7135 if (err < 0) 7136 return err; 7137 err = ca0132_alt_add_front_full_range_switch(codec); 7138 if (err < 0) 7139 return err; 7140 err = ca0132_alt_add_rear_full_range_switch(codec); 7141 if (err < 0) 7142 return err; 7143 err = ca0132_alt_add_bass_redirection_crossover(codec); 7144 if (err < 0) 7145 return err; 7146 err = ca0132_alt_add_bass_redirection_switch(codec); 7147 if (err < 0) 7148 return err; 7149 err = ca0132_alt_add_mic_boost_enum(codec); 7150 if (err < 0) 7151 return err; 7152 /* 7153 * ZxR only has microphone input, there is no front panel 7154 * header on the card, and aux-in is handled by the DBPro board. 7155 */ 7156 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7157 err = ca0132_alt_add_input_enum(codec); 7158 if (err < 0) 7159 return err; 7160 } 7161 } 7162 7163 switch (ca0132_quirk(spec)) { 7164 case QUIRK_AE5: 7165 case QUIRK_AE7: 7166 err = ae5_add_headphone_gain_enum(codec); 7167 if (err < 0) 7168 return err; 7169 err = ae5_add_sound_filter_enum(codec); 7170 if (err < 0) 7171 return err; 7172 break; 7173 case QUIRK_ZXR: 7174 err = zxr_add_headphone_gain_switch(codec); 7175 if (err < 0) 7176 return err; 7177 break; 7178 default: 7179 break; 7180 } 7181 7182 #ifdef ENABLE_TUNING_CONTROLS 7183 add_tuning_ctls(codec); 7184 #endif 7185 7186 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7187 if (err < 0) 7188 return err; 7189 7190 if (spec->dig_out) { 7191 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7192 spec->dig_out); 7193 if (err < 0) 7194 return err; 7195 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7196 if (err < 0) 7197 return err; 7198 /* spec->multiout.share_spdif = 1; */ 7199 } 7200 7201 if (spec->dig_in) { 7202 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7203 if (err < 0) 7204 return err; 7205 } 7206 7207 if (ca0132_use_alt_functions(spec)) 7208 ca0132_alt_add_chmap_ctls(codec); 7209 7210 return 0; 7211 } 7212 7213 static int dbpro_build_controls(struct hda_codec *codec) 7214 { 7215 struct ca0132_spec *spec = codec->spec; 7216 int err = 0; 7217 7218 if (spec->dig_out) { 7219 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7220 spec->dig_out); 7221 if (err < 0) 7222 return err; 7223 } 7224 7225 if (spec->dig_in) { 7226 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7227 if (err < 0) 7228 return err; 7229 } 7230 7231 return 0; 7232 } 7233 7234 /* 7235 * PCM 7236 */ 7237 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7238 .substreams = 1, 7239 .channels_min = 2, 7240 .channels_max = 6, 7241 .ops = { 7242 .prepare = ca0132_playback_pcm_prepare, 7243 .cleanup = ca0132_playback_pcm_cleanup, 7244 .get_delay = ca0132_playback_pcm_delay, 7245 }, 7246 }; 7247 7248 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7249 .substreams = 1, 7250 .channels_min = 2, 7251 .channels_max = 2, 7252 .ops = { 7253 .prepare = ca0132_capture_pcm_prepare, 7254 .cleanup = ca0132_capture_pcm_cleanup, 7255 .get_delay = ca0132_capture_pcm_delay, 7256 }, 7257 }; 7258 7259 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7260 .substreams = 1, 7261 .channels_min = 2, 7262 .channels_max = 2, 7263 .ops = { 7264 .open = ca0132_dig_playback_pcm_open, 7265 .close = ca0132_dig_playback_pcm_close, 7266 .prepare = ca0132_dig_playback_pcm_prepare, 7267 .cleanup = ca0132_dig_playback_pcm_cleanup 7268 }, 7269 }; 7270 7271 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7272 .substreams = 1, 7273 .channels_min = 2, 7274 .channels_max = 2, 7275 }; 7276 7277 static int ca0132_build_pcms(struct hda_codec *codec) 7278 { 7279 struct ca0132_spec *spec = codec->spec; 7280 struct hda_pcm *info; 7281 7282 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7283 if (!info) 7284 return -ENOMEM; 7285 if (ca0132_use_alt_functions(spec)) { 7286 info->own_chmap = true; 7287 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7288 = ca0132_alt_chmaps; 7289 } 7290 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7291 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7292 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7293 spec->multiout.max_channels; 7294 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7295 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7296 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7297 7298 /* With the DSP enabled, desktops don't use this ADC. */ 7299 if (!ca0132_use_alt_functions(spec)) { 7300 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7301 if (!info) 7302 return -ENOMEM; 7303 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7304 ca0132_pcm_analog_capture; 7305 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7306 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7307 } 7308 7309 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7310 if (!info) 7311 return -ENOMEM; 7312 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7313 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7314 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7315 7316 if (!spec->dig_out && !spec->dig_in) 7317 return 0; 7318 7319 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7320 if (!info) 7321 return -ENOMEM; 7322 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7323 if (spec->dig_out) { 7324 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7325 ca0132_pcm_digital_playback; 7326 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7327 } 7328 if (spec->dig_in) { 7329 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7330 ca0132_pcm_digital_capture; 7331 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7332 } 7333 7334 return 0; 7335 } 7336 7337 static int dbpro_build_pcms(struct hda_codec *codec) 7338 { 7339 struct ca0132_spec *spec = codec->spec; 7340 struct hda_pcm *info; 7341 7342 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7343 if (!info) 7344 return -ENOMEM; 7345 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7346 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7347 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7348 7349 7350 if (!spec->dig_out && !spec->dig_in) 7351 return 0; 7352 7353 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7354 if (!info) 7355 return -ENOMEM; 7356 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7357 if (spec->dig_out) { 7358 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7359 ca0132_pcm_digital_playback; 7360 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7361 } 7362 if (spec->dig_in) { 7363 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7364 ca0132_pcm_digital_capture; 7365 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7366 } 7367 7368 return 0; 7369 } 7370 7371 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7372 { 7373 if (pin) { 7374 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7375 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7376 snd_hda_codec_write(codec, pin, 0, 7377 AC_VERB_SET_AMP_GAIN_MUTE, 7378 AMP_OUT_UNMUTE); 7379 } 7380 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7381 snd_hda_codec_write(codec, dac, 0, 7382 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7383 } 7384 7385 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7386 { 7387 if (pin) { 7388 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7389 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7390 snd_hda_codec_write(codec, pin, 0, 7391 AC_VERB_SET_AMP_GAIN_MUTE, 7392 AMP_IN_UNMUTE(0)); 7393 } 7394 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7395 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7396 AMP_IN_UNMUTE(0)); 7397 7398 /* init to 0 dB and unmute. */ 7399 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7400 HDA_AMP_VOLMASK, 0x5a); 7401 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7402 HDA_AMP_MUTE, 0); 7403 } 7404 } 7405 7406 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7407 { 7408 unsigned int caps; 7409 7410 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7411 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7412 snd_hda_override_amp_caps(codec, nid, dir, caps); 7413 } 7414 7415 /* 7416 * Switch between Digital built-in mic and analog mic. 7417 */ 7418 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7419 { 7420 struct ca0132_spec *spec = codec->spec; 7421 unsigned int tmp; 7422 u8 val; 7423 unsigned int oldval; 7424 7425 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7426 7427 oldval = stop_mic1(codec); 7428 ca0132_set_vipsource(codec, 0); 7429 if (enable) { 7430 /* set DMic input as 2-ch */ 7431 tmp = FLOAT_TWO; 7432 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7433 7434 val = spec->dmic_ctl; 7435 val |= 0x80; 7436 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7437 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7438 7439 if (!(spec->dmic_ctl & 0x20)) 7440 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7441 } else { 7442 /* set AMic input as mono */ 7443 tmp = FLOAT_ONE; 7444 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7445 7446 val = spec->dmic_ctl; 7447 /* clear bit7 and bit5 to disable dmic */ 7448 val &= 0x5f; 7449 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7450 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7451 7452 if (!(spec->dmic_ctl & 0x20)) 7453 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7454 } 7455 ca0132_set_vipsource(codec, 1); 7456 resume_mic1(codec, oldval); 7457 } 7458 7459 /* 7460 * Initialization for Digital Mic. 7461 */ 7462 static void ca0132_init_dmic(struct hda_codec *codec) 7463 { 7464 struct ca0132_spec *spec = codec->spec; 7465 u8 val; 7466 7467 /* Setup Digital Mic here, but don't enable. 7468 * Enable based on jack detect. 7469 */ 7470 7471 /* MCLK uses MPIO1, set to enable. 7472 * Bit 2-0: MPIO select 7473 * Bit 3: set to disable 7474 * Bit 7-4: reserved 7475 */ 7476 val = 0x01; 7477 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7478 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7479 7480 /* Data1 uses MPIO3. Data2 not use 7481 * Bit 2-0: Data1 MPIO select 7482 * Bit 3: set disable Data1 7483 * Bit 6-4: Data2 MPIO select 7484 * Bit 7: set disable Data2 7485 */ 7486 val = 0x83; 7487 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7488 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7489 7490 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7491 * Bit 3-0: Channel mask 7492 * Bit 4: set for 48KHz, clear for 32KHz 7493 * Bit 5: mode 7494 * Bit 6: set to select Data2, clear for Data1 7495 * Bit 7: set to enable DMic, clear for AMic 7496 */ 7497 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7498 val = 0x33; 7499 else 7500 val = 0x23; 7501 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7502 spec->dmic_ctl = val; 7503 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7504 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7505 } 7506 7507 /* 7508 * Initialization for Analog Mic 2 7509 */ 7510 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7511 { 7512 struct ca0132_spec *spec = codec->spec; 7513 7514 mutex_lock(&spec->chipio_mutex); 7515 7516 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); 7517 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); 7518 7519 mutex_unlock(&spec->chipio_mutex); 7520 } 7521 7522 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7523 { 7524 struct ca0132_spec *spec = codec->spec; 7525 int i; 7526 7527 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7528 snd_hda_codec_update_widgets(codec); 7529 7530 for (i = 0; i < spec->multiout.num_dacs; i++) 7531 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7532 7533 for (i = 0; i < spec->num_outputs; i++) 7534 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7535 7536 for (i = 0; i < spec->num_inputs; i++) { 7537 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7538 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7539 } 7540 } 7541 7542 7543 /* If there is an active channel for some reason, find it and free it. */ 7544 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) 7545 { 7546 unsigned int i, tmp; 7547 int status; 7548 7549 /* Read active DSPDMAC channel register. */ 7550 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); 7551 if (status >= 0) { 7552 /* AND against 0xfff to get the active channel bits. */ 7553 tmp = tmp & 0xfff; 7554 7555 /* If there are no active channels, nothing to free. */ 7556 if (!tmp) 7557 return; 7558 } else { 7559 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", 7560 __func__); 7561 return; 7562 } 7563 7564 /* 7565 * Check each DSP DMA channel for activity, and if the channel is 7566 * active, free it. 7567 */ 7568 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { 7569 if (dsp_is_dma_active(codec, i)) { 7570 status = dspio_free_dma_chan(codec, i); 7571 if (status < 0) 7572 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", 7573 __func__, i); 7574 } 7575 } 7576 } 7577 7578 /* 7579 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in 7580 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. 7581 * Instead, audio is now routed through the DSP's DMA controllers, which 7582 * the DSP is tasked with setting up itself. Through debugging, it seems the 7583 * cause of most of the no-audio on startup issues were due to improperly 7584 * configured DSP DMA channels. 7585 * 7586 * Normally, the DSP configures these the first time an HDA audio stream is 7587 * started post DSP firmware download. That is why creating a 'dummy' stream 7588 * worked in fixing the audio in some cases. This works most of the time, but 7589 * sometimes if a stream is started/stopped before the DSP can setup the DMA 7590 * configuration registers, it ends up in a broken state. Issues can also 7591 * arise if streams are started in an unusual order, i.e the audio output dma 7592 * channel being sandwiched between the mic1 and mic2 dma channels. 7593 * 7594 * The solution to this is to make sure that the DSP has no DMA channels 7595 * in use post DSP firmware download, and then to manually start each default 7596 * DSP stream that uses the DMA channels. These are 0x0c, the audio output 7597 * stream, 0x03, analog mic 1, and 0x04, analog mic 2. 7598 */ 7599 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) 7600 { 7601 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; 7602 struct ca0132_spec *spec = codec->spec; 7603 unsigned int i, tmp; 7604 7605 /* 7606 * Check if any of the default streams are active, and if they are, 7607 * stop them. 7608 */ 7609 mutex_lock(&spec->chipio_mutex); 7610 7611 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7612 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); 7613 7614 if (tmp) { 7615 chipio_set_stream_control(codec, 7616 dsp_dma_stream_ids[i], 0); 7617 } 7618 } 7619 7620 mutex_unlock(&spec->chipio_mutex); 7621 7622 /* 7623 * If all DSP streams are inactive, there should be no active DSP DMA 7624 * channels. Check and make sure this is the case, and if it isn't, 7625 * free any active channels. 7626 */ 7627 ca0132_alt_free_active_dma_channels(codec); 7628 7629 mutex_lock(&spec->chipio_mutex); 7630 7631 /* Make sure stream 0x0c is six channels. */ 7632 chipio_set_stream_channels(codec, 0x0c, 6); 7633 7634 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7635 chipio_set_stream_control(codec, 7636 dsp_dma_stream_ids[i], 1); 7637 7638 /* Give the DSP some time to setup the DMA channel. */ 7639 msleep(75); 7640 } 7641 7642 mutex_unlock(&spec->chipio_mutex); 7643 } 7644 7645 /* 7646 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio 7647 * router', where each entry represents a 48khz audio channel, with a format 7648 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number 7649 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, 7650 * and 3 if it's using Sample Rate Converter ports. 7651 * An example is: 7652 * 0x0001f8c0 7653 * In this case, f8 is the destination, and c0 is the source. The number value 7654 * is 1. 7655 * This region of memory is normally managed internally by the 8051, where 7656 * the region of exram memory from 0x1477-0x1575 has each byte represent an 7657 * entry within the 0x190000 range, and when a range of entries is in use, the 7658 * ending value is overwritten with 0xff. 7659 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO 7660 * streamID's, where each entry is a starting 0x190000 port offset. 7661 * 0x159d in exram is the same as 0x1578, except it contains the ending port 7662 * offset for the corresponding streamID. 7663 * 7664 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by 7665 * the 8051, then manually overwritten to remap the ports to work with the 7666 * new DACs. 7667 * 7668 * Currently known portID's: 7669 * 0x00-0x1f: HDA audio stream input/output ports. 7670 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to 7671 * have the lower-nibble set to 0x1, 0x2, and 0x9. 7672 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. 7673 * 0xe0-0xff: DAC/ADC audio input/output ports. 7674 * 7675 * Currently known streamID's: 7676 * 0x03: Mic1 ADC to DSP. 7677 * 0x04: Mic2 ADC to DSP. 7678 * 0x05: HDA node 0x02 audio stream to DSP. 7679 * 0x0f: DSP Mic exit to HDA node 0x07. 7680 * 0x0c: DSP processed audio to DACs. 7681 * 0x14: DAC0, front L/R. 7682 * 7683 * It is possible to route the HDA audio streams directly to the DAC and 7684 * bypass the DSP entirely, with the only downside being that since the DSP 7685 * does volume control, the only volume control you'll get is through PCM on 7686 * the PC side, in the same way volume is handled for optical out. This may be 7687 * useful for debugging. 7688 */ 7689 static void chipio_remap_stream(struct hda_codec *codec, 7690 const struct chipio_stream_remap_data *remap_data) 7691 { 7692 unsigned int i, stream_offset; 7693 7694 /* Get the starting port for the stream to be remapped. */ 7695 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7696 &stream_offset); 7697 7698 /* 7699 * Check if the stream's port value is 0xff, because the 8051 may not 7700 * have gotten around to setting up the stream yet. Wait until it's 7701 * setup to remap it's ports. 7702 */ 7703 if (stream_offset == 0xff) { 7704 for (i = 0; i < 5; i++) { 7705 msleep(25); 7706 7707 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7708 &stream_offset); 7709 7710 if (stream_offset != 0xff) 7711 break; 7712 } 7713 } 7714 7715 if (stream_offset == 0xff) { 7716 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", 7717 __func__, remap_data->stream_id); 7718 return; 7719 } 7720 7721 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ 7722 stream_offset *= 0x04; 7723 stream_offset += 0x190000; 7724 7725 for (i = 0; i < remap_data->count; i++) { 7726 chipio_write_no_mutex(codec, 7727 stream_offset + remap_data->offset[i], 7728 remap_data->value[i]); 7729 } 7730 7731 /* Update stream map configuration. */ 7732 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7733 } 7734 7735 /* 7736 * Default speaker tuning values setup for alternative codecs. 7737 */ 7738 static const unsigned int sbz_default_delay_values[] = { 7739 /* Non-zero values are floating point 0.000198. */ 7740 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7741 }; 7742 7743 static const unsigned int zxr_default_delay_values[] = { 7744 /* Non-zero values are floating point 0.000220. */ 7745 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7746 }; 7747 7748 static const unsigned int ae5_default_delay_values[] = { 7749 /* Non-zero values are floating point 0.000100. */ 7750 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7751 }; 7752 7753 /* 7754 * If we never change these, probably only need them on initialization. 7755 */ 7756 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7757 { 7758 struct ca0132_spec *spec = codec->spec; 7759 unsigned int i, tmp, start_req, end_req; 7760 const unsigned int *values; 7761 7762 switch (ca0132_quirk(spec)) { 7763 case QUIRK_SBZ: 7764 values = sbz_default_delay_values; 7765 break; 7766 case QUIRK_ZXR: 7767 values = zxr_default_delay_values; 7768 break; 7769 case QUIRK_AE5: 7770 case QUIRK_AE7: 7771 values = ae5_default_delay_values; 7772 break; 7773 default: 7774 values = sbz_default_delay_values; 7775 break; 7776 } 7777 7778 tmp = FLOAT_ZERO; 7779 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7780 7781 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7782 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7783 for (i = start_req; i < end_req + 1; i++) 7784 dspio_set_uint_param(codec, 0x96, i, tmp); 7785 7786 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7787 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7788 for (i = start_req; i < end_req + 1; i++) 7789 dspio_set_uint_param(codec, 0x96, i, tmp); 7790 7791 7792 for (i = 0; i < 6; i++) 7793 dspio_set_uint_param(codec, 0x96, 7794 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7795 } 7796 7797 /* 7798 * Initialize mic for non-chromebook ca0132 implementations. 7799 */ 7800 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7801 { 7802 struct ca0132_spec *spec = codec->spec; 7803 unsigned int tmp; 7804 7805 /* Mic 1 Setup */ 7806 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7807 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7808 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7809 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7810 tmp = FLOAT_ONE; 7811 } else 7812 tmp = FLOAT_THREE; 7813 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7814 7815 /* Mic 2 setup (not present on desktop cards) */ 7816 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7817 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7818 if (ca0132_quirk(spec) == QUIRK_R3DI) 7819 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7820 tmp = FLOAT_ZERO; 7821 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7822 } 7823 7824 /* 7825 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7826 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7827 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7828 * having an updated DAC, which changes the destination to that DAC. 7829 */ 7830 static void sbz_connect_streams(struct hda_codec *codec) 7831 { 7832 struct ca0132_spec *spec = codec->spec; 7833 7834 mutex_lock(&spec->chipio_mutex); 7835 7836 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7837 7838 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7839 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7840 7841 /* Setup stream 0x14 with it's source and destination points */ 7842 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7843 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7844 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7845 chipio_set_stream_channels(codec, 0x14, 2); 7846 chipio_set_stream_control(codec, 0x14, 1); 7847 7848 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7849 7850 mutex_unlock(&spec->chipio_mutex); 7851 } 7852 7853 /* 7854 * Write data through ChipIO to setup proper stream destinations. 7855 * Not sure how it exactly works, but it seems to direct data 7856 * to different destinations. Example is f8 to c0, e0 to c0. 7857 * All I know is, if you don't set these, you get no sound. 7858 */ 7859 static void sbz_chipio_startup_data(struct hda_codec *codec) 7860 { 7861 const struct chipio_stream_remap_data *dsp_out_remap_data; 7862 struct ca0132_spec *spec = codec->spec; 7863 7864 mutex_lock(&spec->chipio_mutex); 7865 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7866 7867 /* Remap DAC0's output ports. */ 7868 chipio_remap_stream(codec, &stream_remap_data[0]); 7869 7870 /* Remap DSP audio output stream ports. */ 7871 switch (ca0132_quirk(spec)) { 7872 case QUIRK_SBZ: 7873 dsp_out_remap_data = &stream_remap_data[1]; 7874 break; 7875 7876 case QUIRK_ZXR: 7877 dsp_out_remap_data = &stream_remap_data[2]; 7878 break; 7879 7880 default: 7881 dsp_out_remap_data = NULL; 7882 break; 7883 } 7884 7885 if (dsp_out_remap_data) 7886 chipio_remap_stream(codec, dsp_out_remap_data); 7887 7888 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7889 mutex_unlock(&spec->chipio_mutex); 7890 } 7891 7892 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7893 { 7894 struct ca0132_spec *spec = codec->spec; 7895 unsigned int tmp; 7896 7897 chipio_set_stream_control(codec, 0x03, 0); 7898 chipio_set_stream_control(codec, 0x04, 0); 7899 7900 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7901 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7902 7903 tmp = FLOAT_THREE; 7904 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7905 7906 chipio_set_stream_control(codec, 0x03, 1); 7907 chipio_set_stream_control(codec, 0x04, 1); 7908 7909 switch (ca0132_quirk(spec)) { 7910 case QUIRK_SBZ: 7911 chipio_write(codec, 0x18b098, 0x0000000c); 7912 chipio_write(codec, 0x18b09C, 0x0000000c); 7913 break; 7914 case QUIRK_AE5: 7915 chipio_write(codec, 0x18b098, 0x0000000c); 7916 chipio_write(codec, 0x18b09c, 0x0000004c); 7917 break; 7918 default: 7919 break; 7920 } 7921 } 7922 7923 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7924 { 7925 struct ca0132_spec *spec = codec->spec; 7926 7927 chipio_8051_write_direct(codec, 0x93, 0x10); 7928 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 7929 7930 writeb(0xff, spec->mem_base + 0x304); 7931 writeb(0xff, spec->mem_base + 0x304); 7932 writeb(0xff, spec->mem_base + 0x304); 7933 writeb(0xff, spec->mem_base + 0x304); 7934 writeb(0x00, spec->mem_base + 0x100); 7935 writeb(0xff, spec->mem_base + 0x304); 7936 writeb(0x00, spec->mem_base + 0x100); 7937 writeb(0xff, spec->mem_base + 0x304); 7938 writeb(0x00, spec->mem_base + 0x100); 7939 writeb(0xff, spec->mem_base + 0x304); 7940 writeb(0x00, spec->mem_base + 0x100); 7941 writeb(0xff, spec->mem_base + 0x304); 7942 7943 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7944 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7945 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7946 } 7947 7948 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7949 { 7950 /* 7951 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7952 * which seems to be 'multichannel'. This is also mentioned in the 7953 * AE-5's registry values in Windows. 7954 */ 7955 chipio_set_control_param(codec, 3, 0); 7956 /* 7957 * I believe ASI is 'audio serial interface' and that it's used to 7958 * change colors on the external LED strip connected to the AE-5. 7959 */ 7960 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7961 7962 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7963 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7964 7965 chipio_8051_write_exram(codec, 0xfa92, 0x22); 7966 } 7967 7968 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7969 { 7970 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 7971 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); 7972 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); 7973 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 7974 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); 7975 } 7976 7977 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7978 { 7979 struct ca0132_spec *spec = codec->spec; 7980 7981 mutex_lock(&spec->chipio_mutex); 7982 7983 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7984 7985 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7986 7987 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7988 7989 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7990 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7991 chipio_set_stream_channels(codec, 0x18, 6); 7992 chipio_set_stream_control(codec, 0x18, 1); 7993 7994 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7995 7996 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 7997 7998 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7999 8000 mutex_unlock(&spec->chipio_mutex); 8001 } 8002 8003 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 8004 { 8005 struct ca0132_spec *spec = codec->spec; 8006 8007 mutex_lock(&spec->chipio_mutex); 8008 8009 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8010 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8011 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8012 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8013 8014 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8015 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8016 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 8017 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 8018 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 8019 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8020 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8021 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8022 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8023 ca0113_mmio_gpio_set(codec, 0, true); 8024 ca0113_mmio_gpio_set(codec, 1, true); 8025 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 8026 8027 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 8028 8029 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8030 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8031 8032 mutex_unlock(&spec->chipio_mutex); 8033 } 8034 8035 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 8036 { 8037 struct ca0132_spec *spec = codec->spec; 8038 8039 mutex_lock(&spec->chipio_mutex); 8040 8041 /* Seems to share the same port remapping as the SBZ. */ 8042 chipio_remap_stream(codec, &stream_remap_data[1]); 8043 8044 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8045 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 8046 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 8047 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 8048 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 8049 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 8050 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 8051 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 8052 8053 mutex_unlock(&spec->chipio_mutex); 8054 } 8055 8056 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 8057 { 8058 struct ca0132_spec *spec = codec->spec; 8059 8060 mutex_lock(&spec->chipio_mutex); 8061 8062 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 8063 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8064 8065 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 8066 8067 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8068 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8069 8070 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8071 chipio_set_stream_channels(codec, 0x18, 6); 8072 chipio_set_stream_control(codec, 0x18, 1); 8073 8074 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8075 8076 mutex_unlock(&spec->chipio_mutex); 8077 } 8078 8079 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 8080 { 8081 static const unsigned int addr[] = { 8082 0x41, 0x45, 0x40, 0x43, 0x51 8083 }; 8084 static const unsigned int data[] = { 8085 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 8086 }; 8087 unsigned int i; 8088 8089 for (i = 0; i < ARRAY_SIZE(addr); i++) 8090 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); 8091 } 8092 8093 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 8094 { 8095 struct ca0132_spec *spec = codec->spec; 8096 static const unsigned int target[] = { 8097 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 8098 }; 8099 static const unsigned int data[] = { 8100 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 8101 }; 8102 unsigned int i; 8103 8104 mutex_lock(&spec->chipio_mutex); 8105 8106 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8107 8108 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8109 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8110 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8111 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8112 8113 ae7_post_dsp_pll_setup(codec); 8114 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8115 8116 for (i = 0; i < ARRAY_SIZE(target); i++) 8117 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 8118 8119 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8120 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8121 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8122 8123 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 8124 chipio_set_stream_channels(codec, 0x21, 2); 8125 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 8126 8127 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 8128 /* 8129 * In the 8051's memory, this param is referred to as 'n2sid', which I 8130 * believe is 'node to streamID'. It seems to be a way to assign a 8131 * stream to a given HDA node. 8132 */ 8133 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 8134 8135 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 8136 8137 /* 8138 * Now, at this point on Windows, an actual stream is setup and 8139 * seemingly sends data to the HDA node 0x09, which is the digital 8140 * audio input node. This is left out here, because obviously I don't 8141 * know what data is being sent. Interestingly, the AE-5 seems to go 8142 * through the motions of getting here and never actually takes this 8143 * step, but the AE-7 does. 8144 */ 8145 8146 ca0113_mmio_gpio_set(codec, 0, 1); 8147 ca0113_mmio_gpio_set(codec, 1, 1); 8148 8149 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8150 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 8151 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8152 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8153 8154 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8155 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8156 8157 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8158 chipio_set_stream_channels(codec, 0x18, 6); 8159 8160 /* 8161 * Runs again, this has been repeated a few times, but I'm just 8162 * following what the Windows driver does. 8163 */ 8164 ae7_post_dsp_pll_setup(codec); 8165 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8166 8167 mutex_unlock(&spec->chipio_mutex); 8168 } 8169 8170 /* 8171 * The Windows driver has commands that seem to setup ASI, which I believe to 8172 * be some sort of audio serial interface. My current speculation is that it's 8173 * related to communicating with the new DAC. 8174 */ 8175 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8176 { 8177 chipio_8051_write_direct(codec, 0x93, 0x10); 8178 8179 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 8180 8181 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8182 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8183 8184 chipio_set_control_param(codec, 3, 3); 8185 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8186 8187 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8188 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8189 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8190 8191 chipio_8051_write_exram(codec, 0xfa92, 0x22); 8192 8193 ae7_post_dsp_pll_setup(codec); 8194 ae7_post_dsp_asi_stream_setup(codec); 8195 8196 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 8197 8198 ae7_post_dsp_asi_setup_ports(codec); 8199 } 8200 8201 /* 8202 * Setup default parameters for DSP 8203 */ 8204 static void ca0132_setup_defaults(struct hda_codec *codec) 8205 { 8206 struct ca0132_spec *spec = codec->spec; 8207 unsigned int tmp; 8208 int num_fx; 8209 int idx, i; 8210 8211 if (spec->dsp_state != DSP_DOWNLOADED) 8212 return; 8213 8214 /* out, in effects + voicefx */ 8215 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8216 for (idx = 0; idx < num_fx; idx++) { 8217 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8218 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8219 ca0132_effects[idx].reqs[i], 8220 ca0132_effects[idx].def_vals[i]); 8221 } 8222 } 8223 8224 /*remove DSP headroom*/ 8225 tmp = FLOAT_ZERO; 8226 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8227 8228 /*set speaker EQ bypass attenuation*/ 8229 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8230 8231 /* set AMic1 and AMic2 as mono mic */ 8232 tmp = FLOAT_ONE; 8233 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8234 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8235 8236 /* set AMic1 as CrystalVoice input */ 8237 tmp = FLOAT_ONE; 8238 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8239 8240 /* set WUH source */ 8241 tmp = FLOAT_TWO; 8242 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8243 } 8244 8245 /* 8246 * Setup default parameters for Recon3D/Recon3Di DSP. 8247 */ 8248 8249 static void r3d_setup_defaults(struct hda_codec *codec) 8250 { 8251 struct ca0132_spec *spec = codec->spec; 8252 unsigned int tmp; 8253 int num_fx; 8254 int idx, i; 8255 8256 if (spec->dsp_state != DSP_DOWNLOADED) 8257 return; 8258 8259 ca0132_alt_init_analog_mics(codec); 8260 ca0132_alt_start_dsp_audio_streams(codec); 8261 8262 /*remove DSP headroom*/ 8263 tmp = FLOAT_ZERO; 8264 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8265 8266 /* set WUH source */ 8267 tmp = FLOAT_TWO; 8268 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8269 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8270 8271 /* Set speaker source? */ 8272 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8273 8274 if (ca0132_quirk(spec) == QUIRK_R3DI) 8275 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8276 8277 /* Disable mute on Center/LFE. */ 8278 if (ca0132_quirk(spec) == QUIRK_R3D) { 8279 ca0113_mmio_gpio_set(codec, 2, false); 8280 ca0113_mmio_gpio_set(codec, 4, true); 8281 } 8282 8283 /* Setup effect defaults */ 8284 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8285 for (idx = 0; idx < num_fx; idx++) { 8286 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8287 dspio_set_uint_param(codec, 8288 ca0132_effects[idx].mid, 8289 ca0132_effects[idx].reqs[i], 8290 ca0132_effects[idx].def_vals[i]); 8291 } 8292 } 8293 } 8294 8295 /* 8296 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8297 * than the Chromebook setup. 8298 */ 8299 static void sbz_setup_defaults(struct hda_codec *codec) 8300 { 8301 struct ca0132_spec *spec = codec->spec; 8302 unsigned int tmp; 8303 int num_fx; 8304 int idx, i; 8305 8306 if (spec->dsp_state != DSP_DOWNLOADED) 8307 return; 8308 8309 ca0132_alt_init_analog_mics(codec); 8310 ca0132_alt_start_dsp_audio_streams(codec); 8311 sbz_connect_streams(codec); 8312 sbz_chipio_startup_data(codec); 8313 8314 /* 8315 * Sets internal input loopback to off, used to have a switch to 8316 * enable input loopback, but turned out to be way too buggy. 8317 */ 8318 tmp = FLOAT_ONE; 8319 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8320 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8321 8322 /*remove DSP headroom*/ 8323 tmp = FLOAT_ZERO; 8324 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8325 8326 /* set WUH source */ 8327 tmp = FLOAT_TWO; 8328 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8329 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8330 8331 /* Set speaker source? */ 8332 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8333 8334 ca0132_alt_dsp_initial_mic_setup(codec); 8335 8336 /* out, in effects + voicefx */ 8337 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8338 for (idx = 0; idx < num_fx; idx++) { 8339 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8340 dspio_set_uint_param(codec, 8341 ca0132_effects[idx].mid, 8342 ca0132_effects[idx].reqs[i], 8343 ca0132_effects[idx].def_vals[i]); 8344 } 8345 } 8346 8347 ca0132_alt_init_speaker_tuning(codec); 8348 } 8349 8350 /* 8351 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8352 */ 8353 static void ae5_setup_defaults(struct hda_codec *codec) 8354 { 8355 struct ca0132_spec *spec = codec->spec; 8356 unsigned int tmp; 8357 int num_fx; 8358 int idx, i; 8359 8360 if (spec->dsp_state != DSP_DOWNLOADED) 8361 return; 8362 8363 ca0132_alt_init_analog_mics(codec); 8364 ca0132_alt_start_dsp_audio_streams(codec); 8365 8366 /* New, unknown SCP req's */ 8367 tmp = FLOAT_ZERO; 8368 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8369 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8370 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8371 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8372 8373 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8374 ca0113_mmio_gpio_set(codec, 0, false); 8375 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8376 8377 /* Internal loopback off */ 8378 tmp = FLOAT_ONE; 8379 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8380 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8381 8382 /*remove DSP headroom*/ 8383 tmp = FLOAT_ZERO; 8384 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8385 8386 /* set WUH source */ 8387 tmp = FLOAT_TWO; 8388 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8389 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8390 8391 /* Set speaker source? */ 8392 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8393 8394 ca0132_alt_dsp_initial_mic_setup(codec); 8395 ae5_post_dsp_register_set(codec); 8396 ae5_post_dsp_param_setup(codec); 8397 ae5_post_dsp_pll_setup(codec); 8398 ae5_post_dsp_stream_setup(codec); 8399 ae5_post_dsp_startup_data(codec); 8400 8401 /* out, in effects + voicefx */ 8402 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8403 for (idx = 0; idx < num_fx; idx++) { 8404 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8405 dspio_set_uint_param(codec, 8406 ca0132_effects[idx].mid, 8407 ca0132_effects[idx].reqs[i], 8408 ca0132_effects[idx].def_vals[i]); 8409 } 8410 } 8411 8412 ca0132_alt_init_speaker_tuning(codec); 8413 } 8414 8415 /* 8416 * Setup default parameters for the Sound Blaster AE-7 DSP. 8417 */ 8418 static void ae7_setup_defaults(struct hda_codec *codec) 8419 { 8420 struct ca0132_spec *spec = codec->spec; 8421 unsigned int tmp; 8422 int num_fx; 8423 int idx, i; 8424 8425 if (spec->dsp_state != DSP_DOWNLOADED) 8426 return; 8427 8428 ca0132_alt_init_analog_mics(codec); 8429 ca0132_alt_start_dsp_audio_streams(codec); 8430 ae7_post_dsp_setup_ports(codec); 8431 8432 tmp = FLOAT_ZERO; 8433 dspio_set_uint_param(codec, 0x96, 8434 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8435 dspio_set_uint_param(codec, 0x96, 8436 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8437 8438 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8439 8440 /* New, unknown SCP req's */ 8441 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8442 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8443 8444 ca0113_mmio_gpio_set(codec, 0, false); 8445 8446 /* Internal loopback off */ 8447 tmp = FLOAT_ONE; 8448 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8449 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8450 8451 /*remove DSP headroom*/ 8452 tmp = FLOAT_ZERO; 8453 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8454 8455 /* set WUH source */ 8456 tmp = FLOAT_TWO; 8457 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8458 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8459 8460 /* Set speaker source? */ 8461 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8462 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8463 8464 /* 8465 * This is the second time we've called this, but this is seemingly 8466 * what Windows does. 8467 */ 8468 ca0132_alt_init_analog_mics(codec); 8469 8470 ae7_post_dsp_asi_setup(codec); 8471 8472 /* 8473 * Not sure why, but these are both set to 1. They're only set to 0 8474 * upon shutdown. 8475 */ 8476 ca0113_mmio_gpio_set(codec, 0, true); 8477 ca0113_mmio_gpio_set(codec, 1, true); 8478 8479 /* Volume control related. */ 8480 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8481 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8482 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8483 8484 /* out, in effects + voicefx */ 8485 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8486 for (idx = 0; idx < num_fx; idx++) { 8487 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8488 dspio_set_uint_param(codec, 8489 ca0132_effects[idx].mid, 8490 ca0132_effects[idx].reqs[i], 8491 ca0132_effects[idx].def_vals[i]); 8492 } 8493 } 8494 8495 ca0132_alt_init_speaker_tuning(codec); 8496 } 8497 8498 /* 8499 * Initialization of flags in chip 8500 */ 8501 static void ca0132_init_flags(struct hda_codec *codec) 8502 { 8503 struct ca0132_spec *spec = codec->spec; 8504 8505 if (ca0132_use_alt_functions(spec)) { 8506 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8507 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8508 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8509 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8510 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8511 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8512 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8513 chipio_set_control_flag(codec, 8514 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8515 chipio_set_control_flag(codec, 8516 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8517 } else { 8518 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8519 chipio_set_control_flag(codec, 8520 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8521 chipio_set_control_flag(codec, 8522 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8523 chipio_set_control_flag(codec, 8524 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8525 chipio_set_control_flag(codec, 8526 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8527 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8528 } 8529 } 8530 8531 /* 8532 * Initialization of parameters in chip 8533 */ 8534 static void ca0132_init_params(struct hda_codec *codec) 8535 { 8536 struct ca0132_spec *spec = codec->spec; 8537 8538 if (ca0132_use_alt_functions(spec)) { 8539 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8540 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8541 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8542 chipio_set_control_param(codec, 0, 0); 8543 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8544 } 8545 8546 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8547 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8548 } 8549 8550 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8551 { 8552 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8553 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8554 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8555 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8556 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8557 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8558 8559 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8560 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8561 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8562 } 8563 8564 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8565 { 8566 bool dsp_loaded = false; 8567 struct ca0132_spec *spec = codec->spec; 8568 const struct dsp_image_seg *dsp_os_image; 8569 const struct firmware *fw_entry = NULL; 8570 /* 8571 * Alternate firmwares for different variants. The Recon3Di apparently 8572 * can use the default firmware, but I'll leave the option in case 8573 * it needs it again. 8574 */ 8575 switch (ca0132_quirk(spec)) { 8576 case QUIRK_SBZ: 8577 case QUIRK_R3D: 8578 case QUIRK_AE5: 8579 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8580 codec->card->dev) != 0) 8581 codec_dbg(codec, "Desktop firmware not found."); 8582 else 8583 codec_dbg(codec, "Desktop firmware selected."); 8584 break; 8585 case QUIRK_R3DI: 8586 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8587 codec->card->dev) != 0) 8588 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8589 else 8590 codec_dbg(codec, "Recon3Di firmware selected."); 8591 break; 8592 default: 8593 break; 8594 } 8595 /* 8596 * Use default ctefx.bin if no alt firmware is detected, or if none 8597 * exists for your particular codec. 8598 */ 8599 if (!fw_entry) { 8600 codec_dbg(codec, "Default firmware selected."); 8601 if (request_firmware(&fw_entry, EFX_FILE, 8602 codec->card->dev) != 0) 8603 return false; 8604 } 8605 8606 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8607 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8608 codec_err(codec, "ca0132 DSP load image failed\n"); 8609 goto exit_download; 8610 } 8611 8612 dsp_loaded = dspload_wait_loaded(codec); 8613 8614 exit_download: 8615 release_firmware(fw_entry); 8616 8617 return dsp_loaded; 8618 } 8619 8620 static void ca0132_download_dsp(struct hda_codec *codec) 8621 { 8622 struct ca0132_spec *spec = codec->spec; 8623 8624 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8625 return; /* NOP */ 8626 #endif 8627 8628 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8629 return; /* don't retry failures */ 8630 8631 chipio_enable_clocks(codec); 8632 if (spec->dsp_state != DSP_DOWNLOADED) { 8633 spec->dsp_state = DSP_DOWNLOADING; 8634 8635 if (!ca0132_download_dsp_images(codec)) 8636 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8637 else 8638 spec->dsp_state = DSP_DOWNLOADED; 8639 } 8640 8641 /* For codecs using alt functions, this is already done earlier */ 8642 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8643 ca0132_set_dsp_msr(codec, true); 8644 } 8645 8646 static void ca0132_process_dsp_response(struct hda_codec *codec, 8647 struct hda_jack_callback *callback) 8648 { 8649 struct ca0132_spec *spec = codec->spec; 8650 8651 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8652 snd_hda_power_up_pm(codec); 8653 if (spec->wait_scp) { 8654 if (dspio_get_response_data(codec) >= 0) 8655 spec->wait_scp = 0; 8656 } 8657 8658 dspio_clear_response_queue(codec); 8659 snd_hda_power_down_pm(codec); 8660 } 8661 8662 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8663 { 8664 struct ca0132_spec *spec = codec->spec; 8665 struct hda_jack_tbl *tbl; 8666 8667 /* Delay enabling the HP amp, to let the mic-detection 8668 * state machine run. 8669 */ 8670 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8671 if (tbl) 8672 tbl->block_report = 1; 8673 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8674 } 8675 8676 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8677 { 8678 struct ca0132_spec *spec = codec->spec; 8679 8680 if (ca0132_use_alt_functions(spec)) 8681 ca0132_alt_select_in(codec); 8682 else 8683 ca0132_select_mic(codec); 8684 } 8685 8686 static void ca0132_setup_unsol(struct hda_codec *codec) 8687 { 8688 struct ca0132_spec *spec = codec->spec; 8689 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8690 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8691 amic_callback); 8692 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8693 ca0132_process_dsp_response); 8694 /* Front headphone jack detection */ 8695 if (ca0132_use_alt_functions(spec)) 8696 snd_hda_jack_detect_enable_callback(codec, 8697 spec->unsol_tag_front_hp, hp_callback); 8698 } 8699 8700 /* 8701 * Verbs tables. 8702 */ 8703 8704 /* Sends before DSP download. */ 8705 static const struct hda_verb ca0132_base_init_verbs[] = { 8706 /*enable ct extension*/ 8707 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8708 {} 8709 }; 8710 8711 /* Send at exit. */ 8712 static const struct hda_verb ca0132_base_exit_verbs[] = { 8713 /*set afg to D3*/ 8714 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8715 /*disable ct extension*/ 8716 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8717 {} 8718 }; 8719 8720 /* Other verbs tables. Sends after DSP download. */ 8721 8722 static const struct hda_verb ca0132_init_verbs0[] = { 8723 /* chip init verbs */ 8724 {0x15, 0x70D, 0xF0}, 8725 {0x15, 0x70E, 0xFE}, 8726 {0x15, 0x707, 0x75}, 8727 {0x15, 0x707, 0xD3}, 8728 {0x15, 0x707, 0x09}, 8729 {0x15, 0x707, 0x53}, 8730 {0x15, 0x707, 0xD4}, 8731 {0x15, 0x707, 0xEF}, 8732 {0x15, 0x707, 0x75}, 8733 {0x15, 0x707, 0xD3}, 8734 {0x15, 0x707, 0x09}, 8735 {0x15, 0x707, 0x02}, 8736 {0x15, 0x707, 0x37}, 8737 {0x15, 0x707, 0x78}, 8738 {0x15, 0x53C, 0xCE}, 8739 {0x15, 0x575, 0xC9}, 8740 {0x15, 0x53D, 0xCE}, 8741 {0x15, 0x5B7, 0xC9}, 8742 {0x15, 0x70D, 0xE8}, 8743 {0x15, 0x70E, 0xFE}, 8744 {0x15, 0x707, 0x02}, 8745 {0x15, 0x707, 0x68}, 8746 {0x15, 0x707, 0x62}, 8747 {0x15, 0x53A, 0xCE}, 8748 {0x15, 0x546, 0xC9}, 8749 {0x15, 0x53B, 0xCE}, 8750 {0x15, 0x5E8, 0xC9}, 8751 {} 8752 }; 8753 8754 /* Extra init verbs for desktop cards. */ 8755 static const struct hda_verb ca0132_init_verbs1[] = { 8756 {0x15, 0x70D, 0x20}, 8757 {0x15, 0x70E, 0x19}, 8758 {0x15, 0x707, 0x00}, 8759 {0x15, 0x539, 0xCE}, 8760 {0x15, 0x546, 0xC9}, 8761 {0x15, 0x70D, 0xB7}, 8762 {0x15, 0x70E, 0x09}, 8763 {0x15, 0x707, 0x10}, 8764 {0x15, 0x70D, 0xAF}, 8765 {0x15, 0x70E, 0x09}, 8766 {0x15, 0x707, 0x01}, 8767 {0x15, 0x707, 0x05}, 8768 {0x15, 0x70D, 0x73}, 8769 {0x15, 0x70E, 0x09}, 8770 {0x15, 0x707, 0x14}, 8771 {0x15, 0x6FF, 0xC4}, 8772 {} 8773 }; 8774 8775 static void ca0132_init_chip(struct hda_codec *codec) 8776 { 8777 struct ca0132_spec *spec = codec->spec; 8778 int num_fx; 8779 int i; 8780 unsigned int on; 8781 8782 mutex_init(&spec->chipio_mutex); 8783 8784 /* 8785 * The Windows driver always does this upon startup, which seems to 8786 * clear out any previous configuration. This should help issues where 8787 * a boot into Windows prior to a boot into Linux breaks things. Also, 8788 * Windows always sends the reset twice. 8789 */ 8790 if (ca0132_use_alt_functions(spec)) { 8791 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8792 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); 8793 8794 snd_hda_codec_write(codec, codec->core.afg, 0, 8795 AC_VERB_SET_CODEC_RESET, 0); 8796 snd_hda_codec_write(codec, codec->core.afg, 0, 8797 AC_VERB_SET_CODEC_RESET, 0); 8798 } 8799 8800 spec->cur_out_type = SPEAKER_OUT; 8801 if (!ca0132_use_alt_functions(spec)) 8802 spec->cur_mic_type = DIGITAL_MIC; 8803 else 8804 spec->cur_mic_type = REAR_MIC; 8805 8806 spec->cur_mic_boost = 0; 8807 8808 for (i = 0; i < VNODES_COUNT; i++) { 8809 spec->vnode_lvol[i] = 0x5a; 8810 spec->vnode_rvol[i] = 0x5a; 8811 spec->vnode_lswitch[i] = 0; 8812 spec->vnode_rswitch[i] = 0; 8813 } 8814 8815 /* 8816 * Default states for effects are in ca0132_effects[]. 8817 */ 8818 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8819 for (i = 0; i < num_fx; i++) { 8820 on = (unsigned int)ca0132_effects[i].reqs[0]; 8821 spec->effects_switch[i] = on ? 1 : 0; 8822 } 8823 /* 8824 * Sets defaults for the effect slider controls, only for alternative 8825 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8826 */ 8827 if (ca0132_use_alt_controls(spec)) { 8828 /* Set speakers to default to full range. */ 8829 spec->speaker_range_val[0] = 1; 8830 spec->speaker_range_val[1] = 1; 8831 8832 spec->xbass_xover_freq = 8; 8833 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8834 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8835 8836 spec->bass_redirect_xover_freq = 8; 8837 } 8838 8839 spec->voicefx_val = 0; 8840 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8841 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8842 8843 /* 8844 * The ZxR doesn't have a front panel header, and it's line-in is on 8845 * the daughter board. So, there is no input enum control, and we need 8846 * to make sure that spec->in_enum_val is set properly. 8847 */ 8848 if (ca0132_quirk(spec) == QUIRK_ZXR) 8849 spec->in_enum_val = REAR_MIC; 8850 8851 #ifdef ENABLE_TUNING_CONTROLS 8852 ca0132_init_tuning_defaults(codec); 8853 #endif 8854 } 8855 8856 /* 8857 * Recon3Di exit specific commands. 8858 */ 8859 /* prevents popping noise on shutdown */ 8860 static void r3di_gpio_shutdown(struct hda_codec *codec) 8861 { 8862 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8863 } 8864 8865 /* 8866 * Sound Blaster Z exit specific commands. 8867 */ 8868 static void sbz_region2_exit(struct hda_codec *codec) 8869 { 8870 struct ca0132_spec *spec = codec->spec; 8871 unsigned int i; 8872 8873 for (i = 0; i < 4; i++) 8874 writeb(0x0, spec->mem_base + 0x100); 8875 for (i = 0; i < 8; i++) 8876 writeb(0xb3, spec->mem_base + 0x304); 8877 8878 ca0113_mmio_gpio_set(codec, 0, false); 8879 ca0113_mmio_gpio_set(codec, 1, false); 8880 ca0113_mmio_gpio_set(codec, 4, true); 8881 ca0113_mmio_gpio_set(codec, 5, false); 8882 ca0113_mmio_gpio_set(codec, 7, false); 8883 } 8884 8885 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8886 { 8887 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8888 unsigned int i; 8889 8890 snd_hda_codec_write(codec, 0x11, 0, 8891 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8892 8893 for (i = 0; i < ARRAY_SIZE(pins); i++) 8894 snd_hda_codec_write(codec, pins[i], 0, 8895 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8896 } 8897 8898 static void ca0132_clear_unsolicited(struct hda_codec *codec) 8899 { 8900 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8901 unsigned int i; 8902 8903 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8904 snd_hda_codec_write(codec, pins[i], 0, 8905 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8906 } 8907 } 8908 8909 /* On shutdown, sends commands in sets of three */ 8910 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8911 int mask, int data) 8912 { 8913 if (dir >= 0) 8914 snd_hda_codec_write(codec, 0x01, 0, 8915 AC_VERB_SET_GPIO_DIRECTION, dir); 8916 if (mask >= 0) 8917 snd_hda_codec_write(codec, 0x01, 0, 8918 AC_VERB_SET_GPIO_MASK, mask); 8919 8920 if (data >= 0) 8921 snd_hda_codec_write(codec, 0x01, 0, 8922 AC_VERB_SET_GPIO_DATA, data); 8923 } 8924 8925 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8926 { 8927 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8928 unsigned int i; 8929 8930 for (i = 0; i < ARRAY_SIZE(pins); i++) 8931 snd_hda_codec_write(codec, pins[i], 0, 8932 AC_VERB_SET_POWER_STATE, 0x03); 8933 } 8934 8935 static void sbz_exit_chip(struct hda_codec *codec) 8936 { 8937 chipio_set_stream_control(codec, 0x03, 0); 8938 chipio_set_stream_control(codec, 0x04, 0); 8939 8940 /* Mess with GPIO */ 8941 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8942 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8943 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8944 8945 chipio_set_stream_control(codec, 0x14, 0); 8946 chipio_set_stream_control(codec, 0x0C, 0); 8947 8948 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8949 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8950 8951 chipio_write(codec, 0x18a020, 0x00000083); 8952 8953 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8954 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8955 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8956 8957 chipio_set_stream_control(codec, 0x0C, 0); 8958 8959 chipio_set_control_param(codec, 0x0D, 0x24); 8960 8961 ca0132_clear_unsolicited(codec); 8962 sbz_set_pin_ctl_default(codec); 8963 8964 snd_hda_codec_write(codec, 0x0B, 0, 8965 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8966 8967 sbz_region2_exit(codec); 8968 } 8969 8970 static void r3d_exit_chip(struct hda_codec *codec) 8971 { 8972 ca0132_clear_unsolicited(codec); 8973 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8974 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8975 } 8976 8977 static void ae5_exit_chip(struct hda_codec *codec) 8978 { 8979 chipio_set_stream_control(codec, 0x03, 0); 8980 chipio_set_stream_control(codec, 0x04, 0); 8981 8982 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8983 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8984 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8985 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8986 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8987 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 8988 ca0113_mmio_gpio_set(codec, 0, false); 8989 ca0113_mmio_gpio_set(codec, 1, false); 8990 8991 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8992 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8993 8994 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8995 8996 chipio_set_stream_control(codec, 0x18, 0); 8997 chipio_set_stream_control(codec, 0x0c, 0); 8998 8999 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 9000 } 9001 9002 static void ae7_exit_chip(struct hda_codec *codec) 9003 { 9004 chipio_set_stream_control(codec, 0x18, 0); 9005 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 9006 chipio_set_stream_channels(codec, 0x21, 0); 9007 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 9008 chipio_set_control_param(codec, 0x20, 0x01); 9009 9010 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9011 9012 chipio_set_stream_control(codec, 0x18, 0); 9013 chipio_set_stream_control(codec, 0x0c, 0); 9014 9015 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 9016 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 9017 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9018 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 9019 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 9020 ca0113_mmio_gpio_set(codec, 0, false); 9021 ca0113_mmio_gpio_set(codec, 1, false); 9022 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9023 9024 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9025 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9026 } 9027 9028 static void zxr_exit_chip(struct hda_codec *codec) 9029 { 9030 chipio_set_stream_control(codec, 0x03, 0); 9031 chipio_set_stream_control(codec, 0x04, 0); 9032 chipio_set_stream_control(codec, 0x14, 0); 9033 chipio_set_stream_control(codec, 0x0C, 0); 9034 9035 chipio_set_conn_rate(codec, 0x41, SR_192_000); 9036 chipio_set_conn_rate(codec, 0x91, SR_192_000); 9037 9038 chipio_write(codec, 0x18a020, 0x00000083); 9039 9040 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9041 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9042 9043 ca0132_clear_unsolicited(codec); 9044 sbz_set_pin_ctl_default(codec); 9045 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 9046 9047 ca0113_mmio_gpio_set(codec, 5, false); 9048 ca0113_mmio_gpio_set(codec, 2, false); 9049 ca0113_mmio_gpio_set(codec, 3, false); 9050 ca0113_mmio_gpio_set(codec, 0, false); 9051 ca0113_mmio_gpio_set(codec, 4, true); 9052 ca0113_mmio_gpio_set(codec, 0, true); 9053 ca0113_mmio_gpio_set(codec, 5, true); 9054 ca0113_mmio_gpio_set(codec, 2, false); 9055 ca0113_mmio_gpio_set(codec, 3, false); 9056 } 9057 9058 static void ca0132_exit_chip(struct hda_codec *codec) 9059 { 9060 /* put any chip cleanup stuffs here. */ 9061 9062 if (dspload_is_loaded(codec)) 9063 dsp_reset(codec); 9064 } 9065 9066 /* 9067 * This fixes a problem that was hard to reproduce. Very rarely, I would 9068 * boot up, and there would be no sound, but the DSP indicated it had loaded 9069 * properly. I did a few memory dumps to see if anything was different, and 9070 * there were a few areas of memory uninitialized with a1a2a3a4. This function 9071 * checks if those areas are uninitialized, and if they are, it'll attempt to 9072 * reload the card 3 times. Usually it fixes by the second. 9073 */ 9074 static void sbz_dsp_startup_check(struct hda_codec *codec) 9075 { 9076 struct ca0132_spec *spec = codec->spec; 9077 unsigned int dsp_data_check[4]; 9078 unsigned int cur_address = 0x390; 9079 unsigned int i; 9080 unsigned int failure = 0; 9081 unsigned int reload = 3; 9082 9083 if (spec->startup_check_entered) 9084 return; 9085 9086 spec->startup_check_entered = true; 9087 9088 for (i = 0; i < 4; i++) { 9089 chipio_read(codec, cur_address, &dsp_data_check[i]); 9090 cur_address += 0x4; 9091 } 9092 for (i = 0; i < 4; i++) { 9093 if (dsp_data_check[i] == 0xa1a2a3a4) 9094 failure = 1; 9095 } 9096 9097 codec_dbg(codec, "Startup Check: %d ", failure); 9098 if (failure) 9099 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 9100 /* 9101 * While the failure condition is true, and we haven't reached our 9102 * three reload limit, continue trying to reload the driver and 9103 * fix the issue. 9104 */ 9105 while (failure && (reload != 0)) { 9106 codec_info(codec, "Reloading... Tries left: %d", reload); 9107 sbz_exit_chip(codec); 9108 spec->dsp_state = DSP_DOWNLOAD_INIT; 9109 codec->patch_ops.init(codec); 9110 failure = 0; 9111 for (i = 0; i < 4; i++) { 9112 chipio_read(codec, cur_address, &dsp_data_check[i]); 9113 cur_address += 0x4; 9114 } 9115 for (i = 0; i < 4; i++) { 9116 if (dsp_data_check[i] == 0xa1a2a3a4) 9117 failure = 1; 9118 } 9119 reload--; 9120 } 9121 9122 if (!failure && reload < 3) 9123 codec_info(codec, "DSP fixed."); 9124 9125 if (!failure) 9126 return; 9127 9128 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 9129 } 9130 9131 /* 9132 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 9133 * extra precision for decibel values. If you had the dB value in floating point 9134 * you would take the value after the decimal point, multiply by 64, and divide 9135 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 9136 * implement fixed point or floating point dB volumes. For now, I'll set them 9137 * to 0 just incase a value has lingered from a boot into Windows. 9138 */ 9139 static void ca0132_alt_vol_setup(struct hda_codec *codec) 9140 { 9141 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 9142 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 9143 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 9144 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 9145 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 9146 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 9147 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 9148 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 9149 } 9150 9151 /* 9152 * Extra commands that don't really fit anywhere else. 9153 */ 9154 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9155 { 9156 struct ca0132_spec *spec = codec->spec; 9157 9158 writel(0x00820680, spec->mem_base + 0x01C); 9159 writel(0x00820680, spec->mem_base + 0x01C); 9160 9161 chipio_write(codec, 0x18b0a4, 0x000000c2); 9162 9163 snd_hda_codec_write(codec, 0x11, 0, 9164 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9165 } 9166 9167 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9168 { 9169 chipio_write(codec, 0x18b0a4, 0x000000c2); 9170 9171 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9172 9173 snd_hda_codec_write(codec, 0x11, 0, 9174 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9175 } 9176 9177 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9178 { 9179 chipio_write(codec, 0x18b0a4, 0x000000c2); 9180 9181 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9182 chipio_8051_write_exram(codec, 0x1920, 0x00); 9183 chipio_8051_write_exram(codec, 0x1921, 0x40); 9184 9185 snd_hda_codec_write(codec, 0x11, 0, 9186 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9187 } 9188 9189 /* 9190 * The ZxR seems to use alternative DAC's for the surround channels, which 9191 * require PLL PMU setup for the clock rate, I'm guessing. Without setting 9192 * this up, we get no audio out of the surround jacks. 9193 */ 9194 static void zxr_pre_dsp_setup(struct hda_codec *codec) 9195 { 9196 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; 9197 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; 9198 unsigned int i; 9199 9200 chipio_write(codec, 0x189000, 0x0001f100); 9201 msleep(50); 9202 chipio_write(codec, 0x18900c, 0x0001f100); 9203 msleep(50); 9204 9205 /* 9206 * This writes a RET instruction at the entry point of the function at 9207 * 0xfa92 in exram. This function seems to have something to do with 9208 * ASI. Might be some way to prevent the card from reconfiguring the 9209 * ASI stuff itself. 9210 */ 9211 chipio_8051_write_exram(codec, 0xfa92, 0x22); 9212 9213 chipio_8051_write_pll_pmu(codec, 0x51, 0x98); 9214 9215 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); 9216 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); 9217 9218 chipio_write(codec, 0x18902c, 0x00000000); 9219 msleep(50); 9220 chipio_write(codec, 0x18902c, 0x00000003); 9221 msleep(50); 9222 9223 for (i = 0; i < ARRAY_SIZE(addr); i++) 9224 chipio_8051_write_pll_pmu(codec, addr[i], data[i]); 9225 } 9226 9227 /* 9228 * These are sent before the DSP is downloaded. Not sure 9229 * what they do, or if they're necessary. Could possibly 9230 * be removed. Figure they're better to leave in. 9231 */ 9232 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9233 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9234 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9235 }; 9236 9237 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9238 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9239 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9240 0x000000c1, 0x00000080 9241 }; 9242 9243 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9244 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9245 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9246 0x000000c1, 0x00000080 9247 }; 9248 9249 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9250 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9251 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9252 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9253 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9254 }; 9255 9256 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9257 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9258 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9259 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9260 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9261 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9262 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9263 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9264 0x00000080, 0x00880680 9265 }; 9266 9267 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9268 { 9269 struct ca0132_spec *spec = codec->spec; 9270 unsigned int tmp[2], i, count, cur_addr; 9271 const unsigned int *addr, *data; 9272 9273 addr = ca0113_mmio_init_address_sbz; 9274 for (i = 0; i < 3; i++) 9275 writel(0x00000000, spec->mem_base + addr[i]); 9276 9277 cur_addr = i; 9278 switch (ca0132_quirk(spec)) { 9279 case QUIRK_ZXR: 9280 tmp[0] = 0x00880480; 9281 tmp[1] = 0x00000080; 9282 break; 9283 case QUIRK_SBZ: 9284 tmp[0] = 0x00820680; 9285 tmp[1] = 0x00000083; 9286 break; 9287 case QUIRK_R3D: 9288 tmp[0] = 0x00880680; 9289 tmp[1] = 0x00000083; 9290 break; 9291 default: 9292 tmp[0] = 0x00000000; 9293 tmp[1] = 0x00000000; 9294 break; 9295 } 9296 9297 for (i = 0; i < 2; i++) 9298 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9299 9300 cur_addr += i; 9301 9302 switch (ca0132_quirk(spec)) { 9303 case QUIRK_ZXR: 9304 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9305 data = ca0113_mmio_init_data_zxr; 9306 break; 9307 default: 9308 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9309 data = ca0113_mmio_init_data_sbz; 9310 break; 9311 } 9312 9313 for (i = 0; i < count; i++) 9314 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9315 } 9316 9317 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9318 { 9319 struct ca0132_spec *spec = codec->spec; 9320 const unsigned int *addr, *data; 9321 unsigned int i, count; 9322 9323 addr = ca0113_mmio_init_address_ae5; 9324 data = ca0113_mmio_init_data_ae5; 9325 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9326 9327 if (ca0132_quirk(spec) == QUIRK_AE7) { 9328 writel(0x00000680, spec->mem_base + 0x1c); 9329 writel(0x00880680, spec->mem_base + 0x1c); 9330 } 9331 9332 for (i = 0; i < count; i++) { 9333 /* 9334 * AE-7 shares all writes with the AE-5, except that it writes 9335 * a different value to 0x20c. 9336 */ 9337 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9338 writel(0x00800001, spec->mem_base + addr[i]); 9339 continue; 9340 } 9341 9342 writel(data[i], spec->mem_base + addr[i]); 9343 } 9344 9345 if (ca0132_quirk(spec) == QUIRK_AE5) 9346 writel(0x00880680, spec->mem_base + 0x1c); 9347 } 9348 9349 static void ca0132_mmio_init(struct hda_codec *codec) 9350 { 9351 struct ca0132_spec *spec = codec->spec; 9352 9353 switch (ca0132_quirk(spec)) { 9354 case QUIRK_R3D: 9355 case QUIRK_SBZ: 9356 case QUIRK_ZXR: 9357 ca0132_mmio_init_sbz(codec); 9358 break; 9359 case QUIRK_AE5: 9360 ca0132_mmio_init_ae5(codec); 9361 break; 9362 default: 9363 break; 9364 } 9365 } 9366 9367 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9368 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9369 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9370 }; 9371 9372 static const unsigned char ca0132_ae5_register_set_data[] = { 9373 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9374 0x01, 0x6b, 0x57 9375 }; 9376 9377 /* 9378 * This function writes to some SFR's, does some region2 writes, and then 9379 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9380 * what it does. 9381 */ 9382 static void ae5_register_set(struct hda_codec *codec) 9383 { 9384 struct ca0132_spec *spec = codec->spec; 9385 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9386 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9387 const unsigned char *data = ca0132_ae5_register_set_data; 9388 unsigned int i, cur_addr; 9389 unsigned char tmp[3]; 9390 9391 if (ca0132_quirk(spec) == QUIRK_AE7) 9392 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 9393 9394 chipio_8051_write_direct(codec, 0x93, 0x10); 9395 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 9396 9397 if (ca0132_quirk(spec) == QUIRK_AE7) { 9398 tmp[0] = 0x03; 9399 tmp[1] = 0x03; 9400 tmp[2] = 0x07; 9401 } else { 9402 tmp[0] = 0x0f; 9403 tmp[1] = 0x0f; 9404 tmp[2] = 0x0f; 9405 } 9406 9407 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9408 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9409 9410 /* 9411 * First writes are in single bytes, final are in 4 bytes. So, we use 9412 * writeb, then writel. 9413 */ 9414 for (i = 0; cur_addr < 12; i++, cur_addr++) 9415 writeb(data[i], spec->mem_base + addr[cur_addr]); 9416 9417 for (; cur_addr < count; i++, cur_addr++) 9418 writel(data[i], spec->mem_base + addr[cur_addr]); 9419 9420 writel(0x00800001, spec->mem_base + 0x20c); 9421 9422 if (ca0132_quirk(spec) == QUIRK_AE7) { 9423 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9424 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9425 } else { 9426 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9427 } 9428 9429 chipio_8051_write_direct(codec, 0x90, 0x00); 9430 chipio_8051_write_direct(codec, 0x90, 0x10); 9431 9432 if (ca0132_quirk(spec) == QUIRK_AE5) 9433 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9434 } 9435 9436 /* 9437 * Extra init functions for alternative ca0132 codecs. Done 9438 * here so they don't clutter up the main ca0132_init function 9439 * anymore than they have to. 9440 */ 9441 static void ca0132_alt_init(struct hda_codec *codec) 9442 { 9443 struct ca0132_spec *spec = codec->spec; 9444 9445 ca0132_alt_vol_setup(codec); 9446 9447 switch (ca0132_quirk(spec)) { 9448 case QUIRK_SBZ: 9449 codec_dbg(codec, "SBZ alt_init"); 9450 ca0132_gpio_init(codec); 9451 sbz_pre_dsp_setup(codec); 9452 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9453 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9454 break; 9455 case QUIRK_R3DI: 9456 codec_dbg(codec, "R3DI alt_init"); 9457 ca0132_gpio_init(codec); 9458 ca0132_gpio_setup(codec); 9459 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9460 r3di_pre_dsp_setup(codec); 9461 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9462 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9463 break; 9464 case QUIRK_R3D: 9465 r3d_pre_dsp_setup(codec); 9466 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9467 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9468 break; 9469 case QUIRK_AE5: 9470 ca0132_gpio_init(codec); 9471 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9472 chipio_write(codec, 0x18b030, 0x00000020); 9473 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9474 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9475 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9476 break; 9477 case QUIRK_AE7: 9478 ca0132_gpio_init(codec); 9479 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9480 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9481 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9482 chipio_write(codec, 0x18b008, 0x000000f8); 9483 chipio_write(codec, 0x18b008, 0x000000f0); 9484 chipio_write(codec, 0x18b030, 0x00000020); 9485 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9486 break; 9487 case QUIRK_ZXR: 9488 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9489 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9490 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9491 zxr_pre_dsp_setup(codec); 9492 break; 9493 default: 9494 break; 9495 } 9496 } 9497 9498 static int ca0132_init(struct hda_codec *codec) 9499 { 9500 struct ca0132_spec *spec = codec->spec; 9501 struct auto_pin_cfg *cfg = &spec->autocfg; 9502 int i; 9503 bool dsp_loaded; 9504 9505 /* 9506 * If the DSP is already downloaded, and init has been entered again, 9507 * there's only two reasons for it. One, the codec has awaken from a 9508 * suspended state, and in that case dspload_is_loaded will return 9509 * false, and the init will be ran again. The other reason it gets 9510 * re entered is on startup for some reason it triggers a suspend and 9511 * resume state. In this case, it will check if the DSP is downloaded, 9512 * and not run the init function again. For codecs using alt_functions, 9513 * it will check if the DSP is loaded properly. 9514 */ 9515 if (spec->dsp_state == DSP_DOWNLOADED) { 9516 dsp_loaded = dspload_is_loaded(codec); 9517 if (!dsp_loaded) { 9518 spec->dsp_reload = true; 9519 spec->dsp_state = DSP_DOWNLOAD_INIT; 9520 } else { 9521 if (ca0132_quirk(spec) == QUIRK_SBZ) 9522 sbz_dsp_startup_check(codec); 9523 return 0; 9524 } 9525 } 9526 9527 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9528 spec->dsp_state = DSP_DOWNLOAD_INIT; 9529 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9530 9531 if (ca0132_use_pci_mmio(spec)) 9532 ca0132_mmio_init(codec); 9533 9534 snd_hda_power_up_pm(codec); 9535 9536 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9537 ae5_register_set(codec); 9538 9539 ca0132_init_params(codec); 9540 ca0132_init_flags(codec); 9541 9542 snd_hda_sequence_write(codec, spec->base_init_verbs); 9543 9544 if (ca0132_use_alt_functions(spec)) 9545 ca0132_alt_init(codec); 9546 9547 ca0132_download_dsp(codec); 9548 9549 ca0132_refresh_widget_caps(codec); 9550 9551 switch (ca0132_quirk(spec)) { 9552 case QUIRK_R3DI: 9553 case QUIRK_R3D: 9554 r3d_setup_defaults(codec); 9555 break; 9556 case QUIRK_SBZ: 9557 case QUIRK_ZXR: 9558 sbz_setup_defaults(codec); 9559 break; 9560 case QUIRK_AE5: 9561 ae5_setup_defaults(codec); 9562 break; 9563 case QUIRK_AE7: 9564 ae7_setup_defaults(codec); 9565 break; 9566 default: 9567 ca0132_setup_defaults(codec); 9568 ca0132_init_analog_mic2(codec); 9569 ca0132_init_dmic(codec); 9570 break; 9571 } 9572 9573 for (i = 0; i < spec->num_outputs; i++) 9574 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9575 9576 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9577 9578 for (i = 0; i < spec->num_inputs; i++) 9579 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9580 9581 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9582 9583 if (!ca0132_use_alt_functions(spec)) { 9584 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9585 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9586 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9587 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9588 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9589 } 9590 9591 if (ca0132_quirk(spec) == QUIRK_SBZ) 9592 ca0132_gpio_setup(codec); 9593 9594 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9595 if (ca0132_use_alt_functions(spec)) { 9596 ca0132_alt_select_out(codec); 9597 ca0132_alt_select_in(codec); 9598 } else { 9599 ca0132_select_out(codec); 9600 ca0132_select_mic(codec); 9601 } 9602 9603 snd_hda_jack_report_sync(codec); 9604 9605 /* 9606 * Re set the PlayEnhancement switch on a resume event, because the 9607 * controls will not be reloaded. 9608 */ 9609 if (spec->dsp_reload) { 9610 spec->dsp_reload = false; 9611 ca0132_pe_switch_set(codec); 9612 } 9613 9614 snd_hda_power_down_pm(codec); 9615 9616 return 0; 9617 } 9618 9619 static int dbpro_init(struct hda_codec *codec) 9620 { 9621 struct ca0132_spec *spec = codec->spec; 9622 struct auto_pin_cfg *cfg = &spec->autocfg; 9623 unsigned int i; 9624 9625 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9626 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9627 9628 for (i = 0; i < spec->num_inputs; i++) 9629 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9630 9631 return 0; 9632 } 9633 9634 static void ca0132_free(struct hda_codec *codec) 9635 { 9636 struct ca0132_spec *spec = codec->spec; 9637 9638 cancel_delayed_work_sync(&spec->unsol_hp_work); 9639 snd_hda_power_up(codec); 9640 switch (ca0132_quirk(spec)) { 9641 case QUIRK_SBZ: 9642 sbz_exit_chip(codec); 9643 break; 9644 case QUIRK_ZXR: 9645 zxr_exit_chip(codec); 9646 break; 9647 case QUIRK_R3D: 9648 r3d_exit_chip(codec); 9649 break; 9650 case QUIRK_AE5: 9651 ae5_exit_chip(codec); 9652 break; 9653 case QUIRK_AE7: 9654 ae7_exit_chip(codec); 9655 break; 9656 case QUIRK_R3DI: 9657 r3di_gpio_shutdown(codec); 9658 break; 9659 default: 9660 break; 9661 } 9662 9663 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9664 ca0132_exit_chip(codec); 9665 9666 snd_hda_power_down(codec); 9667 #ifdef CONFIG_PCI 9668 if (spec->mem_base) 9669 pci_iounmap(codec->bus->pci, spec->mem_base); 9670 #endif 9671 kfree(spec->spec_init_verbs); 9672 kfree(codec->spec); 9673 } 9674 9675 static void dbpro_free(struct hda_codec *codec) 9676 { 9677 struct ca0132_spec *spec = codec->spec; 9678 9679 zxr_dbpro_power_state_shutdown(codec); 9680 9681 kfree(spec->spec_init_verbs); 9682 kfree(codec->spec); 9683 } 9684 9685 #ifdef CONFIG_PM 9686 static int ca0132_suspend(struct hda_codec *codec) 9687 { 9688 struct ca0132_spec *spec = codec->spec; 9689 9690 cancel_delayed_work_sync(&spec->unsol_hp_work); 9691 return 0; 9692 } 9693 #endif 9694 9695 static const struct hda_codec_ops ca0132_patch_ops = { 9696 .build_controls = ca0132_build_controls, 9697 .build_pcms = ca0132_build_pcms, 9698 .init = ca0132_init, 9699 .free = ca0132_free, 9700 .unsol_event = snd_hda_jack_unsol_event, 9701 #ifdef CONFIG_PM 9702 .suspend = ca0132_suspend, 9703 #endif 9704 }; 9705 9706 static const struct hda_codec_ops dbpro_patch_ops = { 9707 .build_controls = dbpro_build_controls, 9708 .build_pcms = dbpro_build_pcms, 9709 .init = dbpro_init, 9710 .free = dbpro_free, 9711 }; 9712 9713 static void ca0132_config(struct hda_codec *codec) 9714 { 9715 struct ca0132_spec *spec = codec->spec; 9716 9717 spec->dacs[0] = 0x2; 9718 spec->dacs[1] = 0x3; 9719 spec->dacs[2] = 0x4; 9720 9721 spec->multiout.dac_nids = spec->dacs; 9722 spec->multiout.num_dacs = 3; 9723 9724 if (!ca0132_use_alt_functions(spec)) 9725 spec->multiout.max_channels = 2; 9726 else 9727 spec->multiout.max_channels = 6; 9728 9729 switch (ca0132_quirk(spec)) { 9730 case QUIRK_ALIENWARE: 9731 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9732 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9733 break; 9734 case QUIRK_SBZ: 9735 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9736 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9737 break; 9738 case QUIRK_ZXR: 9739 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9740 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9741 break; 9742 case QUIRK_R3D: 9743 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9744 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9745 break; 9746 case QUIRK_R3DI: 9747 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9748 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9749 break; 9750 case QUIRK_AE5: 9751 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9752 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9753 break; 9754 case QUIRK_AE7: 9755 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9756 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9757 break; 9758 default: 9759 break; 9760 } 9761 9762 switch (ca0132_quirk(spec)) { 9763 case QUIRK_ALIENWARE: 9764 spec->num_outputs = 2; 9765 spec->out_pins[0] = 0x0b; /* speaker out */ 9766 spec->out_pins[1] = 0x0f; 9767 spec->shared_out_nid = 0x2; 9768 spec->unsol_tag_hp = 0x0f; 9769 9770 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9771 spec->adcs[1] = 0x8; /* analog mic2 */ 9772 spec->adcs[2] = 0xa; /* what u hear */ 9773 9774 spec->num_inputs = 3; 9775 spec->input_pins[0] = 0x12; 9776 spec->input_pins[1] = 0x11; 9777 spec->input_pins[2] = 0x13; 9778 spec->shared_mic_nid = 0x7; 9779 spec->unsol_tag_amic1 = 0x11; 9780 break; 9781 case QUIRK_SBZ: 9782 case QUIRK_R3D: 9783 spec->num_outputs = 2; 9784 spec->out_pins[0] = 0x0B; /* Line out */ 9785 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9786 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9787 spec->out_pins[3] = 0x11; /* Rear surround */ 9788 spec->shared_out_nid = 0x2; 9789 spec->unsol_tag_hp = spec->out_pins[1]; 9790 spec->unsol_tag_front_hp = spec->out_pins[2]; 9791 9792 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9793 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9794 spec->adcs[2] = 0xa; /* what u hear */ 9795 9796 spec->num_inputs = 2; 9797 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9798 spec->input_pins[1] = 0x13; /* What U Hear */ 9799 spec->shared_mic_nid = 0x7; 9800 spec->unsol_tag_amic1 = spec->input_pins[0]; 9801 9802 /* SPDIF I/O */ 9803 spec->dig_out = 0x05; 9804 spec->multiout.dig_out_nid = spec->dig_out; 9805 spec->dig_in = 0x09; 9806 break; 9807 case QUIRK_ZXR: 9808 spec->num_outputs = 2; 9809 spec->out_pins[0] = 0x0B; /* Line out */ 9810 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9811 spec->out_pins[2] = 0x10; /* Center/LFE */ 9812 spec->out_pins[3] = 0x11; /* Rear surround */ 9813 spec->shared_out_nid = 0x2; 9814 spec->unsol_tag_hp = spec->out_pins[1]; 9815 spec->unsol_tag_front_hp = spec->out_pins[2]; 9816 9817 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9818 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9819 spec->adcs[2] = 0xa; /* what u hear */ 9820 9821 spec->num_inputs = 2; 9822 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9823 spec->input_pins[1] = 0x13; /* What U Hear */ 9824 spec->shared_mic_nid = 0x7; 9825 spec->unsol_tag_amic1 = spec->input_pins[0]; 9826 break; 9827 case QUIRK_ZXR_DBPRO: 9828 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9829 9830 spec->num_inputs = 1; 9831 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9832 9833 spec->dig_out = 0x05; 9834 spec->multiout.dig_out_nid = spec->dig_out; 9835 9836 spec->dig_in = 0x09; 9837 break; 9838 case QUIRK_AE5: 9839 case QUIRK_AE7: 9840 spec->num_outputs = 2; 9841 spec->out_pins[0] = 0x0B; /* Line out */ 9842 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9843 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9844 spec->out_pins[3] = 0x0F; /* Rear surround */ 9845 spec->shared_out_nid = 0x2; 9846 spec->unsol_tag_hp = spec->out_pins[1]; 9847 spec->unsol_tag_front_hp = spec->out_pins[2]; 9848 9849 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9850 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9851 spec->adcs[2] = 0xa; /* what u hear */ 9852 9853 spec->num_inputs = 2; 9854 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9855 spec->input_pins[1] = 0x13; /* What U Hear */ 9856 spec->shared_mic_nid = 0x7; 9857 spec->unsol_tag_amic1 = spec->input_pins[0]; 9858 9859 /* SPDIF I/O */ 9860 spec->dig_out = 0x05; 9861 spec->multiout.dig_out_nid = spec->dig_out; 9862 break; 9863 case QUIRK_R3DI: 9864 spec->num_outputs = 2; 9865 spec->out_pins[0] = 0x0B; /* Line out */ 9866 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9867 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9868 spec->out_pins[3] = 0x11; /* Rear surround */ 9869 spec->shared_out_nid = 0x2; 9870 spec->unsol_tag_hp = spec->out_pins[1]; 9871 spec->unsol_tag_front_hp = spec->out_pins[2]; 9872 9873 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9874 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9875 spec->adcs[2] = 0x0a; /* what u hear */ 9876 9877 spec->num_inputs = 2; 9878 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9879 spec->input_pins[1] = 0x13; /* What U Hear */ 9880 spec->shared_mic_nid = 0x7; 9881 spec->unsol_tag_amic1 = spec->input_pins[0]; 9882 9883 /* SPDIF I/O */ 9884 spec->dig_out = 0x05; 9885 spec->multiout.dig_out_nid = spec->dig_out; 9886 break; 9887 default: 9888 spec->num_outputs = 2; 9889 spec->out_pins[0] = 0x0b; /* speaker out */ 9890 spec->out_pins[1] = 0x10; /* headphone out */ 9891 spec->shared_out_nid = 0x2; 9892 spec->unsol_tag_hp = spec->out_pins[1]; 9893 9894 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9895 spec->adcs[1] = 0x8; /* analog mic2 */ 9896 spec->adcs[2] = 0xa; /* what u hear */ 9897 9898 spec->num_inputs = 3; 9899 spec->input_pins[0] = 0x12; 9900 spec->input_pins[1] = 0x11; 9901 spec->input_pins[2] = 0x13; 9902 spec->shared_mic_nid = 0x7; 9903 spec->unsol_tag_amic1 = spec->input_pins[0]; 9904 9905 /* SPDIF I/O */ 9906 spec->dig_out = 0x05; 9907 spec->multiout.dig_out_nid = spec->dig_out; 9908 spec->dig_in = 0x09; 9909 break; 9910 } 9911 } 9912 9913 static int ca0132_prepare_verbs(struct hda_codec *codec) 9914 { 9915 /* Verbs + terminator (an empty element) */ 9916 #define NUM_SPEC_VERBS 2 9917 struct ca0132_spec *spec = codec->spec; 9918 9919 spec->chip_init_verbs = ca0132_init_verbs0; 9920 /* 9921 * Since desktop cards use pci_mmio, this can be used to determine 9922 * whether or not to use these verbs instead of a separate bool. 9923 */ 9924 if (ca0132_use_pci_mmio(spec)) 9925 spec->desktop_init_verbs = ca0132_init_verbs1; 9926 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 9927 sizeof(struct hda_verb), 9928 GFP_KERNEL); 9929 if (!spec->spec_init_verbs) 9930 return -ENOMEM; 9931 9932 /* config EAPD */ 9933 spec->spec_init_verbs[0].nid = 0x0b; 9934 spec->spec_init_verbs[0].param = 0x78D; 9935 spec->spec_init_verbs[0].verb = 0x00; 9936 9937 /* Previously commented configuration */ 9938 /* 9939 spec->spec_init_verbs[2].nid = 0x0b; 9940 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9941 spec->spec_init_verbs[2].verb = 0x02; 9942 9943 spec->spec_init_verbs[3].nid = 0x10; 9944 spec->spec_init_verbs[3].param = 0x78D; 9945 spec->spec_init_verbs[3].verb = 0x02; 9946 9947 spec->spec_init_verbs[4].nid = 0x10; 9948 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9949 spec->spec_init_verbs[4].verb = 0x02; 9950 */ 9951 9952 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9953 return 0; 9954 } 9955 9956 /* 9957 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9958 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9959 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9960 * daughter boards ID. 9961 */ 9962 static void sbz_detect_quirk(struct hda_codec *codec) 9963 { 9964 struct ca0132_spec *spec = codec->spec; 9965 9966 switch (codec->core.subsystem_id) { 9967 case 0x11020033: 9968 spec->quirk = QUIRK_ZXR; 9969 break; 9970 case 0x1102003f: 9971 spec->quirk = QUIRK_ZXR_DBPRO; 9972 break; 9973 default: 9974 spec->quirk = QUIRK_SBZ; 9975 break; 9976 } 9977 } 9978 9979 static int patch_ca0132(struct hda_codec *codec) 9980 { 9981 struct ca0132_spec *spec; 9982 int err; 9983 const struct snd_pci_quirk *quirk; 9984 9985 codec_dbg(codec, "patch_ca0132\n"); 9986 9987 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 9988 if (!spec) 9989 return -ENOMEM; 9990 codec->spec = spec; 9991 spec->codec = codec; 9992 9993 /* Detect codec quirk */ 9994 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 9995 if (quirk) 9996 spec->quirk = quirk->value; 9997 else 9998 spec->quirk = QUIRK_NONE; 9999 if (ca0132_quirk(spec) == QUIRK_SBZ) 10000 sbz_detect_quirk(codec); 10001 10002 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 10003 codec->patch_ops = dbpro_patch_ops; 10004 else 10005 codec->patch_ops = ca0132_patch_ops; 10006 10007 codec->pcm_format_first = 1; 10008 codec->no_sticky_stream = 1; 10009 10010 10011 spec->dsp_state = DSP_DOWNLOAD_INIT; 10012 spec->num_mixers = 1; 10013 10014 /* Set which mixers each quirk uses. */ 10015 switch (ca0132_quirk(spec)) { 10016 case QUIRK_SBZ: 10017 spec->mixers[0] = desktop_mixer; 10018 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 10019 break; 10020 case QUIRK_ZXR: 10021 spec->mixers[0] = desktop_mixer; 10022 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 10023 break; 10024 case QUIRK_ZXR_DBPRO: 10025 break; 10026 case QUIRK_R3D: 10027 spec->mixers[0] = desktop_mixer; 10028 snd_hda_codec_set_name(codec, "Recon3D"); 10029 break; 10030 case QUIRK_R3DI: 10031 spec->mixers[0] = r3di_mixer; 10032 snd_hda_codec_set_name(codec, "Recon3Di"); 10033 break; 10034 case QUIRK_AE5: 10035 spec->mixers[0] = desktop_mixer; 10036 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 10037 break; 10038 case QUIRK_AE7: 10039 spec->mixers[0] = desktop_mixer; 10040 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 10041 break; 10042 default: 10043 spec->mixers[0] = ca0132_mixer; 10044 break; 10045 } 10046 10047 /* Setup whether or not to use alt functions/controls/pci_mmio */ 10048 switch (ca0132_quirk(spec)) { 10049 case QUIRK_SBZ: 10050 case QUIRK_R3D: 10051 case QUIRK_AE5: 10052 case QUIRK_AE7: 10053 case QUIRK_ZXR: 10054 spec->use_alt_controls = true; 10055 spec->use_alt_functions = true; 10056 spec->use_pci_mmio = true; 10057 break; 10058 case QUIRK_R3DI: 10059 spec->use_alt_controls = true; 10060 spec->use_alt_functions = true; 10061 spec->use_pci_mmio = false; 10062 break; 10063 default: 10064 spec->use_alt_controls = false; 10065 spec->use_alt_functions = false; 10066 spec->use_pci_mmio = false; 10067 break; 10068 } 10069 10070 #ifdef CONFIG_PCI 10071 if (spec->use_pci_mmio) { 10072 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 10073 if (spec->mem_base == NULL) { 10074 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 10075 spec->quirk = QUIRK_NONE; 10076 } 10077 } 10078 #endif 10079 10080 spec->base_init_verbs = ca0132_base_init_verbs; 10081 spec->base_exit_verbs = ca0132_base_exit_verbs; 10082 10083 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 10084 10085 ca0132_init_chip(codec); 10086 10087 ca0132_config(codec); 10088 10089 err = ca0132_prepare_verbs(codec); 10090 if (err < 0) 10091 goto error; 10092 10093 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 10094 if (err < 0) 10095 goto error; 10096 10097 ca0132_setup_unsol(codec); 10098 10099 return 0; 10100 10101 error: 10102 ca0132_free(codec); 10103 return err; 10104 } 10105 10106 /* 10107 * patch entries 10108 */ 10109 static const struct hda_device_id snd_hda_id_ca0132[] = { 10110 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 10111 {} /* terminator */ 10112 }; 10113 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 10114 10115 MODULE_LICENSE("GPL"); 10116 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 10117 10118 static struct hda_codec_driver ca0132_driver = { 10119 .id = snd_hda_id_ca0132, 10120 }; 10121 10122 module_hda_codec_driver(ca0132_driver); 10123