1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm8150.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <38400000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo485"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <488>; 52 dynamic-power-coefficient = <232>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58 power-domains = <&CPU_PD0>; 59 power-domain-names = "psci"; 60 #cooling-cells = <2>; 61 L2_0: l2-cache { 62 compatible = "cache"; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 }; 67 }; 68 }; 69 70 CPU1: cpu@100 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo485"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <488>; 76 dynamic-power-coefficient = <232>; 77 next-level-cache = <&L2_100>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82 power-domains = <&CPU_PD1>; 83 power-domain-names = "psci"; 84 #cooling-cells = <2>; 85 L2_100: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo485"; 95 reg = <0x0 0x200>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <488>; 98 dynamic-power-coefficient = <232>; 99 next-level-cache = <&L2_200>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo485"; 116 reg = <0x0 0x300>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <488>; 119 dynamic-power-coefficient = <232>; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 operating-points-v2 = <&cpu0_opp_table>; 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 #cooling-cells = <2>; 128 L2_300: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo485"; 137 reg = <0x0 0x400>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 dynamic-power-coefficient = <369>; 141 next-level-cache = <&L2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 operating-points-v2 = <&cpu4_opp_table>; 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146 power-domains = <&CPU_PD4>; 147 power-domain-names = "psci"; 148 #cooling-cells = <2>; 149 L2_400: l2-cache { 150 compatible = "cache"; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU5: cpu@500 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo485"; 158 reg = <0x0 0x500>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <369>; 162 next-level-cache = <&L2_500>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167 power-domains = <&CPU_PD5>; 168 power-domain-names = "psci"; 169 #cooling-cells = <2>; 170 L2_500: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU6: cpu@600 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo485"; 179 reg = <0x0 0x600>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <369>; 183 next-level-cache = <&L2_600>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 operating-points-v2 = <&cpu4_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188 power-domains = <&CPU_PD6>; 189 power-domain-names = "psci"; 190 #cooling-cells = <2>; 191 L2_600: l2-cache { 192 compatible = "cache"; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 CPU7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "qcom,kryo485"; 200 reg = <0x0 0x700>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <421>; 204 next-level-cache = <&L2_700>; 205 qcom,freq-domain = <&cpufreq_hw 2>; 206 operating-points-v2 = <&cpu7_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&CPU_PD7>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 L2_700: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&CPU0>; 222 }; 223 224 core1 { 225 cpu = <&CPU1>; 226 }; 227 228 core2 { 229 cpu = <&CPU2>; 230 }; 231 232 core3 { 233 cpu = <&CPU3>; 234 }; 235 236 core4 { 237 cpu = <&CPU4>; 238 }; 239 240 core5 { 241 cpu = <&CPU5>; 242 }; 243 244 core6 { 245 cpu = <&CPU6>; 246 }; 247 248 core7 { 249 cpu = <&CPU7>; 250 }; 251 }; 252 }; 253 254 idle-states { 255 entry-method = "psci"; 256 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "little-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <355>; 262 exit-latency-us = <909>; 263 min-residency-us = <3934>; 264 local-timer-stop; 265 }; 266 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "big-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <241>; 272 exit-latency-us = <1461>; 273 min-residency-us = <4488>; 274 local-timer-stop; 275 }; 276 }; 277 278 domain-idle-states { 279 CLUSTER_SLEEP_0: cluster-sleep-0 { 280 compatible = "domain-idle-state"; 281 idle-state-name = "cluster-power-collapse"; 282 arm,psci-suspend-param = <0x4100c244>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 local-timer-stop; 287 }; 288 }; 289 }; 290 291 cpu0_opp_table: cpu0_opp_table { 292 compatible = "operating-points-v2"; 293 opp-shared; 294 295 cpu0_opp1: opp-300000000 { 296 opp-hz = /bits/ 64 <300000000>; 297 opp-peak-kBps = <800000 9600000>; 298 }; 299 300 cpu0_opp2: opp-403200000 { 301 opp-hz = /bits/ 64 <403200000>; 302 opp-peak-kBps = <800000 9600000>; 303 }; 304 305 cpu0_opp3: opp-499200000 { 306 opp-hz = /bits/ 64 <499200000>; 307 opp-peak-kBps = <800000 12902400>; 308 }; 309 310 cpu0_opp4: opp-576000000 { 311 opp-hz = /bits/ 64 <576000000>; 312 opp-peak-kBps = <800000 12902400>; 313 }; 314 315 cpu0_opp5: opp-672000000 { 316 opp-hz = /bits/ 64 <672000000>; 317 opp-peak-kBps = <800000 15974400>; 318 }; 319 320 cpu0_opp6: opp-768000000 { 321 opp-hz = /bits/ 64 <768000000>; 322 opp-peak-kBps = <1804000 19660800>; 323 }; 324 325 cpu0_opp7: opp-844800000 { 326 opp-hz = /bits/ 64 <844800000>; 327 opp-peak-kBps = <1804000 19660800>; 328 }; 329 330 cpu0_opp8: opp-940800000 { 331 opp-hz = /bits/ 64 <940800000>; 332 opp-peak-kBps = <1804000 22732800>; 333 }; 334 335 cpu0_opp9: opp-1036800000 { 336 opp-hz = /bits/ 64 <1036800000>; 337 opp-peak-kBps = <1804000 22732800>; 338 }; 339 340 cpu0_opp10: opp-1113600000 { 341 opp-hz = /bits/ 64 <1113600000>; 342 opp-peak-kBps = <2188000 25804800>; 343 }; 344 345 cpu0_opp11: opp-1209600000 { 346 opp-hz = /bits/ 64 <1209600000>; 347 opp-peak-kBps = <2188000 31948800>; 348 }; 349 350 cpu0_opp12: opp-1305600000 { 351 opp-hz = /bits/ 64 <1305600000>; 352 opp-peak-kBps = <3072000 31948800>; 353 }; 354 355 cpu0_opp13: opp-1382400000 { 356 opp-hz = /bits/ 64 <1382400000>; 357 opp-peak-kBps = <3072000 31948800>; 358 }; 359 360 cpu0_opp14: opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-peak-kBps = <3072000 31948800>; 363 }; 364 365 cpu0_opp15: opp-1555200000 { 366 opp-hz = /bits/ 64 <1555200000>; 367 opp-peak-kBps = <3072000 40550400>; 368 }; 369 370 cpu0_opp16: opp-1632000000 { 371 opp-hz = /bits/ 64 <1632000000>; 372 opp-peak-kBps = <3072000 40550400>; 373 }; 374 375 cpu0_opp17: opp-1708800000 { 376 opp-hz = /bits/ 64 <1708800000>; 377 opp-peak-kBps = <3072000 43008000>; 378 }; 379 380 cpu0_opp18: opp-1785600000 { 381 opp-hz = /bits/ 64 <1785600000>; 382 opp-peak-kBps = <3072000 43008000>; 383 }; 384 }; 385 386 cpu4_opp_table: cpu4_opp_table { 387 compatible = "operating-points-v2"; 388 opp-shared; 389 390 cpu4_opp1: opp-710400000 { 391 opp-hz = /bits/ 64 <710400000>; 392 opp-peak-kBps = <1804000 15974400>; 393 }; 394 395 cpu4_opp2: opp-825600000 { 396 opp-hz = /bits/ 64 <825600000>; 397 opp-peak-kBps = <2188000 19660800>; 398 }; 399 400 cpu4_opp3: opp-940800000 { 401 opp-hz = /bits/ 64 <940800000>; 402 opp-peak-kBps = <2188000 22732800>; 403 }; 404 405 cpu4_opp4: opp-1056000000 { 406 opp-hz = /bits/ 64 <1056000000>; 407 opp-peak-kBps = <3072000 25804800>; 408 }; 409 410 cpu4_opp5: opp-1171200000 { 411 opp-hz = /bits/ 64 <1171200000>; 412 opp-peak-kBps = <3072000 31948800>; 413 }; 414 415 cpu4_opp6: opp-1286400000 { 416 opp-hz = /bits/ 64 <1286400000>; 417 opp-peak-kBps = <4068000 31948800>; 418 }; 419 420 cpu4_opp7: opp-1401600000 { 421 opp-hz = /bits/ 64 <1401600000>; 422 opp-peak-kBps = <4068000 31948800>; 423 }; 424 425 cpu4_opp8: opp-1497600000 { 426 opp-hz = /bits/ 64 <1497600000>; 427 opp-peak-kBps = <4068000 40550400>; 428 }; 429 430 cpu4_opp9: opp-1612800000 { 431 opp-hz = /bits/ 64 <1612800000>; 432 opp-peak-kBps = <4068000 40550400>; 433 }; 434 435 cpu4_opp10: opp-1708800000 { 436 opp-hz = /bits/ 64 <1708800000>; 437 opp-peak-kBps = <4068000 43008000>; 438 }; 439 440 cpu4_opp11: opp-1804800000 { 441 opp-hz = /bits/ 64 <1804800000>; 442 opp-peak-kBps = <6220000 43008000>; 443 }; 444 445 cpu4_opp12: opp-1920000000 { 446 opp-hz = /bits/ 64 <1920000000>; 447 opp-peak-kBps = <6220000 49152000>; 448 }; 449 450 cpu4_opp13: opp-2016000000 { 451 opp-hz = /bits/ 64 <2016000000>; 452 opp-peak-kBps = <7216000 49152000>; 453 }; 454 455 cpu4_opp14: opp-2131200000 { 456 opp-hz = /bits/ 64 <2131200000>; 457 opp-peak-kBps = <8368000 49152000>; 458 }; 459 460 cpu4_opp15: opp-2227200000 { 461 opp-hz = /bits/ 64 <2227200000>; 462 opp-peak-kBps = <8368000 51609600>; 463 }; 464 465 cpu4_opp16: opp-2323200000 { 466 opp-hz = /bits/ 64 <2323200000>; 467 opp-peak-kBps = <8368000 51609600>; 468 }; 469 470 cpu4_opp17: opp-2419200000 { 471 opp-hz = /bits/ 64 <2419200000>; 472 opp-peak-kBps = <8368000 51609600>; 473 }; 474 }; 475 476 cpu7_opp_table: cpu7_opp_table { 477 compatible = "operating-points-v2"; 478 opp-shared; 479 480 cpu7_opp1: opp-825600000 { 481 opp-hz = /bits/ 64 <825600000>; 482 opp-peak-kBps = <2188000 19660800>; 483 }; 484 485 cpu7_opp2: opp-940800000 { 486 opp-hz = /bits/ 64 <940800000>; 487 opp-peak-kBps = <2188000 22732800>; 488 }; 489 490 cpu7_opp3: opp-1056000000 { 491 opp-hz = /bits/ 64 <1056000000>; 492 opp-peak-kBps = <3072000 25804800>; 493 }; 494 495 cpu7_opp4: opp-1171200000 { 496 opp-hz = /bits/ 64 <1171200000>; 497 opp-peak-kBps = <3072000 31948800>; 498 }; 499 500 cpu7_opp5: opp-1286400000 { 501 opp-hz = /bits/ 64 <1286400000>; 502 opp-peak-kBps = <4068000 31948800>; 503 }; 504 505 cpu7_opp6: opp-1401600000 { 506 opp-hz = /bits/ 64 <1401600000>; 507 opp-peak-kBps = <4068000 31948800>; 508 }; 509 510 cpu7_opp7: opp-1497600000 { 511 opp-hz = /bits/ 64 <1497600000>; 512 opp-peak-kBps = <4068000 40550400>; 513 }; 514 515 cpu7_opp8: opp-1612800000 { 516 opp-hz = /bits/ 64 <1612800000>; 517 opp-peak-kBps = <4068000 40550400>; 518 }; 519 520 cpu7_opp9: opp-1708800000 { 521 opp-hz = /bits/ 64 <1708800000>; 522 opp-peak-kBps = <4068000 43008000>; 523 }; 524 525 cpu7_opp10: opp-1804800000 { 526 opp-hz = /bits/ 64 <1804800000>; 527 opp-peak-kBps = <6220000 43008000>; 528 }; 529 530 cpu7_opp11: opp-1920000000 { 531 opp-hz = /bits/ 64 <1920000000>; 532 opp-peak-kBps = <6220000 49152000>; 533 }; 534 535 cpu7_opp12: opp-2016000000 { 536 opp-hz = /bits/ 64 <2016000000>; 537 opp-peak-kBps = <7216000 49152000>; 538 }; 539 540 cpu7_opp13: opp-2131200000 { 541 opp-hz = /bits/ 64 <2131200000>; 542 opp-peak-kBps = <8368000 49152000>; 543 }; 544 545 cpu7_opp14: opp-2227200000 { 546 opp-hz = /bits/ 64 <2227200000>; 547 opp-peak-kBps = <8368000 51609600>; 548 }; 549 550 cpu7_opp15: opp-2323200000 { 551 opp-hz = /bits/ 64 <2323200000>; 552 opp-peak-kBps = <8368000 51609600>; 553 }; 554 555 cpu7_opp16: opp-2419200000 { 556 opp-hz = /bits/ 64 <2419200000>; 557 opp-peak-kBps = <8368000 51609600>; 558 }; 559 560 cpu7_opp17: opp-2534400000 { 561 opp-hz = /bits/ 64 <2534400000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp18: opp-2649600000 { 566 opp-hz = /bits/ 64 <2649600000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp19: opp-2745600000 { 571 opp-hz = /bits/ 64 <2745600000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 575 cpu7_opp20: opp-2841600000 { 576 opp-hz = /bits/ 64 <2841600000>; 577 opp-peak-kBps = <8368000 51609600>; 578 }; 579 }; 580 581 firmware { 582 scm: scm { 583 compatible = "qcom,scm-sm8150", "qcom,scm"; 584 #reset-cells = <1>; 585 }; 586 }; 587 588 tcsr_mutex: hwlock { 589 compatible = "qcom,tcsr-mutex"; 590 syscon = <&tcsr_mutex_regs 0 0x1000>; 591 #hwlock-cells = <1>; 592 }; 593 594 memory@80000000 { 595 device_type = "memory"; 596 /* We expect the bootloader to fill in the size */ 597 reg = <0x0 0x80000000 0x0 0x0>; 598 }; 599 600 pmu { 601 compatible = "arm,armv8-pmuv3"; 602 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 603 }; 604 605 psci { 606 compatible = "arm,psci-1.0"; 607 method = "smc"; 608 609 CPU_PD0: cpu0 { 610 #power-domain-cells = <0>; 611 power-domains = <&CLUSTER_PD>; 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613 }; 614 615 CPU_PD1: cpu1 { 616 #power-domain-cells = <0>; 617 power-domains = <&CLUSTER_PD>; 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619 }; 620 621 CPU_PD2: cpu2 { 622 #power-domain-cells = <0>; 623 power-domains = <&CLUSTER_PD>; 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625 }; 626 627 CPU_PD3: cpu3 { 628 #power-domain-cells = <0>; 629 power-domains = <&CLUSTER_PD>; 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631 }; 632 633 CPU_PD4: cpu4 { 634 #power-domain-cells = <0>; 635 power-domains = <&CLUSTER_PD>; 636 domain-idle-states = <&BIG_CPU_SLEEP_0>; 637 }; 638 639 CPU_PD5: cpu5 { 640 #power-domain-cells = <0>; 641 power-domains = <&CLUSTER_PD>; 642 domain-idle-states = <&BIG_CPU_SLEEP_0>; 643 }; 644 645 CPU_PD6: cpu6 { 646 #power-domain-cells = <0>; 647 power-domains = <&CLUSTER_PD>; 648 domain-idle-states = <&BIG_CPU_SLEEP_0>; 649 }; 650 651 CPU_PD7: cpu7 { 652 #power-domain-cells = <0>; 653 power-domains = <&CLUSTER_PD>; 654 domain-idle-states = <&BIG_CPU_SLEEP_0>; 655 }; 656 657 CLUSTER_PD: cpu-cluster0 { 658 #power-domain-cells = <0>; 659 domain-idle-states = <&CLUSTER_SLEEP_0>; 660 }; 661 }; 662 663 reserved-memory { 664 #address-cells = <2>; 665 #size-cells = <2>; 666 ranges; 667 668 hyp_mem: memory@85700000 { 669 reg = <0x0 0x85700000 0x0 0x600000>; 670 no-map; 671 }; 672 673 xbl_mem: memory@85d00000 { 674 reg = <0x0 0x85d00000 0x0 0x140000>; 675 no-map; 676 }; 677 678 aop_mem: memory@85f00000 { 679 reg = <0x0 0x85f00000 0x0 0x20000>; 680 no-map; 681 }; 682 683 aop_cmd_db: memory@85f20000 { 684 compatible = "qcom,cmd-db"; 685 reg = <0x0 0x85f20000 0x0 0x20000>; 686 no-map; 687 }; 688 689 smem_mem: memory@86000000 { 690 reg = <0x0 0x86000000 0x0 0x200000>; 691 no-map; 692 }; 693 694 tz_mem: memory@86200000 { 695 reg = <0x0 0x86200000 0x0 0x3900000>; 696 no-map; 697 }; 698 699 rmtfs_mem: memory@89b00000 { 700 compatible = "qcom,rmtfs-mem"; 701 reg = <0x0 0x89b00000 0x0 0x200000>; 702 no-map; 703 704 qcom,client-id = <1>; 705 qcom,vmid = <15>; 706 }; 707 708 camera_mem: memory@8b700000 { 709 reg = <0x0 0x8b700000 0x0 0x500000>; 710 no-map; 711 }; 712 713 wlan_mem: memory@8bc00000 { 714 reg = <0x0 0x8bc00000 0x0 0x180000>; 715 no-map; 716 }; 717 718 npu_mem: memory@8bd80000 { 719 reg = <0x0 0x8bd80000 0x0 0x80000>; 720 no-map; 721 }; 722 723 adsp_mem: memory@8be00000 { 724 reg = <0x0 0x8be00000 0x0 0x1a00000>; 725 no-map; 726 }; 727 728 mpss_mem: memory@8d800000 { 729 reg = <0x0 0x8d800000 0x0 0x9600000>; 730 no-map; 731 }; 732 733 venus_mem: memory@96e00000 { 734 reg = <0x0 0x96e00000 0x0 0x500000>; 735 no-map; 736 }; 737 738 slpi_mem: memory@97300000 { 739 reg = <0x0 0x97300000 0x0 0x1400000>; 740 no-map; 741 }; 742 743 ipa_fw_mem: memory@98700000 { 744 reg = <0x0 0x98700000 0x0 0x10000>; 745 no-map; 746 }; 747 748 ipa_gsi_mem: memory@98710000 { 749 reg = <0x0 0x98710000 0x0 0x5000>; 750 no-map; 751 }; 752 753 gpu_mem: memory@98715000 { 754 reg = <0x0 0x98715000 0x0 0x2000>; 755 no-map; 756 }; 757 758 spss_mem: memory@98800000 { 759 reg = <0x0 0x98800000 0x0 0x100000>; 760 no-map; 761 }; 762 763 cdsp_mem: memory@98900000 { 764 reg = <0x0 0x98900000 0x0 0x1400000>; 765 no-map; 766 }; 767 768 qseecom_mem: memory@9e400000 { 769 reg = <0x0 0x9e400000 0x0 0x1400000>; 770 no-map; 771 }; 772 }; 773 774 smem { 775 compatible = "qcom,smem"; 776 memory-region = <&smem_mem>; 777 hwlocks = <&tcsr_mutex 3>; 778 }; 779 780 smp2p-cdsp { 781 compatible = "qcom,smp2p"; 782 qcom,smem = <94>, <432>; 783 784 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 785 786 mboxes = <&apss_shared 6>; 787 788 qcom,local-pid = <0>; 789 qcom,remote-pid = <5>; 790 791 cdsp_smp2p_out: master-kernel { 792 qcom,entry-name = "master-kernel"; 793 #qcom,smem-state-cells = <1>; 794 }; 795 796 cdsp_smp2p_in: slave-kernel { 797 qcom,entry-name = "slave-kernel"; 798 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 }; 802 }; 803 804 smp2p-lpass { 805 compatible = "qcom,smp2p"; 806 qcom,smem = <443>, <429>; 807 808 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 809 810 mboxes = <&apss_shared 10>; 811 812 qcom,local-pid = <0>; 813 qcom,remote-pid = <2>; 814 815 adsp_smp2p_out: master-kernel { 816 qcom,entry-name = "master-kernel"; 817 #qcom,smem-state-cells = <1>; 818 }; 819 820 adsp_smp2p_in: slave-kernel { 821 qcom,entry-name = "slave-kernel"; 822 823 interrupt-controller; 824 #interrupt-cells = <2>; 825 }; 826 }; 827 828 smp2p-mpss { 829 compatible = "qcom,smp2p"; 830 qcom,smem = <435>, <428>; 831 832 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 833 834 mboxes = <&apss_shared 14>; 835 836 qcom,local-pid = <0>; 837 qcom,remote-pid = <1>; 838 839 modem_smp2p_out: master-kernel { 840 qcom,entry-name = "master-kernel"; 841 #qcom,smem-state-cells = <1>; 842 }; 843 844 modem_smp2p_in: slave-kernel { 845 qcom,entry-name = "slave-kernel"; 846 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 }; 850 }; 851 852 smp2p-slpi { 853 compatible = "qcom,smp2p"; 854 qcom,smem = <481>, <430>; 855 856 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 857 858 mboxes = <&apss_shared 26>; 859 860 qcom,local-pid = <0>; 861 qcom,remote-pid = <3>; 862 863 slpi_smp2p_out: master-kernel { 864 qcom,entry-name = "master-kernel"; 865 #qcom,smem-state-cells = <1>; 866 }; 867 868 slpi_smp2p_in: slave-kernel { 869 qcom,entry-name = "slave-kernel"; 870 871 interrupt-controller; 872 #interrupt-cells = <2>; 873 }; 874 }; 875 876 soc: soc@0 { 877 #address-cells = <2>; 878 #size-cells = <2>; 879 ranges = <0 0 0 0 0x10 0>; 880 dma-ranges = <0 0 0 0 0x10 0>; 881 compatible = "simple-bus"; 882 883 gcc: clock-controller@100000 { 884 compatible = "qcom,gcc-sm8150"; 885 reg = <0x0 0x00100000 0x0 0x1f0000>; 886 #clock-cells = <1>; 887 #reset-cells = <1>; 888 #power-domain-cells = <1>; 889 clock-names = "bi_tcxo", 890 "sleep_clk"; 891 clocks = <&rpmhcc RPMH_CXO_CLK>, 892 <&sleep_clk>; 893 }; 894 895 gpi_dma0: dma-controller@800000 { 896 compatible = "qcom,sm8150-gpi-dma"; 897 reg = <0 0x800000 0 0x60000>; 898 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 911 dma-channels = <13>; 912 dma-channel-mask = <0xfa>; 913 iommus = <&apps_smmu 0x00d6 0x0>; 914 #dma-cells = <3>; 915 status = "disabled"; 916 }; 917 918 qupv3_id_0: geniqup@8c0000 { 919 compatible = "qcom,geni-se-qup"; 920 reg = <0x0 0x008c0000 0x0 0x6000>; 921 clock-names = "m-ahb", "s-ahb"; 922 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 923 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 924 iommus = <&apps_smmu 0xc3 0x0>; 925 #address-cells = <2>; 926 #size-cells = <2>; 927 ranges; 928 status = "disabled"; 929 930 i2c0: i2c@880000 { 931 compatible = "qcom,geni-i2c"; 932 reg = <0 0x00880000 0 0x4000>; 933 clock-names = "se"; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&qup_i2c0_default>; 937 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 status = "disabled"; 941 }; 942 943 spi0: spi@880000 { 944 compatible = "qcom,geni-spi"; 945 reg = <0 0x880000 0 0x4000>; 946 reg-names = "se"; 947 clock-names = "se"; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&qup_spi0_default>; 951 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 952 spi-max-frequency = <50000000>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 status = "disabled"; 956 }; 957 958 i2c1: i2c@884000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00884000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c1_default>; 965 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970 971 spi1: spi@884000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0 0x884000 0 0x4000>; 974 reg-names = "se"; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_spi1_default>; 979 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 980 spi-max-frequency = <50000000>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 status = "disabled"; 984 }; 985 986 i2c2: i2c@888000 { 987 compatible = "qcom,geni-i2c"; 988 reg = <0 0x00888000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&qup_i2c2_default>; 993 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 spi2: spi@888000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0 0x888000 0 0x4000>; 1002 reg-names = "se"; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_spi2_default>; 1007 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1008 spi-max-frequency = <50000000>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 status = "disabled"; 1012 }; 1013 1014 i2c3: i2c@88c000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x0088c000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c3_default>; 1021 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi3: spi@88c000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x88c000 0 0x4000>; 1030 reg-names = "se"; 1031 clock-names = "se"; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_spi3_default>; 1035 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1036 spi-max-frequency = <50000000>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 i2c4: i2c@890000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00890000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c4_default>; 1049 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 spi4: spi@890000 { 1056 compatible = "qcom,geni-spi"; 1057 reg = <0 0x890000 0 0x4000>; 1058 reg-names = "se"; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_spi4_default>; 1063 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1064 spi-max-frequency = <50000000>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 i2c5: i2c@894000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0 0x00894000 0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_i2c5_default>; 1077 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 spi5: spi@894000 { 1084 compatible = "qcom,geni-spi"; 1085 reg = <0 0x894000 0 0x4000>; 1086 reg-names = "se"; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_spi5_default>; 1091 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1092 spi-max-frequency = <50000000>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 i2c6: i2c@898000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0 0x00898000 0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_i2c6_default>; 1105 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 spi6: spi@898000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0 0x898000 0 0x4000>; 1114 reg-names = "se"; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_spi6_default>; 1119 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1120 spi-max-frequency = <50000000>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 i2c7: i2c@89c000 { 1127 compatible = "qcom,geni-i2c"; 1128 reg = <0 0x0089c000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_i2c7_default>; 1133 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 spi7: spi@89c000 { 1140 compatible = "qcom,geni-spi"; 1141 reg = <0 0x89c000 0 0x4000>; 1142 reg-names = "se"; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_spi7_default>; 1147 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1148 spi-max-frequency = <50000000>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 }; 1154 1155 gpi_dma1: dma-controller@a00000 { 1156 compatible = "qcom,sm8150-gpi-dma"; 1157 reg = <0 0xa00000 0 0x60000>; 1158 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1171 dma-channels = <13>; 1172 dma-channel-mask = <0xfa>; 1173 iommus = <&apps_smmu 0x0616 0x0>; 1174 #dma-cells = <3>; 1175 status = "disabled"; 1176 }; 1177 1178 qupv3_id_1: geniqup@ac0000 { 1179 compatible = "qcom,geni-se-qup"; 1180 reg = <0x0 0x00ac0000 0x0 0x6000>; 1181 clock-names = "m-ahb", "s-ahb"; 1182 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1183 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1184 iommus = <&apps_smmu 0x603 0x0>; 1185 #address-cells = <2>; 1186 #size-cells = <2>; 1187 ranges; 1188 status = "disabled"; 1189 1190 i2c8: i2c@a80000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00a80000 0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_i2c8_default>; 1197 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 1203 spi8: spi@a80000 { 1204 compatible = "qcom,geni-spi"; 1205 reg = <0 0xa80000 0 0x4000>; 1206 reg-names = "se"; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_spi8_default>; 1211 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1212 spi-max-frequency = <50000000>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 i2c9: i2c@a84000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0 0x00a84000 0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c9_default>; 1225 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 spi9: spi@a84000 { 1232 compatible = "qcom,geni-spi"; 1233 reg = <0 0xa84000 0 0x4000>; 1234 reg-names = "se"; 1235 clock-names = "se"; 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_spi9_default>; 1239 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1240 spi-max-frequency = <50000000>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 i2c10: i2c@a88000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0 0x00a88000 0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c10_default>; 1253 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 status = "disabled"; 1257 }; 1258 1259 spi10: spi@a88000 { 1260 compatible = "qcom,geni-spi"; 1261 reg = <0 0xa88000 0 0x4000>; 1262 reg-names = "se"; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_spi10_default>; 1267 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1268 spi-max-frequency = <50000000>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 i2c11: i2c@a8c000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00a8c000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_i2c11_default>; 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi11: spi@a8c000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0xa8c000 0 0x4000>; 1290 reg-names = "se"; 1291 clock-names = "se"; 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_spi11_default>; 1295 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1296 spi-max-frequency = <50000000>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 status = "disabled"; 1300 }; 1301 1302 uart2: serial@a90000 { 1303 compatible = "qcom,geni-debug-uart"; 1304 reg = <0x0 0x00a90000 0x0 0x4000>; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1307 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1308 status = "disabled"; 1309 }; 1310 1311 i2c12: i2c@a90000 { 1312 compatible = "qcom,geni-i2c"; 1313 reg = <0 0x00a90000 0 0x4000>; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_i2c12_default>; 1318 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 spi12: spi@a90000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0 0xa90000 0 0x4000>; 1327 reg-names = "se"; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_spi12_default>; 1332 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1333 spi-max-frequency = <50000000>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 i2c16: i2c@94000 { 1340 compatible = "qcom,geni-i2c"; 1341 reg = <0 0x0094000 0 0x4000>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&qup_i2c16_default>; 1346 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1347 #address-cells = <1>; 1348 #size-cells = <0>; 1349 status = "disabled"; 1350 }; 1351 1352 spi16: spi@a94000 { 1353 compatible = "qcom,geni-spi"; 1354 reg = <0 0xa94000 0 0x4000>; 1355 reg-names = "se"; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi16_default>; 1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1361 spi-max-frequency = <50000000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 }; 1367 1368 gpi_dma2: dma-controller@c00000 { 1369 compatible = "qcom,sm8150-gpi-dma"; 1370 reg = <0 0xc00000 0 0x60000>; 1371 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1384 dma-channels = <13>; 1385 dma-channel-mask = <0xfa>; 1386 iommus = <&apps_smmu 0x07b6 0x0>; 1387 #dma-cells = <3>; 1388 status = "disabled"; 1389 }; 1390 1391 qupv3_id_2: geniqup@cc0000 { 1392 compatible = "qcom,geni-se-qup"; 1393 reg = <0x0 0x00cc0000 0x0 0x6000>; 1394 1395 clock-names = "m-ahb", "s-ahb"; 1396 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1397 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1398 iommus = <&apps_smmu 0x7a3 0x0>; 1399 #address-cells = <2>; 1400 #size-cells = <2>; 1401 ranges; 1402 status = "disabled"; 1403 1404 i2c17: i2c@c80000 { 1405 compatible = "qcom,geni-i2c"; 1406 reg = <0 0x00c80000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_i2c17_default>; 1411 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 spi17: spi@c80000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0xc80000 0 0x4000>; 1420 reg-names = "se"; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_spi17_default>; 1425 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1426 spi-max-frequency = <50000000>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 status = "disabled"; 1430 }; 1431 1432 i2c18: i2c@c84000 { 1433 compatible = "qcom,geni-i2c"; 1434 reg = <0 0x00c84000 0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_i2c18_default>; 1439 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 status = "disabled"; 1443 }; 1444 1445 spi18: spi@c84000 { 1446 compatible = "qcom,geni-spi"; 1447 reg = <0 0xc84000 0 0x4000>; 1448 reg-names = "se"; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_spi18_default>; 1453 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1454 spi-max-frequency = <50000000>; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 status = "disabled"; 1458 }; 1459 1460 i2c19: i2c@c88000 { 1461 compatible = "qcom,geni-i2c"; 1462 reg = <0 0x00c88000 0 0x4000>; 1463 clock-names = "se"; 1464 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_i2c19_default>; 1467 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 status = "disabled"; 1471 }; 1472 1473 spi19: spi@c88000 { 1474 compatible = "qcom,geni-spi"; 1475 reg = <0 0xc88000 0 0x4000>; 1476 reg-names = "se"; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_spi19_default>; 1481 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1482 spi-max-frequency = <50000000>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 status = "disabled"; 1486 }; 1487 1488 i2c13: i2c@c8c000 { 1489 compatible = "qcom,geni-i2c"; 1490 reg = <0 0x00c8c000 0 0x4000>; 1491 clock-names = "se"; 1492 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&qup_i2c13_default>; 1495 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 status = "disabled"; 1499 }; 1500 1501 spi13: spi@c8c000 { 1502 compatible = "qcom,geni-spi"; 1503 reg = <0 0xc8c000 0 0x4000>; 1504 reg-names = "se"; 1505 clock-names = "se"; 1506 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_spi13_default>; 1509 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1510 spi-max-frequency = <50000000>; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 i2c14: i2c@c90000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00c90000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c14_default>; 1523 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 status = "disabled"; 1527 }; 1528 1529 spi14: spi@c90000 { 1530 compatible = "qcom,geni-spi"; 1531 reg = <0 0xc90000 0 0x4000>; 1532 reg-names = "se"; 1533 clock-names = "se"; 1534 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1535 pinctrl-names = "default"; 1536 pinctrl-0 = <&qup_spi14_default>; 1537 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1538 spi-max-frequency = <50000000>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 status = "disabled"; 1542 }; 1543 1544 i2c15: i2c@c94000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0 0x00c94000 0 0x4000>; 1547 clock-names = "se"; 1548 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1549 pinctrl-names = "default"; 1550 pinctrl-0 = <&qup_i2c15_default>; 1551 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 status = "disabled"; 1555 }; 1556 1557 spi15: spi@c94000 { 1558 compatible = "qcom,geni-spi"; 1559 reg = <0 0xc94000 0 0x4000>; 1560 reg-names = "se"; 1561 clock-names = "se"; 1562 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_spi15_default>; 1565 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1566 spi-max-frequency = <50000000>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 }; 1572 1573 config_noc: interconnect@1500000 { 1574 compatible = "qcom,sm8150-config-noc"; 1575 reg = <0 0x01500000 0 0x7400>; 1576 #interconnect-cells = <1>; 1577 qcom,bcm-voters = <&apps_bcm_voter>; 1578 }; 1579 1580 system_noc: interconnect@1620000 { 1581 compatible = "qcom,sm8150-system-noc"; 1582 reg = <0 0x01620000 0 0x19400>; 1583 #interconnect-cells = <1>; 1584 qcom,bcm-voters = <&apps_bcm_voter>; 1585 }; 1586 1587 mc_virt: interconnect@163a000 { 1588 compatible = "qcom,sm8150-mc-virt"; 1589 reg = <0 0x0163a000 0 0x1000>; 1590 #interconnect-cells = <1>; 1591 qcom,bcm-voters = <&apps_bcm_voter>; 1592 }; 1593 1594 aggre1_noc: interconnect@16e0000 { 1595 compatible = "qcom,sm8150-aggre1-noc"; 1596 reg = <0 0x016e0000 0 0xd080>; 1597 #interconnect-cells = <1>; 1598 qcom,bcm-voters = <&apps_bcm_voter>; 1599 }; 1600 1601 aggre2_noc: interconnect@1700000 { 1602 compatible = "qcom,sm8150-aggre2-noc"; 1603 reg = <0 0x01700000 0 0x20000>; 1604 #interconnect-cells = <1>; 1605 qcom,bcm-voters = <&apps_bcm_voter>; 1606 }; 1607 1608 compute_noc: interconnect@1720000 { 1609 compatible = "qcom,sm8150-compute-noc"; 1610 reg = <0 0x01720000 0 0x7000>; 1611 #interconnect-cells = <1>; 1612 qcom,bcm-voters = <&apps_bcm_voter>; 1613 }; 1614 1615 mmss_noc: interconnect@1740000 { 1616 compatible = "qcom,sm8150-mmss-noc"; 1617 reg = <0 0x01740000 0 0x1c100>; 1618 #interconnect-cells = <1>; 1619 qcom,bcm-voters = <&apps_bcm_voter>; 1620 }; 1621 1622 system-cache-controller@9200000 { 1623 compatible = "qcom,sm8150-llcc"; 1624 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1625 reg-names = "llcc_base", "llcc_broadcast_base"; 1626 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1627 }; 1628 1629 ufs_mem_hc: ufshc@1d84000 { 1630 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 1631 "jedec,ufs-2.0"; 1632 reg = <0 0x01d84000 0 0x2500>, 1633 <0 0x01d90000 0 0x8000>; 1634 reg-names = "std", "ice"; 1635 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1636 phys = <&ufs_mem_phy_lanes>; 1637 phy-names = "ufsphy"; 1638 lanes-per-direction = <2>; 1639 #reset-cells = <1>; 1640 resets = <&gcc GCC_UFS_PHY_BCR>; 1641 reset-names = "rst"; 1642 1643 iommus = <&apps_smmu 0x300 0>; 1644 1645 clock-names = 1646 "core_clk", 1647 "bus_aggr_clk", 1648 "iface_clk", 1649 "core_clk_unipro", 1650 "ref_clk", 1651 "tx_lane0_sync_clk", 1652 "rx_lane0_sync_clk", 1653 "rx_lane1_sync_clk", 1654 "ice_core_clk"; 1655 clocks = 1656 <&gcc GCC_UFS_PHY_AXI_CLK>, 1657 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1658 <&gcc GCC_UFS_PHY_AHB_CLK>, 1659 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1660 <&rpmhcc RPMH_CXO_CLK>, 1661 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1662 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1663 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1664 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1665 freq-table-hz = 1666 <37500000 300000000>, 1667 <0 0>, 1668 <0 0>, 1669 <37500000 300000000>, 1670 <0 0>, 1671 <0 0>, 1672 <0 0>, 1673 <0 0>, 1674 <0 300000000>; 1675 1676 status = "disabled"; 1677 }; 1678 1679 ufs_mem_phy: phy@1d87000 { 1680 compatible = "qcom,sm8150-qmp-ufs-phy"; 1681 reg = <0 0x01d87000 0 0x1c0>; 1682 #address-cells = <2>; 1683 #size-cells = <2>; 1684 ranges; 1685 clock-names = "ref", 1686 "ref_aux"; 1687 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1688 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1689 1690 resets = <&ufs_mem_hc 0>; 1691 reset-names = "ufsphy"; 1692 status = "disabled"; 1693 1694 ufs_mem_phy_lanes: lanes@1d87400 { 1695 reg = <0 0x01d87400 0 0x108>, 1696 <0 0x01d87600 0 0x1e0>, 1697 <0 0x01d87c00 0 0x1dc>, 1698 <0 0x01d87800 0 0x108>, 1699 <0 0x01d87a00 0 0x1e0>; 1700 #phy-cells = <0>; 1701 }; 1702 }; 1703 1704 ipa_virt: interconnect@1e00000 { 1705 compatible = "qcom,sm8150-ipa-virt"; 1706 reg = <0 0x01e00000 0 0x1000>; 1707 #interconnect-cells = <1>; 1708 qcom,bcm-voters = <&apps_bcm_voter>; 1709 }; 1710 1711 tcsr_mutex_regs: syscon@1f40000 { 1712 compatible = "syscon"; 1713 reg = <0x0 0x01f40000 0x0 0x40000>; 1714 }; 1715 1716 remoteproc_slpi: remoteproc@2400000 { 1717 compatible = "qcom,sm8150-slpi-pas"; 1718 reg = <0x0 0x02400000 0x0 0x4040>; 1719 1720 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 1721 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1722 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1723 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1724 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1725 interrupt-names = "wdog", "fatal", "ready", 1726 "handover", "stop-ack"; 1727 1728 clocks = <&rpmhcc RPMH_CXO_CLK>; 1729 clock-names = "xo"; 1730 1731 power-domains = <&rpmhpd 3>, 1732 <&rpmhpd 2>; 1733 power-domain-names = "lcx", "lmx"; 1734 1735 memory-region = <&slpi_mem>; 1736 1737 qcom,qmp = <&aoss_qmp>; 1738 1739 qcom,smem-states = <&slpi_smp2p_out 0>; 1740 qcom,smem-state-names = "stop"; 1741 1742 status = "disabled"; 1743 1744 glink-edge { 1745 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 1746 label = "dsps"; 1747 qcom,remote-pid = <3>; 1748 mboxes = <&apss_shared 24>; 1749 }; 1750 }; 1751 1752 gpu: gpu@2c00000 { 1753 /* 1754 * note: the amd,imageon compatible makes it possible 1755 * to use the drm/msm driver without the display node, 1756 * make sure to remove it when display node is added 1757 */ 1758 compatible = "qcom,adreno-640.1", 1759 "qcom,adreno", 1760 "amd,imageon"; 1761 #stream-id-cells = <16>; 1762 1763 reg = <0 0x02c00000 0 0x40000>; 1764 reg-names = "kgsl_3d0_reg_memory"; 1765 1766 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1767 1768 iommus = <&adreno_smmu 0 0x401>; 1769 1770 operating-points-v2 = <&gpu_opp_table>; 1771 1772 qcom,gmu = <&gmu>; 1773 1774 status = "disabled"; 1775 1776 zap-shader { 1777 memory-region = <&gpu_mem>; 1778 }; 1779 1780 /* note: downstream checks gpu binning for 675 Mhz */ 1781 gpu_opp_table: opp-table { 1782 compatible = "operating-points-v2"; 1783 1784 opp-675000000 { 1785 opp-hz = /bits/ 64 <675000000>; 1786 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1787 }; 1788 1789 opp-585000000 { 1790 opp-hz = /bits/ 64 <585000000>; 1791 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1792 }; 1793 1794 opp-499200000 { 1795 opp-hz = /bits/ 64 <499200000>; 1796 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1797 }; 1798 1799 opp-427000000 { 1800 opp-hz = /bits/ 64 <427000000>; 1801 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1802 }; 1803 1804 opp-345000000 { 1805 opp-hz = /bits/ 64 <345000000>; 1806 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1807 }; 1808 1809 opp-257000000 { 1810 opp-hz = /bits/ 64 <257000000>; 1811 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1812 }; 1813 }; 1814 }; 1815 1816 gmu: gmu@2c6a000 { 1817 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1818 1819 reg = <0 0x02c6a000 0 0x30000>, 1820 <0 0x0b290000 0 0x10000>, 1821 <0 0x0b490000 0 0x10000>; 1822 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1823 1824 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1826 interrupt-names = "hfi", "gmu"; 1827 1828 clocks = <&gpucc GPU_CC_AHB_CLK>, 1829 <&gpucc GPU_CC_CX_GMU_CLK>, 1830 <&gpucc GPU_CC_CXO_CLK>, 1831 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1832 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1833 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1834 1835 power-domains = <&gpucc GPU_CX_GDSC>, 1836 <&gpucc GPU_GX_GDSC>; 1837 power-domain-names = "cx", "gx"; 1838 1839 iommus = <&adreno_smmu 5 0x400>; 1840 1841 operating-points-v2 = <&gmu_opp_table>; 1842 1843 status = "disabled"; 1844 1845 gmu_opp_table: opp-table { 1846 compatible = "operating-points-v2"; 1847 1848 opp-200000000 { 1849 opp-hz = /bits/ 64 <200000000>; 1850 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1851 }; 1852 }; 1853 }; 1854 1855 gpucc: clock-controller@2c90000 { 1856 compatible = "qcom,sm8150-gpucc"; 1857 reg = <0 0x02c90000 0 0x9000>; 1858 clocks = <&rpmhcc RPMH_CXO_CLK>, 1859 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1860 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1861 clock-names = "bi_tcxo", 1862 "gcc_gpu_gpll0_clk_src", 1863 "gcc_gpu_gpll0_div_clk_src"; 1864 #clock-cells = <1>; 1865 #reset-cells = <1>; 1866 #power-domain-cells = <1>; 1867 }; 1868 1869 adreno_smmu: iommu@2ca0000 { 1870 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1871 reg = <0 0x02ca0000 0 0x10000>; 1872 #iommu-cells = <2>; 1873 #global-interrupts = <1>; 1874 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 1883 clocks = <&gpucc GPU_CC_AHB_CLK>, 1884 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1885 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1886 clock-names = "ahb", "bus", "iface"; 1887 1888 power-domains = <&gpucc GPU_CX_GDSC>; 1889 }; 1890 1891 tlmm: pinctrl@3100000 { 1892 compatible = "qcom,sm8150-pinctrl"; 1893 reg = <0x0 0x03100000 0x0 0x300000>, 1894 <0x0 0x03500000 0x0 0x300000>, 1895 <0x0 0x03900000 0x0 0x300000>, 1896 <0x0 0x03D00000 0x0 0x300000>; 1897 reg-names = "west", "east", "north", "south"; 1898 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1899 gpio-ranges = <&tlmm 0 0 176>; 1900 gpio-controller; 1901 #gpio-cells = <2>; 1902 interrupt-controller; 1903 #interrupt-cells = <2>; 1904 1905 qup_i2c0_default: qup-i2c0-default { 1906 mux { 1907 pins = "gpio0", "gpio1"; 1908 function = "qup0"; 1909 }; 1910 1911 config { 1912 pins = "gpio0", "gpio1"; 1913 drive-strength = <0x02>; 1914 bias-disable; 1915 }; 1916 }; 1917 1918 qup_spi0_default: qup-spi0-default { 1919 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1920 function = "qup0"; 1921 drive-strength = <6>; 1922 bias-disable; 1923 }; 1924 1925 qup_i2c1_default: qup-i2c1-default { 1926 mux { 1927 pins = "gpio114", "gpio115"; 1928 function = "qup1"; 1929 }; 1930 1931 config { 1932 pins = "gpio114", "gpio115"; 1933 drive-strength = <0x02>; 1934 bias-disable; 1935 }; 1936 }; 1937 1938 qup_spi1_default: qup-spi1-default { 1939 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 1940 function = "qup1"; 1941 drive-strength = <6>; 1942 bias-disable; 1943 }; 1944 1945 qup_i2c2_default: qup-i2c2-default { 1946 mux { 1947 pins = "gpio126", "gpio127"; 1948 function = "qup2"; 1949 }; 1950 1951 config { 1952 pins = "gpio126", "gpio127"; 1953 drive-strength = <0x02>; 1954 bias-disable; 1955 }; 1956 }; 1957 1958 qup_spi2_default: qup-spi2-default { 1959 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 1960 function = "qup2"; 1961 drive-strength = <6>; 1962 bias-disable; 1963 }; 1964 1965 qup_i2c3_default: qup-i2c3-default { 1966 mux { 1967 pins = "gpio144", "gpio145"; 1968 function = "qup3"; 1969 }; 1970 1971 config { 1972 pins = "gpio144", "gpio145"; 1973 drive-strength = <0x02>; 1974 bias-disable; 1975 }; 1976 }; 1977 1978 qup_spi3_default: qup-spi3-default { 1979 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 1980 function = "qup3"; 1981 drive-strength = <6>; 1982 bias-disable; 1983 }; 1984 1985 qup_i2c4_default: qup-i2c4-default { 1986 mux { 1987 pins = "gpio51", "gpio52"; 1988 function = "qup4"; 1989 }; 1990 1991 config { 1992 pins = "gpio51", "gpio52"; 1993 drive-strength = <0x02>; 1994 bias-disable; 1995 }; 1996 }; 1997 1998 qup_spi4_default: qup-spi4-default { 1999 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2000 function = "qup4"; 2001 drive-strength = <6>; 2002 bias-disable; 2003 }; 2004 2005 qup_i2c5_default: qup-i2c5-default { 2006 mux { 2007 pins = "gpio121", "gpio122"; 2008 function = "qup5"; 2009 }; 2010 2011 config { 2012 pins = "gpio121", "gpio122"; 2013 drive-strength = <0x02>; 2014 bias-disable; 2015 }; 2016 }; 2017 2018 qup_spi5_default: qup-spi5-default { 2019 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2020 function = "qup5"; 2021 drive-strength = <6>; 2022 bias-disable; 2023 }; 2024 2025 qup_i2c6_default: qup-i2c6-default { 2026 mux { 2027 pins = "gpio6", "gpio7"; 2028 function = "qup6"; 2029 }; 2030 2031 config { 2032 pins = "gpio6", "gpio7"; 2033 drive-strength = <0x02>; 2034 bias-disable; 2035 }; 2036 }; 2037 2038 qup_spi6_default: qup-spi6_default { 2039 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2040 function = "qup6"; 2041 drive-strength = <6>; 2042 bias-disable; 2043 }; 2044 2045 qup_i2c7_default: qup-i2c7-default { 2046 mux { 2047 pins = "gpio98", "gpio99"; 2048 function = "qup7"; 2049 }; 2050 2051 config { 2052 pins = "gpio98", "gpio99"; 2053 drive-strength = <0x02>; 2054 bias-disable; 2055 }; 2056 }; 2057 2058 qup_spi7_default: qup-spi7_default { 2059 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2060 function = "qup7"; 2061 drive-strength = <6>; 2062 bias-disable; 2063 }; 2064 2065 qup_i2c8_default: qup-i2c8-default { 2066 mux { 2067 pins = "gpio88", "gpio89"; 2068 function = "qup8"; 2069 }; 2070 2071 config { 2072 pins = "gpio88", "gpio89"; 2073 drive-strength = <0x02>; 2074 bias-disable; 2075 }; 2076 }; 2077 2078 qup_spi8_default: qup-spi8-default { 2079 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2080 function = "qup8"; 2081 drive-strength = <6>; 2082 bias-disable; 2083 }; 2084 2085 qup_i2c9_default: qup-i2c9-default { 2086 mux { 2087 pins = "gpio39", "gpio40"; 2088 function = "qup9"; 2089 }; 2090 2091 config { 2092 pins = "gpio39", "gpio40"; 2093 drive-strength = <0x02>; 2094 bias-disable; 2095 }; 2096 }; 2097 2098 qup_spi9_default: qup-spi9-default { 2099 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2100 function = "qup9"; 2101 drive-strength = <6>; 2102 bias-disable; 2103 }; 2104 2105 qup_i2c10_default: qup-i2c10-default { 2106 mux { 2107 pins = "gpio9", "gpio10"; 2108 function = "qup10"; 2109 }; 2110 2111 config { 2112 pins = "gpio9", "gpio10"; 2113 drive-strength = <0x02>; 2114 bias-disable; 2115 }; 2116 }; 2117 2118 qup_spi10_default: qup-spi10-default { 2119 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2120 function = "qup10"; 2121 drive-strength = <6>; 2122 bias-disable; 2123 }; 2124 2125 qup_i2c11_default: qup-i2c11-default { 2126 mux { 2127 pins = "gpio94", "gpio95"; 2128 function = "qup11"; 2129 }; 2130 2131 config { 2132 pins = "gpio94", "gpio95"; 2133 drive-strength = <0x02>; 2134 bias-disable; 2135 }; 2136 }; 2137 2138 qup_spi11_default: qup-spi11-default { 2139 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2140 function = "qup11"; 2141 drive-strength = <6>; 2142 bias-disable; 2143 }; 2144 2145 qup_i2c12_default: qup-i2c12-default { 2146 mux { 2147 pins = "gpio83", "gpio84"; 2148 function = "qup12"; 2149 }; 2150 2151 config { 2152 pins = "gpio83", "gpio84"; 2153 drive-strength = <0x02>; 2154 bias-disable; 2155 }; 2156 }; 2157 2158 qup_spi12_default: qup-spi12-default { 2159 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2160 function = "qup12"; 2161 drive-strength = <6>; 2162 bias-disable; 2163 }; 2164 2165 qup_i2c13_default: qup-i2c13-default { 2166 mux { 2167 pins = "gpio43", "gpio44"; 2168 function = "qup13"; 2169 }; 2170 2171 config { 2172 pins = "gpio43", "gpio44"; 2173 drive-strength = <0x02>; 2174 bias-disable; 2175 }; 2176 }; 2177 2178 qup_spi13_default: qup-spi13-default { 2179 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2180 function = "qup13"; 2181 drive-strength = <6>; 2182 bias-disable; 2183 }; 2184 2185 qup_i2c14_default: qup-i2c14-default { 2186 mux { 2187 pins = "gpio47", "gpio48"; 2188 function = "qup14"; 2189 }; 2190 2191 config { 2192 pins = "gpio47", "gpio48"; 2193 drive-strength = <0x02>; 2194 bias-disable; 2195 }; 2196 }; 2197 2198 qup_spi14_default: qup-spi14-default { 2199 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2200 function = "qup14"; 2201 drive-strength = <6>; 2202 bias-disable; 2203 }; 2204 2205 qup_i2c15_default: qup-i2c15-default { 2206 mux { 2207 pins = "gpio27", "gpio28"; 2208 function = "qup15"; 2209 }; 2210 2211 config { 2212 pins = "gpio27", "gpio28"; 2213 drive-strength = <0x02>; 2214 bias-disable; 2215 }; 2216 }; 2217 2218 qup_spi15_default: qup-spi15-default { 2219 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2220 function = "qup15"; 2221 drive-strength = <6>; 2222 bias-disable; 2223 }; 2224 2225 qup_i2c16_default: qup-i2c16-default { 2226 mux { 2227 pins = "gpio86", "gpio85"; 2228 function = "qup16"; 2229 }; 2230 2231 config { 2232 pins = "gpio86", "gpio85"; 2233 drive-strength = <0x02>; 2234 bias-disable; 2235 }; 2236 }; 2237 2238 qup_spi16_default: qup-spi16-default { 2239 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2240 function = "qup16"; 2241 drive-strength = <6>; 2242 bias-disable; 2243 }; 2244 2245 qup_i2c17_default: qup-i2c17-default { 2246 mux { 2247 pins = "gpio55", "gpio56"; 2248 function = "qup17"; 2249 }; 2250 2251 config { 2252 pins = "gpio55", "gpio56"; 2253 drive-strength = <0x02>; 2254 bias-disable; 2255 }; 2256 }; 2257 2258 qup_spi17_default: qup-spi17-default { 2259 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2260 function = "qup17"; 2261 drive-strength = <6>; 2262 bias-disable; 2263 }; 2264 2265 qup_i2c18_default: qup-i2c18-default { 2266 mux { 2267 pins = "gpio23", "gpio24"; 2268 function = "qup18"; 2269 }; 2270 2271 config { 2272 pins = "gpio23", "gpio24"; 2273 drive-strength = <0x02>; 2274 bias-disable; 2275 }; 2276 }; 2277 2278 qup_spi18_default: qup-spi18-default { 2279 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2280 function = "qup18"; 2281 drive-strength = <6>; 2282 bias-disable; 2283 }; 2284 2285 qup_i2c19_default: qup-i2c19-default { 2286 mux { 2287 pins = "gpio57", "gpio58"; 2288 function = "qup19"; 2289 }; 2290 2291 config { 2292 pins = "gpio57", "gpio58"; 2293 drive-strength = <0x02>; 2294 bias-disable; 2295 }; 2296 }; 2297 2298 qup_spi19_default: qup-spi19-default { 2299 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2300 function = "qup19"; 2301 drive-strength = <6>; 2302 bias-disable; 2303 }; 2304 }; 2305 2306 remoteproc_mpss: remoteproc@4080000 { 2307 compatible = "qcom,sm8150-mpss-pas"; 2308 reg = <0x0 0x04080000 0x0 0x4040>; 2309 2310 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2311 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2312 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2313 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2314 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2315 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2316 interrupt-names = "wdog", "fatal", "ready", "handover", 2317 "stop-ack", "shutdown-ack"; 2318 2319 clocks = <&rpmhcc RPMH_CXO_CLK>; 2320 clock-names = "xo"; 2321 2322 power-domains = <&rpmhpd 7>, 2323 <&rpmhpd 0>; 2324 power-domain-names = "cx", "mss"; 2325 2326 memory-region = <&mpss_mem>; 2327 2328 qcom,qmp = <&aoss_qmp>; 2329 2330 qcom,smem-states = <&modem_smp2p_out 0>; 2331 qcom,smem-state-names = "stop"; 2332 2333 status = "disabled"; 2334 2335 glink-edge { 2336 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2337 label = "modem"; 2338 qcom,remote-pid = <1>; 2339 mboxes = <&apss_shared 12>; 2340 }; 2341 }; 2342 2343 stm@6002000 { 2344 compatible = "arm,coresight-stm", "arm,primecell"; 2345 reg = <0 0x06002000 0 0x1000>, 2346 <0 0x16280000 0 0x180000>; 2347 reg-names = "stm-base", "stm-stimulus-base"; 2348 2349 clocks = <&aoss_qmp>; 2350 clock-names = "apb_pclk"; 2351 2352 out-ports { 2353 port { 2354 stm_out: endpoint { 2355 remote-endpoint = <&funnel0_in7>; 2356 }; 2357 }; 2358 }; 2359 }; 2360 2361 funnel@6041000 { 2362 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2363 reg = <0 0x06041000 0 0x1000>; 2364 2365 clocks = <&aoss_qmp>; 2366 clock-names = "apb_pclk"; 2367 2368 out-ports { 2369 port { 2370 funnel0_out: endpoint { 2371 remote-endpoint = <&merge_funnel_in0>; 2372 }; 2373 }; 2374 }; 2375 2376 in-ports { 2377 #address-cells = <1>; 2378 #size-cells = <0>; 2379 2380 port@7 { 2381 reg = <7>; 2382 funnel0_in7: endpoint { 2383 remote-endpoint = <&stm_out>; 2384 }; 2385 }; 2386 }; 2387 }; 2388 2389 funnel@6042000 { 2390 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2391 reg = <0 0x06042000 0 0x1000>; 2392 2393 clocks = <&aoss_qmp>; 2394 clock-names = "apb_pclk"; 2395 2396 out-ports { 2397 port { 2398 funnel1_out: endpoint { 2399 remote-endpoint = <&merge_funnel_in1>; 2400 }; 2401 }; 2402 }; 2403 2404 in-ports { 2405 #address-cells = <1>; 2406 #size-cells = <0>; 2407 2408 port@4 { 2409 reg = <4>; 2410 funnel1_in4: endpoint { 2411 remote-endpoint = <&swao_replicator_out>; 2412 }; 2413 }; 2414 }; 2415 }; 2416 2417 funnel@6043000 { 2418 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2419 reg = <0 0x06043000 0 0x1000>; 2420 2421 clocks = <&aoss_qmp>; 2422 clock-names = "apb_pclk"; 2423 2424 out-ports { 2425 port { 2426 funnel2_out: endpoint { 2427 remote-endpoint = <&merge_funnel_in2>; 2428 }; 2429 }; 2430 }; 2431 2432 in-ports { 2433 #address-cells = <1>; 2434 #size-cells = <0>; 2435 2436 port@2 { 2437 reg = <2>; 2438 funnel2_in2: endpoint { 2439 remote-endpoint = <&apss_merge_funnel_out>; 2440 }; 2441 }; 2442 }; 2443 }; 2444 2445 funnel@6045000 { 2446 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2447 reg = <0 0x06045000 0 0x1000>; 2448 2449 clocks = <&aoss_qmp>; 2450 clock-names = "apb_pclk"; 2451 2452 out-ports { 2453 port { 2454 merge_funnel_out: endpoint { 2455 remote-endpoint = <&etf_in>; 2456 }; 2457 }; 2458 }; 2459 2460 in-ports { 2461 #address-cells = <1>; 2462 #size-cells = <0>; 2463 2464 port@0 { 2465 reg = <0>; 2466 merge_funnel_in0: endpoint { 2467 remote-endpoint = <&funnel0_out>; 2468 }; 2469 }; 2470 2471 port@1 { 2472 reg = <1>; 2473 merge_funnel_in1: endpoint { 2474 remote-endpoint = <&funnel1_out>; 2475 }; 2476 }; 2477 2478 port@2 { 2479 reg = <2>; 2480 merge_funnel_in2: endpoint { 2481 remote-endpoint = <&funnel2_out>; 2482 }; 2483 }; 2484 }; 2485 }; 2486 2487 replicator@6046000 { 2488 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2489 reg = <0 0x06046000 0 0x1000>; 2490 2491 clocks = <&aoss_qmp>; 2492 clock-names = "apb_pclk"; 2493 2494 out-ports { 2495 #address-cells = <1>; 2496 #size-cells = <0>; 2497 2498 port@0 { 2499 reg = <0>; 2500 replicator_out0: endpoint { 2501 remote-endpoint = <&etr_in>; 2502 }; 2503 }; 2504 2505 port@1 { 2506 reg = <1>; 2507 replicator_out1: endpoint { 2508 remote-endpoint = <&replicator1_in>; 2509 }; 2510 }; 2511 }; 2512 2513 in-ports { 2514 port { 2515 replicator_in0: endpoint { 2516 remote-endpoint = <&etf_out>; 2517 }; 2518 }; 2519 }; 2520 }; 2521 2522 etf@6047000 { 2523 compatible = "arm,coresight-tmc", "arm,primecell"; 2524 reg = <0 0x06047000 0 0x1000>; 2525 2526 clocks = <&aoss_qmp>; 2527 clock-names = "apb_pclk"; 2528 2529 out-ports { 2530 port { 2531 etf_out: endpoint { 2532 remote-endpoint = <&replicator_in0>; 2533 }; 2534 }; 2535 }; 2536 2537 in-ports { 2538 port { 2539 etf_in: endpoint { 2540 remote-endpoint = <&merge_funnel_out>; 2541 }; 2542 }; 2543 }; 2544 }; 2545 2546 etr@6048000 { 2547 compatible = "arm,coresight-tmc", "arm,primecell"; 2548 reg = <0 0x06048000 0 0x1000>; 2549 iommus = <&apps_smmu 0x05e0 0x0>; 2550 2551 clocks = <&aoss_qmp>; 2552 clock-names = "apb_pclk"; 2553 arm,scatter-gather; 2554 2555 in-ports { 2556 port { 2557 etr_in: endpoint { 2558 remote-endpoint = <&replicator_out0>; 2559 }; 2560 }; 2561 }; 2562 }; 2563 2564 replicator@604a000 { 2565 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2566 reg = <0 0x0604a000 0 0x1000>; 2567 2568 clocks = <&aoss_qmp>; 2569 clock-names = "apb_pclk"; 2570 2571 out-ports { 2572 #address-cells = <1>; 2573 #size-cells = <0>; 2574 2575 port@1 { 2576 reg = <1>; 2577 replicator1_out: endpoint { 2578 remote-endpoint = <&swao_funnel_in>; 2579 }; 2580 }; 2581 }; 2582 2583 in-ports { 2584 #address-cells = <1>; 2585 #size-cells = <0>; 2586 2587 port@1 { 2588 reg = <1>; 2589 replicator1_in: endpoint { 2590 remote-endpoint = <&replicator_out1>; 2591 }; 2592 }; 2593 }; 2594 }; 2595 2596 funnel@6b08000 { 2597 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2598 reg = <0 0x06b08000 0 0x1000>; 2599 2600 clocks = <&aoss_qmp>; 2601 clock-names = "apb_pclk"; 2602 2603 out-ports { 2604 port { 2605 swao_funnel_out: endpoint { 2606 remote-endpoint = <&swao_etf_in>; 2607 }; 2608 }; 2609 }; 2610 2611 in-ports { 2612 #address-cells = <1>; 2613 #size-cells = <0>; 2614 2615 port@6 { 2616 reg = <6>; 2617 swao_funnel_in: endpoint { 2618 remote-endpoint = <&replicator1_out>; 2619 }; 2620 }; 2621 }; 2622 }; 2623 2624 etf@6b09000 { 2625 compatible = "arm,coresight-tmc", "arm,primecell"; 2626 reg = <0 0x06b09000 0 0x1000>; 2627 2628 clocks = <&aoss_qmp>; 2629 clock-names = "apb_pclk"; 2630 2631 out-ports { 2632 port { 2633 swao_etf_out: endpoint { 2634 remote-endpoint = <&swao_replicator_in>; 2635 }; 2636 }; 2637 }; 2638 2639 in-ports { 2640 port { 2641 swao_etf_in: endpoint { 2642 remote-endpoint = <&swao_funnel_out>; 2643 }; 2644 }; 2645 }; 2646 }; 2647 2648 replicator@6b0a000 { 2649 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2650 reg = <0 0x06b0a000 0 0x1000>; 2651 2652 clocks = <&aoss_qmp>; 2653 clock-names = "apb_pclk"; 2654 qcom,replicator-loses-context; 2655 2656 out-ports { 2657 port { 2658 swao_replicator_out: endpoint { 2659 remote-endpoint = <&funnel1_in4>; 2660 }; 2661 }; 2662 }; 2663 2664 in-ports { 2665 port { 2666 swao_replicator_in: endpoint { 2667 remote-endpoint = <&swao_etf_out>; 2668 }; 2669 }; 2670 }; 2671 }; 2672 2673 etm@7040000 { 2674 compatible = "arm,coresight-etm4x", "arm,primecell"; 2675 reg = <0 0x07040000 0 0x1000>; 2676 2677 cpu = <&CPU0>; 2678 2679 clocks = <&aoss_qmp>; 2680 clock-names = "apb_pclk"; 2681 arm,coresight-loses-context-with-cpu; 2682 qcom,skip-power-up; 2683 2684 out-ports { 2685 port { 2686 etm0_out: endpoint { 2687 remote-endpoint = <&apss_funnel_in0>; 2688 }; 2689 }; 2690 }; 2691 }; 2692 2693 etm@7140000 { 2694 compatible = "arm,coresight-etm4x", "arm,primecell"; 2695 reg = <0 0x07140000 0 0x1000>; 2696 2697 cpu = <&CPU1>; 2698 2699 clocks = <&aoss_qmp>; 2700 clock-names = "apb_pclk"; 2701 arm,coresight-loses-context-with-cpu; 2702 qcom,skip-power-up; 2703 2704 out-ports { 2705 port { 2706 etm1_out: endpoint { 2707 remote-endpoint = <&apss_funnel_in1>; 2708 }; 2709 }; 2710 }; 2711 }; 2712 2713 etm@7240000 { 2714 compatible = "arm,coresight-etm4x", "arm,primecell"; 2715 reg = <0 0x07240000 0 0x1000>; 2716 2717 cpu = <&CPU2>; 2718 2719 clocks = <&aoss_qmp>; 2720 clock-names = "apb_pclk"; 2721 arm,coresight-loses-context-with-cpu; 2722 qcom,skip-power-up; 2723 2724 out-ports { 2725 port { 2726 etm2_out: endpoint { 2727 remote-endpoint = <&apss_funnel_in2>; 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 etm@7340000 { 2734 compatible = "arm,coresight-etm4x", "arm,primecell"; 2735 reg = <0 0x07340000 0 0x1000>; 2736 2737 cpu = <&CPU3>; 2738 2739 clocks = <&aoss_qmp>; 2740 clock-names = "apb_pclk"; 2741 arm,coresight-loses-context-with-cpu; 2742 qcom,skip-power-up; 2743 2744 out-ports { 2745 port { 2746 etm3_out: endpoint { 2747 remote-endpoint = <&apss_funnel_in3>; 2748 }; 2749 }; 2750 }; 2751 }; 2752 2753 etm@7440000 { 2754 compatible = "arm,coresight-etm4x", "arm,primecell"; 2755 reg = <0 0x07440000 0 0x1000>; 2756 2757 cpu = <&CPU4>; 2758 2759 clocks = <&aoss_qmp>; 2760 clock-names = "apb_pclk"; 2761 arm,coresight-loses-context-with-cpu; 2762 qcom,skip-power-up; 2763 2764 out-ports { 2765 port { 2766 etm4_out: endpoint { 2767 remote-endpoint = <&apss_funnel_in4>; 2768 }; 2769 }; 2770 }; 2771 }; 2772 2773 etm@7540000 { 2774 compatible = "arm,coresight-etm4x", "arm,primecell"; 2775 reg = <0 0x07540000 0 0x1000>; 2776 2777 cpu = <&CPU5>; 2778 2779 clocks = <&aoss_qmp>; 2780 clock-names = "apb_pclk"; 2781 arm,coresight-loses-context-with-cpu; 2782 qcom,skip-power-up; 2783 2784 out-ports { 2785 port { 2786 etm5_out: endpoint { 2787 remote-endpoint = <&apss_funnel_in5>; 2788 }; 2789 }; 2790 }; 2791 }; 2792 2793 etm@7640000 { 2794 compatible = "arm,coresight-etm4x", "arm,primecell"; 2795 reg = <0 0x07640000 0 0x1000>; 2796 2797 cpu = <&CPU6>; 2798 2799 clocks = <&aoss_qmp>; 2800 clock-names = "apb_pclk"; 2801 arm,coresight-loses-context-with-cpu; 2802 qcom,skip-power-up; 2803 2804 out-ports { 2805 port { 2806 etm6_out: endpoint { 2807 remote-endpoint = <&apss_funnel_in6>; 2808 }; 2809 }; 2810 }; 2811 }; 2812 2813 etm@7740000 { 2814 compatible = "arm,coresight-etm4x", "arm,primecell"; 2815 reg = <0 0x07740000 0 0x1000>; 2816 2817 cpu = <&CPU7>; 2818 2819 clocks = <&aoss_qmp>; 2820 clock-names = "apb_pclk"; 2821 arm,coresight-loses-context-with-cpu; 2822 qcom,skip-power-up; 2823 2824 out-ports { 2825 port { 2826 etm7_out: endpoint { 2827 remote-endpoint = <&apss_funnel_in7>; 2828 }; 2829 }; 2830 }; 2831 }; 2832 2833 funnel@7800000 { /* APSS Funnel */ 2834 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2835 reg = <0 0x07800000 0 0x1000>; 2836 2837 clocks = <&aoss_qmp>; 2838 clock-names = "apb_pclk"; 2839 2840 out-ports { 2841 port { 2842 apss_funnel_out: endpoint { 2843 remote-endpoint = <&apss_merge_funnel_in>; 2844 }; 2845 }; 2846 }; 2847 2848 in-ports { 2849 #address-cells = <1>; 2850 #size-cells = <0>; 2851 2852 port@0 { 2853 reg = <0>; 2854 apss_funnel_in0: endpoint { 2855 remote-endpoint = <&etm0_out>; 2856 }; 2857 }; 2858 2859 port@1 { 2860 reg = <1>; 2861 apss_funnel_in1: endpoint { 2862 remote-endpoint = <&etm1_out>; 2863 }; 2864 }; 2865 2866 port@2 { 2867 reg = <2>; 2868 apss_funnel_in2: endpoint { 2869 remote-endpoint = <&etm2_out>; 2870 }; 2871 }; 2872 2873 port@3 { 2874 reg = <3>; 2875 apss_funnel_in3: endpoint { 2876 remote-endpoint = <&etm3_out>; 2877 }; 2878 }; 2879 2880 port@4 { 2881 reg = <4>; 2882 apss_funnel_in4: endpoint { 2883 remote-endpoint = <&etm4_out>; 2884 }; 2885 }; 2886 2887 port@5 { 2888 reg = <5>; 2889 apss_funnel_in5: endpoint { 2890 remote-endpoint = <&etm5_out>; 2891 }; 2892 }; 2893 2894 port@6 { 2895 reg = <6>; 2896 apss_funnel_in6: endpoint { 2897 remote-endpoint = <&etm6_out>; 2898 }; 2899 }; 2900 2901 port@7 { 2902 reg = <7>; 2903 apss_funnel_in7: endpoint { 2904 remote-endpoint = <&etm7_out>; 2905 }; 2906 }; 2907 }; 2908 }; 2909 2910 funnel@7810000 { 2911 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2912 reg = <0 0x07810000 0 0x1000>; 2913 2914 clocks = <&aoss_qmp>; 2915 clock-names = "apb_pclk"; 2916 2917 out-ports { 2918 port { 2919 apss_merge_funnel_out: endpoint { 2920 remote-endpoint = <&funnel2_in2>; 2921 }; 2922 }; 2923 }; 2924 2925 in-ports { 2926 port { 2927 apss_merge_funnel_in: endpoint { 2928 remote-endpoint = <&apss_funnel_out>; 2929 }; 2930 }; 2931 }; 2932 }; 2933 2934 remoteproc_cdsp: remoteproc@8300000 { 2935 compatible = "qcom,sm8150-cdsp-pas"; 2936 reg = <0x0 0x08300000 0x0 0x4040>; 2937 2938 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2939 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2940 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2941 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2942 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2943 interrupt-names = "wdog", "fatal", "ready", 2944 "handover", "stop-ack"; 2945 2946 clocks = <&rpmhcc RPMH_CXO_CLK>; 2947 clock-names = "xo"; 2948 2949 power-domains = <&rpmhpd 7>; 2950 2951 memory-region = <&cdsp_mem>; 2952 2953 qcom,qmp = <&aoss_qmp>; 2954 2955 qcom,smem-states = <&cdsp_smp2p_out 0>; 2956 qcom,smem-state-names = "stop"; 2957 2958 status = "disabled"; 2959 2960 glink-edge { 2961 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2962 label = "cdsp"; 2963 qcom,remote-pid = <5>; 2964 mboxes = <&apss_shared 4>; 2965 }; 2966 }; 2967 2968 usb_1_hsphy: phy@88e2000 { 2969 compatible = "qcom,sm8150-usb-hs-phy", 2970 "qcom,usb-snps-hs-7nm-phy"; 2971 reg = <0 0x088e2000 0 0x400>; 2972 status = "disabled"; 2973 #phy-cells = <0>; 2974 2975 clocks = <&rpmhcc RPMH_CXO_CLK>; 2976 clock-names = "ref"; 2977 2978 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2979 }; 2980 2981 usb_2_hsphy: phy@88e3000 { 2982 compatible = "qcom,sm8150-usb-hs-phy", 2983 "qcom,usb-snps-hs-7nm-phy"; 2984 reg = <0 0x088e3000 0 0x400>; 2985 status = "disabled"; 2986 #phy-cells = <0>; 2987 2988 clocks = <&rpmhcc RPMH_CXO_CLK>; 2989 clock-names = "ref"; 2990 2991 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2992 }; 2993 2994 usb_1_qmpphy: phy@88e9000 { 2995 compatible = "qcom,sm8150-qmp-usb3-phy"; 2996 reg = <0 0x088e9000 0 0x18c>, 2997 <0 0x088e8000 0 0x10>; 2998 reg-names = "reg-base", "dp_com"; 2999 status = "disabled"; 3000 #address-cells = <2>; 3001 #size-cells = <2>; 3002 ranges; 3003 3004 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3005 <&rpmhcc RPMH_CXO_CLK>, 3006 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3007 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3008 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3009 3010 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3011 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3012 reset-names = "phy", "common"; 3013 3014 usb_1_ssphy: lanes@88e9200 { 3015 reg = <0 0x088e9200 0 0x200>, 3016 <0 0x088e9400 0 0x200>, 3017 <0 0x088e9c00 0 0x218>, 3018 <0 0x088e9600 0 0x200>, 3019 <0 0x088e9800 0 0x200>, 3020 <0 0x088e9a00 0 0x100>; 3021 #clock-cells = <0>; 3022 #phy-cells = <0>; 3023 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3024 clock-names = "pipe0"; 3025 clock-output-names = "usb3_phy_pipe_clk_src"; 3026 }; 3027 }; 3028 3029 usb_2_qmpphy: phy@88eb000 { 3030 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3031 reg = <0 0x088eb000 0 0x200>; 3032 status = "disabled"; 3033 #address-cells = <2>; 3034 #size-cells = <2>; 3035 ranges; 3036 3037 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3038 <&rpmhcc RPMH_CXO_CLK>, 3039 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3040 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3041 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3042 3043 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3044 <&gcc GCC_USB3_PHY_SEC_BCR>; 3045 reset-names = "phy", "common"; 3046 3047 usb_2_ssphy: lane@88eb200 { 3048 reg = <0 0x088eb200 0 0x200>, 3049 <0 0x088eb400 0 0x200>, 3050 <0 0x088eb800 0 0x800>, 3051 <0 0x088eb600 0 0x200>; 3052 #clock-cells = <0>; 3053 #phy-cells = <0>; 3054 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3055 clock-names = "pipe0"; 3056 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3057 }; 3058 }; 3059 3060 dc_noc: interconnect@9160000 { 3061 compatible = "qcom,sm8150-dc-noc"; 3062 reg = <0 0x09160000 0 0x3200>; 3063 #interconnect-cells = <1>; 3064 qcom,bcm-voters = <&apps_bcm_voter>; 3065 }; 3066 3067 gem_noc: interconnect@9680000 { 3068 compatible = "qcom,sm8150-gem-noc"; 3069 reg = <0 0x09680000 0 0x3e200>; 3070 #interconnect-cells = <1>; 3071 qcom,bcm-voters = <&apps_bcm_voter>; 3072 }; 3073 3074 usb_1: usb@a6f8800 { 3075 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3076 reg = <0 0x0a6f8800 0 0x400>; 3077 status = "disabled"; 3078 #address-cells = <2>; 3079 #size-cells = <2>; 3080 ranges; 3081 dma-ranges; 3082 3083 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3084 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3085 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3086 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3087 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3088 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3089 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3090 "sleep", "xo"; 3091 3092 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3093 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3094 assigned-clock-rates = <19200000>, <200000000>; 3095 3096 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3100 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3101 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3102 3103 power-domains = <&gcc USB30_PRIM_GDSC>; 3104 3105 resets = <&gcc GCC_USB30_PRIM_BCR>; 3106 3107 usb_1_dwc3: dwc3@a600000 { 3108 compatible = "snps,dwc3"; 3109 reg = <0 0x0a600000 0 0xcd00>; 3110 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3111 iommus = <&apps_smmu 0x140 0>; 3112 snps,dis_u2_susphy_quirk; 3113 snps,dis_enblslpm_quirk; 3114 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3115 phy-names = "usb2-phy", "usb3-phy"; 3116 }; 3117 }; 3118 3119 usb_2: usb@a8f8800 { 3120 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3121 reg = <0 0x0a8f8800 0 0x400>; 3122 status = "disabled"; 3123 #address-cells = <2>; 3124 #size-cells = <2>; 3125 ranges; 3126 dma-ranges; 3127 3128 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3129 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3130 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3131 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3132 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3133 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3134 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3135 "sleep", "xo"; 3136 3137 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3138 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3139 assigned-clock-rates = <19200000>, <200000000>; 3140 3141 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3145 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3146 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3147 3148 power-domains = <&gcc USB30_SEC_GDSC>; 3149 3150 resets = <&gcc GCC_USB30_SEC_BCR>; 3151 3152 usb_2_dwc3: usb@a800000 { 3153 compatible = "snps,dwc3"; 3154 reg = <0 0x0a800000 0 0xcd00>; 3155 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3156 iommus = <&apps_smmu 0x160 0>; 3157 snps,dis_u2_susphy_quirk; 3158 snps,dis_enblslpm_quirk; 3159 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3160 phy-names = "usb2-phy", "usb3-phy"; 3161 }; 3162 }; 3163 3164 camnoc_virt: interconnect@ac00000 { 3165 compatible = "qcom,sm8150-camnoc-virt"; 3166 reg = <0 0x0ac00000 0 0x1000>; 3167 #interconnect-cells = <1>; 3168 qcom,bcm-voters = <&apps_bcm_voter>; 3169 }; 3170 3171 aoss_qmp: power-controller@c300000 { 3172 compatible = "qcom,sm8150-aoss-qmp"; 3173 reg = <0x0 0x0c300000 0x0 0x100000>; 3174 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3175 mboxes = <&apss_shared 0>; 3176 3177 #clock-cells = <0>; 3178 }; 3179 3180 tsens0: thermal-sensor@c263000 { 3181 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3182 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3183 <0 0x0c222000 0 0x1ff>; /* SROT */ 3184 #qcom,sensors = <16>; 3185 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3187 interrupt-names = "uplow", "critical"; 3188 #thermal-sensor-cells = <1>; 3189 }; 3190 3191 tsens1: thermal-sensor@c265000 { 3192 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3193 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3194 <0 0x0c223000 0 0x1ff>; /* SROT */ 3195 #qcom,sensors = <8>; 3196 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3198 interrupt-names = "uplow", "critical"; 3199 #thermal-sensor-cells = <1>; 3200 }; 3201 3202 spmi_bus: spmi@c440000 { 3203 compatible = "qcom,spmi-pmic-arb"; 3204 reg = <0x0 0x0c440000 0x0 0x0001100>, 3205 <0x0 0x0c600000 0x0 0x2000000>, 3206 <0x0 0x0e600000 0x0 0x0100000>, 3207 <0x0 0x0e700000 0x0 0x00a0000>, 3208 <0x0 0x0c40a000 0x0 0x0026000>; 3209 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3210 interrupt-names = "periph_irq"; 3211 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3212 qcom,ee = <0>; 3213 qcom,channel = <0>; 3214 #address-cells = <2>; 3215 #size-cells = <0>; 3216 interrupt-controller; 3217 #interrupt-cells = <4>; 3218 cell-index = <0>; 3219 }; 3220 3221 apps_smmu: iommu@15000000 { 3222 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3223 reg = <0 0x15000000 0 0x100000>; 3224 #iommu-cells = <2>; 3225 #global-interrupts = <1>; 3226 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 3307 }; 3308 3309 remoteproc_adsp: remoteproc@17300000 { 3310 compatible = "qcom,sm8150-adsp-pas"; 3311 reg = <0x0 0x17300000 0x0 0x4040>; 3312 3313 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3314 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3315 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3316 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3317 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3318 interrupt-names = "wdog", "fatal", "ready", 3319 "handover", "stop-ack"; 3320 3321 clocks = <&rpmhcc RPMH_CXO_CLK>; 3322 clock-names = "xo"; 3323 3324 power-domains = <&rpmhpd 7>; 3325 3326 memory-region = <&adsp_mem>; 3327 3328 qcom,qmp = <&aoss_qmp>; 3329 3330 qcom,smem-states = <&adsp_smp2p_out 0>; 3331 qcom,smem-state-names = "stop"; 3332 3333 status = "disabled"; 3334 3335 glink-edge { 3336 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3337 label = "lpass"; 3338 qcom,remote-pid = <2>; 3339 mboxes = <&apss_shared 8>; 3340 }; 3341 }; 3342 3343 intc: interrupt-controller@17a00000 { 3344 compatible = "arm,gic-v3"; 3345 interrupt-controller; 3346 #interrupt-cells = <3>; 3347 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3348 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3350 }; 3351 3352 apss_shared: mailbox@17c00000 { 3353 compatible = "qcom,sm8150-apss-shared"; 3354 reg = <0x0 0x17c00000 0x0 0x1000>; 3355 #mbox-cells = <1>; 3356 }; 3357 3358 watchdog@17c10000 { 3359 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3360 reg = <0 0x17c10000 0 0x1000>; 3361 clocks = <&sleep_clk>; 3362 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3363 }; 3364 3365 timer@17c20000 { 3366 #address-cells = <2>; 3367 #size-cells = <2>; 3368 ranges; 3369 compatible = "arm,armv7-timer-mem"; 3370 reg = <0x0 0x17c20000 0x0 0x1000>; 3371 clock-frequency = <19200000>; 3372 3373 frame@17c21000{ 3374 frame-number = <0>; 3375 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3377 reg = <0x0 0x17c21000 0x0 0x1000>, 3378 <0x0 0x17c22000 0x0 0x1000>; 3379 }; 3380 3381 frame@17c23000 { 3382 frame-number = <1>; 3383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3384 reg = <0x0 0x17c23000 0x0 0x1000>; 3385 status = "disabled"; 3386 }; 3387 3388 frame@17c25000 { 3389 frame-number = <2>; 3390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3391 reg = <0x0 0x17c25000 0x0 0x1000>; 3392 status = "disabled"; 3393 }; 3394 3395 frame@17c27000 { 3396 frame-number = <3>; 3397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3398 reg = <0x0 0x17c26000 0x0 0x1000>; 3399 status = "disabled"; 3400 }; 3401 3402 frame@17c29000 { 3403 frame-number = <4>; 3404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3405 reg = <0x0 0x17c29000 0x0 0x1000>; 3406 status = "disabled"; 3407 }; 3408 3409 frame@17c2b000 { 3410 frame-number = <5>; 3411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3412 reg = <0x0 0x17c2b000 0x0 0x1000>; 3413 status = "disabled"; 3414 }; 3415 3416 frame@17c2d000 { 3417 frame-number = <6>; 3418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3419 reg = <0x0 0x17c2d000 0x0 0x1000>; 3420 status = "disabled"; 3421 }; 3422 }; 3423 3424 apps_rsc: rsc@18200000 { 3425 label = "apps_rsc"; 3426 compatible = "qcom,rpmh-rsc"; 3427 reg = <0x0 0x18200000 0x0 0x10000>, 3428 <0x0 0x18210000 0x0 0x10000>, 3429 <0x0 0x18220000 0x0 0x10000>; 3430 reg-names = "drv-0", "drv-1", "drv-2"; 3431 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3434 qcom,tcs-offset = <0xd00>; 3435 qcom,drv-id = <2>; 3436 qcom,tcs-config = <ACTIVE_TCS 2>, 3437 <SLEEP_TCS 1>, 3438 <WAKE_TCS 1>, 3439 <CONTROL_TCS 0>; 3440 3441 rpmhcc: clock-controller { 3442 compatible = "qcom,sm8150-rpmh-clk"; 3443 #clock-cells = <1>; 3444 clock-names = "xo"; 3445 clocks = <&xo_board>; 3446 }; 3447 3448 rpmhpd: power-controller { 3449 compatible = "qcom,sm8150-rpmhpd"; 3450 #power-domain-cells = <1>; 3451 operating-points-v2 = <&rpmhpd_opp_table>; 3452 3453 rpmhpd_opp_table: opp-table { 3454 compatible = "operating-points-v2"; 3455 3456 rpmhpd_opp_ret: opp1 { 3457 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3458 }; 3459 3460 rpmhpd_opp_min_svs: opp2 { 3461 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3462 }; 3463 3464 rpmhpd_opp_low_svs: opp3 { 3465 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3466 }; 3467 3468 rpmhpd_opp_svs: opp4 { 3469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3470 }; 3471 3472 rpmhpd_opp_svs_l1: opp5 { 3473 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3474 }; 3475 3476 rpmhpd_opp_svs_l2: opp6 { 3477 opp-level = <224>; 3478 }; 3479 3480 rpmhpd_opp_nom: opp7 { 3481 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3482 }; 3483 3484 rpmhpd_opp_nom_l1: opp8 { 3485 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3486 }; 3487 3488 rpmhpd_opp_nom_l2: opp9 { 3489 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3490 }; 3491 3492 rpmhpd_opp_turbo: opp10 { 3493 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3494 }; 3495 3496 rpmhpd_opp_turbo_l1: opp11 { 3497 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3498 }; 3499 }; 3500 }; 3501 3502 apps_bcm_voter: bcm_voter { 3503 compatible = "qcom,bcm-voter"; 3504 }; 3505 }; 3506 3507 osm_l3: interconnect@18321000 { 3508 compatible = "qcom,sm8150-osm-l3"; 3509 reg = <0 0x18321000 0 0x1400>; 3510 3511 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3512 clock-names = "xo", "alternate"; 3513 3514 #interconnect-cells = <1>; 3515 }; 3516 3517 cpufreq_hw: cpufreq@18323000 { 3518 compatible = "qcom,cpufreq-hw"; 3519 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3520 <0 0x18327800 0 0x1400>; 3521 reg-names = "freq-domain0", "freq-domain1", 3522 "freq-domain2"; 3523 3524 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3525 clock-names = "xo", "alternate"; 3526 3527 #freq-domain-cells = <1>; 3528 }; 3529 3530 wifi: wifi@18800000 { 3531 compatible = "qcom,wcn3990-wifi"; 3532 reg = <0 0x18800000 0 0x800000>; 3533 reg-names = "membase"; 3534 memory-region = <&wlan_mem>; 3535 clock-names = "cxo_ref_clk_pin", "qdss"; 3536 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 3537 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3549 iommus = <&apps_smmu 0x0640 0x1>; 3550 status = "disabled"; 3551 }; 3552 }; 3553 3554 timer { 3555 compatible = "arm,armv8-timer"; 3556 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3557 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3558 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3559 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3560 }; 3561 3562 thermal-zones { 3563 cpu0-thermal { 3564 polling-delay-passive = <250>; 3565 polling-delay = <1000>; 3566 3567 thermal-sensors = <&tsens0 1>; 3568 3569 trips { 3570 cpu0_alert0: trip-point0 { 3571 temperature = <90000>; 3572 hysteresis = <2000>; 3573 type = "passive"; 3574 }; 3575 3576 cpu0_alert1: trip-point1 { 3577 temperature = <95000>; 3578 hysteresis = <2000>; 3579 type = "passive"; 3580 }; 3581 3582 cpu0_crit: cpu_crit { 3583 temperature = <110000>; 3584 hysteresis = <1000>; 3585 type = "critical"; 3586 }; 3587 }; 3588 3589 cooling-maps { 3590 map0 { 3591 trip = <&cpu0_alert0>; 3592 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3593 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3594 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3595 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3596 }; 3597 map1 { 3598 trip = <&cpu0_alert1>; 3599 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3600 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3601 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3602 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3603 }; 3604 }; 3605 }; 3606 3607 cpu1-thermal { 3608 polling-delay-passive = <250>; 3609 polling-delay = <1000>; 3610 3611 thermal-sensors = <&tsens0 2>; 3612 3613 trips { 3614 cpu1_alert0: trip-point0 { 3615 temperature = <90000>; 3616 hysteresis = <2000>; 3617 type = "passive"; 3618 }; 3619 3620 cpu1_alert1: trip-point1 { 3621 temperature = <95000>; 3622 hysteresis = <2000>; 3623 type = "passive"; 3624 }; 3625 3626 cpu1_crit: cpu_crit { 3627 temperature = <110000>; 3628 hysteresis = <1000>; 3629 type = "critical"; 3630 }; 3631 }; 3632 3633 cooling-maps { 3634 map0 { 3635 trip = <&cpu1_alert0>; 3636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3637 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3638 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3639 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3640 }; 3641 map1 { 3642 trip = <&cpu1_alert1>; 3643 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3644 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3645 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3646 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3647 }; 3648 }; 3649 }; 3650 3651 cpu2-thermal { 3652 polling-delay-passive = <250>; 3653 polling-delay = <1000>; 3654 3655 thermal-sensors = <&tsens0 3>; 3656 3657 trips { 3658 cpu2_alert0: trip-point0 { 3659 temperature = <90000>; 3660 hysteresis = <2000>; 3661 type = "passive"; 3662 }; 3663 3664 cpu2_alert1: trip-point1 { 3665 temperature = <95000>; 3666 hysteresis = <2000>; 3667 type = "passive"; 3668 }; 3669 3670 cpu2_crit: cpu_crit { 3671 temperature = <110000>; 3672 hysteresis = <1000>; 3673 type = "critical"; 3674 }; 3675 }; 3676 3677 cooling-maps { 3678 map0 { 3679 trip = <&cpu2_alert0>; 3680 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3681 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3682 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3683 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3684 }; 3685 map1 { 3686 trip = <&cpu2_alert1>; 3687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3691 }; 3692 }; 3693 }; 3694 3695 cpu3-thermal { 3696 polling-delay-passive = <250>; 3697 polling-delay = <1000>; 3698 3699 thermal-sensors = <&tsens0 4>; 3700 3701 trips { 3702 cpu3_alert0: trip-point0 { 3703 temperature = <90000>; 3704 hysteresis = <2000>; 3705 type = "passive"; 3706 }; 3707 3708 cpu3_alert1: trip-point1 { 3709 temperature = <95000>; 3710 hysteresis = <2000>; 3711 type = "passive"; 3712 }; 3713 3714 cpu3_crit: cpu_crit { 3715 temperature = <110000>; 3716 hysteresis = <1000>; 3717 type = "critical"; 3718 }; 3719 }; 3720 3721 cooling-maps { 3722 map0 { 3723 trip = <&cpu3_alert0>; 3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3728 }; 3729 map1 { 3730 trip = <&cpu3_alert1>; 3731 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3732 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3733 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3734 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3735 }; 3736 }; 3737 }; 3738 3739 cpu4-top-thermal { 3740 polling-delay-passive = <250>; 3741 polling-delay = <1000>; 3742 3743 thermal-sensors = <&tsens0 7>; 3744 3745 trips { 3746 cpu4_top_alert0: trip-point0 { 3747 temperature = <90000>; 3748 hysteresis = <2000>; 3749 type = "passive"; 3750 }; 3751 3752 cpu4_top_alert1: trip-point1 { 3753 temperature = <95000>; 3754 hysteresis = <2000>; 3755 type = "passive"; 3756 }; 3757 3758 cpu4_top_crit: cpu_crit { 3759 temperature = <110000>; 3760 hysteresis = <1000>; 3761 type = "critical"; 3762 }; 3763 }; 3764 3765 cooling-maps { 3766 map0 { 3767 trip = <&cpu4_top_alert0>; 3768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3769 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3770 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3771 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3772 }; 3773 map1 { 3774 trip = <&cpu4_top_alert1>; 3775 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3776 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3777 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3778 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3779 }; 3780 }; 3781 }; 3782 3783 cpu5-top-thermal { 3784 polling-delay-passive = <250>; 3785 polling-delay = <1000>; 3786 3787 thermal-sensors = <&tsens0 8>; 3788 3789 trips { 3790 cpu5_top_alert0: trip-point0 { 3791 temperature = <90000>; 3792 hysteresis = <2000>; 3793 type = "passive"; 3794 }; 3795 3796 cpu5_top_alert1: trip-point1 { 3797 temperature = <95000>; 3798 hysteresis = <2000>; 3799 type = "passive"; 3800 }; 3801 3802 cpu5_top_crit: cpu_crit { 3803 temperature = <110000>; 3804 hysteresis = <1000>; 3805 type = "critical"; 3806 }; 3807 }; 3808 3809 cooling-maps { 3810 map0 { 3811 trip = <&cpu5_top_alert0>; 3812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3816 }; 3817 map1 { 3818 trip = <&cpu5_top_alert1>; 3819 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3820 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3821 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3822 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3823 }; 3824 }; 3825 }; 3826 3827 cpu6-top-thermal { 3828 polling-delay-passive = <250>; 3829 polling-delay = <1000>; 3830 3831 thermal-sensors = <&tsens0 9>; 3832 3833 trips { 3834 cpu6_top_alert0: trip-point0 { 3835 temperature = <90000>; 3836 hysteresis = <2000>; 3837 type = "passive"; 3838 }; 3839 3840 cpu6_top_alert1: trip-point1 { 3841 temperature = <95000>; 3842 hysteresis = <2000>; 3843 type = "passive"; 3844 }; 3845 3846 cpu6_top_crit: cpu_crit { 3847 temperature = <110000>; 3848 hysteresis = <1000>; 3849 type = "critical"; 3850 }; 3851 }; 3852 3853 cooling-maps { 3854 map0 { 3855 trip = <&cpu6_top_alert0>; 3856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3860 }; 3861 map1 { 3862 trip = <&cpu6_top_alert1>; 3863 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3864 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3865 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3867 }; 3868 }; 3869 }; 3870 3871 cpu7-top-thermal { 3872 polling-delay-passive = <250>; 3873 polling-delay = <1000>; 3874 3875 thermal-sensors = <&tsens0 10>; 3876 3877 trips { 3878 cpu7_top_alert0: trip-point0 { 3879 temperature = <90000>; 3880 hysteresis = <2000>; 3881 type = "passive"; 3882 }; 3883 3884 cpu7_top_alert1: trip-point1 { 3885 temperature = <95000>; 3886 hysteresis = <2000>; 3887 type = "passive"; 3888 }; 3889 3890 cpu7_top_crit: cpu_crit { 3891 temperature = <110000>; 3892 hysteresis = <1000>; 3893 type = "critical"; 3894 }; 3895 }; 3896 3897 cooling-maps { 3898 map0 { 3899 trip = <&cpu7_top_alert0>; 3900 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3904 }; 3905 map1 { 3906 trip = <&cpu7_top_alert1>; 3907 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3908 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3909 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3911 }; 3912 }; 3913 }; 3914 3915 cpu4-bottom-thermal { 3916 polling-delay-passive = <250>; 3917 polling-delay = <1000>; 3918 3919 thermal-sensors = <&tsens0 11>; 3920 3921 trips { 3922 cpu4_bottom_alert0: trip-point0 { 3923 temperature = <90000>; 3924 hysteresis = <2000>; 3925 type = "passive"; 3926 }; 3927 3928 cpu4_bottom_alert1: trip-point1 { 3929 temperature = <95000>; 3930 hysteresis = <2000>; 3931 type = "passive"; 3932 }; 3933 3934 cpu4_bottom_crit: cpu_crit { 3935 temperature = <110000>; 3936 hysteresis = <1000>; 3937 type = "critical"; 3938 }; 3939 }; 3940 3941 cooling-maps { 3942 map0 { 3943 trip = <&cpu4_bottom_alert0>; 3944 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3948 }; 3949 map1 { 3950 trip = <&cpu4_bottom_alert1>; 3951 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3952 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3953 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3954 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3955 }; 3956 }; 3957 }; 3958 3959 cpu5-bottom-thermal { 3960 polling-delay-passive = <250>; 3961 polling-delay = <1000>; 3962 3963 thermal-sensors = <&tsens0 12>; 3964 3965 trips { 3966 cpu5_bottom_alert0: trip-point0 { 3967 temperature = <90000>; 3968 hysteresis = <2000>; 3969 type = "passive"; 3970 }; 3971 3972 cpu5_bottom_alert1: trip-point1 { 3973 temperature = <95000>; 3974 hysteresis = <2000>; 3975 type = "passive"; 3976 }; 3977 3978 cpu5_bottom_crit: cpu_crit { 3979 temperature = <110000>; 3980 hysteresis = <1000>; 3981 type = "critical"; 3982 }; 3983 }; 3984 3985 cooling-maps { 3986 map0 { 3987 trip = <&cpu5_bottom_alert0>; 3988 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3990 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3991 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3992 }; 3993 map1 { 3994 trip = <&cpu5_bottom_alert1>; 3995 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3996 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3997 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3998 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3999 }; 4000 }; 4001 }; 4002 4003 cpu6-bottom-thermal { 4004 polling-delay-passive = <250>; 4005 polling-delay = <1000>; 4006 4007 thermal-sensors = <&tsens0 13>; 4008 4009 trips { 4010 cpu6_bottom_alert0: trip-point0 { 4011 temperature = <90000>; 4012 hysteresis = <2000>; 4013 type = "passive"; 4014 }; 4015 4016 cpu6_bottom_alert1: trip-point1 { 4017 temperature = <95000>; 4018 hysteresis = <2000>; 4019 type = "passive"; 4020 }; 4021 4022 cpu6_bottom_crit: cpu_crit { 4023 temperature = <110000>; 4024 hysteresis = <1000>; 4025 type = "critical"; 4026 }; 4027 }; 4028 4029 cooling-maps { 4030 map0 { 4031 trip = <&cpu6_bottom_alert0>; 4032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4034 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4036 }; 4037 map1 { 4038 trip = <&cpu6_bottom_alert1>; 4039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4041 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4042 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4043 }; 4044 }; 4045 }; 4046 4047 cpu7-bottom-thermal { 4048 polling-delay-passive = <250>; 4049 polling-delay = <1000>; 4050 4051 thermal-sensors = <&tsens0 14>; 4052 4053 trips { 4054 cpu7_bottom_alert0: trip-point0 { 4055 temperature = <90000>; 4056 hysteresis = <2000>; 4057 type = "passive"; 4058 }; 4059 4060 cpu7_bottom_alert1: trip-point1 { 4061 temperature = <95000>; 4062 hysteresis = <2000>; 4063 type = "passive"; 4064 }; 4065 4066 cpu7_bottom_crit: cpu_crit { 4067 temperature = <110000>; 4068 hysteresis = <1000>; 4069 type = "critical"; 4070 }; 4071 }; 4072 4073 cooling-maps { 4074 map0 { 4075 trip = <&cpu7_bottom_alert0>; 4076 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4078 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4080 }; 4081 map1 { 4082 trip = <&cpu7_bottom_alert1>; 4083 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4084 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4085 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4087 }; 4088 }; 4089 }; 4090 4091 aoss0-thermal { 4092 polling-delay-passive = <250>; 4093 polling-delay = <1000>; 4094 4095 thermal-sensors = <&tsens0 0>; 4096 4097 trips { 4098 aoss0_alert0: trip-point0 { 4099 temperature = <90000>; 4100 hysteresis = <2000>; 4101 type = "hot"; 4102 }; 4103 }; 4104 }; 4105 4106 cluster0-thermal { 4107 polling-delay-passive = <250>; 4108 polling-delay = <1000>; 4109 4110 thermal-sensors = <&tsens0 5>; 4111 4112 trips { 4113 cluster0_alert0: trip-point0 { 4114 temperature = <90000>; 4115 hysteresis = <2000>; 4116 type = "hot"; 4117 }; 4118 cluster0_crit: cluster0_crit { 4119 temperature = <110000>; 4120 hysteresis = <2000>; 4121 type = "critical"; 4122 }; 4123 }; 4124 }; 4125 4126 cluster1-thermal { 4127 polling-delay-passive = <250>; 4128 polling-delay = <1000>; 4129 4130 thermal-sensors = <&tsens0 6>; 4131 4132 trips { 4133 cluster1_alert0: trip-point0 { 4134 temperature = <90000>; 4135 hysteresis = <2000>; 4136 type = "hot"; 4137 }; 4138 cluster1_crit: cluster1_crit { 4139 temperature = <110000>; 4140 hysteresis = <2000>; 4141 type = "critical"; 4142 }; 4143 }; 4144 }; 4145 4146 gpu-thermal-top { 4147 polling-delay-passive = <250>; 4148 polling-delay = <1000>; 4149 4150 thermal-sensors = <&tsens0 15>; 4151 4152 trips { 4153 gpu1_alert0: trip-point0 { 4154 temperature = <90000>; 4155 hysteresis = <2000>; 4156 type = "hot"; 4157 }; 4158 }; 4159 }; 4160 4161 aoss1-thermal { 4162 polling-delay-passive = <250>; 4163 polling-delay = <1000>; 4164 4165 thermal-sensors = <&tsens1 0>; 4166 4167 trips { 4168 aoss1_alert0: trip-point0 { 4169 temperature = <90000>; 4170 hysteresis = <2000>; 4171 type = "hot"; 4172 }; 4173 }; 4174 }; 4175 4176 wlan-thermal { 4177 polling-delay-passive = <250>; 4178 polling-delay = <1000>; 4179 4180 thermal-sensors = <&tsens1 1>; 4181 4182 trips { 4183 wlan_alert0: trip-point0 { 4184 temperature = <90000>; 4185 hysteresis = <2000>; 4186 type = "hot"; 4187 }; 4188 }; 4189 }; 4190 4191 video-thermal { 4192 polling-delay-passive = <250>; 4193 polling-delay = <1000>; 4194 4195 thermal-sensors = <&tsens1 2>; 4196 4197 trips { 4198 video_alert0: trip-point0 { 4199 temperature = <90000>; 4200 hysteresis = <2000>; 4201 type = "hot"; 4202 }; 4203 }; 4204 }; 4205 4206 mem-thermal { 4207 polling-delay-passive = <250>; 4208 polling-delay = <1000>; 4209 4210 thermal-sensors = <&tsens1 3>; 4211 4212 trips { 4213 mem_alert0: trip-point0 { 4214 temperature = <90000>; 4215 hysteresis = <2000>; 4216 type = "hot"; 4217 }; 4218 }; 4219 }; 4220 4221 q6-hvx-thermal { 4222 polling-delay-passive = <250>; 4223 polling-delay = <1000>; 4224 4225 thermal-sensors = <&tsens1 4>; 4226 4227 trips { 4228 q6_hvx_alert0: trip-point0 { 4229 temperature = <90000>; 4230 hysteresis = <2000>; 4231 type = "hot"; 4232 }; 4233 }; 4234 }; 4235 4236 camera-thermal { 4237 polling-delay-passive = <250>; 4238 polling-delay = <1000>; 4239 4240 thermal-sensors = <&tsens1 5>; 4241 4242 trips { 4243 camera_alert0: trip-point0 { 4244 temperature = <90000>; 4245 hysteresis = <2000>; 4246 type = "hot"; 4247 }; 4248 }; 4249 }; 4250 4251 compute-thermal { 4252 polling-delay-passive = <250>; 4253 polling-delay = <1000>; 4254 4255 thermal-sensors = <&tsens1 6>; 4256 4257 trips { 4258 compute_alert0: trip-point0 { 4259 temperature = <90000>; 4260 hysteresis = <2000>; 4261 type = "hot"; 4262 }; 4263 }; 4264 }; 4265 4266 modem-thermal { 4267 polling-delay-passive = <250>; 4268 polling-delay = <1000>; 4269 4270 thermal-sensors = <&tsens1 7>; 4271 4272 trips { 4273 modem_alert0: trip-point0 { 4274 temperature = <90000>; 4275 hysteresis = <2000>; 4276 type = "hot"; 4277 }; 4278 }; 4279 }; 4280 4281 npu-thermal { 4282 polling-delay-passive = <250>; 4283 polling-delay = <1000>; 4284 4285 thermal-sensors = <&tsens1 8>; 4286 4287 trips { 4288 npu_alert0: trip-point0 { 4289 temperature = <90000>; 4290 hysteresis = <2000>; 4291 type = "hot"; 4292 }; 4293 }; 4294 }; 4295 4296 modem-vec-thermal { 4297 polling-delay-passive = <250>; 4298 polling-delay = <1000>; 4299 4300 thermal-sensors = <&tsens1 9>; 4301 4302 trips { 4303 modem_vec_alert0: trip-point0 { 4304 temperature = <90000>; 4305 hysteresis = <2000>; 4306 type = "hot"; 4307 }; 4308 }; 4309 }; 4310 4311 modem-scl-thermal { 4312 polling-delay-passive = <250>; 4313 polling-delay = <1000>; 4314 4315 thermal-sensors = <&tsens1 10>; 4316 4317 trips { 4318 modem_scl_alert0: trip-point0 { 4319 temperature = <90000>; 4320 hysteresis = <2000>; 4321 type = "hot"; 4322 }; 4323 }; 4324 }; 4325 4326 gpu-thermal-bottom { 4327 polling-delay-passive = <250>; 4328 polling-delay = <1000>; 4329 4330 thermal-sensors = <&tsens1 11>; 4331 4332 trips { 4333 gpu2_alert0: trip-point0 { 4334 temperature = <90000>; 4335 hysteresis = <2000>; 4336 type = "hot"; 4337 }; 4338 }; 4339 }; 4340 }; 4341}; 4342