1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6350.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <76800000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <32764>; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo560"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 capacity-dmips-mhz = <1024>; 44 dynamic-power-coefficient = <100>; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 #cooling-cells = <2>; 48 L2_0: l2-cache { 49 compatible = "cache"; 50 next-level-cache = <&L3_0>; 51 L3_0: l3-cache { 52 compatible = "cache"; 53 }; 54 }; 55 }; 56 57 CPU1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "qcom,kryo560"; 60 reg = <0x0 0x100>; 61 enable-method = "psci"; 62 capacity-dmips-mhz = <1024>; 63 dynamic-power-coefficient = <100>; 64 next-level-cache = <&L2_100>; 65 qcom,freq-domain = <&cpufreq_hw 0>; 66 #cooling-cells = <2>; 67 L2_100: l2-cache { 68 compatible = "cache"; 69 next-level-cache = <&L3_0>; 70 }; 71 }; 72 73 CPU2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo560"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 next-level-cache = <&L2_200>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 L2_200: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU3: cpu@300 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo560"; 92 reg = <0x0 0x300>; 93 enable-method = "psci"; 94 capacity-dmips-mhz = <1024>; 95 dynamic-power-coefficient = <100>; 96 next-level-cache = <&L2_300>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 #cooling-cells = <2>; 99 L2_300: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU4: cpu@400 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo560"; 108 reg = <0x0 0x400>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1024>; 111 dynamic-power-coefficient = <100>; 112 next-level-cache = <&L2_400>; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 #cooling-cells = <2>; 115 L2_400: l2-cache { 116 compatible = "cache"; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo560"; 124 reg = <0x0 0x500>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 next-level-cache = <&L2_500>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 #cooling-cells = <2>; 131 L2_500: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 136 }; 137 138 CPU6: cpu@600 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo560"; 141 reg = <0x0 0x600>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1894>; 144 dynamic-power-coefficient = <703>; 145 next-level-cache = <&L2_600>; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 #cooling-cells = <2>; 148 L2_600: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU7: cpu@700 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo560"; 157 reg = <0x0 0x700>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1894>; 160 dynamic-power-coefficient = <703>; 161 next-level-cache = <&L2_700>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 L2_700: l2-cache { 165 compatible = "cache"; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 cpu-map { 171 cluster0 { 172 core0 { 173 cpu = <&CPU0>; 174 }; 175 176 core1 { 177 cpu = <&CPU1>; 178 }; 179 180 core2 { 181 cpu = <&CPU2>; 182 }; 183 184 core3 { 185 cpu = <&CPU3>; 186 }; 187 188 core4 { 189 cpu = <&CPU4>; 190 }; 191 192 core5 { 193 cpu = <&CPU5>; 194 }; 195 196 core6 { 197 cpu = <&CPU6>; 198 }; 199 200 core7 { 201 cpu = <&CPU7>; 202 }; 203 }; 204 }; 205 }; 206 207 firmware { 208 scm: scm { 209 compatible = "qcom,scm-sm6350", "qcom,scm"; 210 #reset-cells = <1>; 211 }; 212 }; 213 214 memory@80000000 { 215 device_type = "memory"; 216 /* We expect the bootloader to fill in the size */ 217 reg = <0x0 0x80000000 0x0 0x0>; 218 }; 219 220 pmu { 221 compatible = "arm,armv8-pmuv3"; 222 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 223 }; 224 225 psci { 226 compatible = "arm,psci-1.0"; 227 method = "smc"; 228 }; 229 230 reserved_memory: reserved-memory { 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges; 234 235 hyp_mem: memory@80000000 { 236 reg = <0 0x80000000 0 0x600000>; 237 no-map; 238 }; 239 240 xbl_aop_mem: memory@80700000 { 241 reg = <0 0x80700000 0 0x160000>; 242 no-map; 243 }; 244 245 cmd_db: memory@80860000 { 246 compatible = "qcom,cmd-db"; 247 reg = <0 0x80860000 0 0x20000>; 248 no-map; 249 }; 250 251 sec_apps_mem: memory@808ff000 { 252 reg = <0 0x808ff000 0 0x1000>; 253 no-map; 254 }; 255 256 smem_mem: memory@80900000 { 257 reg = <0 0x80900000 0 0x200000>; 258 no-map; 259 }; 260 261 cdsp_sec_mem: memory@80b00000 { 262 reg = <0 0x80b00000 0 0x1e00000>; 263 no-map; 264 }; 265 266 pil_camera_mem: memory@86000000 { 267 reg = <0 0x86000000 0 0x500000>; 268 no-map; 269 }; 270 271 pil_npu_mem: memory@86500000 { 272 reg = <0 0x86500000 0 0x500000>; 273 no-map; 274 }; 275 276 pil_video_mem: memory@86a00000 { 277 reg = <0 0x86a00000 0 0x500000>; 278 no-map; 279 }; 280 281 pil_cdsp_mem: memory@86f00000 { 282 reg = <0 0x86f00000 0 0x1e00000>; 283 no-map; 284 }; 285 286 pil_adsp_mem: memory@88d00000 { 287 reg = <0 0x88d00000 0 0x2800000>; 288 no-map; 289 }; 290 291 wlan_fw_mem: memory@8b500000 { 292 reg = <0 0x8b500000 0 0x200000>; 293 no-map; 294 }; 295 296 pil_ipa_fw_mem: memory@8b700000 { 297 reg = <0 0x8b700000 0 0x10000>; 298 no-map; 299 }; 300 301 pil_ipa_gsi_mem: memory@8b710000 { 302 reg = <0 0x8b710000 0 0x5400>; 303 no-map; 304 }; 305 306 pil_gpu_mem: memory@8b715400 { 307 reg = <0 0x8b715400 0 0x2000>; 308 no-map; 309 }; 310 311 pil_modem_mem: memory@8b800000 { 312 reg = <0 0x8b800000 0 0xf800000>; 313 no-map; 314 }; 315 316 cont_splash_memory: memory@a0000000 { 317 reg = <0 0xa0000000 0 0x2300000>; 318 no-map; 319 }; 320 321 dfps_data_memory: memory@a2300000 { 322 reg = <0 0xa2300000 0 0x100000>; 323 no-map; 324 }; 325 326 removed_region: memory@c0000000 { 327 reg = <0 0xc0000000 0 0x3900000>; 328 no-map; 329 }; 330 331 debug_region: memory@ffb00000 { 332 reg = <0 0xffb00000 0 0xc0000>; 333 no-map; 334 }; 335 336 last_log_region: memory@ffbc0000 { 337 reg = <0 0xffbc0000 0 0x40000>; 338 no-map; 339 }; 340 341 ramoops: ramoops@ffc00000 { 342 compatible = "removed-dma-pool", "ramoops"; 343 reg = <0 0xffc00000 0 0x00100000>; 344 record-size = <0x1000>; 345 console-size = <0x40000>; 346 ftrace-size = <0x0>; 347 msg-size = <0x20000 0x20000>; 348 cc-size = <0x0>; 349 no-map; 350 }; 351 352 cmdline_region: memory@ffd00000 { 353 reg = <0 0xffd00000 0 0x1000>; 354 no-map; 355 }; 356 }; 357 358 smem { 359 compatible = "qcom,smem"; 360 memory-region = <&smem_mem>; 361 hwlocks = <&tcsr_mutex 3>; 362 }; 363 364 smp2p-adsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <443>, <429>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_LPASS 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <2>; 375 376 smp2p_adsp_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 smp2p_adsp_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-cdsp { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <94>, <432>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_CDSP 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <5>; 399 400 smp2p_cdsp_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 smp2p_cdsp_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 }; 411 412 smp2p-mpss { 413 compatible = "qcom,smp2p"; 414 qcom,smem = <435>, <428>; 415 416 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 417 IPCC_MPROC_SIGNAL_SMP2P 418 IRQ_TYPE_EDGE_RISING>; 419 mboxes = <&ipcc IPCC_CLIENT_MPSS 420 IPCC_MPROC_SIGNAL_SMP2P>; 421 422 qcom,local-pid = <0>; 423 qcom,remote-pid = <1>; 424 425 modem_smp2p_out: master-kernel { 426 qcom,entry-name = "master-kernel"; 427 #qcom,smem-state-cells = <1>; 428 }; 429 430 modem_smp2p_in: slave-kernel { 431 qcom,entry-name = "slave-kernel"; 432 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 }; 437 438 soc: soc@0 { 439 #address-cells = <2>; 440 #size-cells = <2>; 441 ranges = <0 0 0 0 0x10 0>; 442 dma-ranges = <0 0 0 0 0x10 0>; 443 compatible = "simple-bus"; 444 445 gcc: clock-controller@100000 { 446 compatible = "qcom,gcc-sm6350"; 447 reg = <0 0x00100000 0 0x1f0000>; 448 #clock-cells = <1>; 449 #reset-cells = <1>; 450 #power-domain-cells = <1>; 451 clock-names = "bi_tcxo", 452 "bi_tcxo_ao", 453 "sleep_clk"; 454 clocks = <&rpmhcc RPMH_CXO_CLK>, 455 <&rpmhcc RPMH_CXO_CLK_A>, 456 <&sleep_clk>; 457 }; 458 459 ipcc: mailbox@408000 { 460 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 461 reg = <0 0x00408000 0 0x1000>; 462 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-controller; 464 #interrupt-cells = <3>; 465 #mbox-cells = <2>; 466 }; 467 468 rng: rng@793000 { 469 compatible = "qcom,prng-ee"; 470 reg = <0 0x00793000 0 0x1000>; 471 clocks = <&gcc GCC_PRNG_AHB_CLK>; 472 clock-names = "core"; 473 }; 474 475 sdhc_1: sdhci@7c4000 { 476 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 477 reg = <0 0x007c4000 0 0x1000>, 478 <0 0x007c5000 0 0x1000>, 479 <0 0x007c8000 0 0x8000>; 480 reg-names = "hc", "cqhci", "ice"; 481 482 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "hc_irq", "pwr_irq"; 485 486 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 487 <&gcc GCC_SDCC1_APPS_CLK>, 488 <&rpmhcc RPMH_CXO_CLK>; 489 clock-names = "iface", "core", "xo"; 490 qcom,dll-config = <0x000f642c>; 491 qcom,ddr-config = <0x80040868>; 492 power-domains = <&rpmhpd 0>; 493 operating-points-v2 = <&sdhc1_opp_table>; 494 bus-width = <8>; 495 non-removable; 496 supports-cqe; 497 498 status = "disabled"; 499 500 sdhc1_opp_table: sdhc1-opp-table { 501 compatible = "operating-points-v2"; 502 503 opp-19200000 { 504 opp-hz = /bits/ 64 <19200000>; 505 required-opps = <&rpmhpd_opp_min_svs>; 506 }; 507 508 opp-100000000 { 509 opp-hz = /bits/ 64 <100000000>; 510 required-opps = <&rpmhpd_opp_low_svs>; 511 }; 512 513 opp-384000000 { 514 opp-hz = /bits/ 64 <384000000>; 515 required-opps = <&rpmhpd_opp_svs_l1>; 516 }; 517 }; 518 }; 519 520 qupv3_id_0: geniqup@8c0000 { 521 compatible = "qcom,geni-se-qup"; 522 reg = <0x0 0x8c0000 0x0 0x2000>; 523 clock-names = "m-ahb", "s-ahb"; 524 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 525 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 526 #address-cells = <2>; 527 #size-cells = <2>; 528 iommus = <&apps_smmu 0x43 0x0>; 529 ranges; 530 status = "disabled"; 531 532 i2c0: i2c@880000 { 533 compatible = "qcom,geni-i2c"; 534 reg = <0 0x00880000 0 0x4000>; 535 clock-names = "se"; 536 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&qup_i2c0_default>; 539 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 status = "disabled"; 543 }; 544 545 i2c2: i2c@888000 { 546 compatible = "qcom,geni-i2c"; 547 reg = <0 0x00888000 0 0x4000>; 548 clock-names = "se"; 549 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&qup_i2c2_default>; 552 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 status = "disabled"; 556 }; 557 }; 558 559 qupv3_id_1: geniqup@9c0000 { 560 compatible = "qcom,geni-se-qup"; 561 reg = <0x0 0x9c0000 0x0 0x2000>; 562 clock-names = "m-ahb", "s-ahb"; 563 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 564 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 565 #address-cells = <2>; 566 #size-cells = <2>; 567 iommus = <&apps_smmu 0x4c3 0x0>; 568 ranges; 569 status = "disabled"; 570 571 i2c6: i2c@980000 { 572 compatible = "qcom,geni-i2c"; 573 reg = <0 0x00980000 0 0x4000>; 574 clock-names = "se"; 575 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&qup_i2c6_default>; 578 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 584 i2c7: i2c@984000 { 585 compatible = "qcom,geni-i2c"; 586 reg = <0 0x00984000 0 0x4000>; 587 clock-names = "se"; 588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&qup_i2c7_default>; 591 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 }; 596 597 i2c8: i2c@988000 { 598 compatible = "qcom,geni-i2c"; 599 reg = <0 0x00988000 0 0x4000>; 600 clock-names = "se"; 601 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&qup_i2c8_default>; 604 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 uart9: serial@98c000 { 611 compatible = "qcom,geni-debug-uart"; 612 reg = <0 0x98c000 0 0x4000>; 613 clock-names = "se"; 614 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&qup_uart9_default>; 617 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 618 status = "disabled"; 619 }; 620 621 i2c10: i2c@990000 { 622 compatible = "qcom,geni-i2c"; 623 reg = <0 0x00990000 0 0x4000>; 624 clock-names = "se"; 625 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&qup_i2c10_default>; 628 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 status = "disabled"; 632 }; 633 634 }; 635 636 ufs_mem_hc: ufs@1d84000 { 637 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 638 "jedec,ufs-2.0"; 639 reg = <0 0x01d84000 0 0x3000>, 640 <0 0x01d90000 0 0x8000>; 641 reg-names = "std", "ice"; 642 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 643 phys = <&ufs_mem_phy_lanes>; 644 phy-names = "ufsphy"; 645 lanes-per-direction = <2>; 646 #reset-cells = <1>; 647 resets = <&gcc GCC_UFS_PHY_BCR>; 648 reset-names = "rst"; 649 650 power-domains = <&gcc UFS_PHY_GDSC>; 651 652 iommus = <&apps_smmu 0x80 0x0>; 653 654 clock-names = "core_clk", 655 "bus_aggr_clk", 656 "iface_clk", 657 "core_clk_unipro", 658 "ref_clk", 659 "tx_lane0_sync_clk", 660 "rx_lane0_sync_clk", 661 "rx_lane1_sync_clk", 662 "ice_core_clk"; 663 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 664 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 665 <&gcc GCC_UFS_PHY_AHB_CLK>, 666 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 667 <&rpmhcc RPMH_QLINK_CLK>, 668 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 669 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 670 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 671 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 672 freq-table-hz = 673 <50000000 200000000>, 674 <0 0>, 675 <0 0>, 676 <37500000 150000000>, 677 <75000000 300000000>, 678 <0 0>, 679 <0 0>, 680 <0 0>, 681 <0 0>; 682 683 status = "disabled"; 684 }; 685 686 ufs_mem_phy: phy@1d87000 { 687 compatible = "qcom,sm6350-qmp-ufs-phy"; 688 reg = <0 0x01d87000 0 0x18c>; 689 #address-cells = <2>; 690 #size-cells = <2>; 691 ranges; 692 693 clock-names = "ref", 694 "ref_aux"; 695 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 696 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 697 698 resets = <&ufs_mem_hc 0>; 699 reset-names = "ufsphy"; 700 701 status = "disabled"; 702 703 ufs_mem_phy_lanes: phy@1d87400 { 704 reg = <0 0x01d87400 0 0x128>, 705 <0 0x01d87600 0 0x1fc>, 706 <0 0x01d87c00 0 0x1dc>, 707 <0 0x01d87800 0 0x128>, 708 <0 0x01d87a00 0 0x1fc>; 709 #phy-cells = <0>; 710 }; 711 }; 712 713 tcsr_mutex: hwlock@1f40000 { 714 compatible = "qcom,tcsr-mutex"; 715 reg = <0x0 0x01f40000 0x0 0x40000>; 716 #hwlock-cells = <1>; 717 }; 718 719 adsp: remoteproc@3000000 { 720 compatible = "qcom,sm6350-adsp-pas"; 721 reg = <0 0x03000000 0 0x100>; 722 723 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 724 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 725 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 726 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 727 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 728 interrupt-names = "wdog", "fatal", "ready", 729 "handover", "stop-ack"; 730 731 clocks = <&rpmhcc RPMH_CXO_CLK>; 732 clock-names = "xo"; 733 734 power-domains = <&rpmhpd SM6350_LCX>, 735 <&rpmhpd SM6350_LMX>; 736 power-domain-names = "lcx", "lmx"; 737 738 memory-region = <&pil_adsp_mem>; 739 740 qcom,qmp = <&aoss_qmp>; 741 742 qcom,smem-states = <&smp2p_adsp_out 0>; 743 qcom,smem-state-names = "stop"; 744 745 status = "disabled"; 746 747 glink-edge { 748 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 749 IPCC_MPROC_SIGNAL_GLINK_QMP 750 IRQ_TYPE_EDGE_RISING>; 751 mboxes = <&ipcc IPCC_CLIENT_LPASS 752 IPCC_MPROC_SIGNAL_GLINK_QMP>; 753 754 label = "lpass"; 755 qcom,remote-pid = <2>; 756 757 fastrpc { 758 compatible = "qcom,fastrpc"; 759 qcom,glink-channels = "fastrpcglink-apps-dsp"; 760 label = "adsp"; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 764 compute-cb@3 { 765 compatible = "qcom,fastrpc-compute-cb"; 766 reg = <3>; 767 iommus = <&apps_smmu 0x1003 0x0>; 768 }; 769 770 compute-cb@4 { 771 compatible = "qcom,fastrpc-compute-cb"; 772 reg = <4>; 773 iommus = <&apps_smmu 0x1004 0x0>; 774 }; 775 776 compute-cb@5 { 777 compatible = "qcom,fastrpc-compute-cb"; 778 reg = <5>; 779 iommus = <&apps_smmu 0x1005 0x0>; 780 qcom,nsessions = <5>; 781 }; 782 }; 783 }; 784 }; 785 786 mpss: remoteproc@4080000 { 787 compatible = "qcom,sm6350-mpss-pas"; 788 reg = <0x0 0x04080000 0x0 0x4040>; 789 790 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 791 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 792 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 793 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 794 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 795 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 796 interrupt-names = "wdog", "fatal", "ready", "handover", 797 "stop-ack", "shutdown-ack"; 798 799 clocks = <&rpmhcc RPMH_CXO_CLK>; 800 clock-names = "xo"; 801 802 power-domains = <&rpmhpd SM6350_CX>, 803 <&rpmhpd SM6350_MSS>; 804 power-domain-names = "cx", "mss"; 805 806 memory-region = <&pil_modem_mem>; 807 808 qcom,qmp = <&aoss_qmp>; 809 810 qcom,smem-states = <&modem_smp2p_out 0>; 811 qcom,smem-state-names = "stop"; 812 813 status = "disabled"; 814 815 glink-edge { 816 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 817 IPCC_MPROC_SIGNAL_GLINK_QMP 818 IRQ_TYPE_EDGE_RISING>; 819 mboxes = <&ipcc IPCC_CLIENT_MPSS 820 IPCC_MPROC_SIGNAL_GLINK_QMP>; 821 label = "modem"; 822 qcom,remote-pid = <1>; 823 }; 824 }; 825 826 cdsp: remoteproc@8300000 { 827 compatible = "qcom,sm6350-cdsp-pas"; 828 reg = <0 0x08300000 0 0x10000>; 829 830 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 831 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 832 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 833 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 834 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 835 interrupt-names = "wdog", "fatal", "ready", 836 "handover", "stop-ack"; 837 838 clocks = <&rpmhcc RPMH_CXO_CLK>; 839 clock-names = "xo"; 840 841 power-domains = <&rpmhpd SM6350_CX>, 842 <&rpmhpd SM6350_MX>; 843 power-domain-names = "cx", "mx"; 844 845 memory-region = <&pil_cdsp_mem>; 846 847 qcom,qmp = <&aoss_qmp>; 848 849 qcom,smem-states = <&smp2p_cdsp_out 0>; 850 qcom,smem-state-names = "stop"; 851 852 status = "disabled"; 853 854 glink-edge { 855 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 856 IPCC_MPROC_SIGNAL_GLINK_QMP 857 IRQ_TYPE_EDGE_RISING>; 858 mboxes = <&ipcc IPCC_CLIENT_CDSP 859 IPCC_MPROC_SIGNAL_GLINK_QMP>; 860 861 label = "cdsp"; 862 qcom,remote-pid = <5>; 863 864 fastrpc { 865 compatible = "qcom,fastrpc"; 866 qcom,glink-channels = "fastrpcglink-apps-dsp"; 867 label = "cdsp"; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 871 compute-cb@1 { 872 compatible = "qcom,fastrpc-compute-cb"; 873 reg = <1>; 874 iommus = <&apps_smmu 0x1401 0x20>; 875 }; 876 877 compute-cb@2 { 878 compatible = "qcom,fastrpc-compute-cb"; 879 reg = <2>; 880 iommus = <&apps_smmu 0x1402 0x20>; 881 }; 882 883 compute-cb@3 { 884 compatible = "qcom,fastrpc-compute-cb"; 885 reg = <3>; 886 iommus = <&apps_smmu 0x1403 0x20>; 887 }; 888 889 compute-cb@4 { 890 compatible = "qcom,fastrpc-compute-cb"; 891 reg = <4>; 892 iommus = <&apps_smmu 0x1404 0x20>; 893 }; 894 895 compute-cb@5 { 896 compatible = "qcom,fastrpc-compute-cb"; 897 reg = <5>; 898 iommus = <&apps_smmu 0x1405 0x20>; 899 }; 900 901 compute-cb@6 { 902 compatible = "qcom,fastrpc-compute-cb"; 903 reg = <6>; 904 iommus = <&apps_smmu 0x1406 0x20>; 905 }; 906 907 compute-cb@7 { 908 compatible = "qcom,fastrpc-compute-cb"; 909 reg = <7>; 910 iommus = <&apps_smmu 0x1407 0x20>; 911 }; 912 913 compute-cb@8 { 914 compatible = "qcom,fastrpc-compute-cb"; 915 reg = <8>; 916 iommus = <&apps_smmu 0x1408 0x20>; 917 }; 918 919 /* note: secure cb9 in downstream */ 920 }; 921 }; 922 }; 923 924 sdhc_2: sdhci@8804000 { 925 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 926 reg = <0 0x08804000 0 0x1000>; 927 928 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "hc_irq", "pwr_irq"; 931 932 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 933 <&gcc GCC_SDCC2_APPS_CLK>, 934 <&rpmhcc RPMH_CXO_CLK>; 935 clock-names = "iface", "core", "xo"; 936 qcom,dll-config = <0x0007642c>; 937 qcom,ddr-config = <0x80040868>; 938 power-domains = <&rpmhpd 0>; 939 operating-points-v2 = <&sdhc2_opp_table>; 940 bus-width = <4>; 941 942 status = "disabled"; 943 944 sdhc2_opp_table: sdhc2-opp-table { 945 compatible = "operating-points-v2"; 946 947 opp-100000000 { 948 opp-hz = /bits/ 64 <100000000>; 949 required-opps = <&rpmhpd_opp_svs_l1>; 950 }; 951 952 opp-202000000 { 953 opp-hz = /bits/ 64 <202000000>; 954 required-opps = <&rpmhpd_opp_nom>; 955 }; 956 }; 957 }; 958 959 usb_1_hsphy: phy@88e3000 { 960 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 961 reg = <0 0x088e3000 0 0x400>; 962 status = "disabled"; 963 #phy-cells = <0>; 964 965 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 966 clock-names = "cfg_ahb", "ref"; 967 968 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 969 }; 970 971 usb_1_qmpphy: phy@88e9000 { 972 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 973 reg = <0 0x088e9000 0 0x200>, 974 <0 0x088e8000 0 0x40>, 975 <0 0x088ea000 0 0x200>; 976 status = "disabled"; 977 #address-cells = <2>; 978 #size-cells = <2>; 979 ranges; 980 981 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 982 <&xo_board>, 983 <&rpmhcc RPMH_QLINK_CLK>, 984 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 985 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 986 987 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 988 <&gcc GCC_USB3_PHY_PRIM_BCR>; 989 reset-names = "phy", "common"; 990 991 usb_1_ssphy: usb3-phy@88e9200 { 992 reg = <0 0x088e9200 0 0x200>, 993 <0 0x088e9400 0 0x200>, 994 <0 0x088e9c00 0 0x400>, 995 <0 0x088e9600 0 0x200>, 996 <0 0x088e9800 0 0x200>, 997 <0 0x088e9a00 0 0x100>; 998 #clock-cells = <0>; 999 #phy-cells = <0>; 1000 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1001 clock-names = "pipe0"; 1002 clock-output-names = "usb3_phy_pipe_clk_src"; 1003 }; 1004 1005 dp_phy: dp-phy@88ea200 { 1006 reg = <0 0x088ea200 0 0x200>, 1007 <0 0x088ea400 0 0x200>, 1008 <0 0x088eac00 0 0x400>, 1009 <0 0x088ea600 0 0x200>, 1010 <0 0x088ea800 0 0x200>, 1011 <0 0x088eaa00 0 0x100>; 1012 #phy-cells = <0>; 1013 #clock-cells = <1>; 1014 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1015 clock-names = "pipe0"; 1016 clock-output-names = "usb3_phy_pipe_clk_src"; 1017 }; 1018 }; 1019 1020 system-cache-controller@9200000 { 1021 compatible = "qcom,sm6350-llcc"; 1022 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1023 reg-names = "llcc_base", "llcc_broadcast_base"; 1024 }; 1025 1026 usb_1: usb@a6f8800 { 1027 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1028 reg = <0 0x0a6f8800 0 0x400>; 1029 status = "disabled"; 1030 #address-cells = <2>; 1031 #size-cells = <2>; 1032 ranges; 1033 1034 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1035 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1036 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1037 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1038 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1039 clock-names = "cfg_noc", 1040 "core", 1041 "iface", 1042 "sleep", 1043 "mock_utmi"; 1044 1045 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1046 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1047 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1048 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1049 1050 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1051 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1052 1053 power-domains = <&gcc USB30_PRIM_GDSC>; 1054 1055 resets = <&gcc GCC_USB30_PRIM_BCR>; 1056 1057 usb_1_dwc3: usb@a600000 { 1058 compatible = "snps,dwc3"; 1059 reg = <0 0x0a600000 0 0xcd00>; 1060 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1061 iommus = <&apps_smmu 0x540 0x0>; 1062 snps,dis_u2_susphy_quirk; 1063 snps,dis_enblslpm_quirk; 1064 snps,has-lpm-erratum; 1065 snps,hird-threshold = /bits/ 8 <0x10>; 1066 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1067 phy-names = "usb2-phy", "usb3-phy"; 1068 }; 1069 }; 1070 1071 pdc: interrupt-controller@b220000 { 1072 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1073 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1074 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1075 <125 63 1>, <126 655 12>, <138 139 15>; 1076 #interrupt-cells = <2>; 1077 interrupt-parent = <&intc>; 1078 interrupt-controller; 1079 }; 1080 1081 tsens0: thermal-sensor@c263000 { 1082 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1083 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1084 <0 0x0c222000 0 0x8>; /* SROT */ 1085 #qcom,sensors = <16>; 1086 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1087 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1088 interrupt-names = "uplow", "critical"; 1089 #thermal-sensor-cells = <1>; 1090 }; 1091 1092 tsens1: thermal-sensor@c265000 { 1093 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1094 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1095 <0 0x0c223000 0 0x8>; /* SROT */ 1096 #qcom,sensors = <16>; 1097 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1098 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1099 interrupt-names = "uplow", "critical"; 1100 #thermal-sensor-cells = <1>; 1101 }; 1102 1103 aoss_qmp: power-controller@c300000 { 1104 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1105 reg = <0 0x0c300000 0 0x1000>; 1106 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1107 IRQ_TYPE_EDGE_RISING>; 1108 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1109 1110 #clock-cells = <0>; 1111 }; 1112 1113 spmi_bus: spmi@c440000 { 1114 compatible = "qcom,spmi-pmic-arb"; 1115 reg = <0 0xc440000 0 0x1100>, 1116 <0 0xc600000 0 0x2000000>, 1117 <0 0xe600000 0 0x100000>, 1118 <0 0xe700000 0 0xa0000>, 1119 <0 0xc40a000 0 0x26000>; 1120 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1121 interrupt-names = "periph_irq"; 1122 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1123 qcom,ee = <0>; 1124 qcom,channel = <0>; 1125 #address-cells = <2>; 1126 #size-cells = <0>; 1127 interrupt-controller; 1128 #interrupt-cells = <4>; 1129 }; 1130 1131 tlmm: pinctrl@f100000 { 1132 compatible = "qcom,sm6350-tlmm"; 1133 reg = <0 0x0f100000 0 0x300000>; 1134 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1143 gpio-controller; 1144 #gpio-cells = <2>; 1145 interrupt-controller; 1146 #interrupt-cells = <2>; 1147 gpio-ranges = <&tlmm 0 0 157>; 1148 1149 qup_uart9_default: qup-uart9-default { 1150 pins = "gpio25", "gpio26"; 1151 function = "qup13_f2"; 1152 drive-strength = <2>; 1153 bias-disable; 1154 }; 1155 1156 qup_i2c0_default: qup-i2c0-default { 1157 pins = "gpio0", "gpio1"; 1158 function = "qup00"; 1159 drive-strength = <2>; 1160 bias-pull-up; 1161 }; 1162 1163 qup_i2c2_default: qup-i2c2-default { 1164 pins = "gpio45", "gpio46"; 1165 function = "qup02"; 1166 drive-strength = <2>; 1167 bias-pull-up; 1168 }; 1169 1170 qup_i2c6_default: qup-i2c6-default { 1171 pins = "gpio13", "gpio14"; 1172 function = "qup10"; 1173 drive-strength = <2>; 1174 bias-pull-up; 1175 }; 1176 1177 qup_i2c7_default: qup-i2c7-default { 1178 pins = "gpio27", "gpio28"; 1179 function = "qup11"; 1180 drive-strength = <2>; 1181 bias-pull-up; 1182 }; 1183 1184 qup_i2c8_default: qup-i2c8-default { 1185 pins = "gpio19", "gpio20"; 1186 function = "qup12"; 1187 drive-strength = <2>; 1188 bias-pull-up; 1189 }; 1190 1191 qup_i2c10_default: qup-i2c10-default { 1192 pins = "gpio4", "gpio5"; 1193 function = "qup14"; 1194 drive-strength = <2>; 1195 bias-pull-up; 1196 }; 1197 }; 1198 1199 apps_smmu: iommu@15000000 { 1200 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1201 reg = <0 0x15000000 0 0x100000>; 1202 #iommu-cells = <2>; 1203 #global-interrupts = <1>; 1204 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1285 }; 1286 1287 intc: interrupt-controller@17a00000 { 1288 compatible = "arm,gic-v3"; 1289 #interrupt-cells = <3>; 1290 interrupt-controller; 1291 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1292 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1293 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1294 }; 1295 1296 watchdog@17c10000 { 1297 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 1298 reg = <0 0x17c10000 0 0x1000>; 1299 clocks = <&sleep_clk>; 1300 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1301 }; 1302 1303 timer@17c20000 { 1304 compatible = "arm,armv7-timer-mem"; 1305 reg = <0x0 0x17c20000 0x0 0x1000>; 1306 clock-frequency = <19200000>; 1307 #address-cells = <2>; 1308 #size-cells = <2>; 1309 ranges; 1310 1311 frame@17c21000 { 1312 frame-number = <0>; 1313 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1315 reg = <0x0 0x17c21000 0x0 0x1000>, 1316 <0x0 0x17c22000 0x0 0x1000>; 1317 }; 1318 1319 frame@17c23000 { 1320 frame-number = <1>; 1321 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1322 reg = <0x0 0x17c23000 0x0 0x1000>; 1323 status = "disabled"; 1324 }; 1325 1326 frame@17c25000 { 1327 frame-number = <2>; 1328 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1329 reg = <0x0 0x17c25000 0x0 0x1000>; 1330 status = "disabled"; 1331 }; 1332 1333 frame@17c27000 { 1334 frame-number = <3>; 1335 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1336 reg = <0x0 0x17c27000 0x0 0x1000>; 1337 status = "disabled"; 1338 }; 1339 1340 frame@17c29000 { 1341 frame-number = <4>; 1342 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1343 reg = <0x0 0x17c29000 0x0 0x1000>; 1344 status = "disabled"; 1345 }; 1346 1347 frame@17c2b000 { 1348 frame-number = <5>; 1349 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1350 reg = <0x0 0x17c2b000 0x0 0x1000>; 1351 status = "disabled"; 1352 }; 1353 1354 frame@17c2d000 { 1355 frame-number = <6>; 1356 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1357 reg = <0x0 0x17c2d000 0x0 0x1000>; 1358 status = "disabled"; 1359 }; 1360 }; 1361 1362 wifi: wifi@18800000 { 1363 compatible = "qcom,wcn3990-wifi"; 1364 reg = <0 0x18800000 0 0x800000>; 1365 reg-names = "membase"; 1366 memory-region = <&wlan_fw_mem>; 1367 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1379 iommus = <&apps_smmu 0x20 0x1>; 1380 qcom,msa-fixed-perm; 1381 status = "disabled"; 1382 }; 1383 1384 apps_rsc: rsc@18200000 { 1385 compatible = "qcom,rpmh-rsc"; 1386 label = "apps_rsc"; 1387 reg = <0x0 0x18200000 0x0 0x10000>, 1388 <0x0 0x18210000 0x0 0x10000>, 1389 <0x0 0x18220000 0x0 0x10000>; 1390 reg-names = "drv-0", "drv-1", "drv-2"; 1391 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1394 qcom,tcs-offset = <0xd00>; 1395 qcom,drv-id = <2>; 1396 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1397 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1398 1399 rpmhcc: clock-controller { 1400 compatible = "qcom,sm6350-rpmh-clk"; 1401 #clock-cells = <1>; 1402 clock-names = "xo"; 1403 clocks = <&xo_board>; 1404 }; 1405 1406 rpmhpd: power-controller { 1407 compatible = "qcom,sm6350-rpmhpd"; 1408 #power-domain-cells = <1>; 1409 operating-points-v2 = <&rpmhpd_opp_table>; 1410 1411 rpmhpd_opp_table: opp-table { 1412 compatible = "operating-points-v2"; 1413 1414 rpmhpd_opp_ret: opp1 { 1415 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1416 }; 1417 1418 rpmhpd_opp_min_svs: opp2 { 1419 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1420 }; 1421 1422 rpmhpd_opp_low_svs: opp3 { 1423 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1424 }; 1425 1426 rpmhpd_opp_svs: opp4 { 1427 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1428 }; 1429 1430 rpmhpd_opp_svs_l1: opp5 { 1431 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1432 }; 1433 1434 rpmhpd_opp_nom: opp6 { 1435 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1436 }; 1437 1438 rpmhpd_opp_nom_l1: opp7 { 1439 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1440 }; 1441 1442 rpmhpd_opp_nom_l2: opp8 { 1443 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1444 }; 1445 1446 rpmhpd_opp_turbo: opp9 { 1447 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1448 }; 1449 1450 rpmhpd_opp_turbo_l1: opp10 { 1451 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1452 }; 1453 }; 1454 }; 1455 1456 apps_bcm_voter: bcm-voter { 1457 compatible = "qcom,bcm-voter"; 1458 }; 1459 }; 1460 1461 cpufreq_hw: cpufreq@18323000 { 1462 compatible = "qcom,cpufreq-hw"; 1463 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 1464 reg-names = "freq-domain0", "freq-domain1"; 1465 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1466 clock-names = "xo", "alternate"; 1467 1468 #freq-domain-cells = <1>; 1469 }; 1470 }; 1471 1472 timer { 1473 compatible = "arm,armv8-timer"; 1474 clock-frequency = <19200000>; 1475 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1476 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1477 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1478 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1479 }; 1480}; 1481