1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) 6 #define _DPU_TRACE_H_ 7 8 #include <linux/stringify.h> 9 #include <linux/types.h> 10 #include <linux/tracepoint.h> 11 12 #include <drm/drm_rect.h> 13 #include "dpu_crtc.h" 14 #include "dpu_encoder_phys.h" 15 #include "dpu_hw_mdss.h" 16 #include "dpu_hw_vbif.h" 17 #include "dpu_plane.h" 18 19 #undef TRACE_SYSTEM 20 #define TRACE_SYSTEM dpu 21 #undef TRACE_INCLUDE_FILE 22 #define TRACE_INCLUDE_FILE dpu_trace 23 24 TRACE_EVENT(dpu_perf_set_qos_luts, 25 TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl, 26 u32 lut, u32 lut_usage), 27 TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage), 28 TP_STRUCT__entry( 29 __field(u32, pnum) 30 __field(u32, fmt) 31 __field(bool, rt) 32 __field(u32, fl) 33 __field(u64, lut) 34 __field(u32, lut_usage) 35 ), 36 TP_fast_assign( 37 __entry->pnum = pnum; 38 __entry->fmt = fmt; 39 __entry->rt = rt; 40 __entry->fl = fl; 41 __entry->lut = lut; 42 __entry->lut_usage = lut_usage; 43 ), 44 TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d", 45 __entry->pnum, __entry->fmt, 46 __entry->rt, __entry->fl, 47 __entry->lut, __entry->lut_usage) 48 ); 49 50 TRACE_EVENT(dpu_perf_set_danger_luts, 51 TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut, 52 u32 safe_lut), 53 TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut), 54 TP_STRUCT__entry( 55 __field(u32, pnum) 56 __field(u32, fmt) 57 __field(u32, mode) 58 __field(u32, danger_lut) 59 __field(u32, safe_lut) 60 ), 61 TP_fast_assign( 62 __entry->pnum = pnum; 63 __entry->fmt = fmt; 64 __entry->mode = mode; 65 __entry->danger_lut = danger_lut; 66 __entry->safe_lut = safe_lut; 67 ), 68 TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]", 69 __entry->pnum, __entry->fmt, 70 __entry->mode, __entry->danger_lut, 71 __entry->safe_lut) 72 ); 73 74 TRACE_EVENT(dpu_perf_set_ot, 75 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx), 76 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx), 77 TP_STRUCT__entry( 78 __field(u32, pnum) 79 __field(u32, xin_id) 80 __field(u32, rd_lim) 81 __field(u32, vbif_idx) 82 ), 83 TP_fast_assign( 84 __entry->pnum = pnum; 85 __entry->xin_id = xin_id; 86 __entry->rd_lim = rd_lim; 87 __entry->vbif_idx = vbif_idx; 88 ), 89 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d", 90 __entry->pnum, __entry->xin_id, __entry->rd_lim, 91 __entry->vbif_idx) 92 ) 93 94 TRACE_EVENT(dpu_cmd_release_bw, 95 TP_PROTO(u32 crtc_id), 96 TP_ARGS(crtc_id), 97 TP_STRUCT__entry( 98 __field(u32, crtc_id) 99 ), 100 TP_fast_assign( 101 __entry->crtc_id = crtc_id; 102 ), 103 TP_printk("crtc:%d", __entry->crtc_id) 104 ); 105 106 TRACE_EVENT(tracing_mark_write, 107 TP_PROTO(int pid, const char *name, bool trace_begin), 108 TP_ARGS(pid, name, trace_begin), 109 TP_STRUCT__entry( 110 __field(int, pid) 111 __string(trace_name, name) 112 __field(bool, trace_begin) 113 ), 114 TP_fast_assign( 115 __entry->pid = pid; 116 __assign_str(trace_name, name); 117 __entry->trace_begin = trace_begin; 118 ), 119 TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E", 120 __entry->pid, __get_str(trace_name)) 121 ) 122 123 TRACE_EVENT(dpu_trace_counter, 124 TP_PROTO(int pid, char *name, int value), 125 TP_ARGS(pid, name, value), 126 TP_STRUCT__entry( 127 __field(int, pid) 128 __string(counter_name, name) 129 __field(int, value) 130 ), 131 TP_fast_assign( 132 __entry->pid = current->tgid; 133 __assign_str(counter_name, name); 134 __entry->value = value; 135 ), 136 TP_printk("%d|%s|%d", __entry->pid, 137 __get_str(counter_name), __entry->value) 138 ) 139 140 TRACE_EVENT(dpu_perf_crtc_update, 141 TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate, 142 bool stop_req, bool update_bus, bool update_clk), 143 TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk), 144 TP_STRUCT__entry( 145 __field(u32, crtc) 146 __field(u64, bw_ctl) 147 __field(u32, core_clk_rate) 148 __field(bool, stop_req) 149 __field(u32, update_bus) 150 __field(u32, update_clk) 151 ), 152 TP_fast_assign( 153 __entry->crtc = crtc; 154 __entry->bw_ctl = bw_ctl; 155 __entry->core_clk_rate = core_clk_rate; 156 __entry->stop_req = stop_req; 157 __entry->update_bus = update_bus; 158 __entry->update_clk = update_clk; 159 ), 160 TP_printk( 161 "crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d", 162 __entry->crtc, 163 __entry->bw_ctl, 164 __entry->core_clk_rate, 165 __entry->stop_req, 166 __entry->update_bus, 167 __entry->update_clk) 168 ); 169 170 DECLARE_EVENT_CLASS(dpu_enc_irq_template, 171 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, 172 int irq_idx), 173 TP_ARGS(drm_id, intr_idx, irq_idx), 174 TP_STRUCT__entry( 175 __field( uint32_t, drm_id ) 176 __field( enum dpu_intr_idx, intr_idx ) 177 __field( int, irq_idx ) 178 ), 179 TP_fast_assign( 180 __entry->drm_id = drm_id; 181 __entry->intr_idx = intr_idx; 182 __entry->irq_idx = irq_idx; 183 ), 184 TP_printk("id=%u, intr=%d, irq=%d", 185 __entry->drm_id, __entry->intr_idx, 186 __entry->irq_idx) 187 ); 188 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success, 189 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, 190 int irq_idx), 191 TP_ARGS(drm_id, intr_idx, irq_idx) 192 ); 193 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success, 194 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, 195 int irq_idx), 196 TP_ARGS(drm_id, intr_idx, irq_idx) 197 ); 198 199 TRACE_EVENT(dpu_enc_irq_wait_success, 200 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, 201 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt), 202 TP_ARGS(drm_id, intr_idx, irq_idx, pp_idx, atomic_cnt), 203 TP_STRUCT__entry( 204 __field( uint32_t, drm_id ) 205 __field( enum dpu_intr_idx, intr_idx ) 206 __field( int, irq_idx ) 207 __field( enum dpu_pingpong, pp_idx ) 208 __field( int, atomic_cnt ) 209 ), 210 TP_fast_assign( 211 __entry->drm_id = drm_id; 212 __entry->intr_idx = intr_idx; 213 __entry->irq_idx = irq_idx; 214 __entry->pp_idx = pp_idx; 215 __entry->atomic_cnt = atomic_cnt; 216 ), 217 TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d", 218 __entry->drm_id, __entry->intr_idx, 219 __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt) 220 ); 221 222 DECLARE_EVENT_CLASS(dpu_drm_obj_template, 223 TP_PROTO(uint32_t drm_id), 224 TP_ARGS(drm_id), 225 TP_STRUCT__entry( 226 __field( uint32_t, drm_id ) 227 ), 228 TP_fast_assign( 229 __entry->drm_id = drm_id; 230 ), 231 TP_printk("id=%u", __entry->drm_id) 232 ); 233 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check, 234 TP_PROTO(uint32_t drm_id), 235 TP_ARGS(drm_id) 236 ); 237 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set, 238 TP_PROTO(uint32_t drm_id), 239 TP_ARGS(drm_id) 240 ); 241 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable, 242 TP_PROTO(uint32_t drm_id), 243 TP_ARGS(drm_id) 244 ); 245 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff, 246 TP_PROTO(uint32_t drm_id), 247 TP_ARGS(drm_id) 248 ); 249 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff, 250 TP_PROTO(uint32_t drm_id), 251 TP_ARGS(drm_id) 252 ); 253 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset, 254 TP_PROTO(uint32_t drm_id), 255 TP_ARGS(drm_id) 256 ); 257 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip, 258 TP_PROTO(uint32_t drm_id), 259 TP_ARGS(drm_id) 260 ); 261 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb, 262 TP_PROTO(uint32_t drm_id), 263 TP_ARGS(drm_id) 264 ); 265 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit, 266 TP_PROTO(uint32_t drm_id), 267 TP_ARGS(drm_id) 268 ); 269 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit, 270 TP_PROTO(uint32_t drm_id), 271 TP_ARGS(drm_id) 272 ); 273 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done, 274 TP_PROTO(uint32_t drm_id), 275 TP_ARGS(drm_id) 276 ); 277 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume, 278 TP_PROTO(uint32_t drm_id), 279 TP_ARGS(drm_id) 280 ); 281 282 TRACE_EVENT(dpu_enc_enable, 283 TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay), 284 TP_ARGS(drm_id, hdisplay, vdisplay), 285 TP_STRUCT__entry( 286 __field( uint32_t, drm_id ) 287 __field( int, hdisplay ) 288 __field( int, vdisplay ) 289 ), 290 TP_fast_assign( 291 __entry->drm_id = drm_id; 292 __entry->hdisplay = hdisplay; 293 __entry->vdisplay = vdisplay; 294 ), 295 TP_printk("id=%u, mode=%dx%d", 296 __entry->drm_id, __entry->hdisplay, __entry->vdisplay) 297 ); 298 299 DECLARE_EVENT_CLASS(dpu_enc_keyval_template, 300 TP_PROTO(uint32_t drm_id, int val), 301 TP_ARGS(drm_id, val), 302 TP_STRUCT__entry( 303 __field( uint32_t, drm_id ) 304 __field( int, val ) 305 ), 306 TP_fast_assign( 307 __entry->drm_id = drm_id; 308 __entry->val = val; 309 ), 310 TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val) 311 ); 312 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb, 313 TP_PROTO(uint32_t drm_id, int count), 314 TP_ARGS(drm_id, count) 315 ); 316 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start, 317 TP_PROTO(uint32_t drm_id, int ctl_idx), 318 TP_ARGS(drm_id, ctl_idx) 319 ); 320 321 TRACE_EVENT(dpu_enc_atomic_check_flags, 322 TP_PROTO(uint32_t drm_id, unsigned int flags), 323 TP_ARGS(drm_id, flags), 324 TP_STRUCT__entry( 325 __field( uint32_t, drm_id ) 326 __field( unsigned int, flags ) 327 ), 328 TP_fast_assign( 329 __entry->drm_id = drm_id; 330 __entry->flags = flags; 331 ), 332 TP_printk("id=%u, flags=%u", 333 __entry->drm_id, __entry->flags) 334 ); 335 336 DECLARE_EVENT_CLASS(dpu_enc_id_enable_template, 337 TP_PROTO(uint32_t drm_id, bool enable), 338 TP_ARGS(drm_id, enable), 339 TP_STRUCT__entry( 340 __field( uint32_t, drm_id ) 341 __field( bool, enable ) 342 ), 343 TP_fast_assign( 344 __entry->drm_id = drm_id; 345 __entry->enable = enable; 346 ), 347 TP_printk("id=%u, enable=%s", 348 __entry->drm_id, __entry->enable ? "true" : "false") 349 ); 350 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper, 351 TP_PROTO(uint32_t drm_id, bool enable), 352 TP_ARGS(drm_id, enable) 353 ); 354 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb, 355 TP_PROTO(uint32_t drm_id, bool enable), 356 TP_ARGS(drm_id, enable) 357 ); 358 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb, 359 TP_PROTO(uint32_t drm_id, bool enable), 360 TP_ARGS(drm_id, enable) 361 ); 362 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te, 363 TP_PROTO(uint32_t drm_id, bool enable), 364 TP_ARGS(drm_id, enable) 365 ); 366 367 TRACE_EVENT(dpu_enc_rc, 368 TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported, 369 int rc_state, const char *stage), 370 TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage), 371 TP_STRUCT__entry( 372 __field( uint32_t, drm_id ) 373 __field( u32, sw_event ) 374 __field( bool, idle_pc_supported ) 375 __field( int, rc_state ) 376 __string( stage_str, stage ) 377 ), 378 TP_fast_assign( 379 __entry->drm_id = drm_id; 380 __entry->sw_event = sw_event; 381 __entry->idle_pc_supported = idle_pc_supported; 382 __entry->rc_state = rc_state; 383 __assign_str(stage_str, stage); 384 ), 385 TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d", 386 __get_str(stage_str), __entry->drm_id, __entry->sw_event, 387 __entry->idle_pc_supported ? "true" : "false", 388 __entry->rc_state) 389 ); 390 391 TRACE_EVENT(dpu_enc_frame_done_cb_not_busy, 392 TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx), 393 TP_ARGS(drm_id, event, intf_idx), 394 TP_STRUCT__entry( 395 __field( uint32_t, drm_id ) 396 __field( u32, event ) 397 __field( enum dpu_intf, intf_idx ) 398 ), 399 TP_fast_assign( 400 __entry->drm_id = drm_id; 401 __entry->event = event; 402 __entry->intf_idx = intf_idx; 403 ), 404 TP_printk("id=%u, event=%u, intf=%d", __entry->drm_id, __entry->event, 405 __entry->intf_idx) 406 ); 407 408 TRACE_EVENT(dpu_enc_frame_done_cb, 409 TP_PROTO(uint32_t drm_id, unsigned int idx, 410 unsigned long frame_busy_mask), 411 TP_ARGS(drm_id, idx, frame_busy_mask), 412 TP_STRUCT__entry( 413 __field( uint32_t, drm_id ) 414 __field( unsigned int, idx ) 415 __field( unsigned long, frame_busy_mask ) 416 ), 417 TP_fast_assign( 418 __entry->drm_id = drm_id; 419 __entry->idx = idx; 420 __entry->frame_busy_mask = frame_busy_mask; 421 ), 422 TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id, 423 __entry->idx, __entry->frame_busy_mask) 424 ); 425 426 TRACE_EVENT(dpu_enc_trigger_flush, 427 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, 428 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits, 429 u32 pending_flush_ret), 430 TP_ARGS(drm_id, intf_idx, pending_kickoff_cnt, ctl_idx, 431 extra_flush_bits, pending_flush_ret), 432 TP_STRUCT__entry( 433 __field( uint32_t, drm_id ) 434 __field( enum dpu_intf, intf_idx ) 435 __field( int, pending_kickoff_cnt ) 436 __field( int, ctl_idx ) 437 __field( u32, extra_flush_bits ) 438 __field( u32, pending_flush_ret ) 439 ), 440 TP_fast_assign( 441 __entry->drm_id = drm_id; 442 __entry->intf_idx = intf_idx; 443 __entry->pending_kickoff_cnt = pending_kickoff_cnt; 444 __entry->ctl_idx = ctl_idx; 445 __entry->extra_flush_bits = extra_flush_bits; 446 __entry->pending_flush_ret = pending_flush_ret; 447 ), 448 TP_printk("id=%u, intf_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d " 449 "extra_flush_bits=0x%x pending_flush_ret=0x%x", 450 __entry->drm_id, __entry->intf_idx, 451 __entry->pending_kickoff_cnt, __entry->ctl_idx, 452 __entry->extra_flush_bits, __entry->pending_flush_ret) 453 ); 454 455 DECLARE_EVENT_CLASS(dpu_enc_ktime_template, 456 TP_PROTO(uint32_t drm_id, ktime_t time), 457 TP_ARGS(drm_id, time), 458 TP_STRUCT__entry( 459 __field( uint32_t, drm_id ) 460 __field( ktime_t, time ) 461 ), 462 TP_fast_assign( 463 __entry->drm_id = drm_id; 464 __entry->time = time; 465 ), 466 TP_printk("id=%u, time=%lld", __entry->drm_id, 467 ktime_to_ms(__entry->time)) 468 ); 469 DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work, 470 TP_PROTO(uint32_t drm_id, ktime_t time), 471 TP_ARGS(drm_id, time) 472 ); 473 DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff, 474 TP_PROTO(uint32_t drm_id, ktime_t time), 475 TP_ARGS(drm_id, time) 476 ); 477 478 DECLARE_EVENT_CLASS(dpu_id_event_template, 479 TP_PROTO(uint32_t drm_id, u32 event), 480 TP_ARGS(drm_id, event), 481 TP_STRUCT__entry( 482 __field( uint32_t, drm_id ) 483 __field( u32, event ) 484 ), 485 TP_fast_assign( 486 __entry->drm_id = drm_id; 487 __entry->event = event; 488 ), 489 TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event) 490 ); 491 DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout, 492 TP_PROTO(uint32_t drm_id, u32 event), 493 TP_ARGS(drm_id, event) 494 ); 495 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb, 496 TP_PROTO(uint32_t drm_id, u32 event), 497 TP_ARGS(drm_id, event) 498 ); 499 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done, 500 TP_PROTO(uint32_t drm_id, u32 event), 501 TP_ARGS(drm_id, event) 502 ); 503 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending, 504 TP_PROTO(uint32_t drm_id, u32 event), 505 TP_ARGS(drm_id, event) 506 ); 507 508 TRACE_EVENT(dpu_enc_wait_event_timeout, 509 TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time, 510 s64 expected_time, int atomic_cnt), 511 TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt), 512 TP_STRUCT__entry( 513 __field( uint32_t, drm_id ) 514 __field( int, irq_idx ) 515 __field( int, rc ) 516 __field( s64, time ) 517 __field( s64, expected_time ) 518 __field( int, atomic_cnt ) 519 ), 520 TP_fast_assign( 521 __entry->drm_id = drm_id; 522 __entry->irq_idx = irq_idx; 523 __entry->rc = rc; 524 __entry->time = time; 525 __entry->expected_time = expected_time; 526 __entry->atomic_cnt = atomic_cnt; 527 ), 528 TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d", 529 __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time, 530 __entry->expected_time, __entry->atomic_cnt) 531 ); 532 533 TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl, 534 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable, 535 int refcnt), 536 TP_ARGS(drm_id, pp, enable, refcnt), 537 TP_STRUCT__entry( 538 __field( uint32_t, drm_id ) 539 __field( enum dpu_pingpong, pp ) 540 __field( bool, enable ) 541 __field( int, refcnt ) 542 ), 543 TP_fast_assign( 544 __entry->drm_id = drm_id; 545 __entry->pp = pp; 546 __entry->enable = enable; 547 __entry->refcnt = refcnt; 548 ), 549 TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id, 550 __entry->pp, __entry->enable ? "true" : "false", 551 __entry->refcnt) 552 ); 553 554 TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done, 555 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count, 556 u32 event), 557 TP_ARGS(drm_id, pp, new_count, event), 558 TP_STRUCT__entry( 559 __field( uint32_t, drm_id ) 560 __field( enum dpu_pingpong, pp ) 561 __field( int, new_count ) 562 __field( u32, event ) 563 ), 564 TP_fast_assign( 565 __entry->drm_id = drm_id; 566 __entry->pp = pp; 567 __entry->new_count = new_count; 568 __entry->event = event; 569 ), 570 TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id, 571 __entry->pp, __entry->new_count, __entry->event) 572 ); 573 574 TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout, 575 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count, 576 int kickoff_count, u32 event), 577 TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event), 578 TP_STRUCT__entry( 579 __field( uint32_t, drm_id ) 580 __field( enum dpu_pingpong, pp ) 581 __field( int, timeout_count ) 582 __field( int, kickoff_count ) 583 __field( u32, event ) 584 ), 585 TP_fast_assign( 586 __entry->drm_id = drm_id; 587 __entry->pp = pp; 588 __entry->timeout_count = timeout_count; 589 __entry->kickoff_count = kickoff_count; 590 __entry->event = event; 591 ), 592 TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u", 593 __entry->drm_id, __entry->pp, __entry->timeout_count, 594 __entry->kickoff_count, __entry->event) 595 ); 596 597 TRACE_EVENT(dpu_enc_phys_vid_post_kickoff, 598 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx), 599 TP_ARGS(drm_id, intf_idx), 600 TP_STRUCT__entry( 601 __field( uint32_t, drm_id ) 602 __field( enum dpu_intf, intf_idx ) 603 ), 604 TP_fast_assign( 605 __entry->drm_id = drm_id; 606 __entry->intf_idx = intf_idx; 607 ), 608 TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx) 609 ); 610 611 TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, 612 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable, 613 int refcnt), 614 TP_ARGS(drm_id, intf_idx, enable, refcnt), 615 TP_STRUCT__entry( 616 __field( uint32_t, drm_id ) 617 __field( enum dpu_intf, intf_idx ) 618 __field( bool, enable ) 619 __field( int, refcnt ) 620 ), 621 TP_fast_assign( 622 __entry->drm_id = drm_id; 623 __entry->intf_idx = intf_idx; 624 __entry->enable = enable; 625 __entry->refcnt = refcnt; 626 ), 627 TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id, 628 __entry->intf_idx, __entry->enable ? "true" : "false", 629 __entry->drm_id) 630 ); 631 632 TRACE_EVENT(dpu_crtc_setup_mixer, 633 TP_PROTO(uint32_t crtc_id, uint32_t plane_id, 634 struct drm_plane_state *state, struct dpu_plane_state *pstate, 635 uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format, 636 uint64_t modifier), 637 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp, 638 pixel_format, modifier), 639 TP_STRUCT__entry( 640 __field( uint32_t, crtc_id ) 641 __field( uint32_t, plane_id ) 642 __field( uint32_t, fb_id ) 643 __field_struct( struct drm_rect, src_rect ) 644 __field_struct( struct drm_rect, dst_rect ) 645 __field( uint32_t, stage_idx ) 646 __field( enum dpu_stage, stage ) 647 __field( enum dpu_sspp, sspp ) 648 __field( uint32_t, multirect_idx ) 649 __field( uint32_t, multirect_mode ) 650 __field( uint32_t, pixel_format ) 651 __field( uint64_t, modifier ) 652 ), 653 TP_fast_assign( 654 __entry->crtc_id = crtc_id; 655 __entry->plane_id = plane_id; 656 __entry->fb_id = state ? state->fb->base.id : 0; 657 __entry->src_rect = drm_plane_state_src(state); 658 __entry->dst_rect = drm_plane_state_dest(state); 659 __entry->stage_idx = stage_idx; 660 __entry->stage = pstate->stage; 661 __entry->sspp = sspp; 662 __entry->multirect_idx = pstate->multirect_index; 663 __entry->multirect_mode = pstate->multirect_mode; 664 __entry->pixel_format = pixel_format; 665 __entry->modifier = modifier; 666 ), 667 TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT 668 " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d " 669 "multirect_index:%d multirect_mode:%u pix_format:%u " 670 "modifier:%llu", 671 __entry->crtc_id, __entry->plane_id, __entry->fb_id, 672 DRM_RECT_FP_ARG(&__entry->src_rect), 673 DRM_RECT_ARG(&__entry->dst_rect), 674 __entry->stage_idx, __entry->stage, __entry->sspp, 675 __entry->multirect_idx, __entry->multirect_mode, 676 __entry->pixel_format, __entry->modifier) 677 ); 678 679 TRACE_EVENT(dpu_crtc_setup_lm_bounds, 680 TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds), 681 TP_ARGS(drm_id, mixer, bounds), 682 TP_STRUCT__entry( 683 __field( uint32_t, drm_id ) 684 __field( int, mixer ) 685 __field_struct( struct drm_rect, bounds ) 686 ), 687 TP_fast_assign( 688 __entry->drm_id = drm_id; 689 __entry->mixer = mixer; 690 __entry->bounds = *bounds; 691 ), 692 TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id, 693 __entry->mixer, DRM_RECT_ARG(&__entry->bounds)) 694 ); 695 696 TRACE_EVENT(dpu_crtc_vblank_enable, 697 TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable, 698 struct dpu_crtc *crtc), 699 TP_ARGS(drm_id, enc_id, enable, crtc), 700 TP_STRUCT__entry( 701 __field( uint32_t, drm_id ) 702 __field( uint32_t, enc_id ) 703 __field( bool, enable ) 704 __field( bool, enabled ) 705 ), 706 TP_fast_assign( 707 __entry->drm_id = drm_id; 708 __entry->enc_id = enc_id; 709 __entry->enable = enable; 710 __entry->enabled = crtc->enabled; 711 ), 712 TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}", 713 __entry->drm_id, __entry->enc_id, 714 __entry->enable ? "true" : "false", 715 __entry->enabled ? "true" : "false") 716 ); 717 718 DECLARE_EVENT_CLASS(dpu_crtc_enable_template, 719 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 720 TP_ARGS(drm_id, enable, crtc), 721 TP_STRUCT__entry( 722 __field( uint32_t, drm_id ) 723 __field( bool, enable ) 724 __field( bool, enabled ) 725 ), 726 TP_fast_assign( 727 __entry->drm_id = drm_id; 728 __entry->enable = enable; 729 __entry->enabled = crtc->enabled; 730 ), 731 TP_printk("id:%u enable:%s state{enabled:%s}", 732 __entry->drm_id, __entry->enable ? "true" : "false", 733 __entry->enabled ? "true" : "false") 734 ); 735 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable, 736 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 737 TP_ARGS(drm_id, enable, crtc) 738 ); 739 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable, 740 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 741 TP_ARGS(drm_id, enable, crtc) 742 ); 743 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank, 744 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 745 TP_ARGS(drm_id, enable, crtc) 746 ); 747 748 TRACE_EVENT(dpu_crtc_disable_frame_pending, 749 TP_PROTO(uint32_t drm_id, int frame_pending), 750 TP_ARGS(drm_id, frame_pending), 751 TP_STRUCT__entry( 752 __field( uint32_t, drm_id ) 753 __field( int, frame_pending ) 754 ), 755 TP_fast_assign( 756 __entry->drm_id = drm_id; 757 __entry->frame_pending = frame_pending; 758 ), 759 TP_printk("id:%u frame_pending:%d", __entry->drm_id, 760 __entry->frame_pending) 761 ); 762 763 TRACE_EVENT(dpu_plane_set_scanout, 764 TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout, 765 enum dpu_sspp_multirect_index multirect_index), 766 TP_ARGS(index, layout, multirect_index), 767 TP_STRUCT__entry( 768 __field( enum dpu_sspp, index ) 769 __field_struct( struct dpu_hw_fmt_layout, layout ) 770 __field( enum dpu_sspp_multirect_index, multirect_index) 771 ), 772 TP_fast_assign( 773 __entry->index = index; 774 __entry->layout = *layout; 775 __entry->multirect_index = multirect_index; 776 ), 777 TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} " 778 "multirect_index:%d", __entry->index, __entry->layout.width, 779 __entry->layout.height, __entry->layout.plane_addr[0], 780 __entry->layout.plane_size[0], 781 __entry->layout.plane_addr[1], 782 __entry->layout.plane_size[1], 783 __entry->layout.plane_addr[2], 784 __entry->layout.plane_size[2], 785 __entry->layout.plane_addr[3], 786 __entry->layout.plane_size[3], __entry->multirect_index) 787 ); 788 789 TRACE_EVENT(dpu_plane_disable, 790 TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode), 791 TP_ARGS(drm_id, is_virtual, multirect_mode), 792 TP_STRUCT__entry( 793 __field( uint32_t, drm_id ) 794 __field( bool, is_virtual ) 795 __field( uint32_t, multirect_mode ) 796 ), 797 TP_fast_assign( 798 __entry->drm_id = drm_id; 799 __entry->is_virtual = is_virtual; 800 __entry->multirect_mode = multirect_mode; 801 ), 802 TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id, 803 __entry->is_virtual ? "true" : "false", 804 __entry->multirect_mode) 805 ); 806 807 DECLARE_EVENT_CLASS(dpu_rm_iter_template, 808 TP_PROTO(uint32_t id, uint32_t enc_id), 809 TP_ARGS(id, enc_id), 810 TP_STRUCT__entry( 811 __field( uint32_t, id ) 812 __field( uint32_t, enc_id ) 813 ), 814 TP_fast_assign( 815 __entry->id = id; 816 __entry->enc_id = enc_id; 817 ), 818 TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id) 819 ); 820 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf, 821 TP_PROTO(uint32_t id, uint32_t enc_id), 822 TP_ARGS(id, enc_id) 823 ); 824 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls, 825 TP_PROTO(uint32_t id, uint32_t enc_id), 826 TP_ARGS(id, enc_id) 827 ); 828 829 TRACE_EVENT(dpu_rm_reserve_lms, 830 TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id), 831 TP_ARGS(id, enc_id, pp_id), 832 TP_STRUCT__entry( 833 __field( uint32_t, id ) 834 __field( uint32_t, enc_id ) 835 __field( uint32_t, pp_id ) 836 ), 837 TP_fast_assign( 838 __entry->id = id; 839 __entry->enc_id = enc_id; 840 __entry->pp_id = pp_id; 841 ), 842 TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id, 843 __entry->enc_id, __entry->pp_id) 844 ); 845 846 TRACE_EVENT(dpu_vbif_wait_xin_halt_fail, 847 TP_PROTO(enum dpu_vbif index, u32 xin_id), 848 TP_ARGS(index, xin_id), 849 TP_STRUCT__entry( 850 __field( enum dpu_vbif, index ) 851 __field( u32, xin_id ) 852 ), 853 TP_fast_assign( 854 __entry->index = index; 855 __entry->xin_id = xin_id; 856 ), 857 TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id) 858 ); 859 860 TRACE_EVENT(dpu_pp_connect_ext_te, 861 TP_PROTO(enum dpu_pingpong pp, u32 cfg), 862 TP_ARGS(pp, cfg), 863 TP_STRUCT__entry( 864 __field( enum dpu_pingpong, pp ) 865 __field( u32, cfg ) 866 ), 867 TP_fast_assign( 868 __entry->pp = pp; 869 __entry->cfg = cfg; 870 ), 871 TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg) 872 ); 873 874 DECLARE_EVENT_CLASS(dpu_core_irq_callback_template, 875 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 876 TP_ARGS(irq_idx, callback), 877 TP_STRUCT__entry( 878 __field( int, irq_idx ) 879 __field( struct dpu_irq_callback *, callback) 880 ), 881 TP_fast_assign( 882 __entry->irq_idx = irq_idx; 883 __entry->callback = callback; 884 ), 885 TP_printk("irq_idx:%d callback:%pK", __entry->irq_idx, 886 __entry->callback) 887 ); 888 DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_register_callback, 889 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 890 TP_ARGS(irq_idx, callback) 891 ); 892 DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_unregister_callback, 893 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 894 TP_ARGS(irq_idx, callback) 895 ); 896 897 TRACE_EVENT(dpu_core_perf_update_clk, 898 TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate), 899 TP_ARGS(dev, stop_req, clk_rate), 900 TP_STRUCT__entry( 901 __string( dev_name, dev->unique ) 902 __field( bool, stop_req ) 903 __field( u64, clk_rate ) 904 ), 905 TP_fast_assign( 906 __assign_str(dev_name, dev->unique); 907 __entry->stop_req = stop_req; 908 __entry->clk_rate = clk_rate; 909 ), 910 TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name), 911 __entry->stop_req ? "true" : "false", __entry->clk_rate) 912 ); 913 914 TRACE_EVENT(dpu_hw_ctl_update_pending_flush, 915 TP_PROTO(u32 new_bits, u32 pending_mask), 916 TP_ARGS(new_bits, pending_mask), 917 TP_STRUCT__entry( 918 __field( u32, new_bits ) 919 __field( u32, pending_mask ) 920 ), 921 TP_fast_assign( 922 __entry->new_bits = new_bits; 923 __entry->pending_mask = pending_mask; 924 ), 925 TP_printk("new=%x existing=%x", __entry->new_bits, 926 __entry->pending_mask) 927 ); 928 929 DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template, 930 TP_PROTO(u32 pending_mask, u32 ctl_flush), 931 TP_ARGS(pending_mask, ctl_flush), 932 TP_STRUCT__entry( 933 __field( u32, pending_mask ) 934 __field( u32, ctl_flush ) 935 ), 936 TP_fast_assign( 937 __entry->pending_mask = pending_mask; 938 __entry->ctl_flush = ctl_flush; 939 ), 940 TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask, 941 __entry->ctl_flush) 942 ); 943 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush, 944 TP_PROTO(u32 pending_mask, u32 ctl_flush), 945 TP_ARGS(pending_mask, ctl_flush) 946 ); 947 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, 948 dpu_hw_ctl_trigger_pending_flush, 949 TP_PROTO(u32 pending_mask, u32 ctl_flush), 950 TP_ARGS(pending_mask, ctl_flush) 951 ); 952 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare, 953 TP_PROTO(u32 pending_mask, u32 ctl_flush), 954 TP_ARGS(pending_mask, ctl_flush) 955 ); 956 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start, 957 TP_PROTO(u32 pending_mask, u32 ctl_flush), 958 TP_ARGS(pending_mask, ctl_flush) 959 ); 960 961 #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0) 962 #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1) 963 #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__) 964 965 #define DPU_ATRACE_INT(name, value) \ 966 trace_dpu_trace_counter(current->tgid, name, value) 967 968 #endif /* _DPU_TRACE_H_ */ 969 970 /* This part must be outside protection */ 971 #undef TRACE_INCLUDE_PATH 972 #define TRACE_INCLUDE_PATH . 973 #include <trace/define_trace.h> 974