1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_H 8 #define __DRV_CLK_MTK_H 9 10 #include <linux/clk-provider.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 #include <linux/types.h> 15 16 #include "reset.h" 17 18 #define MAX_MUX_GATE_BIT 31 19 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) 20 21 #define MHZ (1000 * 1000) 22 23 struct platform_device; 24 25 struct mtk_fixed_clk { 26 int id; 27 const char *name; 28 const char *parent; 29 unsigned long rate; 30 }; 31 32 #define FIXED_CLK(_id, _name, _parent, _rate) { \ 33 .id = _id, \ 34 .name = _name, \ 35 .parent = _parent, \ 36 .rate = _rate, \ 37 } 38 39 int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, 40 struct clk_hw_onecell_data *clk_data); 41 void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num, 42 struct clk_hw_onecell_data *clk_data); 43 44 struct mtk_fixed_factor { 45 int id; 46 const char *name; 47 const char *parent_name; 48 int mult; 49 int div; 50 }; 51 52 #define FACTOR(_id, _name, _parent, _mult, _div) { \ 53 .id = _id, \ 54 .name = _name, \ 55 .parent_name = _parent, \ 56 .mult = _mult, \ 57 .div = _div, \ 58 } 59 60 int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, 61 struct clk_hw_onecell_data *clk_data); 62 void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, 63 struct clk_hw_onecell_data *clk_data); 64 65 struct mtk_composite { 66 int id; 67 const char *name; 68 const char * const *parent_names; 69 const char *parent; 70 unsigned flags; 71 72 uint32_t mux_reg; 73 uint32_t divider_reg; 74 uint32_t gate_reg; 75 76 signed char mux_shift; 77 signed char mux_width; 78 signed char gate_shift; 79 80 signed char divider_shift; 81 signed char divider_width; 82 83 u8 mux_flags; 84 85 signed char num_parents; 86 }; 87 88 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ 89 _width, _gate, _flags, _muxflags) { \ 90 .id = _id, \ 91 .name = _name, \ 92 .mux_reg = _reg, \ 93 .mux_shift = _shift, \ 94 .mux_width = _width, \ 95 .gate_reg = _reg, \ 96 .gate_shift = _gate, \ 97 .divider_shift = -1, \ 98 .parent_names = _parents, \ 99 .num_parents = ARRAY_SIZE(_parents), \ 100 .flags = _flags, \ 101 .mux_flags = _muxflags, \ 102 } 103 104 /* 105 * In case the rate change propagation to parent clocks is undesirable, 106 * this macro allows to specify the clock flags manually. 107 */ 108 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 109 _gate, _flags) \ 110 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ 111 _shift, _width, _gate, _flags, 0) 112 113 /* 114 * Unless necessary, all MUX_GATE clocks propagate rate changes to their 115 * parent clock by default. 116 */ 117 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ 118 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 119 _gate, CLK_SET_RATE_PARENT) 120 121 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ 122 MUX_FLAGS(_id, _name, _parents, _reg, \ 123 _shift, _width, CLK_SET_RATE_PARENT) 124 125 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ 126 .id = _id, \ 127 .name = _name, \ 128 .mux_reg = _reg, \ 129 .mux_shift = _shift, \ 130 .mux_width = _width, \ 131 .gate_shift = -1, \ 132 .divider_shift = -1, \ 133 .parent_names = _parents, \ 134 .num_parents = ARRAY_SIZE(_parents), \ 135 .flags = _flags, \ 136 } 137 138 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ 139 _div_width, _div_shift) { \ 140 .id = _id, \ 141 .parent = _parent, \ 142 .name = _name, \ 143 .divider_reg = _div_reg, \ 144 .divider_shift = _div_shift, \ 145 .divider_width = _div_width, \ 146 .gate_reg = _gate_reg, \ 147 .gate_shift = _gate_shift, \ 148 .mux_shift = -1, \ 149 .flags = 0, \ 150 } 151 152 int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, 153 void __iomem *base, spinlock_t *lock, 154 struct clk_hw_onecell_data *clk_data); 155 void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, 156 struct clk_hw_onecell_data *clk_data); 157 158 struct mtk_clk_divider { 159 int id; 160 const char *name; 161 const char *parent_name; 162 unsigned long flags; 163 164 u32 div_reg; 165 unsigned char div_shift; 166 unsigned char div_width; 167 unsigned char clk_divider_flags; 168 const struct clk_div_table *clk_div_table; 169 }; 170 171 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ 172 .id = _id, \ 173 .name = _name, \ 174 .parent_name = _parent, \ 175 .div_reg = _reg, \ 176 .div_shift = _shift, \ 177 .div_width = _width, \ 178 } 179 180 int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, 181 void __iomem *base, spinlock_t *lock, 182 struct clk_hw_onecell_data *clk_data); 183 void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, 184 struct clk_hw_onecell_data *clk_data); 185 186 struct clk_hw_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); 187 struct clk_hw_onecell_data *mtk_devm_alloc_clk_data(struct device *dev, 188 unsigned int clk_num); 189 void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data); 190 191 struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name, 192 const char *parent_name, void __iomem *reg); 193 void mtk_clk_unregister_ref2usb_tx(struct clk_hw *hw); 194 195 struct mtk_clk_desc { 196 const struct mtk_gate *clks; 197 size_t num_clks; 198 const struct mtk_clk_rst_desc *rst_desc; 199 }; 200 201 int mtk_clk_simple_probe(struct platform_device *pdev); 202 int mtk_clk_simple_remove(struct platform_device *pdev); 203 204 #endif /* __DRV_CLK_MTK_H */ 205