1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces 4 // 5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <dt-bindings/sound/microchip,pdmc.h> 10 11 #include <linux/clk.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/regmap.h> 15 16 #include <sound/core.h> 17 #include <sound/dmaengine_pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/tlv.h> 20 21 /* 22 * ---- PDMC Register map ---- 23 */ 24 #define MCHP_PDMC_CR 0x00 /* Control Register */ 25 #define MCHP_PDMC_MR 0x04 /* Mode Register */ 26 #define MCHP_PDMC_CFGR 0x08 /* Configuration Register */ 27 #define MCHP_PDMC_RHR 0x0C /* Receive Holding Register */ 28 #define MCHP_PDMC_IER 0x14 /* Interrupt Enable Register */ 29 #define MCHP_PDMC_IDR 0x18 /* Interrupt Disable Register */ 30 #define MCHP_PDMC_IMR 0x1C /* Interrupt Mask Register */ 31 #define MCHP_PDMC_ISR 0x20 /* Interrupt Status Register */ 32 #define MCHP_PDMC_VER 0x50 /* Version Register */ 33 34 /* 35 * ---- Control Register (Write-only) ---- 36 */ 37 #define MCHP_PDMC_CR_SWRST BIT(0) /* Software Reset */ 38 39 /* 40 * ---- Mode Register (Read/Write) ---- 41 */ 42 #define MCHP_PDMC_MR_PDMCEN_MASK GENMASK(3, 0) 43 #define MCHP_PDMC_MR_PDMCEN(ch) (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK) 44 45 #define MCHP_PDMC_MR_OSR_MASK GENMASK(17, 16) 46 #define MCHP_PDMC_MR_OSR64 (1 << 16) 47 #define MCHP_PDMC_MR_OSR128 (2 << 16) 48 #define MCHP_PDMC_MR_OSR256 (3 << 16) 49 50 #define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20) 51 #define MCHP_PDMC_MR_SINCORDER(order) (((order) << 20) & \ 52 MCHP_PDMC_MR_SINCORDER_MASK) 53 54 #define MCHP_PDMC_MR_SINC_OSR_MASK GENMASK(27, 24) 55 #define MCHP_PDMC_MR_SINC_OSR_DIS (0 << 24) 56 #define MCHP_PDMC_MR_SINC_OSR_8 (1 << 24) 57 #define MCHP_PDMC_MR_SINC_OSR_16 (2 << 24) 58 #define MCHP_PDMC_MR_SINC_OSR_32 (3 << 24) 59 #define MCHP_PDMC_MR_SINC_OSR_64 (4 << 24) 60 #define MCHP_PDMC_MR_SINC_OSR_128 (5 << 24) 61 #define MCHP_PDMC_MR_SINC_OSR_256 (6 << 24) 62 63 #define MCHP_PDMC_MR_CHUNK_MASK GENMASK(31, 28) 64 #define MCHP_PDMC_MR_CHUNK(chunk) (((chunk) << 28) & \ 65 MCHP_PDMC_MR_CHUNK_MASK) 66 67 /* 68 * ---- Configuration Register (Read/Write) ---- 69 */ 70 #define MCHP_PDMC_CFGR_BSSEL_MASK (BIT(0) | BIT(2) | BIT(4) | BIT(6)) 71 #define MCHP_PDMC_CFGR_BSSEL(ch) BIT((ch) * 2) 72 73 #define MCHP_PDMC_CFGR_PDMSEL_MASK (BIT(16) | BIT(18) | BIT(20) | BIT(22)) 74 #define MCHP_PDMC_CFGR_PDMSEL(ch) BIT((ch) * 2 + 16) 75 76 /* 77 * ---- Interrupt Enable/Disable/Mask/Status Registers ---- 78 */ 79 #define MCHP_PDMC_IR_RXRDY BIT(0) 80 #define MCHP_PDMC_IR_RXEMPTY BIT(1) 81 #define MCHP_PDMC_IR_RXFULL BIT(2) 82 #define MCHP_PDMC_IR_RXCHUNK BIT(3) 83 #define MCHP_PDMC_IR_RXUDR BIT(4) 84 #define MCHP_PDMC_IR_RXOVR BIT(5) 85 86 /* 87 * ---- Version Register (Read-only) ---- 88 */ 89 #define MCHP_PDMC_VER_VERSION GENMASK(11, 0) 90 91 #define MCHP_PDMC_MAX_CHANNELS 4 92 #define MCHP_PDMC_DS_NO 2 93 #define MCHP_PDMC_EDGE_NO 2 94 95 struct mic_map { 96 int ds_pos; 97 int clk_edge; 98 }; 99 100 struct mchp_pdmc_chmap { 101 struct snd_pcm_chmap_elem *chmap; 102 struct mchp_pdmc *dd; 103 struct snd_pcm *pcm; 104 struct snd_kcontrol *kctl; 105 }; 106 107 struct mchp_pdmc { 108 struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS]; 109 struct device *dev; 110 struct snd_dmaengine_dai_dma_data addr; 111 struct regmap *regmap; 112 struct clk *pclk; 113 struct clk *gclk; 114 u32 pdmcen; 115 int mic_no; 116 int sinc_order; 117 bool audio_filter_en; 118 u8 gclk_enabled:1; 119 }; 120 121 static const char *const mchp_pdmc_sinc_filter_order_text[] = { 122 "1", "2", "3", "4", "5" 123 }; 124 125 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = { 126 1, 2, 3, 4, 5, 127 }; 128 129 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = { 130 .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text), 131 .texts = mchp_pdmc_sinc_filter_order_text, 132 .values = mchp_pdmc_sinc_filter_order_values, 133 }; 134 135 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol, 136 struct snd_ctl_elem_value *uvalue) 137 { 138 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 139 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 140 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 141 unsigned int item; 142 143 item = snd_soc_enum_val_to_item(e, dd->sinc_order); 144 uvalue->value.enumerated.item[0] = item; 145 146 return 0; 147 } 148 149 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol, 150 struct snd_ctl_elem_value *uvalue) 151 { 152 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 153 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 154 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 155 unsigned int *item = uvalue->value.enumerated.item; 156 unsigned int val; 157 158 if (item[0] >= e->items) 159 return -EINVAL; 160 161 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 162 if (val == dd->sinc_order) 163 return 0; 164 165 dd->sinc_order = val; 166 167 return 1; 168 } 169 170 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol, 171 struct snd_ctl_elem_value *uvalue) 172 { 173 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 174 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 175 176 uvalue->value.integer.value[0] = !!dd->audio_filter_en; 177 178 return 0; 179 } 180 181 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol, 182 struct snd_ctl_elem_value *uvalue) 183 { 184 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 185 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 186 bool af = uvalue->value.integer.value[0] ? true : false; 187 188 if (dd->audio_filter_en == af) 189 return 0; 190 191 dd->audio_filter_en = af; 192 193 return 1; 194 } 195 196 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 197 { 198 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 199 200 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 201 uinfo->count = info->dd->mic_no; 202 uinfo->value.integer.min = 0; 203 uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */ 204 return 0; 205 } 206 207 static inline struct snd_pcm_substream * 208 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx) 209 { 210 struct snd_pcm_substream *s; 211 212 for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next) 213 if (s->number == idx) 214 return s; 215 return NULL; 216 } 217 218 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream, 219 struct mchp_pdmc_chmap *ch_info) 220 { 221 struct snd_pcm_chmap_elem *map; 222 223 for (map = ch_info->chmap; map->channels; map++) { 224 if (map->channels == substream->runtime->channels) 225 return map; 226 } 227 return NULL; 228 } 229 230 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol, 231 struct snd_ctl_elem_value *ucontrol) 232 { 233 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 234 struct mchp_pdmc *dd = info->dd; 235 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 236 struct snd_pcm_substream *substream; 237 const struct snd_pcm_chmap_elem *map; 238 int i; 239 u32 cfgr_val = 0; 240 241 if (!info->chmap) 242 return -EINVAL; 243 substream = mchp_pdmc_chmap_substream(info, idx); 244 if (!substream) 245 return -ENODEV; 246 memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no); 247 if (!substream->runtime) 248 return 0; /* no channels set */ 249 250 map = mchp_pdmc_chmap_get(substream, info); 251 if (!map) 252 return -EINVAL; 253 254 for (i = 0; i < map->channels; i++) { 255 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO : 256 map->map[i] - SNDRV_CHMAP_FL; 257 258 /* make sure the reported channel map is the real one, so write the map */ 259 if (dd->channel_mic_map[map_idx].ds_pos) 260 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 261 if (dd->channel_mic_map[map_idx].clk_edge) 262 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 263 264 ucontrol->value.integer.value[i] = map->map[i]; 265 } 266 267 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val); 268 269 return 0; 270 } 271 272 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol, 273 struct snd_ctl_elem_value *ucontrol) 274 { 275 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 276 struct mchp_pdmc *dd = info->dd; 277 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 278 struct snd_pcm_substream *substream; 279 struct snd_pcm_chmap_elem *map; 280 u32 cfgr_val = 0; 281 int i; 282 283 if (!info->chmap) 284 return -EINVAL; 285 substream = mchp_pdmc_chmap_substream(info, idx); 286 if (!substream) 287 return -ENODEV; 288 289 map = mchp_pdmc_chmap_get(substream, info); 290 if (!map) 291 return -EINVAL; 292 293 for (i = 0; i < map->channels; i++) { 294 int map_idx; 295 296 map->map[i] = ucontrol->value.integer.value[i]; 297 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO : 298 map->map[i] - SNDRV_CHMAP_FL; 299 300 /* configure IP for the desired channel map */ 301 if (dd->channel_mic_map[map_idx].ds_pos) 302 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 303 if (dd->channel_mic_map[map_idx].clk_edge) 304 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 305 } 306 307 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val); 308 309 return 0; 310 } 311 312 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol) 313 { 314 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 315 316 info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL; 317 kfree(info); 318 } 319 320 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, 321 unsigned int size, unsigned int __user *tlv) 322 { 323 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 324 const struct snd_pcm_chmap_elem *map; 325 unsigned int __user *dst; 326 int c, count = 0; 327 328 if (!info->chmap) 329 return -EINVAL; 330 if (size < 8) 331 return -ENOMEM; 332 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv)) 333 return -EFAULT; 334 size -= 8; 335 dst = tlv + 2; 336 for (map = info->chmap; map->channels; map++) { 337 int chs_bytes = map->channels * 4; 338 339 if (size < 8) 340 return -ENOMEM; 341 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) || 342 put_user(chs_bytes, dst + 1)) 343 return -EFAULT; 344 dst += 2; 345 size -= 8; 346 count += 8; 347 if (size < chs_bytes) 348 return -ENOMEM; 349 size -= chs_bytes; 350 count += chs_bytes; 351 for (c = 0; c < map->channels; c++) { 352 if (put_user(map->map[c], dst)) 353 return -EFAULT; 354 dst++; 355 } 356 } 357 if (put_user(count, tlv + 1)) 358 return -EFAULT; 359 return 0; 360 } 361 362 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = { 363 SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put), 364 { 365 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 366 .name = "SINC Filter Order", 367 .info = snd_soc_info_enum_double, 368 .get = mchp_pdmc_sinc_order_get, 369 .put = mchp_pdmc_sinc_order_put, 370 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum, 371 }, 372 }; 373 374 static int mchp_pdmc_close(struct snd_soc_component *component, 375 struct snd_pcm_substream *substream) 376 { 377 return snd_soc_add_component_controls(component, mchp_pdmc_snd_controls, 378 ARRAY_SIZE(mchp_pdmc_snd_controls)); 379 } 380 381 static int mchp_pdmc_open(struct snd_soc_component *component, 382 struct snd_pcm_substream *substream) 383 { 384 int i; 385 386 /* remove controls that can't be changed at runtime */ 387 for (i = 0; i < ARRAY_SIZE(mchp_pdmc_snd_controls); i++) { 388 const struct snd_kcontrol_new *control = &mchp_pdmc_snd_controls[i]; 389 struct snd_ctl_elem_id id; 390 struct snd_kcontrol *kctl; 391 int err; 392 393 if (component->name_prefix) 394 snprintf(id.name, sizeof(id.name), "%s %s", component->name_prefix, 395 control->name); 396 else 397 strscpy(id.name, control->name, sizeof(id.name)); 398 399 id.numid = 0; 400 id.iface = control->iface; 401 id.device = control->device; 402 id.subdevice = control->subdevice; 403 id.index = control->index; 404 kctl = snd_ctl_find_id(component->card->snd_card, &id); 405 if (!kctl) { 406 dev_err(component->dev, "Failed to find %s\n", control->name); 407 continue; 408 } 409 err = snd_ctl_remove(component->card->snd_card, kctl); 410 if (err < 0) { 411 dev_err(component->dev, "%d: Failed to remove %s\n", err, 412 control->name); 413 continue; 414 } 415 } 416 417 return 0; 418 } 419 420 static const struct snd_soc_component_driver mchp_pdmc_dai_component = { 421 .name = "mchp-pdmc", 422 .controls = mchp_pdmc_snd_controls, 423 .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls), 424 .open = &mchp_pdmc_open, 425 .close = &mchp_pdmc_close, 426 }; 427 428 static const unsigned int mchp_pdmc_1mic[] = {1}; 429 static const unsigned int mchp_pdmc_2mic[] = {1, 2}; 430 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3}; 431 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4}; 432 433 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = { 434 { 435 .list = mchp_pdmc_1mic, 436 .count = ARRAY_SIZE(mchp_pdmc_1mic), 437 }, 438 { 439 .list = mchp_pdmc_2mic, 440 .count = ARRAY_SIZE(mchp_pdmc_2mic), 441 }, 442 { 443 .list = mchp_pdmc_3mic, 444 .count = ARRAY_SIZE(mchp_pdmc_3mic), 445 }, 446 { 447 .list = mchp_pdmc_4mic, 448 .count = ARRAY_SIZE(mchp_pdmc_4mic), 449 }, 450 }; 451 452 static int mchp_pdmc_startup(struct snd_pcm_substream *substream, 453 struct snd_soc_dai *dai) 454 { 455 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 456 int ret; 457 458 ret = clk_prepare_enable(dd->pclk); 459 if (ret) { 460 dev_err(dd->dev, "failed to enable the peripheral clock: %d\n", ret); 461 return ret; 462 } 463 464 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST); 465 466 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 467 &mchp_pdmc_chan_constr[dd->mic_no - 1]); 468 469 return 0; 470 } 471 472 static void mchp_pdmc_shutdown(struct snd_pcm_substream *substream, 473 struct snd_soc_dai *dai) 474 { 475 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 476 477 clk_disable_unprepare(dd->pclk); 478 } 479 480 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai) 481 { 482 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 483 484 snd_soc_dai_init_dma_data(dai, NULL, &dd->addr); 485 486 return 0; 487 } 488 489 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 490 { 491 unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK; 492 unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 493 494 /* IP needs to be bitclock master */ 495 if (fmt_master != SND_SOC_DAIFMT_CBS_CFS && 496 fmt_master != SND_SOC_DAIFMT_CBS_CFM) 497 return -EINVAL; 498 499 /* IP supports only PDM interface */ 500 if (fmt_format != SND_SOC_DAIFMT_PDM) 501 return -EINVAL; 502 503 return 0; 504 } 505 506 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr) 507 { 508 if (audio_filter_en) { 509 switch (osr) { 510 case 64: 511 return MCHP_PDMC_MR_OSR64; 512 case 128: 513 return MCHP_PDMC_MR_OSR128; 514 case 256: 515 return MCHP_PDMC_MR_OSR256; 516 } 517 } else { 518 switch (osr) { 519 case 8: 520 return MCHP_PDMC_MR_SINC_OSR_8; 521 case 16: 522 return MCHP_PDMC_MR_SINC_OSR_16; 523 case 32: 524 return MCHP_PDMC_MR_SINC_OSR_32; 525 case 64: 526 return MCHP_PDMC_MR_SINC_OSR_64; 527 case 128: 528 return MCHP_PDMC_MR_SINC_OSR_128; 529 case 256: 530 return MCHP_PDMC_MR_SINC_OSR_256; 531 } 532 } 533 return 0; 534 } 535 536 static inline int mchp_pdmc_period_to_maxburst(int period_size) 537 { 538 if (!(period_size % 8)) 539 return 8; 540 if (!(period_size % 4)) 541 return 4; 542 if (!(period_size % 2)) 543 return 2; 544 return 1; 545 } 546 547 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = { 548 { .channels = 1, 549 .map = { SNDRV_CHMAP_MONO } }, 550 { .channels = 2, 551 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 552 { .channels = 3, 553 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 554 SNDRV_CHMAP_RL } }, 555 { .channels = 4, 556 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 557 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 558 { } 559 }; 560 561 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream, 562 struct snd_pcm_hw_params *params, 563 struct snd_soc_dai *dai) 564 { 565 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 566 struct snd_soc_component *comp = dai->component; 567 unsigned long gclk_rate = 0; 568 unsigned long best_diff_rate = ~0UL; 569 unsigned int channels = params_channels(params); 570 unsigned int osr = 0, osr_start; 571 unsigned int fs = params_rate(params); 572 u32 mr_val = 0; 573 u32 cfgr_val = 0; 574 int i; 575 int ret; 576 577 dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 578 __func__, params_rate(params), params_format(params), 579 params_width(params), params_channels(params)); 580 581 if (channels > dd->mic_no) { 582 dev_err(comp->dev, "more channels %u than microphones %d\n", 583 channels, dd->mic_no); 584 return -EINVAL; 585 } 586 587 dd->pdmcen = 0; 588 for (i = 0; i < channels; i++) { 589 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i); 590 if (dd->channel_mic_map[i].ds_pos) 591 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 592 if (dd->channel_mic_map[i].clk_edge) 593 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 594 } 595 596 if (dd->gclk_enabled) { 597 clk_disable_unprepare(dd->gclk); 598 dd->gclk_enabled = 0; 599 } 600 601 for (osr_start = dd->audio_filter_en ? 64 : 8; 602 osr_start <= 256 && best_diff_rate; osr_start *= 2) { 603 long round_rate; 604 unsigned long diff_rate; 605 606 round_rate = clk_round_rate(dd->gclk, 607 (unsigned long)fs * 16 * osr_start); 608 if (round_rate < 0) 609 continue; 610 diff_rate = abs((fs * 16 * osr_start) - round_rate); 611 if (diff_rate < best_diff_rate) { 612 best_diff_rate = diff_rate; 613 osr = osr_start; 614 gclk_rate = fs * 16 * osr; 615 } 616 } 617 if (!gclk_rate) { 618 dev_err(comp->dev, "invalid sampling rate: %u\n", fs); 619 return -EINVAL; 620 } 621 622 /* set the rate */ 623 ret = clk_set_rate(dd->gclk, gclk_rate); 624 if (ret) { 625 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", 626 gclk_rate, ret); 627 return ret; 628 } 629 630 mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr); 631 632 mr_val |= MCHP_PDMC_MR_SINCORDER(dd->sinc_order); 633 634 dd->addr.maxburst = mchp_pdmc_period_to_maxburst(snd_pcm_lib_period_bytes(substream)); 635 mr_val |= MCHP_PDMC_MR_CHUNK(dd->addr.maxburst); 636 dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst); 637 638 clk_prepare_enable(dd->gclk); 639 dd->gclk_enabled = 1; 640 641 snd_soc_component_update_bits(comp, MCHP_PDMC_MR, 642 MCHP_PDMC_MR_OSR_MASK | 643 MCHP_PDMC_MR_SINCORDER_MASK | 644 MCHP_PDMC_MR_SINC_OSR_MASK | 645 MCHP_PDMC_MR_CHUNK_MASK, mr_val); 646 647 snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val); 648 649 return 0; 650 } 651 652 static int mchp_pdmc_hw_free(struct snd_pcm_substream *substream, 653 struct snd_soc_dai *dai) 654 { 655 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 656 657 if (dd->gclk_enabled) { 658 clk_disable_unprepare(dd->gclk); 659 dd->gclk_enabled = 0; 660 } 661 662 return 0; 663 } 664 665 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream, 666 int cmd, struct snd_soc_dai *dai) 667 { 668 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 669 struct snd_soc_component *cpu = dai->component; 670 #ifdef DEBUG 671 u32 val; 672 #endif 673 674 switch (cmd) { 675 case SNDRV_PCM_TRIGGER_START: 676 case SNDRV_PCM_TRIGGER_RESUME: 677 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 678 /* Enable overrun and underrun error interrupts */ 679 regmap_write(dd->regmap, MCHP_PDMC_IER, 680 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); 681 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, 682 MCHP_PDMC_MR_PDMCEN_MASK, 683 dd->pdmcen); 684 break; 685 case SNDRV_PCM_TRIGGER_STOP: 686 case SNDRV_PCM_TRIGGER_SUSPEND: 687 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 688 /* Disable overrun and underrun error interrupts */ 689 regmap_write(dd->regmap, MCHP_PDMC_IDR, 690 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); 691 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, 692 MCHP_PDMC_MR_PDMCEN_MASK, 0); 693 break; 694 default: 695 return -EINVAL; 696 } 697 698 #ifdef DEBUG 699 regmap_read(dd->regmap, MCHP_PDMC_MR, &val); 700 dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val); 701 regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val); 702 dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val); 703 regmap_read(dd->regmap, MCHP_PDMC_IMR, &val); 704 dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val); 705 #endif 706 707 return 0; 708 } 709 710 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = { 711 .set_fmt = mchp_pdmc_set_fmt, 712 .startup = mchp_pdmc_startup, 713 .shutdown = mchp_pdmc_shutdown, 714 .hw_params = mchp_pdmc_hw_params, 715 .hw_free = mchp_pdmc_hw_free, 716 .trigger = mchp_pdmc_trigger, 717 }; 718 719 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd) 720 { 721 struct mchp_pdmc_chmap *info; 722 struct snd_kcontrol_new knew = { 723 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 724 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 725 SNDRV_CTL_ELEM_ACCESS_TLV_READ | 726 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, 727 .info = mchp_pdmc_chmap_ctl_info, 728 .get = mchp_pdmc_chmap_ctl_get, 729 .put = mchp_pdmc_chmap_ctl_put, 730 .tlv.c = mchp_pdmc_chmap_ctl_tlv, 731 }; 732 int err; 733 734 if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl)) 735 return -EBUSY; 736 info = kzalloc(sizeof(*info), GFP_KERNEL); 737 if (!info) 738 return -ENOMEM; 739 info->pcm = pcm; 740 info->dd = dd; 741 info->chmap = mchp_pdmc_std_chmaps; 742 knew.name = "Capture Channel Map"; 743 knew.device = pcm->device; 744 knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count; 745 info->kctl = snd_ctl_new1(&knew, info); 746 if (!info->kctl) { 747 kfree(info); 748 return -ENOMEM; 749 } 750 info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free; 751 err = snd_ctl_add(pcm->card, info->kctl); 752 if (err < 0) 753 return err; 754 pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl; 755 return 0; 756 } 757 758 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd, 759 struct snd_soc_dai *dai) 760 { 761 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 762 int ret; 763 764 ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd); 765 if (ret < 0) { 766 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret); 767 return ret; 768 } 769 770 return 0; 771 } 772 773 static struct snd_soc_dai_driver mchp_pdmc_dai = { 774 .probe = mchp_pdmc_dai_probe, 775 .capture = { 776 .stream_name = "Capture", 777 .channels_min = 1, 778 .channels_max = 4, 779 .rate_min = 8000, 780 .rate_max = 192000, 781 .rates = SNDRV_PCM_RATE_KNOT, 782 .formats = SNDRV_PCM_FMTBIT_S24_LE, 783 }, 784 .ops = &mchp_pdmc_dai_ops, 785 .pcm_new = &mchp_pdmc_pcm_new, 786 }; 787 788 /* PDMC interrupt handler */ 789 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id) 790 { 791 struct mchp_pdmc *dd = (struct mchp_pdmc *)dev_id; 792 u32 isr, msr, pending; 793 irqreturn_t ret = IRQ_NONE; 794 795 regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr); 796 regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr); 797 798 pending = isr & msr; 799 dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n", 800 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending); 801 if (!pending) 802 return IRQ_NONE; 803 804 if (pending & MCHP_PDMC_IR_RXUDR) { 805 dev_warn(dd->dev, "underrun detected\n"); 806 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR); 807 ret = IRQ_HANDLED; 808 } 809 if (pending & MCHP_PDMC_IR_RXOVR) { 810 dev_warn(dd->dev, "overrun detected\n"); 811 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR); 812 ret = IRQ_HANDLED; 813 } 814 815 return ret; 816 } 817 818 /* regmap configuration */ 819 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg) 820 { 821 switch (reg) { 822 case MCHP_PDMC_MR: 823 case MCHP_PDMC_CFGR: 824 case MCHP_PDMC_IMR: 825 case MCHP_PDMC_ISR: 826 case MCHP_PDMC_VER: 827 return true; 828 default: 829 return false; 830 } 831 } 832 833 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg) 834 { 835 switch (reg) { 836 case MCHP_PDMC_CR: 837 case MCHP_PDMC_MR: 838 case MCHP_PDMC_CFGR: 839 case MCHP_PDMC_IER: 840 case MCHP_PDMC_IDR: 841 return true; 842 default: 843 return false; 844 } 845 } 846 847 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg) 848 { 849 switch (reg) { 850 case MCHP_PDMC_RHR: 851 case MCHP_PDMC_ISR: 852 return true; 853 default: 854 return false; 855 } 856 } 857 858 static const struct regmap_config mchp_pdmc_regmap_config = { 859 .reg_bits = 32, 860 .reg_stride = 4, 861 .val_bits = 32, 862 .max_register = MCHP_PDMC_VER, 863 .readable_reg = mchp_pdmc_readable_reg, 864 .writeable_reg = mchp_pdmc_writeable_reg, 865 .precious_reg = mchp_pdmc_precious_reg, 866 }; 867 868 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd) 869 { 870 struct device_node *np = dd->dev->of_node; 871 bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0}; 872 int i; 873 int ret; 874 875 if (!np) { 876 dev_err(dd->dev, "device node not found\n"); 877 return -EINVAL; 878 } 879 880 dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos"); 881 if (dd->mic_no < 0) { 882 dev_err(dd->dev, "failed to get microchip,mic-pos: %d", 883 dd->mic_no); 884 return dd->mic_no; 885 } 886 if (!dd->mic_no || dd->mic_no % 2 || 887 dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) { 888 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d", 889 dd->mic_no); 890 return -EINVAL; 891 } 892 893 dd->mic_no /= 2; 894 895 dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no); 896 897 /* 898 * by default, we consider the order of microphones in 899 * microchip,mic-pos to be the same with the channel mapping; 900 * 1st microphone channel 0, 2nd microphone channel 1, etc. 901 */ 902 for (i = 0; i < dd->mic_no; i++) { 903 int ds; 904 int edge; 905 906 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2, 907 &ds); 908 if (ret) { 909 dev_err(dd->dev, 910 "failed to get value no %d value from microchip,mic-pos: %d", 911 i * 2, ret); 912 return ret; 913 } 914 if (ds >= MCHP_PDMC_DS_NO) { 915 dev_err(dd->dev, 916 "invalid DS index in microchip,mic-pos array: %d", 917 ds); 918 return -EINVAL; 919 } 920 921 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1, 922 &edge); 923 if (ret) { 924 dev_err(dd->dev, 925 "failed to get value no %d value from microchip,mic-pos: %d", 926 i * 2 + 1, ret); 927 return ret; 928 } 929 930 if (edge != MCHP_PDMC_CLK_POSITIVE && 931 edge != MCHP_PDMC_CLK_NEGATIVE) { 932 dev_err(dd->dev, 933 "invalid edge in microchip,mic-pos array: %d", edge); 934 return -EINVAL; 935 } 936 if (mic_ch[ds][edge]) { 937 dev_err(dd->dev, 938 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array", 939 ds, edge); 940 return -EINVAL; 941 } 942 mic_ch[ds][edge] = true; 943 dd->channel_mic_map[i].ds_pos = ds; 944 dd->channel_mic_map[i].clk_edge = edge; 945 } 946 947 return 0; 948 } 949 950 /* used to clean the channel index found on RHR's MSB */ 951 static int mchp_pdmc_process(struct snd_pcm_substream *substream, 952 int channel, unsigned long hwoff, 953 void *buf, unsigned long bytes) 954 { 955 struct snd_pcm_runtime *runtime = substream->runtime; 956 u8 *dma_ptr = runtime->dma_area + hwoff + 957 channel * (runtime->dma_bytes / runtime->channels); 958 u8 *dma_ptr_end = dma_ptr + bytes; 959 unsigned int sample_size = samples_to_bytes(runtime, 1); 960 961 for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size) 962 *dma_ptr = 0; 963 964 return 0; 965 } 966 967 static struct snd_dmaengine_pcm_config mchp_pdmc_config = { 968 .process = mchp_pdmc_process, 969 }; 970 971 static int mchp_pdmc_probe(struct platform_device *pdev) 972 { 973 struct device *dev = &pdev->dev; 974 struct mchp_pdmc *dd; 975 struct resource *res; 976 void __iomem *io_base; 977 u32 version; 978 int irq; 979 int ret; 980 981 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL); 982 if (!dd) 983 return -ENOMEM; 984 985 dd->dev = &pdev->dev; 986 ret = mchp_pdmc_dt_init(dd); 987 if (ret < 0) 988 return ret; 989 990 irq = platform_get_irq(pdev, 0); 991 if (irq < 0) 992 return irq; 993 994 dd->pclk = devm_clk_get(dev, "pclk"); 995 if (IS_ERR(dd->pclk)) { 996 ret = PTR_ERR(dd->pclk); 997 dev_err(dev, "failed to get peripheral clock: %d\n", ret); 998 return ret; 999 } 1000 1001 dd->gclk = devm_clk_get(dev, "gclk"); 1002 if (IS_ERR(dd->gclk)) { 1003 ret = PTR_ERR(dd->gclk); 1004 dev_err(dev, "failed to get GCK: %d\n", ret); 1005 return ret; 1006 } 1007 1008 io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1009 if (IS_ERR(io_base)) { 1010 ret = PTR_ERR(io_base); 1011 dev_err(dev, "failed to remap register memory: %d\n", ret); 1012 return ret; 1013 } 1014 1015 dd->regmap = devm_regmap_init_mmio(dev, io_base, 1016 &mchp_pdmc_regmap_config); 1017 if (IS_ERR(dd->regmap)) { 1018 ret = PTR_ERR(dd->regmap); 1019 dev_err(dev, "failed to init register map: %d\n", ret); 1020 return ret; 1021 } 1022 1023 ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0, 1024 dev_name(&pdev->dev), (void *)dd); 1025 if (ret < 0) { 1026 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 1027 irq, ret); 1028 return ret; 1029 } 1030 1031 /* by default audio filter is enabled and the SINC Filter order 1032 * will be set to the recommended value, 3 1033 */ 1034 dd->audio_filter_en = true; 1035 dd->sinc_order = 3; 1036 1037 dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR; 1038 platform_set_drvdata(pdev, dd); 1039 1040 /* register platform */ 1041 ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0); 1042 if (ret) { 1043 dev_err(dev, "could not register platform: %d\n", ret); 1044 return ret; 1045 } 1046 1047 ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component, 1048 &mchp_pdmc_dai, 1); 1049 if (ret) { 1050 dev_err(dev, "could not register CPU DAI: %d\n", ret); 1051 return ret; 1052 } 1053 1054 /* print IP version */ 1055 regmap_read(dd->regmap, MCHP_PDMC_VER, &version); 1056 dev_info(dd->dev, "hw version: %#lx\n", 1057 version & MCHP_PDMC_VER_VERSION); 1058 1059 return 0; 1060 } 1061 1062 static const struct of_device_id mchp_pdmc_of_match[] = { 1063 { 1064 .compatible = "microchip,sama7g5-pdmc", 1065 }, { 1066 /* sentinel */ 1067 } 1068 }; 1069 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match); 1070 1071 static struct platform_driver mchp_pdmc_driver = { 1072 .driver = { 1073 .name = "mchp-pdmc", 1074 .of_match_table = of_match_ptr(mchp_pdmc_of_match), 1075 .pm = &snd_soc_pm_ops, 1076 }, 1077 .probe = mchp_pdmc_probe, 1078 }; 1079 module_platform_driver(mchp_pdmc_driver); 1080 1081 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture"); 1082 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 1083 MODULE_LICENSE("GPL v2"); 1084