1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/ingenic,tcu.h> 3#include <dt-bindings/clock/ingenic,x1830-cgu.h> 4#include <dt-bindings/dma/x1830-dma.h> 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "ingenic,x1830"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "ingenic,xburst-fpu2.0-mxu2.0"; 18 reg = <0>; 19 20 clocks = <&cgu X1830_CLK_CPU>; 21 clock-names = "cpu"; 22 }; 23 }; 24 25 cpuintc: interrupt-controller { 26 #address-cells = <0>; 27 #interrupt-cells = <1>; 28 interrupt-controller; 29 compatible = "mti,cpu-interrupt-controller"; 30 }; 31 32 intc: interrupt-controller@10001000 { 33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc"; 34 reg = <0x10001000 0x50>; 35 36 interrupt-controller; 37 #interrupt-cells = <1>; 38 39 interrupt-parent = <&cpuintc>; 40 interrupts = <2>; 41 }; 42 43 exclk: ext { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 rtclk: rtc { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <32768>; 52 }; 53 54 cgu: x1830-cgu@10000000 { 55 compatible = "ingenic,x1830-cgu", "simple-mfd"; 56 reg = <0x10000000 0x100>; 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges = <0x0 0x10000000 0x100>; 60 61 #clock-cells = <1>; 62 63 clocks = <&exclk>, <&rtclk>; 64 clock-names = "ext", "rtc"; 65 66 otg_phy: usb-phy@3c { 67 compatible = "ingenic,x1830-phy"; 68 reg = <0x3c 0x10>; 69 70 clocks = <&cgu X1830_CLK_OTGPHY>; 71 72 #phy-cells = <0>; 73 74 status = "disabled"; 75 }; 76 77 mac_phy_ctrl: mac-phy-ctrl@e8 { 78 compatible = "syscon"; 79 reg = <0xe8 0x4>; 80 }; 81 }; 82 83 ost: timer@12000000 { 84 compatible = "ingenic,x1830-ost", "ingenic,x1000-ost"; 85 reg = <0x12000000 0x3c>; 86 87 #clock-cells = <1>; 88 89 clocks = <&cgu X1830_CLK_OST>; 90 clock-names = "ost"; 91 92 interrupt-parent = <&cpuintc>; 93 interrupts = <4>; 94 }; 95 96 tcu: timer@10002000 { 97 compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd"; 98 reg = <0x10002000 0x1000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0x0 0x10002000 0x1000>; 102 103 #clock-cells = <1>; 104 105 clocks = <&cgu X1830_CLK_RTCLK>, 106 <&cgu X1830_CLK_EXCLK>, 107 <&cgu X1830_CLK_PCLK>; 108 clock-names = "rtc", "ext", "pclk"; 109 110 interrupt-controller; 111 #interrupt-cells = <1>; 112 113 interrupt-parent = <&intc>; 114 interrupts = <27 26 25>; 115 116 wdt: watchdog@0 { 117 compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog"; 118 reg = <0x0 0x10>; 119 120 clocks = <&tcu TCU_CLK_WDT>; 121 clock-names = "wdt"; 122 }; 123 124 pwm: pwm@40 { 125 compatible = "ingenic,x1830-pwm", "ingenic,jz4740-pwm"; 126 reg = <0x40 0x80>; 127 128 #pwm-cells = <3>; 129 130 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, 131 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, 132 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, 133 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; 134 clock-names = "timer0", "timer1", "timer2", "timer3", 135 "timer4", "timer5", "timer6", "timer7"; 136 }; 137 }; 138 139 rtc: rtc@10003000 { 140 compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc"; 141 reg = <0x10003000 0x4c>; 142 143 interrupt-parent = <&intc>; 144 interrupts = <32>; 145 146 clocks = <&cgu X1830_CLK_RTCLK>; 147 clock-names = "rtc"; 148 }; 149 150 pinctrl: pin-controller@10010000 { 151 compatible = "ingenic,x1830-pinctrl"; 152 reg = <0x10010000 0x800>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 gpa: gpio@0 { 157 compatible = "ingenic,x1830-gpio"; 158 reg = <0>; 159 160 gpio-controller; 161 gpio-ranges = <&pinctrl 0 0 32>; 162 #gpio-cells = <2>; 163 164 interrupt-controller; 165 #interrupt-cells = <2>; 166 167 interrupt-parent = <&intc>; 168 interrupts = <17>; 169 }; 170 171 gpb: gpio@1 { 172 compatible = "ingenic,x1830-gpio"; 173 reg = <1>; 174 175 gpio-controller; 176 gpio-ranges = <&pinctrl 0 32 32>; 177 #gpio-cells = <2>; 178 179 interrupt-controller; 180 #interrupt-cells = <2>; 181 182 interrupt-parent = <&intc>; 183 interrupts = <16>; 184 }; 185 186 gpc: gpio@2 { 187 compatible = "ingenic,x1830-gpio"; 188 reg = <2>; 189 190 gpio-controller; 191 gpio-ranges = <&pinctrl 0 64 32>; 192 #gpio-cells = <2>; 193 194 interrupt-controller; 195 #interrupt-cells = <2>; 196 197 interrupt-parent = <&intc>; 198 interrupts = <15>; 199 }; 200 201 gpd: gpio@3 { 202 compatible = "ingenic,x1830-gpio"; 203 reg = <3>; 204 205 gpio-controller; 206 gpio-ranges = <&pinctrl 0 96 32>; 207 #gpio-cells = <2>; 208 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 212 interrupt-parent = <&intc>; 213 interrupts = <14>; 214 }; 215 }; 216 217 uart0: serial@10030000 { 218 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart"; 219 reg = <0x10030000 0x100>; 220 221 interrupt-parent = <&intc>; 222 interrupts = <51>; 223 224 clocks = <&exclk>, <&cgu X1830_CLK_UART0>; 225 clock-names = "baud", "module"; 226 227 status = "disabled"; 228 }; 229 230 uart1: serial@10031000 { 231 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart"; 232 reg = <0x10031000 0x100>; 233 234 interrupt-parent = <&intc>; 235 interrupts = <50>; 236 237 clocks = <&exclk>, <&cgu X1830_CLK_UART1>; 238 clock-names = "baud", "module"; 239 240 status = "disabled"; 241 }; 242 243 ssi0: spi@10043000 { 244 compatible = "ingenic,x1830-spi", "ingenic,x1000-spi"; 245 reg = <0x10043000 0x20>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 249 interrupt-parent = <&intc>; 250 interrupts = <9>; 251 252 clocks = <&cgu X1830_CLK_SSI0>; 253 clock-names = "spi"; 254 255 dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>, 256 <&pdma X1830_DMA_SSI0_TX 0xffffffff>; 257 dma-names = "rx", "tx"; 258 259 status = "disabled"; 260 }; 261 262 ssi1: spi@10044000 { 263 compatible = "ingenic,x1830-spi", "ingenic,x1000-spi"; 264 reg = <0x10044000 0x20>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 268 interrupt-parent = <&intc>; 269 interrupts = <8>; 270 271 clocks = <&cgu X1830_CLK_SSI1>; 272 clock-names = "spi"; 273 274 dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>, 275 <&pdma X1830_DMA_SSI1_TX 0xffffffff>; 276 dma-names = "rx", "tx"; 277 278 status = "disabled"; 279 }; 280 281 i2c0: i2c-controller@10050000 { 282 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 283 reg = <0x10050000 0x1000>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 287 interrupt-parent = <&intc>; 288 interrupts = <60>; 289 290 clocks = <&cgu X1830_CLK_SMB0>; 291 292 status = "disabled"; 293 }; 294 295 i2c1: i2c-controller@10051000 { 296 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 297 reg = <0x10051000 0x1000>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 301 interrupt-parent = <&intc>; 302 interrupts = <59>; 303 304 clocks = <&cgu X1830_CLK_SMB1>; 305 306 status = "disabled"; 307 }; 308 309 i2c2: i2c-controller@10052000 { 310 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 311 reg = <0x10052000 0x1000>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 315 interrupt-parent = <&intc>; 316 interrupts = <58>; 317 318 clocks = <&cgu X1830_CLK_SMB2>; 319 320 status = "disabled"; 321 }; 322 323 dtrng: trng@10072000 { 324 compatible = "ingenic,x1830-dtrng"; 325 reg = <0x10072000 0xc>; 326 327 clocks = <&cgu X1830_CLK_DTRNG>; 328 329 status = "disabled"; 330 }; 331 332 pdma: dma-controller@13420000 { 333 compatible = "ingenic,x1830-dma"; 334 reg = <0x13420000 0x400>, <0x13421000 0x40>; 335 336 #dma-cells = <2>; 337 338 interrupt-parent = <&intc>; 339 interrupts = <10>; 340 341 clocks = <&cgu X1830_CLK_PDMA>; 342 }; 343 344 msc0: mmc@13450000 { 345 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc"; 346 reg = <0x13450000 0x1000>; 347 348 interrupt-parent = <&intc>; 349 interrupts = <37>; 350 351 clocks = <&cgu X1830_CLK_MSC0>; 352 clock-names = "mmc"; 353 354 cap-sd-highspeed; 355 cap-mmc-highspeed; 356 cap-sdio-irq; 357 358 dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>, 359 <&pdma X1830_DMA_MSC0_TX 0xffffffff>; 360 dma-names = "rx", "tx"; 361 362 status = "disabled"; 363 }; 364 365 msc1: mmc@13460000 { 366 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc"; 367 reg = <0x13460000 0x1000>; 368 369 interrupt-parent = <&intc>; 370 interrupts = <36>; 371 372 clocks = <&cgu X1830_CLK_MSC1>; 373 clock-names = "mmc"; 374 375 cap-sd-highspeed; 376 cap-mmc-highspeed; 377 cap-sdio-irq; 378 379 dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>, 380 <&pdma X1830_DMA_MSC1_TX 0xffffffff>; 381 dma-names = "rx", "tx"; 382 383 status = "disabled"; 384 }; 385 386 mac: ethernet@134b0000 { 387 compatible = "ingenic,x1830-mac", "snps,dwmac"; 388 reg = <0x134b0000 0x2000>; 389 390 interrupt-parent = <&intc>; 391 interrupts = <55>; 392 interrupt-names = "macirq"; 393 394 clocks = <&cgu X1830_CLK_MAC>; 395 clock-names = "stmmaceth"; 396 397 mode-reg = <&mac_phy_ctrl>; 398 399 status = "disabled"; 400 401 mdio: mdio { 402 compatible = "snps,dwmac-mdio"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 406 status = "disabled"; 407 }; 408 }; 409 410 otg: usb@13500000 { 411 compatible = "ingenic,x1830-otg"; 412 reg = <0x13500000 0x40000>; 413 414 interrupt-parent = <&intc>; 415 interrupts = <21>; 416 417 clocks = <&cgu X1830_CLK_OTG>; 418 clock-names = "otg"; 419 420 phys = <&otg_phy>; 421 phy-names = "usb2-phy"; 422 423 g-rx-fifo-size = <768>; 424 g-np-tx-fifo-size = <256>; 425 g-tx-fifo-size = <256 256 256 256 256 256 256 512>; 426 427 status = "disabled"; 428 }; 429}; 430