1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9#include "imx8mq.dtsi"
10
11/ {
12	model = "NXP i.MX8MQ EVK";
13	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0xc0000000>;
22	};
23
24	pcie0_refclk: pcie0-refclk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <100000000>;
28	};
29
30	reg_usdhc2_vmmc: regulator-vsd-3v3 {
31		pinctrl-names = "default";
32		pinctrl-0 = <&pinctrl_reg_usdhc2>;
33		compatible = "regulator-fixed";
34		regulator-name = "VSD_3V3";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38		enable-active-high;
39	};
40
41	buck2_reg: regulator-buck2 {
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_buck2>;
44		compatible = "regulator-gpio";
45		regulator-name = "vdd_arm";
46		regulator-min-microvolt = <900000>;
47		regulator-max-microvolt = <1000000>;
48		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
49		states = <1000000 0x0
50			  900000 0x1>;
51		regulator-boot-on;
52		regulator-always-on;
53	};
54
55	ir-receiver {
56		compatible = "gpio-ir-receiver";
57		gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
58		pinctrl-names = "default";
59		pinctrl-0 = <&pinctrl_ir>;
60		linux,autosuspend-period = <125>;
61	};
62
63	wm8524: audio-codec {
64		#sound-dai-cells = <0>;
65		compatible = "wlf,wm8524";
66		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
67	};
68
69	sound-wm8524 {
70		compatible = "simple-audio-card";
71		simple-audio-card,name = "wm8524-audio";
72		simple-audio-card,format = "i2s";
73		simple-audio-card,frame-master = <&cpudai>;
74		simple-audio-card,bitclock-master = <&cpudai>;
75		simple-audio-card,widgets =
76			"Line", "Left Line Out Jack",
77			"Line", "Right Line Out Jack";
78		simple-audio-card,routing =
79			"Left Line Out Jack", "LINEVOUTL",
80			"Right Line Out Jack", "LINEVOUTR";
81
82		cpudai: simple-audio-card,cpu {
83			sound-dai = <&sai2>;
84		};
85
86		link_codec: simple-audio-card,codec {
87			sound-dai = <&wm8524>;
88			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
89		};
90	};
91
92	sound-spdif {
93		compatible = "fsl,imx-audio-spdif";
94		model = "imx-spdif";
95		spdif-controller = <&spdif1>;
96		spdif-out;
97		spdif-in;
98	};
99
100	sound-hdmi-arc {
101		compatible = "fsl,imx-audio-spdif";
102		model = "imx-hdmi-arc";
103		spdif-controller = <&spdif2>;
104		spdif-in;
105	};
106};
107
108&A53_0 {
109	cpu-supply = <&buck2_reg>;
110};
111
112&A53_1 {
113	cpu-supply = <&buck2_reg>;
114};
115
116&A53_2 {
117	cpu-supply = <&buck2_reg>;
118};
119
120&A53_3 {
121	cpu-supply = <&buck2_reg>;
122};
123
124&ddrc {
125	operating-points-v2 = <&ddrc_opp_table>;
126
127	ddrc_opp_table: opp-table {
128		compatible = "operating-points-v2";
129
130		opp-25M {
131			opp-hz = /bits/ 64 <25000000>;
132		};
133
134		opp-100M {
135			opp-hz = /bits/ 64 <100000000>;
136		};
137
138		/*
139		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
140		 */
141		opp-166M {
142			opp-hz = /bits/ 64 <166935483>;
143		};
144
145		opp-800M {
146			opp-hz = /bits/ 64 <800000000>;
147		};
148	};
149};
150
151&dphy {
152	status = "okay";
153};
154
155&fec1 {
156	pinctrl-names = "default";
157	pinctrl-0 = <&pinctrl_fec1>;
158	phy-mode = "rgmii-id";
159	phy-handle = <&ethphy0>;
160	fsl,magic-packet;
161	status = "okay";
162
163	mdio {
164		#address-cells = <1>;
165		#size-cells = <0>;
166
167		ethphy0: ethernet-phy@0 {
168			compatible = "ethernet-phy-ieee802.3-c22";
169			reg = <0>;
170			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
171			reset-assert-us = <10000>;
172			qca,disable-smarteee;
173			vddio-supply = <&vddh>;
174
175			vddh: vddh-regulator {
176			};
177		};
178	};
179};
180
181&gpio5 {
182	pinctrl-names = "default";
183	pinctrl-0 = <&pinctrl_wifi_reset>;
184
185	wl-reg-on-hog {
186		gpio-hog;
187		gpios = <29 GPIO_ACTIVE_HIGH>;
188		output-high;
189	};
190};
191
192&i2c1 {
193	clock-frequency = <100000>;
194	pinctrl-names = "default";
195	pinctrl-0 = <&pinctrl_i2c1>;
196	status = "okay";
197
198	pmic@8 {
199		compatible = "fsl,pfuze100";
200		reg = <0x8>;
201
202		regulators {
203			sw1a_reg: sw1ab {
204				regulator-min-microvolt = <825000>;
205				regulator-max-microvolt = <1100000>;
206			};
207
208			sw1c_reg: sw1c {
209				regulator-min-microvolt = <825000>;
210				regulator-max-microvolt = <1100000>;
211			};
212
213			sw2_reg: sw2 {
214				regulator-min-microvolt = <1100000>;
215				regulator-max-microvolt = <1100000>;
216				regulator-always-on;
217			};
218
219			sw3a_reg: sw3ab {
220				regulator-min-microvolt = <825000>;
221				regulator-max-microvolt = <1100000>;
222				regulator-always-on;
223			};
224
225			sw4_reg: sw4 {
226				regulator-min-microvolt = <1800000>;
227				regulator-max-microvolt = <1800000>;
228				regulator-always-on;
229			};
230
231			swbst_reg: swbst {
232				regulator-min-microvolt = <5000000>;
233				regulator-max-microvolt = <5150000>;
234			};
235
236			snvs_reg: vsnvs {
237				regulator-min-microvolt = <1000000>;
238				regulator-max-microvolt = <3000000>;
239				regulator-always-on;
240			};
241
242			vref_reg: vrefddr {
243				regulator-always-on;
244			};
245
246			vgen1_reg: vgen1 {
247				regulator-min-microvolt = <800000>;
248				regulator-max-microvolt = <1550000>;
249			};
250
251			vgen2_reg: vgen2 {
252				regulator-min-microvolt = <850000>;
253				regulator-max-microvolt = <975000>;
254				regulator-always-on;
255			};
256
257			vgen3_reg: vgen3 {
258				regulator-min-microvolt = <1675000>;
259				regulator-max-microvolt = <1975000>;
260				regulator-always-on;
261			};
262
263			vgen4_reg: vgen4 {
264				regulator-min-microvolt = <1625000>;
265				regulator-max-microvolt = <1875000>;
266				regulator-always-on;
267			};
268
269			vgen5_reg: vgen5 {
270				regulator-min-microvolt = <3075000>;
271				regulator-max-microvolt = <3625000>;
272				regulator-always-on;
273			};
274
275			vgen6_reg: vgen6 {
276				regulator-min-microvolt = <1800000>;
277				regulator-max-microvolt = <3300000>;
278			};
279		};
280	};
281};
282
283&lcdif {
284	status = "okay";
285};
286
287&mipi_dsi {
288	#address-cells = <1>;
289	#size-cells = <0>;
290	status = "okay";
291
292	panel@0 {
293		pinctrl-0 = <&pinctrl_mipi_dsi>;
294		pinctrl-names = "default";
295		compatible = "raydium,rm67191";
296		reg = <0>;
297		reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
298		dsi-lanes = <4>;
299
300		port {
301			panel_in: endpoint {
302				remote-endpoint = <&mipi_dsi_out>;
303			};
304		};
305	};
306
307	ports {
308		port@1 {
309			reg = <1>;
310			mipi_dsi_out: endpoint {
311				remote-endpoint = <&panel_in>;
312			};
313		};
314	};
315};
316
317&pcie0 {
318	pinctrl-names = "default";
319	pinctrl-0 = <&pinctrl_pcie0>;
320	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
321	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
322		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
323		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
324		 <&pcie0_refclk>;
325	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
326	vph-supply = <&vgen5_reg>;
327	status = "okay";
328};
329
330&pgc_gpu {
331	power-supply = <&sw1a_reg>;
332};
333
334&pgc_vpu {
335	power-supply = <&sw1c_reg>;
336};
337
338&qspi0 {
339	pinctrl-names = "default";
340	pinctrl-0 = <&pinctrl_qspi>;
341	status = "okay";
342
343	n25q256a: flash@0 {
344		reg = <0>;
345		#address-cells = <1>;
346		#size-cells = <1>;
347		compatible = "micron,n25q256a", "jedec,spi-nor";
348		spi-max-frequency = <29000000>;
349		spi-tx-bus-width = <1>;
350		spi-rx-bus-width = <4>;
351	};
352};
353
354&sai2 {
355	pinctrl-names = "default";
356	pinctrl-0 = <&pinctrl_sai2>;
357	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
358	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
359	assigned-clock-rates = <0>, <24576000>;
360	status = "okay";
361};
362
363&snvs_pwrkey {
364	status = "okay";
365};
366
367&spdif1 {
368	pinctrl-names = "default";
369	pinctrl-0 = <&pinctrl_spdif1>;
370	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
371	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
372	assigned-clock-rates = <24576000>;
373	status = "okay";
374};
375
376&spdif2 {
377	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
378	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
379	assigned-clock-rates = <24576000>;
380	status = "okay";
381};
382
383&uart1 {
384	pinctrl-names = "default";
385	pinctrl-0 = <&pinctrl_uart1>;
386	status = "okay";
387};
388
389&usb3_phy1 {
390	status = "okay";
391};
392
393&usb_dwc3_1 {
394	dr_mode = "host";
395	status = "okay";
396};
397
398&usdhc1 {
399	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
400	assigned-clock-rates = <400000000>;
401	pinctrl-names = "default", "state_100mhz", "state_200mhz";
402	pinctrl-0 = <&pinctrl_usdhc1>;
403	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
404	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
405	vqmmc-supply = <&sw4_reg>;
406	bus-width = <8>;
407	non-removable;
408	no-sd;
409	no-sdio;
410	status = "okay";
411};
412
413&usdhc2 {
414	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
415	assigned-clock-rates = <200000000>;
416	pinctrl-names = "default", "state_100mhz", "state_200mhz";
417	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
418	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
419	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
420	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
421	vmmc-supply = <&reg_usdhc2_vmmc>;
422	status = "okay";
423};
424
425&wdog1 {
426	pinctrl-names = "default";
427	pinctrl-0 = <&pinctrl_wdog>;
428	fsl,ext-reset-output;
429	status = "okay";
430};
431
432&iomuxc {
433	pinctrl_buck2: vddarmgrp {
434		fsl,pins = <
435			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
436		>;
437	};
438
439	pinctrl_fec1: fec1grp {
440		fsl,pins = <
441			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
442			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
443			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
444			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
445			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
446			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
447			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
448			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
449			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
450			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
451			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
452			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
453			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
454			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
455			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
456		>;
457	};
458
459	pinctrl_i2c1: i2c1grp {
460		fsl,pins = <
461			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
462			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
463		>;
464	};
465
466	pinctrl_ir: irgrp {
467		fsl,pins = <
468			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x4f
469		>;
470	};
471
472	pinctrl_mipi_dsi: mipidsigrp {
473		fsl,pins = <
474			MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6		0x16
475		>;
476	};
477
478	pinctrl_pcie0: pcie0grp {
479		fsl,pins = <
480			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
481			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16
482		>;
483	};
484
485	pinctrl_qspi: qspigrp {
486		fsl,pins = <
487			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
488			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
489			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
490			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
491			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
492			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
493		>;
494	};
495
496	pinctrl_reg_usdhc2: regusdhc2gpiogrp {
497		fsl,pins = <
498			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
499		>;
500	};
501
502	pinctrl_sai2: sai2grp {
503		fsl,pins = <
504			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
505			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
506			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
507			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
508			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
509		>;
510	};
511
512	pinctrl_spdif1: spdif1grp {
513		fsl,pins = <
514			MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
515			MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
516		>;
517	};
518
519	pinctrl_uart1: uart1grp {
520		fsl,pins = <
521			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
522			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
523		>;
524	};
525
526	pinctrl_usdhc1: usdhc1grp {
527		fsl,pins = <
528			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
529			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
530			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
531			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
532			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
533			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
534			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
535			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
536			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
537			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
538			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
539			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
540		>;
541	};
542
543	pinctrl_usdhc1_100mhz: usdhc1-100grp {
544		fsl,pins = <
545			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
546			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
547			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
548			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
549			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
550			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
551			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
552			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
553			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
554			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
555			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
556			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
557		>;
558	};
559
560	pinctrl_usdhc1_200mhz: usdhc1-200grp {
561		fsl,pins = <
562			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
563			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
564			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
565			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
566			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
567			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
568			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
569			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
570			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
571			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
572			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
573			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
574		>;
575	};
576
577	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
578		fsl,pins = <
579			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
580		>;
581	};
582
583	pinctrl_usdhc2: usdhc2grp {
584		fsl,pins = <
585			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
586			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
587			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
588			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
589			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
590			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
591			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
592		>;
593	};
594
595	pinctrl_usdhc2_100mhz: usdhc2-100grp {
596		fsl,pins = <
597			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
598			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
599			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
600			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
601			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
602			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
603			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
604		>;
605	};
606
607	pinctrl_usdhc2_200mhz: usdhc2-200grp {
608		fsl,pins = <
609			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
610			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
611			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
612			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
613			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
614			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
615			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
616		>;
617	};
618
619	pinctrl_wdog: wdog1grp {
620		fsl,pins = <
621			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
622		>;
623	};
624
625	pinctrl_wifi_reset: wifiresetgrp {
626		fsl,pins = <
627			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
628		>;
629	};
630};
631