1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41-lib.c -- CS35L41 Common functions for HDA and ASoC Audio drivers 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 // Author: Lucas Tanure <lucas.tanure@cirrus.com> 9 10 #include <linux/dev_printk.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/slab.h> 15 16 #include <sound/cs35l41.h> 17 18 static const struct reg_default cs35l41_reg[] = { 19 { CS35L41_PWR_CTRL1, 0x00000000 }, 20 { CS35L41_PWR_CTRL2, 0x00000000 }, 21 { CS35L41_PWR_CTRL3, 0x01000010 }, 22 { CS35L41_GPIO_PAD_CONTROL, 0x00000000 }, 23 { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, 24 { CS35L41_TST_FS_MON0, 0x00020016 }, 25 { CS35L41_BSTCVRT_COEFF, 0x00002424 }, 26 { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 }, 27 { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A }, 28 { CS35L41_SP_ENABLES, 0x00000000 }, 29 { CS35L41_SP_RATE_CTRL, 0x00000028 }, 30 { CS35L41_SP_FORMAT, 0x18180200 }, 31 { CS35L41_SP_HIZ_CTRL, 0x00000002 }, 32 { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 }, 33 { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 }, 34 { CS35L41_SP_TX_WL, 0x00000018 }, 35 { CS35L41_SP_RX_WL, 0x00000018 }, 36 { CS35L41_DAC_PCM1_SRC, 0x00000008 }, 37 { CS35L41_ASP_TX1_SRC, 0x00000018 }, 38 { CS35L41_ASP_TX2_SRC, 0x00000019 }, 39 { CS35L41_ASP_TX3_SRC, 0x00000020 }, 40 { CS35L41_ASP_TX4_SRC, 0x00000021 }, 41 { CS35L41_DSP1_RX1_SRC, 0x00000008 }, 42 { CS35L41_DSP1_RX2_SRC, 0x00000009 }, 43 { CS35L41_DSP1_RX3_SRC, 0x00000018 }, 44 { CS35L41_DSP1_RX4_SRC, 0x00000019 }, 45 { CS35L41_DSP1_RX5_SRC, 0x00000020 }, 46 { CS35L41_DSP1_RX6_SRC, 0x00000021 }, 47 { CS35L41_DSP1_RX7_SRC, 0x0000003A }, 48 { CS35L41_DSP1_RX8_SRC, 0x00000001 }, 49 { CS35L41_NGATE1_SRC, 0x00000008 }, 50 { CS35L41_NGATE2_SRC, 0x00000009 }, 51 { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 }, 52 { CS35L41_CLASSH_CFG, 0x000B0405 }, 53 { CS35L41_WKFET_CFG, 0x00000111 }, 54 { CS35L41_NG_CFG, 0x00000033 }, 55 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 56 { CS35L41_IRQ1_MASK1, 0xFFFFFFFF }, 57 { CS35L41_IRQ1_MASK2, 0xFFFFFFFF }, 58 { CS35L41_IRQ1_MASK3, 0xFFFF87FF }, 59 { CS35L41_IRQ1_MASK4, 0xFEFFFFFF }, 60 { CS35L41_GPIO1_CTRL1, 0xE1000001 }, 61 { CS35L41_GPIO2_CTRL1, 0xE1000001 }, 62 { CS35L41_MIXER_NGATE_CFG, 0x00000000 }, 63 { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 }, 64 { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 }, 65 { CS35L41_DSP1_CCM_CORE_CTRL, 0x00000101 }, 66 }; 67 68 static bool cs35l41_readable_reg(struct device *dev, unsigned int reg) 69 { 70 switch (reg) { 71 case CS35L41_DEVID: 72 case CS35L41_REVID: 73 case CS35L41_FABID: 74 case CS35L41_RELID: 75 case CS35L41_OTPID: 76 case CS35L41_TEST_KEY_CTL: 77 case CS35L41_USER_KEY_CTL: 78 case CS35L41_OTP_CTRL0: 79 case CS35L41_OTP_CTRL3: 80 case CS35L41_OTP_CTRL4: 81 case CS35L41_OTP_CTRL5: 82 case CS35L41_OTP_CTRL6: 83 case CS35L41_OTP_CTRL7: 84 case CS35L41_OTP_CTRL8: 85 case CS35L41_PWR_CTRL1: 86 case CS35L41_PWR_CTRL2: 87 case CS35L41_PWR_CTRL3: 88 case CS35L41_CTRL_OVRRIDE: 89 case CS35L41_AMP_OUT_MUTE: 90 case CS35L41_PROTECT_REL_ERR_IGN: 91 case CS35L41_GPIO_PAD_CONTROL: 92 case CS35L41_JTAG_CONTROL: 93 case CS35L41_PWRMGT_CTL: 94 case CS35L41_WAKESRC_CTL: 95 case CS35L41_PWRMGT_STS: 96 case CS35L41_PLL_CLK_CTRL: 97 case CS35L41_DSP_CLK_CTRL: 98 case CS35L41_GLOBAL_CLK_CTRL: 99 case CS35L41_DATA_FS_SEL: 100 case CS35L41_TST_FS_MON0: 101 case CS35L41_MDSYNC_EN: 102 case CS35L41_MDSYNC_TX_ID: 103 case CS35L41_MDSYNC_PWR_CTRL: 104 case CS35L41_MDSYNC_DATA_TX: 105 case CS35L41_MDSYNC_TX_STATUS: 106 case CS35L41_MDSYNC_DATA_RX: 107 case CS35L41_MDSYNC_RX_STATUS: 108 case CS35L41_MDSYNC_ERR_STATUS: 109 case CS35L41_MDSYNC_SYNC_PTE2: 110 case CS35L41_MDSYNC_SYNC_PTE3: 111 case CS35L41_MDSYNC_SYNC_MSM_STATUS: 112 case CS35L41_BSTCVRT_VCTRL1: 113 case CS35L41_BSTCVRT_VCTRL2: 114 case CS35L41_BSTCVRT_PEAK_CUR: 115 case CS35L41_BSTCVRT_SFT_RAMP: 116 case CS35L41_BSTCVRT_COEFF: 117 case CS35L41_BSTCVRT_SLOPE_LBST: 118 case CS35L41_BSTCVRT_SW_FREQ: 119 case CS35L41_BSTCVRT_DCM_CTRL: 120 case CS35L41_BSTCVRT_DCM_MODE_FORCE: 121 case CS35L41_BSTCVRT_OVERVOLT_CTRL: 122 case CS35L41_VI_VOL_POL: 123 case CS35L41_DTEMP_WARN_THLD: 124 case CS35L41_DTEMP_CFG: 125 case CS35L41_DTEMP_EN: 126 case CS35L41_VPVBST_FS_SEL: 127 case CS35L41_SP_ENABLES: 128 case CS35L41_SP_RATE_CTRL: 129 case CS35L41_SP_FORMAT: 130 case CS35L41_SP_HIZ_CTRL: 131 case CS35L41_SP_FRAME_TX_SLOT: 132 case CS35L41_SP_FRAME_RX_SLOT: 133 case CS35L41_SP_TX_WL: 134 case CS35L41_SP_RX_WL: 135 case CS35L41_DAC_PCM1_SRC: 136 case CS35L41_ASP_TX1_SRC: 137 case CS35L41_ASP_TX2_SRC: 138 case CS35L41_ASP_TX3_SRC: 139 case CS35L41_ASP_TX4_SRC: 140 case CS35L41_DSP1_RX1_SRC: 141 case CS35L41_DSP1_RX2_SRC: 142 case CS35L41_DSP1_RX3_SRC: 143 case CS35L41_DSP1_RX4_SRC: 144 case CS35L41_DSP1_RX5_SRC: 145 case CS35L41_DSP1_RX6_SRC: 146 case CS35L41_DSP1_RX7_SRC: 147 case CS35L41_DSP1_RX8_SRC: 148 case CS35L41_NGATE1_SRC: 149 case CS35L41_NGATE2_SRC: 150 case CS35L41_AMP_DIG_VOL_CTRL: 151 case CS35L41_VPBR_CFG: 152 case CS35L41_VBBR_CFG: 153 case CS35L41_VPBR_STATUS: 154 case CS35L41_VBBR_STATUS: 155 case CS35L41_OVERTEMP_CFG: 156 case CS35L41_AMP_ERR_VOL: 157 case CS35L41_VOL_STATUS_TO_DSP: 158 case CS35L41_CLASSH_CFG: 159 case CS35L41_WKFET_CFG: 160 case CS35L41_NG_CFG: 161 case CS35L41_AMP_GAIN_CTRL: 162 case CS35L41_DAC_MSM_CFG: 163 case CS35L41_IRQ1_CFG: 164 case CS35L41_IRQ1_STATUS: 165 case CS35L41_IRQ1_STATUS1: 166 case CS35L41_IRQ1_STATUS2: 167 case CS35L41_IRQ1_STATUS3: 168 case CS35L41_IRQ1_STATUS4: 169 case CS35L41_IRQ1_RAW_STATUS1: 170 case CS35L41_IRQ1_RAW_STATUS2: 171 case CS35L41_IRQ1_RAW_STATUS3: 172 case CS35L41_IRQ1_RAW_STATUS4: 173 case CS35L41_IRQ1_MASK1: 174 case CS35L41_IRQ1_MASK2: 175 case CS35L41_IRQ1_MASK3: 176 case CS35L41_IRQ1_MASK4: 177 case CS35L41_IRQ1_FRC1: 178 case CS35L41_IRQ1_FRC2: 179 case CS35L41_IRQ1_FRC3: 180 case CS35L41_IRQ1_FRC4: 181 case CS35L41_IRQ1_EDGE1: 182 case CS35L41_IRQ1_EDGE4: 183 case CS35L41_IRQ1_POL1: 184 case CS35L41_IRQ1_POL2: 185 case CS35L41_IRQ1_POL3: 186 case CS35L41_IRQ1_POL4: 187 case CS35L41_IRQ1_DB3: 188 case CS35L41_IRQ2_CFG: 189 case CS35L41_IRQ2_STATUS: 190 case CS35L41_IRQ2_STATUS1: 191 case CS35L41_IRQ2_STATUS2: 192 case CS35L41_IRQ2_STATUS3: 193 case CS35L41_IRQ2_STATUS4: 194 case CS35L41_IRQ2_RAW_STATUS1: 195 case CS35L41_IRQ2_RAW_STATUS2: 196 case CS35L41_IRQ2_RAW_STATUS3: 197 case CS35L41_IRQ2_RAW_STATUS4: 198 case CS35L41_IRQ2_MASK1: 199 case CS35L41_IRQ2_MASK2: 200 case CS35L41_IRQ2_MASK3: 201 case CS35L41_IRQ2_MASK4: 202 case CS35L41_IRQ2_FRC1: 203 case CS35L41_IRQ2_FRC2: 204 case CS35L41_IRQ2_FRC3: 205 case CS35L41_IRQ2_FRC4: 206 case CS35L41_IRQ2_EDGE1: 207 case CS35L41_IRQ2_EDGE4: 208 case CS35L41_IRQ2_POL1: 209 case CS35L41_IRQ2_POL2: 210 case CS35L41_IRQ2_POL3: 211 case CS35L41_IRQ2_POL4: 212 case CS35L41_IRQ2_DB3: 213 case CS35L41_GPIO_STATUS1: 214 case CS35L41_GPIO1_CTRL1: 215 case CS35L41_GPIO2_CTRL1: 216 case CS35L41_MIXER_NGATE_CFG: 217 case CS35L41_MIXER_NGATE_CH1_CFG: 218 case CS35L41_MIXER_NGATE_CH2_CFG: 219 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: 220 case CS35L41_CLOCK_DETECT_1: 221 case CS35L41_DIE_STS1: 222 case CS35L41_DIE_STS2: 223 case CS35L41_TEMP_CAL1: 224 case CS35L41_TEMP_CAL2: 225 case CS35L41_DSP1_TIMESTAMP_COUNT: 226 case CS35L41_DSP1_SYS_ID: 227 case CS35L41_DSP1_SYS_VERSION: 228 case CS35L41_DSP1_SYS_CORE_ID: 229 case CS35L41_DSP1_SYS_AHB_ADDR: 230 case CS35L41_DSP1_SYS_XSRAM_SIZE: 231 case CS35L41_DSP1_SYS_YSRAM_SIZE: 232 case CS35L41_DSP1_SYS_PSRAM_SIZE: 233 case CS35L41_DSP1_SYS_PM_BOOT_SIZE: 234 case CS35L41_DSP1_SYS_FEATURES: 235 case CS35L41_DSP1_SYS_FIR_FILTERS: 236 case CS35L41_DSP1_SYS_LMS_FILTERS: 237 case CS35L41_DSP1_SYS_XM_BANK_SIZE: 238 case CS35L41_DSP1_SYS_YM_BANK_SIZE: 239 case CS35L41_DSP1_SYS_PM_BANK_SIZE: 240 case CS35L41_DSP1_RX1_RATE: 241 case CS35L41_DSP1_RX2_RATE: 242 case CS35L41_DSP1_RX3_RATE: 243 case CS35L41_DSP1_RX4_RATE: 244 case CS35L41_DSP1_RX5_RATE: 245 case CS35L41_DSP1_RX6_RATE: 246 case CS35L41_DSP1_RX7_RATE: 247 case CS35L41_DSP1_RX8_RATE: 248 case CS35L41_DSP1_TX1_RATE: 249 case CS35L41_DSP1_TX2_RATE: 250 case CS35L41_DSP1_TX3_RATE: 251 case CS35L41_DSP1_TX4_RATE: 252 case CS35L41_DSP1_TX5_RATE: 253 case CS35L41_DSP1_TX6_RATE: 254 case CS35L41_DSP1_TX7_RATE: 255 case CS35L41_DSP1_TX8_RATE: 256 case CS35L41_DSP1_SCRATCH1: 257 case CS35L41_DSP1_SCRATCH2: 258 case CS35L41_DSP1_SCRATCH3: 259 case CS35L41_DSP1_SCRATCH4: 260 case CS35L41_DSP1_CCM_CORE_CTRL: 261 case CS35L41_DSP1_CCM_CLK_OVERRIDE: 262 case CS35L41_DSP1_XM_MSTR_EN: 263 case CS35L41_DSP1_XM_CORE_PRI: 264 case CS35L41_DSP1_XM_AHB_PACK_PL_PRI: 265 case CS35L41_DSP1_XM_AHB_UP_PL_PRI: 266 case CS35L41_DSP1_XM_ACCEL_PL0_PRI: 267 case CS35L41_DSP1_XM_NPL0_PRI: 268 case CS35L41_DSP1_YM_MSTR_EN: 269 case CS35L41_DSP1_YM_CORE_PRI: 270 case CS35L41_DSP1_YM_AHB_PACK_PL_PRI: 271 case CS35L41_DSP1_YM_AHB_UP_PL_PRI: 272 case CS35L41_DSP1_YM_ACCEL_PL0_PRI: 273 case CS35L41_DSP1_YM_NPL0_PRI: 274 case CS35L41_DSP1_MPU_XM_ACCESS0: 275 case CS35L41_DSP1_MPU_YM_ACCESS0: 276 case CS35L41_DSP1_MPU_WNDW_ACCESS0: 277 case CS35L41_DSP1_MPU_XREG_ACCESS0: 278 case CS35L41_DSP1_MPU_YREG_ACCESS0: 279 case CS35L41_DSP1_MPU_XM_ACCESS1: 280 case CS35L41_DSP1_MPU_YM_ACCESS1: 281 case CS35L41_DSP1_MPU_WNDW_ACCESS1: 282 case CS35L41_DSP1_MPU_XREG_ACCESS1: 283 case CS35L41_DSP1_MPU_YREG_ACCESS1: 284 case CS35L41_DSP1_MPU_XM_ACCESS2: 285 case CS35L41_DSP1_MPU_YM_ACCESS2: 286 case CS35L41_DSP1_MPU_WNDW_ACCESS2: 287 case CS35L41_DSP1_MPU_XREG_ACCESS2: 288 case CS35L41_DSP1_MPU_YREG_ACCESS2: 289 case CS35L41_DSP1_MPU_XM_ACCESS3: 290 case CS35L41_DSP1_MPU_YM_ACCESS3: 291 case CS35L41_DSP1_MPU_WNDW_ACCESS3: 292 case CS35L41_DSP1_MPU_XREG_ACCESS3: 293 case CS35L41_DSP1_MPU_YREG_ACCESS3: 294 case CS35L41_DSP1_MPU_XM_VIO_ADDR: 295 case CS35L41_DSP1_MPU_XM_VIO_STATUS: 296 case CS35L41_DSP1_MPU_YM_VIO_ADDR: 297 case CS35L41_DSP1_MPU_YM_VIO_STATUS: 298 case CS35L41_DSP1_MPU_PM_VIO_ADDR: 299 case CS35L41_DSP1_MPU_PM_VIO_STATUS: 300 case CS35L41_DSP1_MPU_LOCK_CONFIG: 301 case CS35L41_DSP1_MPU_WDT_RST_CTRL: 302 case CS35L41_OTP_TRIM_1: 303 case CS35L41_OTP_TRIM_2: 304 case CS35L41_OTP_TRIM_3: 305 case CS35L41_OTP_TRIM_4: 306 case CS35L41_OTP_TRIM_5: 307 case CS35L41_OTP_TRIM_6: 308 case CS35L41_OTP_TRIM_7: 309 case CS35L41_OTP_TRIM_8: 310 case CS35L41_OTP_TRIM_9: 311 case CS35L41_OTP_TRIM_10: 312 case CS35L41_OTP_TRIM_11: 313 case CS35L41_OTP_TRIM_12: 314 case CS35L41_OTP_TRIM_13: 315 case CS35L41_OTP_TRIM_14: 316 case CS35L41_OTP_TRIM_15: 317 case CS35L41_OTP_TRIM_16: 318 case CS35L41_OTP_TRIM_17: 319 case CS35L41_OTP_TRIM_18: 320 case CS35L41_OTP_TRIM_19: 321 case CS35L41_OTP_TRIM_20: 322 case CS35L41_OTP_TRIM_21: 323 case CS35L41_OTP_TRIM_22: 324 case CS35L41_OTP_TRIM_23: 325 case CS35L41_OTP_TRIM_24: 326 case CS35L41_OTP_TRIM_25: 327 case CS35L41_OTP_TRIM_26: 328 case CS35L41_OTP_TRIM_27: 329 case CS35L41_OTP_TRIM_28: 330 case CS35L41_OTP_TRIM_29: 331 case CS35L41_OTP_TRIM_30: 332 case CS35L41_OTP_TRIM_31: 333 case CS35L41_OTP_TRIM_32: 334 case CS35L41_OTP_TRIM_33: 335 case CS35L41_OTP_TRIM_34: 336 case CS35L41_OTP_TRIM_35: 337 case CS35L41_OTP_TRIM_36: 338 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 339 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 340 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: 341 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: 342 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 343 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: 344 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: 345 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 346 /*test regs*/ 347 case CS35L41_PLL_OVR: 348 case CS35L41_BST_TEST_DUTY: 349 case CS35L41_DIGPWM_IOCTRL: 350 return true; 351 default: 352 return false; 353 } 354 } 355 356 static bool cs35l41_precious_reg(struct device *dev, unsigned int reg) 357 { 358 switch (reg) { 359 case CS35L41_TEST_KEY_CTL: 360 case CS35L41_USER_KEY_CTL: 361 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 362 case CS35L41_TST_FS_MON0: 363 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 364 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 365 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 366 return true; 367 default: 368 return false; 369 } 370 } 371 372 static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg) 373 { 374 switch (reg) { 375 case CS35L41_DEVID: 376 case CS35L41_SFT_RESET: 377 case CS35L41_FABID: 378 case CS35L41_REVID: 379 case CS35L41_OTPID: 380 case CS35L41_TEST_KEY_CTL: 381 case CS35L41_USER_KEY_CTL: 382 case CS35L41_PWRMGT_CTL: 383 case CS35L41_WAKESRC_CTL: 384 case CS35L41_PWRMGT_STS: 385 case CS35L41_DTEMP_EN: 386 case CS35L41_IRQ1_STATUS: 387 case CS35L41_IRQ1_STATUS1: 388 case CS35L41_IRQ1_STATUS2: 389 case CS35L41_IRQ1_STATUS3: 390 case CS35L41_IRQ1_STATUS4: 391 case CS35L41_IRQ1_RAW_STATUS1: 392 case CS35L41_IRQ1_RAW_STATUS2: 393 case CS35L41_IRQ1_RAW_STATUS3: 394 case CS35L41_IRQ1_RAW_STATUS4: 395 case CS35L41_IRQ2_STATUS: 396 case CS35L41_IRQ2_STATUS1: 397 case CS35L41_IRQ2_STATUS2: 398 case CS35L41_IRQ2_STATUS3: 399 case CS35L41_IRQ2_STATUS4: 400 case CS35L41_IRQ2_RAW_STATUS1: 401 case CS35L41_IRQ2_RAW_STATUS2: 402 case CS35L41_IRQ2_RAW_STATUS3: 403 case CS35L41_IRQ2_RAW_STATUS4: 404 case CS35L41_GPIO_STATUS1: 405 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: 406 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 407 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: 408 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: 409 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 410 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: 411 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: 412 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 413 case CS35L41_DSP1_SCRATCH1: 414 case CS35L41_DSP1_SCRATCH2: 415 case CS35L41_DSP1_SCRATCH3: 416 case CS35L41_DSP1_SCRATCH4: 417 case CS35L41_DSP1_CCM_CLK_OVERRIDE ... CS35L41_DSP1_WDT_STATUS: 418 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 419 return true; 420 default: 421 return false; 422 } 423 } 424 425 static const struct cs35l41_otp_packed_element_t otp_map_1[CS35L41_NUM_OTP_ELEM] = { 426 /* addr shift size */ 427 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ 428 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ 429 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ 430 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ 431 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ 432 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ 433 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ 434 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ 435 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ 436 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ 437 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ 438 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ 439 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ 440 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ 441 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ 442 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ 443 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ 444 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ 445 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ 446 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ 447 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ 448 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ 449 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ 450 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ 451 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ 452 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ 453 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ 454 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ 455 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ 456 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ 457 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ 458 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ 459 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ 460 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ 461 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ 462 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ 463 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ 464 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ 465 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ 466 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ 467 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ 468 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ 469 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ 470 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ 471 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ 472 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ 473 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ 474 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ 475 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ 476 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ 477 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ 478 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ 479 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ 480 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ 481 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ 482 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ 483 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ 484 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ 485 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ 486 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ 487 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ 488 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ 489 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ 490 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ 491 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ 492 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ 493 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ 494 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ 495 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ 496 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ 497 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ 498 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ 499 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ 500 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ 501 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ 502 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ 503 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ 504 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ 505 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ 506 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ 507 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ 508 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ 509 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ 510 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ 511 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ 512 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ 513 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ 514 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ 515 { 0x00007434, 17, 1 }, /*FORCE_CAL*/ 516 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ 517 { 0x00007068, 0, 9 }, /*MODIX*/ 518 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ 519 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ 520 { 0x00000000, 0, 1 }, /*extra bit*/ 521 { 0x00017040, 0, 8 }, /*X_COORDINATE*/ 522 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ 523 { 0x00017040, 16, 8 }, /*WAFER_ID*/ 524 { 0x00017040, 24, 8 }, /*DVS*/ 525 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ 526 }; 527 528 static const struct cs35l41_otp_packed_element_t otp_map_2[CS35L41_NUM_OTP_ELEM] = { 529 /* addr shift size */ 530 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ 531 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ 532 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ 533 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ 534 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ 535 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ 536 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ 537 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ 538 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ 539 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ 540 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ 541 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ 542 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ 543 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ 544 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ 545 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ 546 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ 547 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ 548 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ 549 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ 550 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ 551 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ 552 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ 553 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ 554 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ 555 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ 556 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ 557 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ 558 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ 559 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ 560 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ 561 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ 562 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ 563 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ 564 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ 565 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ 566 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ 567 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ 568 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ 569 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ 570 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ 571 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ 572 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ 573 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ 574 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ 575 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ 576 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ 577 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ 578 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ 579 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ 580 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ 581 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ 582 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ 583 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ 584 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ 585 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ 586 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ 587 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ 588 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ 589 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ 590 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ 591 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ 592 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ 593 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ 594 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ 595 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ 596 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ 597 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ 598 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ 599 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ 600 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ 601 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ 602 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ 603 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ 604 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ 605 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ 606 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ 607 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ 608 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ 609 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ 610 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ 611 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ 612 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ 613 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ 614 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ 615 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ 616 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ 617 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ 618 { 0x00007434, 17, 1 }, /*FORCE_CAL*/ 619 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ 620 { 0x00007068, 0, 9 }, /*MODIX*/ 621 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ 622 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ 623 { 0x00004000, 11, 1 }, /*VMON_POL*/ 624 { 0x00017040, 0, 8 }, /*X_COORDINATE*/ 625 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ 626 { 0x00017040, 16, 8 }, /*WAFER_ID*/ 627 { 0x00017040, 24, 8 }, /*DVS*/ 628 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ 629 }; 630 631 static const struct reg_sequence cs35l41_reva0_errata_patch[] = { 632 { 0x00003854, 0x05180240 }, 633 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 634 { 0x00004310, 0x00000000 }, 635 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 636 { CS35L41_OTP_TRIM_30, 0x9091A1C8 }, 637 { 0x00003014, 0x0200EE0E }, 638 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 639 { 0x00000054, 0x00000004 }, 640 { CS35L41_IRQ1_DB3, 0x00000000 }, 641 { CS35L41_IRQ2_DB3, 0x00000000 }, 642 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 643 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 644 { CS35L41_PWR_CTRL2, 0x00000000 }, 645 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 646 }; 647 648 static const struct reg_sequence cs35l41_revb0_errata_patch[] = { 649 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 650 { 0x00004310, 0x00000000 }, 651 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 652 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 653 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 654 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 655 { CS35L41_PWR_CTRL2, 0x00000000 }, 656 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 657 }; 658 659 static const struct reg_sequence cs35l41_revb2_errata_patch[] = { 660 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 661 { 0x00004310, 0x00000000 }, 662 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 663 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 664 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 665 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 666 { CS35L41_PWR_CTRL2, 0x00000000 }, 667 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 668 }; 669 670 static const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = { 671 { 672 .id = 0x01, 673 .map = otp_map_1, 674 .num_elements = CS35L41_NUM_OTP_ELEM, 675 .bit_offset = 16, 676 .word_offset = 2, 677 }, 678 { 679 .id = 0x02, 680 .map = otp_map_2, 681 .num_elements = CS35L41_NUM_OTP_ELEM, 682 .bit_offset = 16, 683 .word_offset = 2, 684 }, 685 { 686 .id = 0x03, 687 .map = otp_map_2, 688 .num_elements = CS35L41_NUM_OTP_ELEM, 689 .bit_offset = 16, 690 .word_offset = 2, 691 }, 692 { 693 .id = 0x06, 694 .map = otp_map_2, 695 .num_elements = CS35L41_NUM_OTP_ELEM, 696 .bit_offset = 16, 697 .word_offset = 2, 698 }, 699 { 700 .id = 0x08, 701 .map = otp_map_1, 702 .num_elements = CS35L41_NUM_OTP_ELEM, 703 .bit_offset = 16, 704 .word_offset = 2, 705 }, 706 }; 707 708 struct regmap_config cs35l41_regmap_i2c = { 709 .reg_bits = 32, 710 .val_bits = 32, 711 .reg_stride = CS35L41_REGSTRIDE, 712 .reg_format_endian = REGMAP_ENDIAN_BIG, 713 .val_format_endian = REGMAP_ENDIAN_BIG, 714 .max_register = CS35L41_LASTREG, 715 .reg_defaults = cs35l41_reg, 716 .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), 717 .volatile_reg = cs35l41_volatile_reg, 718 .readable_reg = cs35l41_readable_reg, 719 .precious_reg = cs35l41_precious_reg, 720 .cache_type = REGCACHE_RBTREE, 721 }; 722 EXPORT_SYMBOL_GPL(cs35l41_regmap_i2c); 723 724 struct regmap_config cs35l41_regmap_spi = { 725 .reg_bits = 32, 726 .val_bits = 32, 727 .pad_bits = 16, 728 .reg_stride = CS35L41_REGSTRIDE, 729 .reg_format_endian = REGMAP_ENDIAN_BIG, 730 .val_format_endian = REGMAP_ENDIAN_BIG, 731 .max_register = CS35L41_LASTREG, 732 .reg_defaults = cs35l41_reg, 733 .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), 734 .volatile_reg = cs35l41_volatile_reg, 735 .readable_reg = cs35l41_readable_reg, 736 .precious_reg = cs35l41_precious_reg, 737 .cache_type = REGCACHE_RBTREE, 738 }; 739 EXPORT_SYMBOL_GPL(cs35l41_regmap_spi); 740 741 static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id) 742 { 743 int i; 744 745 for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) { 746 if (cs35l41_otp_map_map[i].id == otp_id) 747 return &cs35l41_otp_map_map[i]; 748 } 749 750 return NULL; 751 } 752 753 int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap) 754 { 755 static const struct reg_sequence unlock[] = { 756 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 757 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 758 }; 759 int ret; 760 761 ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock)); 762 if (ret) 763 dev_err(dev, "Failed to unlock test key: %d\n", ret); 764 765 return ret; 766 } 767 EXPORT_SYMBOL_GPL(cs35l41_test_key_unlock); 768 769 int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap) 770 { 771 static const struct reg_sequence unlock[] = { 772 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 773 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 774 }; 775 int ret; 776 777 ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock)); 778 if (ret) 779 dev_err(dev, "Failed to lock test key: %d\n", ret); 780 781 return ret; 782 } 783 EXPORT_SYMBOL_GPL(cs35l41_test_key_lock); 784 785 /* Must be called with the TEST_KEY unlocked */ 786 int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap) 787 { 788 const struct cs35l41_otp_map_element_t *otp_map_match; 789 const struct cs35l41_otp_packed_element_t *otp_map; 790 int bit_offset, word_offset, ret, i; 791 unsigned int bit_sum = 8; 792 u32 otp_val, otp_id_reg; 793 u32 *otp_mem; 794 795 otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), GFP_KERNEL); 796 if (!otp_mem) 797 return -ENOMEM; 798 799 ret = regmap_read(regmap, CS35L41_OTPID, &otp_id_reg); 800 if (ret) { 801 dev_err(dev, "Read OTP ID failed: %d\n", ret); 802 goto err_otp_unpack; 803 } 804 805 otp_map_match = cs35l41_find_otp_map(otp_id_reg); 806 807 if (!otp_map_match) { 808 dev_err(dev, "OTP Map matching ID %d not found\n", otp_id_reg); 809 ret = -EINVAL; 810 goto err_otp_unpack; 811 } 812 813 ret = regmap_bulk_read(regmap, CS35L41_OTP_MEM0, otp_mem, CS35L41_OTP_SIZE_WORDS); 814 if (ret) { 815 dev_err(dev, "Read OTP Mem failed: %d\n", ret); 816 goto err_otp_unpack; 817 } 818 819 otp_map = otp_map_match->map; 820 821 bit_offset = otp_map_match->bit_offset; 822 word_offset = otp_map_match->word_offset; 823 824 for (i = 0; i < otp_map_match->num_elements; i++) { 825 dev_dbg(dev, "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d\n", 826 bit_offset, word_offset, bit_sum % 32); 827 if (bit_offset + otp_map[i].size - 1 >= 32) { 828 otp_val = (otp_mem[word_offset] & 829 GENMASK(31, bit_offset)) >> bit_offset; 830 otp_val |= (otp_mem[++word_offset] & 831 GENMASK(bit_offset + otp_map[i].size - 33, 0)) << 832 (32 - bit_offset); 833 bit_offset += otp_map[i].size - 32; 834 } else { 835 otp_val = (otp_mem[word_offset] & 836 GENMASK(bit_offset + otp_map[i].size - 1, bit_offset) 837 ) >> bit_offset; 838 bit_offset += otp_map[i].size; 839 } 840 bit_sum += otp_map[i].size; 841 842 if (bit_offset == 32) { 843 bit_offset = 0; 844 word_offset++; 845 } 846 847 if (otp_map[i].reg != 0) { 848 ret = regmap_update_bits(regmap, otp_map[i].reg, 849 GENMASK(otp_map[i].shift + otp_map[i].size - 1, 850 otp_map[i].shift), 851 otp_val << otp_map[i].shift); 852 if (ret < 0) { 853 dev_err(dev, "Write OTP val failed: %d\n", ret); 854 goto err_otp_unpack; 855 } 856 } 857 } 858 859 ret = 0; 860 861 err_otp_unpack: 862 kfree(otp_mem); 863 864 return ret; 865 } 866 EXPORT_SYMBOL_GPL(cs35l41_otp_unpack); 867 868 /* Must be called with the TEST_KEY unlocked */ 869 int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid) 870 { 871 char *rev; 872 int ret; 873 874 switch (reg_revid) { 875 case CS35L41_REVID_A0: 876 ret = regmap_register_patch(reg, cs35l41_reva0_errata_patch, 877 ARRAY_SIZE(cs35l41_reva0_errata_patch)); 878 rev = "A0"; 879 break; 880 case CS35L41_REVID_B0: 881 ret = regmap_register_patch(reg, cs35l41_revb0_errata_patch, 882 ARRAY_SIZE(cs35l41_revb0_errata_patch)); 883 rev = "B0"; 884 break; 885 case CS35L41_REVID_B2: 886 ret = regmap_register_patch(reg, cs35l41_revb2_errata_patch, 887 ARRAY_SIZE(cs35l41_revb2_errata_patch)); 888 rev = "B2"; 889 break; 890 default: 891 ret = -EINVAL; 892 rev = "XX"; 893 break; 894 } 895 896 if (ret) 897 dev_err(dev, "Failed to apply %s errata patch: %d\n", rev, ret); 898 899 ret = regmap_write(reg, CS35L41_DSP1_CCM_CORE_CTRL, 0); 900 if (ret < 0) 901 dev_err(dev, "Write CCM_CORE_CTRL failed: %d\n", ret); 902 903 return ret; 904 } 905 EXPORT_SYMBOL_GPL(cs35l41_register_errata_patch); 906 907 int cs35l41_set_channels(struct device *dev, struct regmap *reg, 908 unsigned int tx_num, unsigned int *tx_slot, 909 unsigned int rx_num, unsigned int *rx_slot) 910 { 911 unsigned int val, mask; 912 int i; 913 914 if (tx_num > 4 || rx_num > 2) 915 return -EINVAL; 916 917 val = 0; 918 mask = 0; 919 for (i = 0; i < rx_num; i++) { 920 dev_dbg(dev, "rx slot %d position = %d\n", i, rx_slot[i]); 921 val |= rx_slot[i] << (i * 8); 922 mask |= 0x3F << (i * 8); 923 } 924 regmap_update_bits(reg, CS35L41_SP_FRAME_RX_SLOT, mask, val); 925 926 val = 0; 927 mask = 0; 928 for (i = 0; i < tx_num; i++) { 929 dev_dbg(dev, "tx slot %d position = %d\n", i, tx_slot[i]); 930 val |= tx_slot[i] << (i * 8); 931 mask |= 0x3F << (i * 8); 932 } 933 regmap_update_bits(reg, CS35L41_SP_FRAME_TX_SLOT, mask, val); 934 935 return 0; 936 } 937 EXPORT_SYMBOL_GPL(cs35l41_set_channels); 938 939 static const unsigned char cs35l41_bst_k1_table[4][5] = { 940 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 941 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 942 { 0x40, 0x32, 0x32, 0x4F, 0x57 }, 943 { 0x40, 0x32, 0x32, 0x4F, 0x57 } 944 }; 945 946 static const unsigned char cs35l41_bst_k2_table[4][5] = { 947 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 948 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 949 { 0x48, 0x49, 0x66, 0xA3, 0xEA }, 950 { 0x48, 0x49, 0x66, 0xA3, 0xEA } 951 }; 952 953 static const unsigned char cs35l41_bst_slope_table[4] = { 954 0x75, 0x6B, 0x3B, 0x28 955 }; 956 957 958 int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap, 959 int boost_ipk) 960 { 961 unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; 962 int ret; 963 964 switch (boost_ind) { 965 case 1000: /* 1.0 uH */ 966 bst_lbst_val = 0; 967 break; 968 case 1200: /* 1.2 uH */ 969 bst_lbst_val = 1; 970 break; 971 case 1500: /* 1.5 uH */ 972 bst_lbst_val = 2; 973 break; 974 case 2200: /* 2.2 uH */ 975 bst_lbst_val = 3; 976 break; 977 default: 978 dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind); 979 return -EINVAL; 980 } 981 982 switch (boost_cap) { 983 case 0 ... 19: 984 bst_cbst_range = 0; 985 break; 986 case 20 ... 50: 987 bst_cbst_range = 1; 988 break; 989 case 51 ... 100: 990 bst_cbst_range = 2; 991 break; 992 case 101 ... 200: 993 bst_cbst_range = 3; 994 break; 995 default: /* 201 uF and greater */ 996 bst_cbst_range = 4; 997 } 998 999 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF, 1000 CS35L41_BST_K1_MASK | CS35L41_BST_K2_MASK, 1001 cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range] 1002 << CS35L41_BST_K1_SHIFT | 1003 cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range] 1004 << CS35L41_BST_K2_SHIFT); 1005 if (ret) { 1006 dev_err(dev, "Failed to write boost coefficients: %d\n", ret); 1007 return ret; 1008 } 1009 1010 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, 1011 CS35L41_BST_SLOPE_MASK | CS35L41_BST_LBST_VAL_MASK, 1012 cs35l41_bst_slope_table[bst_lbst_val] 1013 << CS35L41_BST_SLOPE_SHIFT | 1014 bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT); 1015 if (ret) { 1016 dev_err(dev, "Failed to write boost slope/inductor value: %d\n", ret); 1017 return ret; 1018 } 1019 1020 if (boost_ipk < 1600 || boost_ipk > 4500) { 1021 dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk); 1022 return -EINVAL; 1023 } 1024 bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; 1025 1026 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, CS35L41_BST_IPK_MASK, 1027 bst_ipk_scaled << CS35L41_BST_IPK_SHIFT); 1028 if (ret) { 1029 dev_err(dev, "Failed to write boost inductor peak current: %d\n", ret); 1030 return ret; 1031 } 1032 1033 return 0; 1034 } 1035 EXPORT_SYMBOL_GPL(cs35l41_boost_config); 1036 1037 MODULE_DESCRIPTION("CS35L41 library"); 1038 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1039 MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>"); 1040 MODULE_LICENSE("GPL"); 1041