1 /* 2 * Intel 82860 Memory Controller kernel module 3 * (C) 2005 Red Hat (http://www.redhat.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * Written by Ben Woodard <woodard@redhat.com> 8 * shamelessly copied from and based upon the edac_i82875 driver 9 * by Thayne Harbaugh of Linux Networx. (http://lnxi.com) 10 */ 11 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/pci_ids.h> 16 #include <linux/edac.h> 17 #include "edac_module.h" 18 19 #define EDAC_MOD_STR "i82860_edac" 20 21 #define i82860_printk(level, fmt, arg...) \ 22 edac_printk(level, "i82860", fmt, ##arg) 23 24 #define i82860_mc_printk(mci, level, fmt, arg...) \ 25 edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg) 26 27 #ifndef PCI_DEVICE_ID_INTEL_82860_0 28 #define PCI_DEVICE_ID_INTEL_82860_0 0x2531 29 #endif /* PCI_DEVICE_ID_INTEL_82860_0 */ 30 31 #define I82860_MCHCFG 0x50 32 #define I82860_GBA 0x60 33 #define I82860_GBA_MASK 0x7FF 34 #define I82860_GBA_SHIFT 24 35 #define I82860_ERRSTS 0xC8 36 #define I82860_EAP 0xE4 37 #define I82860_DERRCTL_STS 0xE2 38 39 enum i82860_chips { 40 I82860 = 0, 41 }; 42 43 struct i82860_dev_info { 44 const char *ctl_name; 45 }; 46 47 struct i82860_error_info { 48 u16 errsts; 49 u32 eap; 50 u16 derrsyn; 51 u16 errsts2; 52 }; 53 54 static const struct i82860_dev_info i82860_devs[] = { 55 [I82860] = { 56 .ctl_name = "i82860"}, 57 }; 58 59 static struct pci_dev *mci_pdev; /* init dev: in case that AGP code 60 * has already registered driver 61 */ 62 static struct edac_pci_ctl_info *i82860_pci; 63 64 static void i82860_get_error_info(struct mem_ctl_info *mci, 65 struct i82860_error_info *info) 66 { 67 struct pci_dev *pdev; 68 69 pdev = to_pci_dev(mci->pdev); 70 71 /* 72 * This is a mess because there is no atomic way to read all the 73 * registers at once and the registers can transition from CE being 74 * overwritten by UE. 75 */ 76 pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts); 77 pci_read_config_dword(pdev, I82860_EAP, &info->eap); 78 pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn); 79 pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2); 80 81 pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003); 82 83 /* 84 * If the error is the same for both reads then the first set of reads 85 * is valid. If there is a change then there is a CE no info and the 86 * second set of reads is valid and should be UE info. 87 */ 88 if (!(info->errsts2 & 0x0003)) 89 return; 90 91 if ((info->errsts ^ info->errsts2) & 0x0003) { 92 pci_read_config_dword(pdev, I82860_EAP, &info->eap); 93 pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn); 94 } 95 } 96 97 static int i82860_process_error_info(struct mem_ctl_info *mci, 98 struct i82860_error_info *info, 99 int handle_errors) 100 { 101 struct dimm_info *dimm; 102 int row; 103 104 if (!(info->errsts2 & 0x0003)) 105 return 0; 106 107 if (!handle_errors) 108 return 1; 109 110 if ((info->errsts ^ info->errsts2) & 0x0003) { 111 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 112 -1, -1, -1, "UE overwrote CE", ""); 113 info->errsts = info->errsts2; 114 } 115 116 info->eap >>= PAGE_SHIFT; 117 row = edac_mc_find_csrow_by_page(mci, info->eap); 118 dimm = mci->csrows[row]->channels[0]->dimm; 119 120 if (info->errsts & 0x0002) 121 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 122 info->eap, 0, 0, 123 dimm->location[0], dimm->location[1], -1, 124 "i82860 UE", ""); 125 else 126 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 127 info->eap, 0, info->derrsyn, 128 dimm->location[0], dimm->location[1], -1, 129 "i82860 CE", ""); 130 131 return 1; 132 } 133 134 static void i82860_check(struct mem_ctl_info *mci) 135 { 136 struct i82860_error_info info; 137 138 i82860_get_error_info(mci, &info); 139 i82860_process_error_info(mci, &info, 1); 140 } 141 142 static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev) 143 { 144 unsigned long last_cumul_size; 145 u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */ 146 u16 value; 147 u32 cumul_size; 148 struct csrow_info *csrow; 149 struct dimm_info *dimm; 150 int index; 151 152 pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim); 153 mchcfg_ddim = mchcfg_ddim & 0x180; 154 last_cumul_size = 0; 155 156 /* The group row boundary (GRA) reg values are boundary address 157 * for each DRAM row with a granularity of 16MB. GRA regs are 158 * cumulative; therefore GRA15 will contain the total memory contained 159 * in all eight rows. 160 */ 161 for (index = 0; index < mci->nr_csrows; index++) { 162 csrow = mci->csrows[index]; 163 dimm = csrow->channels[0]->dimm; 164 165 pci_read_config_word(pdev, I82860_GBA + index * 2, &value); 166 cumul_size = (value & I82860_GBA_MASK) << 167 (I82860_GBA_SHIFT - PAGE_SHIFT); 168 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size); 169 170 if (cumul_size == last_cumul_size) 171 continue; /* not populated */ 172 173 csrow->first_page = last_cumul_size; 174 csrow->last_page = cumul_size - 1; 175 dimm->nr_pages = cumul_size - last_cumul_size; 176 last_cumul_size = cumul_size; 177 dimm->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */ 178 dimm->mtype = MEM_RMBS; 179 dimm->dtype = DEV_UNKNOWN; 180 dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE; 181 } 182 } 183 184 static int i82860_probe1(struct pci_dev *pdev, int dev_idx) 185 { 186 struct mem_ctl_info *mci; 187 struct edac_mc_layer layers[2]; 188 struct i82860_error_info discard; 189 190 /* 191 * RDRAM has channels but these don't map onto the csrow abstraction. 192 * According with the datasheet, there are 2 Rambus channels, supporting 193 * up to 16 direct RDRAM devices. 194 * The device groups from the GRA registers seem to map reasonably 195 * well onto the notion of a chip select row. 196 * There are 16 GRA registers and since the name is associated with 197 * the channel and the GRA registers map to physical devices so we are 198 * going to make 1 channel for group. 199 */ 200 layers[0].type = EDAC_MC_LAYER_CHANNEL; 201 layers[0].size = 2; 202 layers[0].is_virt_csrow = true; 203 layers[1].type = EDAC_MC_LAYER_SLOT; 204 layers[1].size = 8; 205 layers[1].is_virt_csrow = true; 206 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); 207 if (!mci) 208 return -ENOMEM; 209 210 edac_dbg(3, "init mci\n"); 211 mci->pdev = &pdev->dev; 212 mci->mtype_cap = MEM_FLAG_DDR; 213 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 214 /* I"m not sure about this but I think that all RDRAM is SECDED */ 215 mci->edac_cap = EDAC_FLAG_SECDED; 216 mci->mod_name = EDAC_MOD_STR; 217 mci->ctl_name = i82860_devs[dev_idx].ctl_name; 218 mci->dev_name = pci_name(pdev); 219 mci->edac_check = i82860_check; 220 mci->ctl_page_to_phys = NULL; 221 i82860_init_csrows(mci, pdev); 222 i82860_get_error_info(mci, &discard); /* clear counters */ 223 224 /* Here we assume that we will never see multiple instances of this 225 * type of memory controller. The ID is therefore hardcoded to 0. 226 */ 227 if (edac_mc_add_mc(mci)) { 228 edac_dbg(3, "failed edac_mc_add_mc()\n"); 229 goto fail; 230 } 231 232 /* allocating generic PCI control info */ 233 i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 234 if (!i82860_pci) { 235 printk(KERN_WARNING 236 "%s(): Unable to create PCI control\n", 237 __func__); 238 printk(KERN_WARNING 239 "%s(): PCI error report via EDAC not setup\n", 240 __func__); 241 } 242 243 /* get this far and it's successful */ 244 edac_dbg(3, "success\n"); 245 246 return 0; 247 248 fail: 249 edac_mc_free(mci); 250 return -ENODEV; 251 } 252 253 /* returns count (>= 0), or negative on error */ 254 static int i82860_init_one(struct pci_dev *pdev, 255 const struct pci_device_id *ent) 256 { 257 int rc; 258 259 edac_dbg(0, "\n"); 260 i82860_printk(KERN_INFO, "i82860 init one\n"); 261 262 if (pci_enable_device(pdev) < 0) 263 return -EIO; 264 265 rc = i82860_probe1(pdev, ent->driver_data); 266 267 if (rc == 0) 268 mci_pdev = pci_dev_get(pdev); 269 270 return rc; 271 } 272 273 static void i82860_remove_one(struct pci_dev *pdev) 274 { 275 struct mem_ctl_info *mci; 276 277 edac_dbg(0, "\n"); 278 279 if (i82860_pci) 280 edac_pci_release_generic_ctl(i82860_pci); 281 282 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 283 return; 284 285 edac_mc_free(mci); 286 } 287 288 static const struct pci_device_id i82860_pci_tbl[] = { 289 { 290 PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 291 I82860}, 292 { 293 0, 294 } /* 0 terminated list. */ 295 }; 296 297 MODULE_DEVICE_TABLE(pci, i82860_pci_tbl); 298 299 static struct pci_driver i82860_driver = { 300 .name = EDAC_MOD_STR, 301 .probe = i82860_init_one, 302 .remove = i82860_remove_one, 303 .id_table = i82860_pci_tbl, 304 }; 305 306 static int __init i82860_init(void) 307 { 308 int pci_rc; 309 310 edac_dbg(3, "\n"); 311 312 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 313 opstate_init(); 314 315 if ((pci_rc = pci_register_driver(&i82860_driver)) < 0) 316 goto fail0; 317 318 if (!mci_pdev) { 319 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 320 PCI_DEVICE_ID_INTEL_82860_0, NULL); 321 322 if (mci_pdev == NULL) { 323 edac_dbg(0, "860 pci_get_device fail\n"); 324 pci_rc = -ENODEV; 325 goto fail1; 326 } 327 328 pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl); 329 330 if (pci_rc < 0) { 331 edac_dbg(0, "860 init fail\n"); 332 pci_rc = -ENODEV; 333 goto fail1; 334 } 335 } 336 337 return 0; 338 339 fail1: 340 pci_unregister_driver(&i82860_driver); 341 342 fail0: 343 pci_dev_put(mci_pdev); 344 return pci_rc; 345 } 346 347 static void __exit i82860_exit(void) 348 { 349 edac_dbg(3, "\n"); 350 pci_unregister_driver(&i82860_driver); 351 pci_dev_put(mci_pdev); 352 } 353 354 module_init(i82860_init); 355 module_exit(i82860_exit); 356 357 MODULE_LICENSE("GPL"); 358 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) Ben Woodard <woodard@redhat.com>"); 359 MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers"); 360 361 module_param(edac_op_state, int, 0444); 362 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 363