1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 /* External CAN clock - to be overridden by boards that provide it */ 29 can_clk: can { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 a53_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0>; 43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 45 next-level-cache = <&L2_CA53>; 46 enable-method = "psci"; 47 }; 48 49 a53_1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <1>; 53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 55 next-level-cache = <&L2_CA53>; 56 enable-method = "psci"; 57 }; 58 59 a53_2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <2>; 63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 65 next-level-cache = <&L2_CA53>; 66 enable-method = "psci"; 67 }; 68 69 a53_3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <3>; 73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 }; 78 79 L2_CA53: cache-controller { 80 compatible = "cache"; 81 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 82 cache-unified; 83 cache-level = <2>; 84 }; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 /* External PCIe clock - can be overridden by the board */ 102 pcie_bus_clk: pcie_bus { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 pmu_a53 { 109 compatible = "arm,cortex-a53-pmu"; 110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 111 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 112 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 113 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0", "arm,psci-0.2"; 119 method = "smc"; 120 }; 121 122 /* External SCIF clock - to be overridden by boards that provide it */ 123 scif_clk: scif { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-frequency = <0>; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 interrupt-parent = <&gic>; 132 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 rwdt: watchdog@e6020000 { 138 compatible = "renesas,r8a77980-wdt", 139 "renesas,rcar-gen3-wdt"; 140 reg = <0 0xe6020000 0 0x0c>; 141 clocks = <&cpg CPG_MOD 402>; 142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 143 resets = <&cpg 402>; 144 status = "disabled"; 145 }; 146 147 gpio0: gpio@e6050000 { 148 compatible = "renesas,gpio-r8a77980", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6050000 0 0x50>; 151 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 0 22>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 912>; 158 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 159 resets = <&cpg 912>; 160 }; 161 162 gpio1: gpio@e6051000 { 163 compatible = "renesas,gpio-r8a77980", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6051000 0 0x50>; 166 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 32 28>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 911>; 173 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 174 resets = <&cpg 911>; 175 }; 176 177 gpio2: gpio@e6052000 { 178 compatible = "renesas,gpio-r8a77980", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6052000 0 0x50>; 181 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 64 30>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 910>; 188 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 189 resets = <&cpg 910>; 190 }; 191 192 gpio3: gpio@e6053000 { 193 compatible = "renesas,gpio-r8a77980", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6053000 0 0x50>; 196 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 96 17>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 909>; 203 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 204 resets = <&cpg 909>; 205 }; 206 207 gpio4: gpio@e6054000 { 208 compatible = "renesas,gpio-r8a77980", 209 "renesas,rcar-gen3-gpio"; 210 reg = <0 0xe6054000 0 0x50>; 211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 212 #gpio-cells = <2>; 213 gpio-controller; 214 gpio-ranges = <&pfc 0 128 25>; 215 #interrupt-cells = <2>; 216 interrupt-controller; 217 clocks = <&cpg CPG_MOD 908>; 218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 219 resets = <&cpg 908>; 220 }; 221 222 gpio5: gpio@e6055000 { 223 compatible = "renesas,gpio-r8a77980", 224 "renesas,rcar-gen3-gpio"; 225 reg = <0 0xe6055000 0 0x50>; 226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 227 #gpio-cells = <2>; 228 gpio-controller; 229 gpio-ranges = <&pfc 0 160 15>; 230 #interrupt-cells = <2>; 231 interrupt-controller; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 234 resets = <&cpg 907>; 235 }; 236 237 pfc: pinctrl@e6060000 { 238 compatible = "renesas,pfc-r8a77980"; 239 reg = <0 0xe6060000 0 0x50c>; 240 }; 241 242 cmt0: timer@e60f0000 { 243 compatible = "renesas,r8a77980-cmt0", 244 "renesas,rcar-gen3-cmt0"; 245 reg = <0 0xe60f0000 0 0x1004>; 246 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&cpg CPG_MOD 303>; 249 clock-names = "fck"; 250 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 251 resets = <&cpg 303>; 252 status = "disabled"; 253 }; 254 255 cmt1: timer@e6130000 { 256 compatible = "renesas,r8a77980-cmt1", 257 "renesas,rcar-gen3-cmt1"; 258 reg = <0 0xe6130000 0 0x1004>; 259 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 302>; 268 clock-names = "fck"; 269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 270 resets = <&cpg 302>; 271 status = "disabled"; 272 }; 273 274 cmt2: timer@e6140000 { 275 compatible = "renesas,r8a77980-cmt1", 276 "renesas,rcar-gen3-cmt1"; 277 reg = <0 0xe6140000 0 0x1004>; 278 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 301>; 287 clock-names = "fck"; 288 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 289 resets = <&cpg 301>; 290 status = "disabled"; 291 }; 292 293 cmt3: timer@e6148000 { 294 compatible = "renesas,r8a77980-cmt1", 295 "renesas,rcar-gen3-cmt1"; 296 reg = <0 0xe6148000 0 0x1004>; 297 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cpg CPG_MOD 300>; 306 clock-names = "fck"; 307 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 308 resets = <&cpg 300>; 309 status = "disabled"; 310 }; 311 312 cpg: clock-controller@e6150000 { 313 compatible = "renesas,r8a77980-cpg-mssr"; 314 reg = <0 0xe6150000 0 0x1000>; 315 clocks = <&extal_clk>, <&extalr_clk>; 316 clock-names = "extal", "extalr"; 317 #clock-cells = <2>; 318 #power-domain-cells = <0>; 319 #reset-cells = <1>; 320 }; 321 322 rst: reset-controller@e6160000 { 323 compatible = "renesas,r8a77980-rst"; 324 reg = <0 0xe6160000 0 0x200>; 325 }; 326 327 sysc: system-controller@e6180000 { 328 compatible = "renesas,r8a77980-sysc"; 329 reg = <0 0xe6180000 0 0x440>; 330 #power-domain-cells = <1>; 331 }; 332 333 tsc: thermal@e6198000 { 334 compatible = "renesas,r8a77980-thermal"; 335 reg = <0 0xe6198000 0 0x100>, 336 <0 0xe61a0000 0 0x100>; 337 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 522>; 341 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 342 resets = <&cpg 522>; 343 #thermal-sensor-cells = <1>; 344 }; 345 346 intc_ex: interrupt-controller@e61c0000 { 347 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 348 #interrupt-cells = <2>; 349 interrupt-controller; 350 reg = <0 0xe61c0000 0 0x200>; 351 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&cpg CPG_MOD 407>; 358 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 359 resets = <&cpg 407>; 360 }; 361 362 tmu0: timer@e61e0000 { 363 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 364 reg = <0 0xe61e0000 0 0x30>; 365 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&cpg CPG_MOD 125>; 369 clock-names = "fck"; 370 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 371 resets = <&cpg 125>; 372 status = "disabled"; 373 }; 374 375 tmu1: timer@e6fc0000 { 376 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 377 reg = <0 0xe6fc0000 0 0x30>; 378 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cpg CPG_MOD 124>; 382 clock-names = "fck"; 383 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 384 resets = <&cpg 124>; 385 status = "disabled"; 386 }; 387 388 tmu2: timer@e6fd0000 { 389 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 390 reg = <0 0xe6fd0000 0 0x30>; 391 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cpg CPG_MOD 123>; 395 clock-names = "fck"; 396 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 397 resets = <&cpg 123>; 398 status = "disabled"; 399 }; 400 401 tmu3: timer@e6fe0000 { 402 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 403 reg = <0 0xe6fe0000 0 0x30>; 404 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&cpg CPG_MOD 122>; 408 clock-names = "fck"; 409 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 410 resets = <&cpg 122>; 411 status = "disabled"; 412 }; 413 414 tmu4: timer@ffc00000 { 415 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 416 reg = <0 0xffc00000 0 0x30>; 417 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&cpg CPG_MOD 121>; 421 clock-names = "fck"; 422 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 423 resets = <&cpg 121>; 424 status = "disabled"; 425 }; 426 427 i2c0: i2c@e6500000 { 428 compatible = "renesas,i2c-r8a77980", 429 "renesas,rcar-gen3-i2c"; 430 reg = <0 0xe6500000 0 0x40>; 431 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cpg CPG_MOD 931>; 433 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 434 resets = <&cpg 931>; 435 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 436 <&dmac2 0x91>, <&dmac2 0x90>; 437 dma-names = "tx", "rx", "tx", "rx"; 438 i2c-scl-internal-delay-ns = <6>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 i2c1: i2c@e6508000 { 445 compatible = "renesas,i2c-r8a77980", 446 "renesas,rcar-gen3-i2c"; 447 reg = <0 0xe6508000 0 0x40>; 448 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cpg CPG_MOD 930>; 450 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 451 resets = <&cpg 930>; 452 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 453 <&dmac2 0x93>, <&dmac2 0x92>; 454 dma-names = "tx", "rx", "tx", "rx"; 455 i2c-scl-internal-delay-ns = <6>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 status = "disabled"; 459 }; 460 461 i2c2: i2c@e6510000 { 462 compatible = "renesas,i2c-r8a77980", 463 "renesas,rcar-gen3-i2c"; 464 reg = <0 0xe6510000 0 0x40>; 465 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cpg CPG_MOD 929>; 467 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 468 resets = <&cpg 929>; 469 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 470 <&dmac2 0x95>, <&dmac2 0x94>; 471 dma-names = "tx", "rx", "tx", "rx"; 472 i2c-scl-internal-delay-ns = <6>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 status = "disabled"; 476 }; 477 478 i2c3: i2c@e66d0000 { 479 compatible = "renesas,i2c-r8a77980", 480 "renesas,rcar-gen3-i2c"; 481 reg = <0 0xe66d0000 0 0x40>; 482 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&cpg CPG_MOD 928>; 484 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 485 resets = <&cpg 928>; 486 i2c-scl-internal-delay-ns = <6>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 status = "disabled"; 490 }; 491 492 i2c4: i2c@e66d8000 { 493 compatible = "renesas,i2c-r8a77980", 494 "renesas,rcar-gen3-i2c"; 495 reg = <0 0xe66d8000 0 0x40>; 496 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cpg CPG_MOD 927>; 498 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 499 resets = <&cpg 927>; 500 i2c-scl-internal-delay-ns = <6>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 status = "disabled"; 504 }; 505 506 i2c5: i2c@e66e0000 { 507 compatible = "renesas,i2c-r8a77980", 508 "renesas,rcar-gen3-i2c"; 509 reg = <0 0xe66e0000 0 0x40>; 510 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cpg CPG_MOD 919>; 512 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 513 resets = <&cpg 919>; 514 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 515 <&dmac2 0x9b>, <&dmac2 0x9a>; 516 dma-names = "tx", "rx", "tx", "rx"; 517 i2c-scl-internal-delay-ns = <6>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 status = "disabled"; 521 }; 522 523 hscif0: serial@e6540000 { 524 compatible = "renesas,hscif-r8a77980", 525 "renesas,rcar-gen3-hscif", 526 "renesas,hscif"; 527 reg = <0 0xe6540000 0 0x60>; 528 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cpg CPG_MOD 520>, 530 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 531 <&scif_clk>; 532 clock-names = "fck", "brg_int", "scif_clk"; 533 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 534 <&dmac2 0x31>, <&dmac2 0x30>; 535 dma-names = "tx", "rx", "tx", "rx"; 536 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 537 resets = <&cpg 520>; 538 status = "disabled"; 539 }; 540 541 hscif1: serial@e6550000 { 542 compatible = "renesas,hscif-r8a77980", 543 "renesas,rcar-gen3-hscif", 544 "renesas,hscif"; 545 reg = <0 0xe6550000 0 0x60>; 546 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&cpg CPG_MOD 519>, 548 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 549 <&scif_clk>; 550 clock-names = "fck", "brg_int", "scif_clk"; 551 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 552 <&dmac2 0x33>, <&dmac2 0x32>; 553 dma-names = "tx", "rx", "tx", "rx"; 554 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 555 resets = <&cpg 519>; 556 status = "disabled"; 557 }; 558 559 hscif2: serial@e6560000 { 560 compatible = "renesas,hscif-r8a77980", 561 "renesas,rcar-gen3-hscif", 562 "renesas,hscif"; 563 reg = <0 0xe6560000 0 0x60>; 564 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cpg CPG_MOD 518>, 566 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 567 <&scif_clk>; 568 clock-names = "fck", "brg_int", "scif_clk"; 569 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 570 <&dmac2 0x35>, <&dmac2 0x34>; 571 dma-names = "tx", "rx", "tx", "rx"; 572 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 573 resets = <&cpg 518>; 574 status = "disabled"; 575 }; 576 577 hscif3: serial@e66a0000 { 578 compatible = "renesas,hscif-r8a77980", 579 "renesas,rcar-gen3-hscif", 580 "renesas,hscif"; 581 reg = <0 0xe66a0000 0 0x60>; 582 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cpg CPG_MOD 517>, 584 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 585 <&scif_clk>; 586 clock-names = "fck", "brg_int", "scif_clk"; 587 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 588 <&dmac2 0x37>, <&dmac2 0x36>; 589 dma-names = "tx", "rx", "tx", "rx"; 590 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 591 resets = <&cpg 517>; 592 status = "disabled"; 593 }; 594 595 pcie_phy: pcie-phy@e65d0000 { 596 compatible = "renesas,r8a77980-pcie-phy"; 597 reg = <0 0xe65d0000 0 0x8000>; 598 #phy-cells = <0>; 599 clocks = <&cpg CPG_MOD 319>; 600 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 601 resets = <&cpg 319>; 602 status = "disabled"; 603 }; 604 605 canfd: can@e66c0000 { 606 compatible = "renesas,r8a77980-canfd", 607 "renesas,rcar-gen3-canfd"; 608 reg = <0 0xe66c0000 0 0x8000>; 609 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cpg CPG_MOD 914>, 612 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 613 <&can_clk>; 614 clock-names = "fck", "canfd", "can_clk"; 615 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 616 assigned-clock-rates = <40000000>; 617 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 618 resets = <&cpg 914>; 619 status = "disabled"; 620 621 channel0 { 622 status = "disabled"; 623 }; 624 625 channel1 { 626 status = "disabled"; 627 }; 628 }; 629 630 avb: ethernet@e6800000 { 631 compatible = "renesas,etheravb-r8a77980", 632 "renesas,etheravb-rcar-gen3"; 633 reg = <0 0xe6800000 0 0x800>; 634 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 659 interrupt-names = "ch0", "ch1", "ch2", "ch3", 660 "ch4", "ch5", "ch6", "ch7", 661 "ch8", "ch9", "ch10", "ch11", 662 "ch12", "ch13", "ch14", "ch15", 663 "ch16", "ch17", "ch18", "ch19", 664 "ch20", "ch21", "ch22", "ch23", 665 "ch24"; 666 clocks = <&cpg CPG_MOD 812>; 667 clock-names = "fck"; 668 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 669 resets = <&cpg 812>; 670 phy-mode = "rgmii"; 671 rx-internal-delay-ps = <0>; 672 tx-internal-delay-ps = <2000>; 673 iommus = <&ipmmu_ds1 33>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 status = "disabled"; 677 }; 678 679 pwm0: pwm@e6e30000 { 680 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 681 reg = <0 0xe6e30000 0 0x10>; 682 #pwm-cells = <2>; 683 clocks = <&cpg CPG_MOD 523>; 684 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 685 resets = <&cpg 523>; 686 status = "disabled"; 687 }; 688 689 pwm1: pwm@e6e31000 { 690 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 691 reg = <0 0xe6e31000 0 0x10>; 692 #pwm-cells = <2>; 693 clocks = <&cpg CPG_MOD 523>; 694 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 695 resets = <&cpg 523>; 696 status = "disabled"; 697 }; 698 699 pwm2: pwm@e6e32000 { 700 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 701 reg = <0 0xe6e32000 0 0x10>; 702 #pwm-cells = <2>; 703 clocks = <&cpg CPG_MOD 523>; 704 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 705 resets = <&cpg 523>; 706 status = "disabled"; 707 }; 708 709 pwm3: pwm@e6e33000 { 710 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 711 reg = <0 0xe6e33000 0 0x10>; 712 #pwm-cells = <2>; 713 clocks = <&cpg CPG_MOD 523>; 714 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 715 resets = <&cpg 523>; 716 status = "disabled"; 717 }; 718 719 pwm4: pwm@e6e34000 { 720 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 721 reg = <0 0xe6e34000 0 0x10>; 722 #pwm-cells = <2>; 723 clocks = <&cpg CPG_MOD 523>; 724 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 725 resets = <&cpg 523>; 726 status = "disabled"; 727 }; 728 729 scif0: serial@e6e60000 { 730 compatible = "renesas,scif-r8a77980", 731 "renesas,rcar-gen3-scif", 732 "renesas,scif"; 733 reg = <0 0xe6e60000 0 0x40>; 734 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&cpg CPG_MOD 207>, 736 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 737 <&scif_clk>; 738 clock-names = "fck", "brg_int", "scif_clk"; 739 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 740 <&dmac2 0x51>, <&dmac2 0x50>; 741 dma-names = "tx", "rx", "tx", "rx"; 742 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 743 resets = <&cpg 207>; 744 status = "disabled"; 745 }; 746 747 scif1: serial@e6e68000 { 748 compatible = "renesas,scif-r8a77980", 749 "renesas,rcar-gen3-scif", 750 "renesas,scif"; 751 reg = <0 0xe6e68000 0 0x40>; 752 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&cpg CPG_MOD 206>, 754 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 755 <&scif_clk>; 756 clock-names = "fck", "brg_int", "scif_clk"; 757 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 758 <&dmac2 0x53>, <&dmac2 0x52>; 759 dma-names = "tx", "rx", "tx", "rx"; 760 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 761 resets = <&cpg 206>; 762 status = "disabled"; 763 }; 764 765 scif3: serial@e6c50000 { 766 compatible = "renesas,scif-r8a77980", 767 "renesas,rcar-gen3-scif", 768 "renesas,scif"; 769 reg = <0 0xe6c50000 0 0x40>; 770 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&cpg CPG_MOD 204>, 772 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 773 <&scif_clk>; 774 clock-names = "fck", "brg_int", "scif_clk"; 775 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 776 <&dmac2 0x57>, <&dmac2 0x56>; 777 dma-names = "tx", "rx", "tx", "rx"; 778 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 779 resets = <&cpg 204>; 780 status = "disabled"; 781 }; 782 783 scif4: serial@e6c40000 { 784 compatible = "renesas,scif-r8a77980", 785 "renesas,rcar-gen3-scif", 786 "renesas,scif"; 787 reg = <0 0xe6c40000 0 0x40>; 788 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&cpg CPG_MOD 203>, 790 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 791 <&scif_clk>; 792 clock-names = "fck", "brg_int", "scif_clk"; 793 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 794 <&dmac2 0x59>, <&dmac2 0x58>; 795 dma-names = "tx", "rx", "tx", "rx"; 796 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 797 resets = <&cpg 203>; 798 status = "disabled"; 799 }; 800 801 tpu: pwm@e6e80000 { 802 compatible = "renesas,tpu-r8a77980", "renesas,tpu"; 803 reg = <0 0xe6e80000 0 0x148>; 804 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&cpg CPG_MOD 304>; 806 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 807 resets = <&cpg 304>; 808 #pwm-cells = <3>; 809 status = "disabled"; 810 }; 811 812 msiof0: spi@e6e90000 { 813 compatible = "renesas,msiof-r8a77980", 814 "renesas,rcar-gen3-msiof"; 815 reg = <0 0xe6e90000 0 0x64>; 816 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&cpg CPG_MOD 211>; 818 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 819 resets = <&cpg 211>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 msiof1: spi@e6ea0000 { 826 compatible = "renesas,msiof-r8a77980", 827 "renesas,rcar-gen3-msiof"; 828 reg = <0 0xe6ea0000 0 0x0064>; 829 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&cpg CPG_MOD 210>; 831 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 832 resets = <&cpg 210>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 msiof2: spi@e6c00000 { 839 compatible = "renesas,msiof-r8a77980", 840 "renesas,rcar-gen3-msiof"; 841 reg = <0 0xe6c00000 0 0x0064>; 842 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&cpg CPG_MOD 209>; 844 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 845 resets = <&cpg 209>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 status = "disabled"; 849 }; 850 851 msiof3: spi@e6c10000 { 852 compatible = "renesas,msiof-r8a77980", 853 "renesas,rcar-gen3-msiof"; 854 reg = <0 0xe6c10000 0 0x0064>; 855 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&cpg CPG_MOD 208>; 857 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 858 resets = <&cpg 208>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 status = "disabled"; 862 }; 863 864 vin0: video@e6ef0000 { 865 compatible = "renesas,vin-r8a77980"; 866 reg = <0 0xe6ef0000 0 0x1000>; 867 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cpg CPG_MOD 811>; 869 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 870 resets = <&cpg 811>; 871 renesas,id = <0>; 872 status = "disabled"; 873 874 ports { 875 #address-cells = <1>; 876 #size-cells = <0>; 877 878 port@1 { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 reg = <1>; 883 884 vin0csi40: endpoint@2 { 885 reg = <2>; 886 remote-endpoint = <&csi40vin0>; 887 }; 888 }; 889 }; 890 }; 891 892 vin1: video@e6ef1000 { 893 compatible = "renesas,vin-r8a77980"; 894 reg = <0 0xe6ef1000 0 0x1000>; 895 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&cpg CPG_MOD 810>; 897 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 898 status = "disabled"; 899 renesas,id = <1>; 900 resets = <&cpg 810>; 901 902 ports { 903 #address-cells = <1>; 904 #size-cells = <0>; 905 906 port@1 { 907 #address-cells = <1>; 908 #size-cells = <0>; 909 910 reg = <1>; 911 912 vin1csi40: endpoint@2 { 913 reg = <2>; 914 remote-endpoint = <&csi40vin1>; 915 }; 916 }; 917 }; 918 }; 919 920 vin2: video@e6ef2000 { 921 compatible = "renesas,vin-r8a77980"; 922 reg = <0 0xe6ef2000 0 0x1000>; 923 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&cpg CPG_MOD 809>; 925 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 926 resets = <&cpg 809>; 927 renesas,id = <2>; 928 status = "disabled"; 929 930 ports { 931 #address-cells = <1>; 932 #size-cells = <0>; 933 934 port@1 { 935 #address-cells = <1>; 936 #size-cells = <0>; 937 938 reg = <1>; 939 940 vin2csi40: endpoint@2 { 941 reg = <2>; 942 remote-endpoint = <&csi40vin2>; 943 }; 944 }; 945 }; 946 }; 947 948 vin3: video@e6ef3000 { 949 compatible = "renesas,vin-r8a77980"; 950 reg = <0 0xe6ef3000 0 0x1000>; 951 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&cpg CPG_MOD 808>; 953 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 954 resets = <&cpg 808>; 955 renesas,id = <3>; 956 status = "disabled"; 957 958 ports { 959 #address-cells = <1>; 960 #size-cells = <0>; 961 962 port@1 { 963 #address-cells = <1>; 964 #size-cells = <0>; 965 966 reg = <1>; 967 968 vin3csi40: endpoint@2 { 969 reg = <2>; 970 remote-endpoint = <&csi40vin3>; 971 }; 972 }; 973 }; 974 }; 975 976 vin4: video@e6ef4000 { 977 compatible = "renesas,vin-r8a77980"; 978 reg = <0 0xe6ef4000 0 0x1000>; 979 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&cpg CPG_MOD 807>; 981 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 982 resets = <&cpg 807>; 983 renesas,id = <4>; 984 status = "disabled"; 985 986 ports { 987 #address-cells = <1>; 988 #size-cells = <0>; 989 990 port@1 { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 994 reg = <1>; 995 996 vin4csi41: endpoint@3 { 997 reg = <3>; 998 remote-endpoint = <&csi41vin4>; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 vin5: video@e6ef5000 { 1005 compatible = "renesas,vin-r8a77980"; 1006 reg = <0 0xe6ef5000 0 0x1000>; 1007 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&cpg CPG_MOD 806>; 1009 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1010 resets = <&cpg 806>; 1011 renesas,id = <5>; 1012 status = "disabled"; 1013 1014 ports { 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 1018 port@1 { 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 1022 reg = <1>; 1023 1024 vin5csi41: endpoint@3 { 1025 reg = <3>; 1026 remote-endpoint = <&csi41vin5>; 1027 }; 1028 }; 1029 }; 1030 }; 1031 1032 vin6: video@e6ef6000 { 1033 compatible = "renesas,vin-r8a77980"; 1034 reg = <0 0xe6ef6000 0 0x1000>; 1035 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&cpg CPG_MOD 805>; 1037 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1038 resets = <&cpg 805>; 1039 renesas,id = <6>; 1040 status = "disabled"; 1041 1042 ports { 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 1046 port@1 { 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 1050 reg = <1>; 1051 1052 vin6csi41: endpoint@3 { 1053 reg = <3>; 1054 remote-endpoint = <&csi41vin6>; 1055 }; 1056 }; 1057 }; 1058 }; 1059 1060 vin7: video@e6ef7000 { 1061 compatible = "renesas,vin-r8a77980"; 1062 reg = <0 0xe6ef7000 0 0x1000>; 1063 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&cpg CPG_MOD 804>; 1065 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1066 resets = <&cpg 804>; 1067 renesas,id = <7>; 1068 status = "disabled"; 1069 1070 ports { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 1074 port@1 { 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 1078 reg = <1>; 1079 1080 vin7csi41: endpoint@3 { 1081 reg = <3>; 1082 remote-endpoint = <&csi41vin7>; 1083 }; 1084 }; 1085 }; 1086 }; 1087 1088 vin8: video@e6ef8000 { 1089 compatible = "renesas,vin-r8a77980"; 1090 reg = <0 0xe6ef8000 0 0x1000>; 1091 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&cpg CPG_MOD 628>; 1093 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1094 resets = <&cpg 628>; 1095 renesas,id = <8>; 1096 status = "disabled"; 1097 }; 1098 1099 vin9: video@e6ef9000 { 1100 compatible = "renesas,vin-r8a77980"; 1101 reg = <0 0xe6ef9000 0 0x1000>; 1102 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&cpg CPG_MOD 627>; 1104 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1105 resets = <&cpg 627>; 1106 renesas,id = <9>; 1107 status = "disabled"; 1108 }; 1109 1110 vin10: video@e6efa000 { 1111 compatible = "renesas,vin-r8a77980"; 1112 reg = <0 0xe6efa000 0 0x1000>; 1113 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&cpg CPG_MOD 625>; 1115 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1116 resets = <&cpg 625>; 1117 renesas,id = <10>; 1118 status = "disabled"; 1119 }; 1120 1121 vin11: video@e6efb000 { 1122 compatible = "renesas,vin-r8a77980"; 1123 reg = <0 0xe6efb000 0 0x1000>; 1124 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&cpg CPG_MOD 618>; 1126 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1127 resets = <&cpg 618>; 1128 renesas,id = <11>; 1129 status = "disabled"; 1130 }; 1131 1132 vin12: video@e6efc000 { 1133 compatible = "renesas,vin-r8a77980"; 1134 reg = <0 0xe6efc000 0 0x1000>; 1135 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&cpg CPG_MOD 612>; 1137 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1138 resets = <&cpg 612>; 1139 renesas,id = <12>; 1140 status = "disabled"; 1141 }; 1142 1143 vin13: video@e6efd000 { 1144 compatible = "renesas,vin-r8a77980"; 1145 reg = <0 0xe6efd000 0 0x1000>; 1146 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&cpg CPG_MOD 608>; 1148 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1149 resets = <&cpg 608>; 1150 renesas,id = <13>; 1151 status = "disabled"; 1152 }; 1153 1154 vin14: video@e6efe000 { 1155 compatible = "renesas,vin-r8a77980"; 1156 reg = <0 0xe6efe000 0 0x1000>; 1157 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&cpg CPG_MOD 605>; 1159 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1160 resets = <&cpg 605>; 1161 renesas,id = <14>; 1162 status = "disabled"; 1163 }; 1164 1165 vin15: video@e6eff000 { 1166 compatible = "renesas,vin-r8a77980"; 1167 reg = <0 0xe6eff000 0 0x1000>; 1168 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1169 clocks = <&cpg CPG_MOD 604>; 1170 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1171 resets = <&cpg 604>; 1172 renesas,id = <15>; 1173 status = "disabled"; 1174 }; 1175 1176 dmac1: dma-controller@e7300000 { 1177 compatible = "renesas,dmac-r8a77980", 1178 "renesas,rcar-dmac"; 1179 reg = <0 0xe7300000 0 0x10000>; 1180 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1197 interrupt-names = "error", 1198 "ch0", "ch1", "ch2", "ch3", 1199 "ch4", "ch5", "ch6", "ch7", 1200 "ch8", "ch9", "ch10", "ch11", 1201 "ch12", "ch13", "ch14", "ch15"; 1202 clocks = <&cpg CPG_MOD 218>; 1203 clock-names = "fck"; 1204 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1205 resets = <&cpg 218>; 1206 #dma-cells = <1>; 1207 dma-channels = <16>; 1208 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1209 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1210 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1211 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1212 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1213 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1214 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1215 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1216 }; 1217 1218 dmac2: dma-controller@e7310000 { 1219 compatible = "renesas,dmac-r8a77980", 1220 "renesas,rcar-dmac"; 1221 reg = <0 0xe7310000 0 0x10000>; 1222 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1239 interrupt-names = "error", 1240 "ch0", "ch1", "ch2", "ch3", 1241 "ch4", "ch5", "ch6", "ch7", 1242 "ch8", "ch9", "ch10", "ch11", 1243 "ch12", "ch13", "ch14", "ch15"; 1244 clocks = <&cpg CPG_MOD 217>; 1245 clock-names = "fck"; 1246 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1247 resets = <&cpg 217>; 1248 #dma-cells = <1>; 1249 dma-channels = <16>; 1250 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1251 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1252 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1253 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1254 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1255 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1256 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1257 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1258 }; 1259 1260 gether: ethernet@e7400000 { 1261 compatible = "renesas,gether-r8a77980"; 1262 reg = <0 0xe7400000 0 0x1000>; 1263 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&cpg CPG_MOD 813>; 1265 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1266 resets = <&cpg 813>; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 status = "disabled"; 1270 }; 1271 1272 ipmmu_ds1: iommu@e7740000 { 1273 compatible = "renesas,ipmmu-r8a77980"; 1274 reg = <0 0xe7740000 0 0x1000>; 1275 renesas,ipmmu-main = <&ipmmu_mm 0>; 1276 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1277 #iommu-cells = <1>; 1278 }; 1279 1280 ipmmu_ir: iommu@ff8b0000 { 1281 compatible = "renesas,ipmmu-r8a77980"; 1282 reg = <0 0xff8b0000 0 0x1000>; 1283 renesas,ipmmu-main = <&ipmmu_mm 3>; 1284 power-domains = <&sysc R8A77980_PD_A3IR>; 1285 #iommu-cells = <1>; 1286 }; 1287 1288 ipmmu_mm: iommu@e67b0000 { 1289 compatible = "renesas,ipmmu-r8a77980"; 1290 reg = <0 0xe67b0000 0 0x1000>; 1291 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1294 #iommu-cells = <1>; 1295 }; 1296 1297 ipmmu_rt: iommu@ffc80000 { 1298 compatible = "renesas,ipmmu-r8a77980"; 1299 reg = <0 0xffc80000 0 0x1000>; 1300 renesas,ipmmu-main = <&ipmmu_mm 10>; 1301 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1302 #iommu-cells = <1>; 1303 }; 1304 1305 ipmmu_vc0: iommu@fe990000 { 1306 compatible = "renesas,ipmmu-r8a77980"; 1307 reg = <0 0xfe990000 0 0x1000>; 1308 renesas,ipmmu-main = <&ipmmu_mm 12>; 1309 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1310 #iommu-cells = <1>; 1311 }; 1312 1313 ipmmu_vi0: iommu@febd0000 { 1314 compatible = "renesas,ipmmu-r8a77980"; 1315 reg = <0 0xfebd0000 0 0x1000>; 1316 renesas,ipmmu-main = <&ipmmu_mm 14>; 1317 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1318 #iommu-cells = <1>; 1319 }; 1320 1321 ipmmu_vip0: iommu@e7b00000 { 1322 compatible = "renesas,ipmmu-r8a77980"; 1323 reg = <0 0xe7b00000 0 0x1000>; 1324 renesas,ipmmu-main = <&ipmmu_mm 4>; 1325 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1326 #iommu-cells = <1>; 1327 }; 1328 1329 ipmmu_vip1: iommu@e7960000 { 1330 compatible = "renesas,ipmmu-r8a77980"; 1331 reg = <0 0xe7960000 0 0x1000>; 1332 renesas,ipmmu-main = <&ipmmu_mm 11>; 1333 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1334 #iommu-cells = <1>; 1335 }; 1336 1337 mmc0: mmc@ee140000 { 1338 compatible = "renesas,sdhi-r8a77980", 1339 "renesas,rcar-gen3-sdhi"; 1340 reg = <0 0xee140000 0 0x2000>; 1341 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>; 1343 clock-names = "core", "clkh"; 1344 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1345 resets = <&cpg 314>; 1346 max-frequency = <200000000>; 1347 iommus = <&ipmmu_ds1 32>; 1348 status = "disabled"; 1349 }; 1350 1351 rpc: spi@ee200000 { 1352 compatible = "renesas,r8a77980-rpc-if", 1353 "renesas,rcar-gen3-rpc-if"; 1354 reg = <0 0xee200000 0 0x200>, 1355 <0 0x08000000 0 0x4000000>, 1356 <0 0xee208000 0 0x100>; 1357 reg-names = "regs", "dirmap", "wbuf"; 1358 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&cpg CPG_MOD 917>; 1360 clock-names = "rpc"; 1361 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1362 resets = <&cpg 917>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 status = "disabled"; 1366 }; 1367 1368 gic: interrupt-controller@f1010000 { 1369 compatible = "arm,gic-400"; 1370 #interrupt-cells = <3>; 1371 #address-cells = <0>; 1372 interrupt-controller; 1373 reg = <0x0 0xf1010000 0 0x1000>, 1374 <0x0 0xf1020000 0 0x20000>, 1375 <0x0 0xf1040000 0 0x20000>, 1376 <0x0 0xf1060000 0 0x20000>; 1377 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 1378 IRQ_TYPE_LEVEL_HIGH)>; 1379 clocks = <&cpg CPG_MOD 408>; 1380 clock-names = "clk"; 1381 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1382 resets = <&cpg 408>; 1383 }; 1384 1385 pciec: pcie@fe000000 { 1386 compatible = "renesas,pcie-r8a77980", 1387 "renesas,pcie-rcar-gen3"; 1388 reg = <0 0xfe000000 0 0x80000>; 1389 #address-cells = <3>; 1390 #size-cells = <2>; 1391 bus-range = <0x00 0xff>; 1392 device_type = "pci"; 1393 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>, 1394 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, 1395 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, 1396 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; 1397 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1398 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1401 #interrupt-cells = <1>; 1402 interrupt-map-mask = <0 0 0 0>; 1403 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1405 clock-names = "pcie", "pcie_bus"; 1406 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1407 resets = <&cpg 319>; 1408 phys = <&pcie_phy>; 1409 phy-names = "pcie"; 1410 status = "disabled"; 1411 }; 1412 1413 vspd0: vsp@fea20000 { 1414 compatible = "renesas,vsp2"; 1415 reg = <0 0xfea20000 0 0x5000>; 1416 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1417 clocks = <&cpg CPG_MOD 623>; 1418 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1419 resets = <&cpg 623>; 1420 renesas,fcp = <&fcpvd0>; 1421 }; 1422 1423 fcpvd0: fcp@fea27000 { 1424 compatible = "renesas,fcpv"; 1425 reg = <0 0xfea27000 0 0x200>; 1426 clocks = <&cpg CPG_MOD 603>; 1427 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1428 resets = <&cpg 603>; 1429 }; 1430 1431 csi40: csi2@feaa0000 { 1432 compatible = "renesas,r8a77980-csi2"; 1433 reg = <0 0xfeaa0000 0 0x10000>; 1434 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1435 clocks = <&cpg CPG_MOD 716>; 1436 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1437 resets = <&cpg 716>; 1438 status = "disabled"; 1439 1440 ports { 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 1444 port@0 { 1445 reg = <0>; 1446 }; 1447 1448 port@1 { 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 1452 reg = <1>; 1453 1454 csi40vin0: endpoint@0 { 1455 reg = <0>; 1456 remote-endpoint = <&vin0csi40>; 1457 }; 1458 csi40vin1: endpoint@1 { 1459 reg = <1>; 1460 remote-endpoint = <&vin1csi40>; 1461 }; 1462 csi40vin2: endpoint@2 { 1463 reg = <2>; 1464 remote-endpoint = <&vin2csi40>; 1465 }; 1466 csi40vin3: endpoint@3 { 1467 reg = <3>; 1468 remote-endpoint = <&vin3csi40>; 1469 }; 1470 }; 1471 }; 1472 }; 1473 1474 csi41: csi2@feab0000 { 1475 compatible = "renesas,r8a77980-csi2"; 1476 reg = <0 0xfeab0000 0 0x10000>; 1477 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&cpg CPG_MOD 715>; 1479 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1480 resets = <&cpg 715>; 1481 status = "disabled"; 1482 1483 ports { 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 1487 port@0 { 1488 reg = <0>; 1489 }; 1490 1491 port@1 { 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 1495 reg = <1>; 1496 1497 csi41vin4: endpoint@0 { 1498 reg = <0>; 1499 remote-endpoint = <&vin4csi41>; 1500 }; 1501 csi41vin5: endpoint@1 { 1502 reg = <1>; 1503 remote-endpoint = <&vin5csi41>; 1504 }; 1505 csi41vin6: endpoint@2 { 1506 reg = <2>; 1507 remote-endpoint = <&vin6csi41>; 1508 }; 1509 csi41vin7: endpoint@3 { 1510 reg = <3>; 1511 remote-endpoint = <&vin7csi41>; 1512 }; 1513 }; 1514 }; 1515 }; 1516 1517 du: display@feb00000 { 1518 compatible = "renesas,du-r8a77980"; 1519 reg = <0 0xfeb00000 0 0x80000>; 1520 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&cpg CPG_MOD 724>; 1522 clock-names = "du.0"; 1523 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1524 resets = <&cpg 724>; 1525 reset-names = "du.0"; 1526 renesas,vsps = <&vspd0 0>; 1527 1528 status = "disabled"; 1529 1530 ports { 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 1534 port@0 { 1535 reg = <0>; 1536 du_out_rgb: endpoint { 1537 }; 1538 }; 1539 1540 port@1 { 1541 reg = <1>; 1542 du_out_lvds0: endpoint { 1543 remote-endpoint = <&lvds0_in>; 1544 }; 1545 }; 1546 }; 1547 }; 1548 1549 lvds0: lvds-encoder@feb90000 { 1550 compatible = "renesas,r8a77980-lvds"; 1551 reg = <0 0xfeb90000 0 0x14>; 1552 clocks = <&cpg CPG_MOD 727>; 1553 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1554 resets = <&cpg 727>; 1555 status = "disabled"; 1556 1557 ports { 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 1561 port@0 { 1562 reg = <0>; 1563 lvds0_in: endpoint { 1564 remote-endpoint = 1565 <&du_out_lvds0>; 1566 }; 1567 }; 1568 1569 port@1 { 1570 reg = <1>; 1571 lvds0_out: endpoint { 1572 }; 1573 }; 1574 }; 1575 }; 1576 1577 prr: chipid@fff00044 { 1578 compatible = "renesas,prr"; 1579 reg = <0 0xfff00044 0 4>; 1580 }; 1581 }; 1582 1583 thermal-zones { 1584 sensor1_thermal: sensor1-thermal { 1585 polling-delay-passive = <250>; 1586 polling-delay = <1000>; 1587 thermal-sensors = <&tsc 0>; 1588 1589 trips { 1590 sensor1-passive { 1591 temperature = <95000>; 1592 hysteresis = <1000>; 1593 type = "passive"; 1594 }; 1595 sensor1-critical { 1596 temperature = <120000>; 1597 hysteresis = <1000>; 1598 type = "critical"; 1599 }; 1600 }; 1601 }; 1602 1603 sensor2_thermal: sensor2-thermal { 1604 polling-delay-passive = <250>; 1605 polling-delay = <1000>; 1606 thermal-sensors = <&tsc 1>; 1607 1608 trips { 1609 sensor2-passive { 1610 temperature = <95000>; 1611 hysteresis = <1000>; 1612 type = "passive"; 1613 }; 1614 sensor2-critical { 1615 temperature = <120000>; 1616 hysteresis = <1000>; 1617 type = "critical"; 1618 }; 1619 }; 1620 }; 1621 }; 1622 1623 timer { 1624 compatible = "arm,armv8-timer"; 1625 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 1626 IRQ_TYPE_LEVEL_LOW)>, 1627 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 1628 IRQ_TYPE_LEVEL_LOW)>, 1629 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 1630 IRQ_TYPE_LEVEL_LOW)>, 1631 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 1632 IRQ_TYPE_LEVEL_LOW)>; 1633 }; 1634}; 1635