1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/reset/qcom,gcc-msm8960.h>
7#include <dt-bindings/clock/qcom,lcc-msm8960.h>
8#include <dt-bindings/mfd/qcom-rpm.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14	model = "Qualcomm MSM8960";
15	compatible = "qcom,msm8960";
16	interrupt-parent = <&intc>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21		interrupts = <GIC_PPI 14 0x304>;
22
23		cpu@0 {
24			compatible = "qcom,krait";
25			enable-method = "qcom,kpss-acc-v1";
26			device_type = "cpu";
27			reg = <0>;
28			next-level-cache = <&L2>;
29			qcom,acc = <&acc0>;
30			qcom,saw = <&saw0>;
31		};
32
33		cpu@1 {
34			compatible = "qcom,krait";
35			enable-method = "qcom,kpss-acc-v1";
36			device_type = "cpu";
37			reg = <1>;
38			next-level-cache = <&L2>;
39			qcom,acc = <&acc1>;
40			qcom,saw = <&saw1>;
41		};
42
43		L2: l2-cache {
44			compatible = "cache";
45			cache-level = <2>;
46		};
47	};
48
49	memory {
50		device_type = "memory";
51		reg = <0x0 0x0>;
52	};
53
54	cpu-pmu {
55		compatible = "qcom,krait-pmu";
56		interrupts = <GIC_PPI 10 0x304>;
57		qcom,no-pc-write;
58	};
59
60	clocks {
61		cxo_board: cxo_board {
62			compatible = "fixed-clock";
63			#clock-cells = <0>;
64			clock-frequency = <19200000>;
65			clock-output-names = "cxo_board";
66		};
67
68		pxo_board: pxo_board {
69			compatible = "fixed-clock";
70			#clock-cells = <0>;
71			clock-frequency = <27000000>;
72			clock-output-names = "pxo_board";
73		};
74
75		sleep_clk: sleep_clk {
76			compatible = "fixed-clock";
77			#clock-cells = <0>;
78			clock-frequency = <32768>;
79			clock-output-names = "sleep_clk";
80		};
81	};
82
83	/* Temporary fixed regulator */
84	vsdcc_fixed: vsdcc-regulator {
85		compatible = "regulator-fixed";
86		regulator-name = "SDCC Power";
87		regulator-min-microvolt = <2700000>;
88		regulator-max-microvolt = <2700000>;
89		regulator-always-on;
90	};
91
92	soc: soc {
93		#address-cells = <1>;
94		#size-cells = <1>;
95		ranges;
96		compatible = "simple-bus";
97
98		intc: interrupt-controller@2000000 {
99			compatible = "qcom,msm-qgic2";
100			interrupt-controller;
101			#interrupt-cells = <3>;
102			reg = <0x02000000 0x1000>,
103			      <0x02002000 0x1000>;
104		};
105
106		timer@200a000 {
107			compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
108				     "qcom,msm-timer";
109			interrupts = <GIC_PPI 1 0x301>,
110				     <GIC_PPI 2 0x301>,
111				     <GIC_PPI 3 0x301>;
112			reg = <0x0200a000 0x100>;
113			clock-frequency = <27000000>;
114			cpu-offset = <0x80000>;
115		};
116
117		msmgpio: pinctrl@800000 {
118			compatible = "qcom,msm8960-pinctrl";
119			gpio-controller;
120			gpio-ranges = <&msmgpio 0 0 152>;
121			#gpio-cells = <2>;
122			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
123			interrupt-controller;
124			#interrupt-cells = <2>;
125			reg = <0x800000 0x4000>;
126		};
127
128		gcc: clock-controller@900000 {
129			compatible = "qcom,gcc-msm8960";
130			#clock-cells = <1>;
131			#power-domain-cells = <1>;
132			#reset-cells = <1>;
133			reg = <0x900000 0x4000>;
134			clocks = <&cxo_board>,
135				 <&pxo_board>,
136				 <&lcc PLL4>;
137			clock-names = "cxo", "pxo", "pll4";
138		};
139
140		lcc: clock-controller@28000000 {
141			compatible = "qcom,lcc-msm8960";
142			reg = <0x28000000 0x1000>;
143			#clock-cells = <1>;
144			#reset-cells = <1>;
145			clocks = <&pxo_board>,
146				 <&gcc PLL4_VOTE>,
147				 <0>,
148				 <0>, <0>,
149				 <0>, <0>,
150				 <0>;
151			clock-names = "pxo",
152				      "pll4_vote",
153				      "mi2s_codec_clk",
154				      "codec_i2s_mic_codec_clk",
155				      "spare_i2s_mic_codec_clk",
156				      "codec_i2s_spkr_codec_clk",
157				      "spare_i2s_spkr_codec_clk",
158				      "pcm_codec_clk";
159		};
160
161		clock-controller@4000000 {
162			compatible = "qcom,mmcc-msm8960";
163			reg = <0x4000000 0x1000>;
164			#clock-cells = <1>;
165			#power-domain-cells = <1>;
166			#reset-cells = <1>;
167			clocks = <&pxo_board>,
168				 <&gcc PLL3>,
169				 <&gcc PLL8_VOTE>,
170				 <0>,
171				 <0>,
172				 <0>,
173				 <0>,
174				 <0>;
175			clock-names = "pxo",
176				      "pll3",
177				      "pll8_vote",
178				      "dsi1pll",
179				      "dsi1pllbyte",
180				      "dsi2pll",
181				      "dsi2pllbyte",
182				      "hdmipll";
183		};
184
185		l2cc: clock-controller@2011000 {
186			compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
187			reg = <0x2011000 0x1000>;
188			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
189			clock-names = "pll8_vote", "pxo";
190			#clock-cells = <0>;
191		};
192
193		rpm: rpm@108000 {
194			compatible = "qcom,rpm-msm8960";
195			reg = <0x108000 0x1000>;
196			qcom,ipc = <&l2cc 0x8 2>;
197
198			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
199				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
200				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
201			interrupt-names = "ack", "err", "wakeup";
202
203			regulators {
204				compatible = "qcom,rpm-pm8921-regulators";
205			};
206		};
207
208		acc0: clock-controller@2088000 {
209			compatible = "qcom,kpss-acc-v1";
210			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
211			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
212			clock-names = "pll8_vote", "pxo";
213			clock-output-names = "acpu0_aux";
214			#clock-cells = <0>;
215		};
216
217		acc1: clock-controller@2098000 {
218			compatible = "qcom,kpss-acc-v1";
219			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
220			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
221			clock-names = "pll8_vote", "pxo";
222			clock-output-names = "acpu1_aux";
223			#clock-cells = <0>;
224		};
225
226		saw0: regulator@2089000 {
227			compatible = "qcom,saw2";
228			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
229			regulator;
230		};
231
232		saw1: regulator@2099000 {
233			compatible = "qcom,saw2";
234			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
235			regulator;
236		};
237
238		gsbi5: gsbi@16400000 {
239			compatible = "qcom,gsbi-v1.0.0";
240			cell-index = <5>;
241			reg = <0x16400000 0x100>;
242			clocks = <&gcc GSBI5_H_CLK>;
243			clock-names = "iface";
244			#address-cells = <1>;
245			#size-cells = <1>;
246			ranges;
247
248			syscon-tcsr = <&tcsr>;
249
250			gsbi5_serial: serial@16440000 {
251				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
252				reg = <0x16440000 0x1000>,
253				      <0x16400000 0x1000>;
254				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
255				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
256				clock-names = "core", "iface";
257				status = "disabled";
258			};
259		};
260
261		ssbi@500000 {
262			compatible = "qcom,ssbi";
263			reg = <0x500000 0x1000>;
264			qcom,controller-type = "pmic-arbiter";
265
266			pmicintc: pmic {
267				compatible = "qcom,pm8921";
268				interrupt-parent = <&msmgpio>;
269				interrupts = <104 IRQ_TYPE_LEVEL_LOW>;
270				#interrupt-cells = <2>;
271				interrupt-controller;
272				#address-cells = <1>;
273				#size-cells = <0>;
274
275				pwrkey@1c {
276					compatible = "qcom,pm8921-pwrkey";
277					reg = <0x1c>;
278					interrupt-parent = <&pmicintc>;
279					interrupts = <50 IRQ_TYPE_EDGE_RISING>,
280						     <51 IRQ_TYPE_EDGE_RISING>;
281					debounce = <15625>;
282					pull-up;
283				};
284
285				keypad@148 {
286					compatible = "qcom,pm8921-keypad";
287					reg = <0x148>;
288					interrupt-parent = <&pmicintc>;
289					interrupts = <74 IRQ_TYPE_EDGE_RISING>,
290						     <75 IRQ_TYPE_EDGE_RISING>;
291					debounce = <15>;
292					scan-delay = <32>;
293					row-hold = <91500>;
294				};
295
296				rtc@11d {
297					compatible = "qcom,pm8921-rtc";
298					interrupt-parent = <&pmicintc>;
299					interrupts = <39 IRQ_TYPE_EDGE_RISING>;
300					reg = <0x11d>;
301					allow-set-time;
302				};
303			};
304		};
305
306		rng@1a500000 {
307			compatible = "qcom,prng";
308			reg = <0x1a500000 0x200>;
309			clocks = <&gcc PRNG_CLK>;
310			clock-names = "core";
311		};
312
313		sdcc3: mmc@12180000 {
314			compatible = "arm,pl18x", "arm,primecell";
315			arm,primecell-periphid = <0x00051180>;
316			status = "disabled";
317			reg = <0x12180000 0x8000>;
318			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
319			clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
320			clock-names = "mclk", "apb_pclk";
321			bus-width = <4>;
322			cap-sd-highspeed;
323			cap-mmc-highspeed;
324			max-frequency = <192000000>;
325			no-1-8-v;
326			vmmc-supply = <&vsdcc_fixed>;
327		};
328
329		sdcc1: mmc@12400000 {
330			status = "disabled";
331			compatible = "arm,pl18x", "arm,primecell";
332			arm,primecell-periphid = <0x00051180>;
333			reg = <0x12400000 0x8000>;
334			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
335			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
336			clock-names = "mclk", "apb_pclk";
337			bus-width = <8>;
338			max-frequency = <96000000>;
339			non-removable;
340			cap-sd-highspeed;
341			cap-mmc-highspeed;
342			vmmc-supply = <&vsdcc_fixed>;
343		};
344
345		tcsr: syscon@1a400000 {
346			compatible = "qcom,tcsr-msm8960", "syscon";
347			reg = <0x1a400000 0x100>;
348		};
349
350		gsbi1: gsbi@16000000 {
351			compatible = "qcom,gsbi-v1.0.0";
352			cell-index = <1>;
353			reg = <0x16000000 0x100>;
354			clocks = <&gcc GSBI1_H_CLK>;
355			clock-names = "iface";
356			#address-cells = <1>;
357			#size-cells = <1>;
358			ranges;
359
360			gsbi1_spi: spi@16080000 {
361				compatible = "qcom,spi-qup-v1.1.1";
362				#address-cells = <1>;
363				#size-cells = <0>;
364				reg = <0x16080000 0x1000>;
365				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
366				spi-max-frequency = <24000000>;
367				cs-gpios = <&msmgpio 8 0>;
368
369				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
370				clock-names = "core", "iface";
371				status = "disabled";
372			};
373		};
374
375		usb1: usb@12500000 {
376			compatible = "qcom,ci-hdrc";
377			reg = <0x12500000 0x200>,
378			      <0x12500200 0x200>;
379			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
380			clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
381			clock-names = "core", "iface";
382			assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
383			assigned-clock-rates = <60000000>;
384			resets = <&gcc USB_HS1_RESET>;
385			reset-names = "core";
386			phy_type = "ulpi";
387			ahb-burst-config = <0>;
388			phys = <&usb_hs1_phy>;
389			phy-names = "usb-phy";
390			#reset-cells = <1>;
391			status = "disabled";
392
393			ulpi {
394				usb_hs1_phy: phy {
395					compatible = "qcom,usb-hs-phy-msm8960",
396						     "qcom,usb-hs-phy";
397					clocks = <&sleep_clk>, <&cxo_board>;
398					clock-names = "sleep", "ref";
399					resets = <&usb1 0>;
400					reset-names = "por";
401					#phy-cells = <0>;
402				};
403			};
404		};
405	};
406};
407