1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,apr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6afe.h> 20#include <dt-bindings/thermal/thermal.h> 21#include <dt-bindings/clock/qcom,videocc-sm8250.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 i2c4 = &i2c4; 35 i2c5 = &i2c5; 36 i2c6 = &i2c6; 37 i2c7 = &i2c7; 38 i2c8 = &i2c8; 39 i2c9 = &i2c9; 40 i2c10 = &i2c10; 41 i2c11 = &i2c11; 42 i2c12 = &i2c12; 43 i2c13 = &i2c13; 44 i2c14 = &i2c14; 45 i2c15 = &i2c15; 46 i2c16 = &i2c16; 47 i2c17 = &i2c17; 48 i2c18 = &i2c18; 49 i2c19 = &i2c19; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 spi16 = &spi16; 67 spi17 = &spi17; 68 spi18 = &spi18; 69 spi19 = &spi19; 70 }; 71 72 chosen { }; 73 74 clocks { 75 xo_board: xo-board { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <38400000>; 79 clock-output-names = "xo_board"; 80 }; 81 82 sleep_clk: sleep-clk { 83 compatible = "fixed-clock"; 84 clock-frequency = <32768>; 85 #clock-cells = <0>; 86 }; 87 }; 88 89 cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo485"; 96 reg = <0x0 0x0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <448>; 99 dynamic-power-coefficient = <205>; 100 next-level-cache = <&L2_0>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 #cooling-cells = <2>; 103 L2_0: l2-cache { 104 compatible = "cache"; 105 next-level-cache = <&L3_0>; 106 L3_0: l3-cache { 107 compatible = "cache"; 108 }; 109 }; 110 }; 111 112 CPU1: cpu@100 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo485"; 115 reg = <0x0 0x100>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <448>; 118 dynamic-power-coefficient = <205>; 119 next-level-cache = <&L2_100>; 120 qcom,freq-domain = <&cpufreq_hw 0>; 121 #cooling-cells = <2>; 122 L2_100: l2-cache { 123 compatible = "cache"; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU2: cpu@200 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo485"; 131 reg = <0x0 0x200>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <448>; 134 dynamic-power-coefficient = <205>; 135 next-level-cache = <&L2_200>; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 #cooling-cells = <2>; 138 L2_200: l2-cache { 139 compatible = "cache"; 140 next-level-cache = <&L3_0>; 141 }; 142 }; 143 144 CPU3: cpu@300 { 145 device_type = "cpu"; 146 compatible = "qcom,kryo485"; 147 reg = <0x0 0x300>; 148 enable-method = "psci"; 149 capacity-dmips-mhz = <448>; 150 dynamic-power-coefficient = <205>; 151 next-level-cache = <&L2_300>; 152 qcom,freq-domain = <&cpufreq_hw 0>; 153 #cooling-cells = <2>; 154 L2_300: l2-cache { 155 compatible = "cache"; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 160 CPU4: cpu@400 { 161 device_type = "cpu"; 162 compatible = "qcom,kryo485"; 163 reg = <0x0 0x400>; 164 enable-method = "psci"; 165 capacity-dmips-mhz = <1024>; 166 dynamic-power-coefficient = <379>; 167 next-level-cache = <&L2_400>; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 #cooling-cells = <2>; 170 L2_400: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU5: cpu@500 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo485"; 179 reg = <0x0 0x500>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <379>; 183 next-level-cache = <&L2_500>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 #cooling-cells = <2>; 186 L2_500: l2-cache { 187 compatible = "cache"; 188 next-level-cache = <&L3_0>; 189 }; 190 191 }; 192 193 CPU6: cpu@600 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo485"; 196 reg = <0x0 0x600>; 197 enable-method = "psci"; 198 capacity-dmips-mhz = <1024>; 199 dynamic-power-coefficient = <379>; 200 next-level-cache = <&L2_600>; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 #cooling-cells = <2>; 203 L2_600: l2-cache { 204 compatible = "cache"; 205 next-level-cache = <&L3_0>; 206 }; 207 }; 208 209 CPU7: cpu@700 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo485"; 212 reg = <0x0 0x700>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1024>; 215 dynamic-power-coefficient = <444>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 }; 261 262 firmware { 263 scm: scm { 264 compatible = "qcom,scm"; 265 #reset-cells = <1>; 266 }; 267 }; 268 269 memory@80000000 { 270 device_type = "memory"; 271 /* We expect the bootloader to fill in the size */ 272 reg = <0x0 0x80000000 0x0 0x0>; 273 }; 274 275 mmcx_reg: mmcx-reg { 276 compatible = "regulator-fixed-domain"; 277 power-domains = <&rpmhpd SM8250_MMCX>; 278 required-opps = <&rpmhpd_opp_low_svs>; 279 regulator-name = "MMCX"; 280 }; 281 282 pmu { 283 compatible = "arm,armv8-pmuv3"; 284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 285 }; 286 287 psci { 288 compatible = "arm,psci-1.0"; 289 method = "smc"; 290 }; 291 292 reserved-memory { 293 #address-cells = <2>; 294 #size-cells = <2>; 295 ranges; 296 297 hyp_mem: memory@80000000 { 298 reg = <0x0 0x80000000 0x0 0x600000>; 299 no-map; 300 }; 301 302 xbl_aop_mem: memory@80700000 { 303 reg = <0x0 0x80700000 0x0 0x160000>; 304 no-map; 305 }; 306 307 cmd_db: memory@80860000 { 308 compatible = "qcom,cmd-db"; 309 reg = <0x0 0x80860000 0x0 0x20000>; 310 no-map; 311 }; 312 313 smem_mem: memory@80900000 { 314 reg = <0x0 0x80900000 0x0 0x200000>; 315 no-map; 316 }; 317 318 removed_mem: memory@80b00000 { 319 reg = <0x0 0x80b00000 0x0 0x5300000>; 320 no-map; 321 }; 322 323 camera_mem: memory@86200000 { 324 reg = <0x0 0x86200000 0x0 0x500000>; 325 no-map; 326 }; 327 328 wlan_mem: memory@86700000 { 329 reg = <0x0 0x86700000 0x0 0x100000>; 330 no-map; 331 }; 332 333 ipa_fw_mem: memory@86800000 { 334 reg = <0x0 0x86800000 0x0 0x10000>; 335 no-map; 336 }; 337 338 ipa_gsi_mem: memory@86810000 { 339 reg = <0x0 0x86810000 0x0 0xa000>; 340 no-map; 341 }; 342 343 gpu_mem: memory@8681a000 { 344 reg = <0x0 0x8681a000 0x0 0x2000>; 345 no-map; 346 }; 347 348 npu_mem: memory@86900000 { 349 reg = <0x0 0x86900000 0x0 0x500000>; 350 no-map; 351 }; 352 353 video_mem: memory@86e00000 { 354 reg = <0x0 0x86e00000 0x0 0x500000>; 355 no-map; 356 }; 357 358 cvp_mem: memory@87300000 { 359 reg = <0x0 0x87300000 0x0 0x500000>; 360 no-map; 361 }; 362 363 cdsp_mem: memory@87800000 { 364 reg = <0x0 0x87800000 0x0 0x1400000>; 365 no-map; 366 }; 367 368 slpi_mem: memory@88c00000 { 369 reg = <0x0 0x88c00000 0x0 0x1500000>; 370 no-map; 371 }; 372 373 adsp_mem: memory@8a100000 { 374 reg = <0x0 0x8a100000 0x0 0x1d00000>; 375 no-map; 376 }; 377 378 spss_mem: memory@8be00000 { 379 reg = <0x0 0x8be00000 0x0 0x100000>; 380 no-map; 381 }; 382 383 cdsp_secure_heap: memory@8bf00000 { 384 reg = <0x0 0x8bf00000 0x0 0x4600000>; 385 no-map; 386 }; 387 }; 388 389 smem { 390 compatible = "qcom,smem"; 391 memory-region = <&smem_mem>; 392 hwlocks = <&tcsr_mutex 3>; 393 }; 394 395 smp2p-adsp { 396 compatible = "qcom,smp2p"; 397 qcom,smem = <443>, <429>; 398 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 399 IPCC_MPROC_SIGNAL_SMP2P 400 IRQ_TYPE_EDGE_RISING>; 401 mboxes = <&ipcc IPCC_CLIENT_LPASS 402 IPCC_MPROC_SIGNAL_SMP2P>; 403 404 qcom,local-pid = <0>; 405 qcom,remote-pid = <2>; 406 407 smp2p_adsp_out: master-kernel { 408 qcom,entry-name = "master-kernel"; 409 #qcom,smem-state-cells = <1>; 410 }; 411 412 smp2p_adsp_in: slave-kernel { 413 qcom,entry-name = "slave-kernel"; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 }; 417 }; 418 419 smp2p-cdsp { 420 compatible = "qcom,smp2p"; 421 qcom,smem = <94>, <432>; 422 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 423 IPCC_MPROC_SIGNAL_SMP2P 424 IRQ_TYPE_EDGE_RISING>; 425 mboxes = <&ipcc IPCC_CLIENT_CDSP 426 IPCC_MPROC_SIGNAL_SMP2P>; 427 428 qcom,local-pid = <0>; 429 qcom,remote-pid = <5>; 430 431 smp2p_cdsp_out: master-kernel { 432 qcom,entry-name = "master-kernel"; 433 #qcom,smem-state-cells = <1>; 434 }; 435 436 smp2p_cdsp_in: slave-kernel { 437 qcom,entry-name = "slave-kernel"; 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 }; 441 }; 442 443 smp2p-slpi { 444 compatible = "qcom,smp2p"; 445 qcom,smem = <481>, <430>; 446 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 447 IPCC_MPROC_SIGNAL_SMP2P 448 IRQ_TYPE_EDGE_RISING>; 449 mboxes = <&ipcc IPCC_CLIENT_SLPI 450 IPCC_MPROC_SIGNAL_SMP2P>; 451 452 qcom,local-pid = <0>; 453 qcom,remote-pid = <3>; 454 455 smp2p_slpi_out: master-kernel { 456 qcom,entry-name = "master-kernel"; 457 #qcom,smem-state-cells = <1>; 458 }; 459 460 smp2p_slpi_in: slave-kernel { 461 qcom,entry-name = "slave-kernel"; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 }; 465 }; 466 467 soc: soc@0 { 468 #address-cells = <2>; 469 #size-cells = <2>; 470 ranges = <0 0 0 0 0x10 0>; 471 dma-ranges = <0 0 0 0 0x10 0>; 472 compatible = "simple-bus"; 473 474 gcc: clock-controller@100000 { 475 compatible = "qcom,gcc-sm8250"; 476 reg = <0x0 0x00100000 0x0 0x1f0000>; 477 #clock-cells = <1>; 478 #reset-cells = <1>; 479 #power-domain-cells = <1>; 480 clock-names = "bi_tcxo", 481 "bi_tcxo_ao", 482 "sleep_clk"; 483 clocks = <&rpmhcc RPMH_CXO_CLK>, 484 <&rpmhcc RPMH_CXO_CLK_A>, 485 <&sleep_clk>; 486 }; 487 488 ipcc: mailbox@408000 { 489 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 490 reg = <0 0x00408000 0 0x1000>; 491 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-controller; 493 #interrupt-cells = <3>; 494 #mbox-cells = <2>; 495 }; 496 497 rng: rng@793000 { 498 compatible = "qcom,prng-ee"; 499 reg = <0 0x00793000 0 0x1000>; 500 clocks = <&gcc GCC_PRNG_AHB_CLK>; 501 clock-names = "core"; 502 }; 503 504 qup_opp_table: qup-opp-table { 505 compatible = "operating-points-v2"; 506 507 opp-50000000 { 508 opp-hz = /bits/ 64 <50000000>; 509 required-opps = <&rpmhpd_opp_min_svs>; 510 }; 511 512 opp-75000000 { 513 opp-hz = /bits/ 64 <75000000>; 514 required-opps = <&rpmhpd_opp_low_svs>; 515 }; 516 517 opp-120000000 { 518 opp-hz = /bits/ 64 <120000000>; 519 required-opps = <&rpmhpd_opp_svs>; 520 }; 521 }; 522 523 gpi_dma2: dma-controller@800000 { 524 compatible = "qcom,sm8250-gpi-dma"; 525 reg = <0 0x00800000 0 0x70000>; 526 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 536 dma-channels = <10>; 537 dma-channel-mask = <0x3f>; 538 iommus = <&apps_smmu 0x76 0x0>; 539 #dma-cells = <3>; 540 status = "disabled"; 541 }; 542 543 qupv3_id_2: geniqup@8c0000 { 544 compatible = "qcom,geni-se-qup"; 545 reg = <0x0 0x008c0000 0x0 0x6000>; 546 clock-names = "m-ahb", "s-ahb"; 547 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 548 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 549 #address-cells = <2>; 550 #size-cells = <2>; 551 iommus = <&apps_smmu 0x63 0x0>; 552 ranges; 553 status = "disabled"; 554 555 i2c14: i2c@880000 { 556 compatible = "qcom,geni-i2c"; 557 reg = <0 0x00880000 0 0x4000>; 558 clock-names = "se"; 559 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&qup_i2c14_default>; 562 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 563 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 564 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 565 dma-names = "tx", "rx"; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 }; 570 571 spi14: spi@880000 { 572 compatible = "qcom,geni-spi"; 573 reg = <0 0x00880000 0 0x4000>; 574 clock-names = "se"; 575 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 576 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 577 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 578 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 579 dma-names = "tx", "rx"; 580 power-domains = <&rpmhpd SM8250_CX>; 581 operating-points-v2 = <&qup_opp_table>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 i2c15: i2c@884000 { 588 compatible = "qcom,geni-i2c"; 589 reg = <0 0x00884000 0 0x4000>; 590 clock-names = "se"; 591 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&qup_i2c15_default>; 594 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 595 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 596 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 597 dma-names = "tx", "rx"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 spi15: spi@884000 { 604 compatible = "qcom,geni-spi"; 605 reg = <0 0x00884000 0 0x4000>; 606 clock-names = "se"; 607 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 608 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 609 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 610 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 611 dma-names = "tx", "rx"; 612 power-domains = <&rpmhpd SM8250_CX>; 613 operating-points-v2 = <&qup_opp_table>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 status = "disabled"; 617 }; 618 619 i2c16: i2c@888000 { 620 compatible = "qcom,geni-i2c"; 621 reg = <0 0x00888000 0 0x4000>; 622 clock-names = "se"; 623 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&qup_i2c16_default>; 626 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 627 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 628 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 629 dma-names = "tx", "rx"; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 status = "disabled"; 633 }; 634 635 spi16: spi@888000 { 636 compatible = "qcom,geni-spi"; 637 reg = <0 0x00888000 0 0x4000>; 638 clock-names = "se"; 639 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 640 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 641 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 642 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 643 dma-names = "tx", "rx"; 644 power-domains = <&rpmhpd SM8250_CX>; 645 operating-points-v2 = <&qup_opp_table>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 i2c17: i2c@88c000 { 652 compatible = "qcom,geni-i2c"; 653 reg = <0 0x0088c000 0 0x4000>; 654 clock-names = "se"; 655 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&qup_i2c17_default>; 658 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 659 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 660 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 661 dma-names = "tx", "rx"; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 status = "disabled"; 665 }; 666 667 spi17: spi@88c000 { 668 compatible = "qcom,geni-spi"; 669 reg = <0 0x0088c000 0 0x4000>; 670 clock-names = "se"; 671 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 672 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 673 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 674 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 675 dma-names = "tx", "rx"; 676 power-domains = <&rpmhpd SM8250_CX>; 677 operating-points-v2 = <&qup_opp_table>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 status = "disabled"; 681 }; 682 683 uart17: serial@88c000 { 684 compatible = "qcom,geni-uart"; 685 reg = <0 0x0088c000 0 0x4000>; 686 clock-names = "se"; 687 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&qup_uart17_default>; 690 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 691 power-domains = <&rpmhpd SM8250_CX>; 692 operating-points-v2 = <&qup_opp_table>; 693 status = "disabled"; 694 }; 695 696 i2c18: i2c@890000 { 697 compatible = "qcom,geni-i2c"; 698 reg = <0 0x00890000 0 0x4000>; 699 clock-names = "se"; 700 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&qup_i2c18_default>; 703 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 704 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 705 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 706 dma-names = "tx", "rx"; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 status = "disabled"; 710 }; 711 712 spi18: spi@890000 { 713 compatible = "qcom,geni-spi"; 714 reg = <0 0x00890000 0 0x4000>; 715 clock-names = "se"; 716 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 717 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 718 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 719 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 720 dma-names = "tx", "rx"; 721 power-domains = <&rpmhpd SM8250_CX>; 722 operating-points-v2 = <&qup_opp_table>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 status = "disabled"; 726 }; 727 728 uart18: serial@890000 { 729 compatible = "qcom,geni-uart"; 730 reg = <0 0x00890000 0 0x4000>; 731 clock-names = "se"; 732 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&qup_uart18_default>; 735 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 736 power-domains = <&rpmhpd SM8250_CX>; 737 operating-points-v2 = <&qup_opp_table>; 738 status = "disabled"; 739 }; 740 741 i2c19: i2c@894000 { 742 compatible = "qcom,geni-i2c"; 743 reg = <0 0x00894000 0 0x4000>; 744 clock-names = "se"; 745 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&qup_i2c19_default>; 748 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 749 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 750 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 751 dma-names = "tx", "rx"; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 757 spi19: spi@894000 { 758 compatible = "qcom,geni-spi"; 759 reg = <0 0x00894000 0 0x4000>; 760 clock-names = "se"; 761 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 762 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 763 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 764 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 765 dma-names = "tx", "rx"; 766 power-domains = <&rpmhpd SM8250_CX>; 767 operating-points-v2 = <&qup_opp_table>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 status = "disabled"; 771 }; 772 }; 773 774 gpi_dma0: dma-controller@900000 { 775 compatible = "qcom,sm8250-gpi-dma"; 776 reg = <0 0x00900000 0 0x70000>; 777 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 790 dma-channels = <15>; 791 dma-channel-mask = <0x7ff>; 792 iommus = <&apps_smmu 0x5b6 0x0>; 793 #dma-cells = <3>; 794 status = "disabled"; 795 }; 796 797 qupv3_id_0: geniqup@9c0000 { 798 compatible = "qcom,geni-se-qup"; 799 reg = <0x0 0x009c0000 0x0 0x6000>; 800 clock-names = "m-ahb", "s-ahb"; 801 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 802 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 803 #address-cells = <2>; 804 #size-cells = <2>; 805 iommus = <&apps_smmu 0x5a3 0x0>; 806 ranges; 807 status = "disabled"; 808 809 i2c0: i2c@980000 { 810 compatible = "qcom,geni-i2c"; 811 reg = <0 0x00980000 0 0x4000>; 812 clock-names = "se"; 813 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 814 pinctrl-names = "default"; 815 pinctrl-0 = <&qup_i2c0_default>; 816 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 817 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 818 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 819 dma-names = "tx", "rx"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 spi0: spi@980000 { 826 compatible = "qcom,geni-spi"; 827 reg = <0 0x00980000 0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 830 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 831 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 832 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 833 dma-names = "tx", "rx"; 834 power-domains = <&rpmhpd SM8250_CX>; 835 operating-points-v2 = <&qup_opp_table>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 i2c1: i2c@984000 { 842 compatible = "qcom,geni-i2c"; 843 reg = <0 0x00984000 0 0x4000>; 844 clock-names = "se"; 845 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&qup_i2c1_default>; 848 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 849 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 850 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 851 dma-names = "tx", "rx"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 status = "disabled"; 855 }; 856 857 spi1: spi@984000 { 858 compatible = "qcom,geni-spi"; 859 reg = <0 0x00984000 0 0x4000>; 860 clock-names = "se"; 861 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 862 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 863 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 864 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 865 dma-names = "tx", "rx"; 866 power-domains = <&rpmhpd SM8250_CX>; 867 operating-points-v2 = <&qup_opp_table>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 status = "disabled"; 871 }; 872 873 i2c2: i2c@988000 { 874 compatible = "qcom,geni-i2c"; 875 reg = <0 0x00988000 0 0x4000>; 876 clock-names = "se"; 877 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&qup_i2c2_default>; 880 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 881 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 882 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 883 dma-names = "tx", "rx"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 status = "disabled"; 887 }; 888 889 spi2: spi@988000 { 890 compatible = "qcom,geni-spi"; 891 reg = <0 0x00988000 0 0x4000>; 892 clock-names = "se"; 893 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 894 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 895 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 896 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 897 dma-names = "tx", "rx"; 898 power-domains = <&rpmhpd SM8250_CX>; 899 operating-points-v2 = <&qup_opp_table>; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 905 uart2: serial@988000 { 906 compatible = "qcom,geni-debug-uart"; 907 reg = <0 0x00988000 0 0x4000>; 908 clock-names = "se"; 909 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 910 pinctrl-names = "default"; 911 pinctrl-0 = <&qup_uart2_default>; 912 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 913 power-domains = <&rpmhpd SM8250_CX>; 914 operating-points-v2 = <&qup_opp_table>; 915 status = "disabled"; 916 }; 917 918 i2c3: i2c@98c000 { 919 compatible = "qcom,geni-i2c"; 920 reg = <0 0x0098c000 0 0x4000>; 921 clock-names = "se"; 922 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_i2c3_default>; 925 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 926 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 927 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 928 dma-names = "tx", "rx"; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 status = "disabled"; 932 }; 933 934 spi3: spi@98c000 { 935 compatible = "qcom,geni-spi"; 936 reg = <0 0x0098c000 0 0x4000>; 937 clock-names = "se"; 938 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 939 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 940 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 941 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 942 dma-names = "tx", "rx"; 943 power-domains = <&rpmhpd SM8250_CX>; 944 operating-points-v2 = <&qup_opp_table>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 i2c4: i2c@990000 { 951 compatible = "qcom,geni-i2c"; 952 reg = <0 0x00990000 0 0x4000>; 953 clock-names = "se"; 954 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 955 pinctrl-names = "default"; 956 pinctrl-0 = <&qup_i2c4_default>; 957 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 958 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 959 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 960 dma-names = "tx", "rx"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 status = "disabled"; 964 }; 965 966 spi4: spi@990000 { 967 compatible = "qcom,geni-spi"; 968 reg = <0 0x00990000 0 0x4000>; 969 clock-names = "se"; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 971 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 972 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 973 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 974 dma-names = "tx", "rx"; 975 power-domains = <&rpmhpd SM8250_CX>; 976 operating-points-v2 = <&qup_opp_table>; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 status = "disabled"; 980 }; 981 982 i2c5: i2c@994000 { 983 compatible = "qcom,geni-i2c"; 984 reg = <0 0x00994000 0 0x4000>; 985 clock-names = "se"; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_i2c5_default>; 989 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 990 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 991 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 status = "disabled"; 996 }; 997 998 spi5: spi@994000 { 999 compatible = "qcom,geni-spi"; 1000 reg = <0 0x00994000 0 0x4000>; 1001 clock-names = "se"; 1002 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1003 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1004 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1005 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1006 dma-names = "tx", "rx"; 1007 power-domains = <&rpmhpd SM8250_CX>; 1008 operating-points-v2 = <&qup_opp_table>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 status = "disabled"; 1012 }; 1013 1014 i2c6: i2c@998000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x00998000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c6_default>; 1021 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1022 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1023 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1024 dma-names = "tx", "rx"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 spi6: spi@998000 { 1031 compatible = "qcom,geni-spi"; 1032 reg = <0 0x00998000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1035 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1036 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1037 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1038 dma-names = "tx", "rx"; 1039 power-domains = <&rpmhpd SM8250_CX>; 1040 operating-points-v2 = <&qup_opp_table>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 status = "disabled"; 1044 }; 1045 1046 uart6: serial@998000 { 1047 compatible = "qcom,geni-uart"; 1048 reg = <0 0x00998000 0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&qup_uart6_default>; 1053 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1054 power-domains = <&rpmhpd SM8250_CX>; 1055 operating-points-v2 = <&qup_opp_table>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c7: i2c@99c000 { 1060 compatible = "qcom,geni-i2c"; 1061 reg = <0 0x0099c000 0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_i2c7_default>; 1066 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1067 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1068 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1069 dma-names = "tx", "rx"; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 spi7: spi@99c000 { 1076 compatible = "qcom,geni-spi"; 1077 reg = <0 0x0099c000 0 0x4000>; 1078 clock-names = "se"; 1079 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1080 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1081 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1082 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1083 dma-names = "tx", "rx"; 1084 power-domains = <&rpmhpd SM8250_CX>; 1085 operating-points-v2 = <&qup_opp_table>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 status = "disabled"; 1089 }; 1090 }; 1091 1092 gpi_dma1: dma-controller@a00000 { 1093 compatible = "qcom,sm8250-gpi-dma"; 1094 reg = <0 0x00a00000 0 0x70000>; 1095 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1105 dma-channels = <10>; 1106 dma-channel-mask = <0x3f>; 1107 iommus = <&apps_smmu 0x56 0x0>; 1108 #dma-cells = <3>; 1109 status = "disabled"; 1110 }; 1111 1112 qupv3_id_1: geniqup@ac0000 { 1113 compatible = "qcom,geni-se-qup"; 1114 reg = <0x0 0x00ac0000 0x0 0x6000>; 1115 clock-names = "m-ahb", "s-ahb"; 1116 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1117 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1118 #address-cells = <2>; 1119 #size-cells = <2>; 1120 iommus = <&apps_smmu 0x43 0x0>; 1121 ranges; 1122 status = "disabled"; 1123 1124 i2c8: i2c@a80000 { 1125 compatible = "qcom,geni-i2c"; 1126 reg = <0 0x00a80000 0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_i2c8_default>; 1131 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1132 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1133 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1134 dma-names = "tx", "rx"; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi8: spi@a80000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00a80000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1145 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1146 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1147 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1148 dma-names = "tx", "rx"; 1149 power-domains = <&rpmhpd SM8250_CX>; 1150 operating-points-v2 = <&qup_opp_table>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c9: i2c@a84000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x00a84000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_i2c9_default>; 1163 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1164 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1165 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1166 dma-names = "tx", "rx"; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 spi9: spi@a84000 { 1173 compatible = "qcom,geni-spi"; 1174 reg = <0 0x00a84000 0 0x4000>; 1175 clock-names = "se"; 1176 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1177 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1178 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1179 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1180 dma-names = "tx", "rx"; 1181 power-domains = <&rpmhpd SM8250_CX>; 1182 operating-points-v2 = <&qup_opp_table>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 status = "disabled"; 1186 }; 1187 1188 i2c10: i2c@a88000 { 1189 compatible = "qcom,geni-i2c"; 1190 reg = <0 0x00a88000 0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_i2c10_default>; 1195 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1196 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1197 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1198 dma-names = "tx", "rx"; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 status = "disabled"; 1202 }; 1203 1204 spi10: spi@a88000 { 1205 compatible = "qcom,geni-spi"; 1206 reg = <0 0x00a88000 0 0x4000>; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1209 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1210 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1211 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1212 dma-names = "tx", "rx"; 1213 power-domains = <&rpmhpd SM8250_CX>; 1214 operating-points-v2 = <&qup_opp_table>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 i2c11: i2c@a8c000 { 1221 compatible = "qcom,geni-i2c"; 1222 reg = <0 0x00a8c000 0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&qup_i2c11_default>; 1227 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1228 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1229 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1230 dma-names = "tx", "rx"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 spi11: spi@a8c000 { 1237 compatible = "qcom,geni-spi"; 1238 reg = <0 0x00a8c000 0 0x4000>; 1239 clock-names = "se"; 1240 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1241 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1242 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1243 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1244 dma-names = "tx", "rx"; 1245 power-domains = <&rpmhpd SM8250_CX>; 1246 operating-points-v2 = <&qup_opp_table>; 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 status = "disabled"; 1250 }; 1251 1252 i2c12: i2c@a90000 { 1253 compatible = "qcom,geni-i2c"; 1254 reg = <0 0x00a90000 0 0x4000>; 1255 clock-names = "se"; 1256 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&qup_i2c12_default>; 1259 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1260 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1261 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1262 dma-names = "tx", "rx"; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 status = "disabled"; 1266 }; 1267 1268 spi12: spi@a90000 { 1269 compatible = "qcom,geni-spi"; 1270 reg = <0 0x00a90000 0 0x4000>; 1271 clock-names = "se"; 1272 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1273 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1274 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1275 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1276 dma-names = "tx", "rx"; 1277 power-domains = <&rpmhpd SM8250_CX>; 1278 operating-points-v2 = <&qup_opp_table>; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 1284 uart12: serial@a90000 { 1285 compatible = "qcom,geni-debug-uart"; 1286 reg = <0x0 0x00a90000 0x0 0x4000>; 1287 clock-names = "se"; 1288 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1289 pinctrl-names = "default"; 1290 pinctrl-0 = <&qup_uart12_default>; 1291 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1292 power-domains = <&rpmhpd SM8250_CX>; 1293 operating-points-v2 = <&qup_opp_table>; 1294 status = "disabled"; 1295 }; 1296 1297 i2c13: i2c@a94000 { 1298 compatible = "qcom,geni-i2c"; 1299 reg = <0 0x00a94000 0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_i2c13_default>; 1304 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1305 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1306 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1307 dma-names = "tx", "rx"; 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 status = "disabled"; 1311 }; 1312 1313 spi13: spi@a94000 { 1314 compatible = "qcom,geni-spi"; 1315 reg = <0 0x00a94000 0 0x4000>; 1316 clock-names = "se"; 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1318 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1319 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1320 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1321 dma-names = "tx", "rx"; 1322 power-domains = <&rpmhpd SM8250_CX>; 1323 operating-points-v2 = <&qup_opp_table>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 status = "disabled"; 1327 }; 1328 }; 1329 1330 config_noc: interconnect@1500000 { 1331 compatible = "qcom,sm8250-config-noc"; 1332 reg = <0 0x01500000 0 0xa580>; 1333 #interconnect-cells = <1>; 1334 qcom,bcm-voters = <&apps_bcm_voter>; 1335 }; 1336 1337 system_noc: interconnect@1620000 { 1338 compatible = "qcom,sm8250-system-noc"; 1339 reg = <0 0x01620000 0 0x1c200>; 1340 #interconnect-cells = <1>; 1341 qcom,bcm-voters = <&apps_bcm_voter>; 1342 }; 1343 1344 mc_virt: interconnect@163d000 { 1345 compatible = "qcom,sm8250-mc-virt"; 1346 reg = <0 0x0163d000 0 0x1000>; 1347 #interconnect-cells = <1>; 1348 qcom,bcm-voters = <&apps_bcm_voter>; 1349 }; 1350 1351 aggre1_noc: interconnect@16e0000 { 1352 compatible = "qcom,sm8250-aggre1-noc"; 1353 reg = <0 0x016e0000 0 0x1f180>; 1354 #interconnect-cells = <1>; 1355 qcom,bcm-voters = <&apps_bcm_voter>; 1356 }; 1357 1358 aggre2_noc: interconnect@1700000 { 1359 compatible = "qcom,sm8250-aggre2-noc"; 1360 reg = <0 0x01700000 0 0x33000>; 1361 #interconnect-cells = <1>; 1362 qcom,bcm-voters = <&apps_bcm_voter>; 1363 }; 1364 1365 compute_noc: interconnect@1733000 { 1366 compatible = "qcom,sm8250-compute-noc"; 1367 reg = <0 0x01733000 0 0xa180>; 1368 #interconnect-cells = <1>; 1369 qcom,bcm-voters = <&apps_bcm_voter>; 1370 }; 1371 1372 mmss_noc: interconnect@1740000 { 1373 compatible = "qcom,sm8250-mmss-noc"; 1374 reg = <0 0x01740000 0 0x1f080>; 1375 #interconnect-cells = <1>; 1376 qcom,bcm-voters = <&apps_bcm_voter>; 1377 }; 1378 1379 pcie0: pci@1c00000 { 1380 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1381 reg = <0 0x01c00000 0 0x3000>, 1382 <0 0x60000000 0 0xf1d>, 1383 <0 0x60000f20 0 0xa8>, 1384 <0 0x60001000 0 0x1000>, 1385 <0 0x60100000 0 0x100000>; 1386 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1387 device_type = "pci"; 1388 linux,pci-domain = <0>; 1389 bus-range = <0x00 0xff>; 1390 num-lanes = <1>; 1391 1392 #address-cells = <3>; 1393 #size-cells = <2>; 1394 1395 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1396 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1397 1398 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1399 interrupt-names = "msi"; 1400 #interrupt-cells = <1>; 1401 interrupt-map-mask = <0 0 0 0x7>; 1402 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1403 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1404 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1405 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1406 1407 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1408 <&gcc GCC_PCIE_0_AUX_CLK>, 1409 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1410 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1411 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1412 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1413 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1414 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1415 clock-names = "pipe", 1416 "aux", 1417 "cfg", 1418 "bus_master", 1419 "bus_slave", 1420 "slave_q2a", 1421 "tbu", 1422 "ddrss_sf_tbu"; 1423 1424 iommus = <&apps_smmu 0x1c00 0x7f>; 1425 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1426 <0x100 &apps_smmu 0x1c01 0x1>; 1427 1428 resets = <&gcc GCC_PCIE_0_BCR>; 1429 reset-names = "pci"; 1430 1431 power-domains = <&gcc PCIE_0_GDSC>; 1432 1433 phys = <&pcie0_lane>; 1434 phy-names = "pciephy"; 1435 1436 perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; 1437 enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1438 1439 pinctrl-names = "default"; 1440 pinctrl-0 = <&pcie0_default_state>; 1441 1442 status = "disabled"; 1443 }; 1444 1445 pcie0_phy: phy@1c06000 { 1446 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1447 reg = <0 0x01c06000 0 0x1c0>; 1448 #address-cells = <2>; 1449 #size-cells = <2>; 1450 ranges; 1451 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1452 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1453 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1454 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1455 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1456 1457 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1458 reset-names = "phy"; 1459 1460 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1461 assigned-clock-rates = <100000000>; 1462 1463 status = "disabled"; 1464 1465 pcie0_lane: lanes@1c06200 { 1466 reg = <0 0x1c06200 0 0x170>, /* tx */ 1467 <0 0x1c06400 0 0x200>, /* rx */ 1468 <0 0x1c06800 0 0x1f0>, /* pcs */ 1469 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1470 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1471 clock-names = "pipe0"; 1472 1473 #phy-cells = <0>; 1474 clock-output-names = "pcie_0_pipe_clk"; 1475 }; 1476 }; 1477 1478 pcie1: pci@1c08000 { 1479 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1480 reg = <0 0x01c08000 0 0x3000>, 1481 <0 0x40000000 0 0xf1d>, 1482 <0 0x40000f20 0 0xa8>, 1483 <0 0x40001000 0 0x1000>, 1484 <0 0x40100000 0 0x100000>; 1485 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1486 device_type = "pci"; 1487 linux,pci-domain = <1>; 1488 bus-range = <0x00 0xff>; 1489 num-lanes = <2>; 1490 1491 #address-cells = <3>; 1492 #size-cells = <2>; 1493 1494 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1495 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1496 1497 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1498 interrupt-names = "msi"; 1499 #interrupt-cells = <1>; 1500 interrupt-map-mask = <0 0 0 0x7>; 1501 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1502 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1503 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1504 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1505 1506 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1507 <&gcc GCC_PCIE_1_AUX_CLK>, 1508 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1509 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1510 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1511 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1512 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1513 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1514 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1515 clock-names = "pipe", 1516 "aux", 1517 "cfg", 1518 "bus_master", 1519 "bus_slave", 1520 "slave_q2a", 1521 "ref", 1522 "tbu", 1523 "ddrss_sf_tbu"; 1524 1525 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1526 assigned-clock-rates = <19200000>; 1527 1528 iommus = <&apps_smmu 0x1c80 0x7f>; 1529 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1530 <0x100 &apps_smmu 0x1c81 0x1>; 1531 1532 resets = <&gcc GCC_PCIE_1_BCR>; 1533 reset-names = "pci"; 1534 1535 power-domains = <&gcc PCIE_1_GDSC>; 1536 1537 phys = <&pcie1_lane>; 1538 phy-names = "pciephy"; 1539 1540 perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; 1541 enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1542 1543 pinctrl-names = "default"; 1544 pinctrl-0 = <&pcie1_default_state>; 1545 1546 status = "disabled"; 1547 }; 1548 1549 pcie1_phy: phy@1c0e000 { 1550 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1551 reg = <0 0x01c0e000 0 0x1c0>; 1552 #address-cells = <2>; 1553 #size-cells = <2>; 1554 ranges; 1555 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1556 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1557 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1558 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1559 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1560 1561 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1562 reset-names = "phy"; 1563 1564 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1565 assigned-clock-rates = <100000000>; 1566 1567 status = "disabled"; 1568 1569 pcie1_lane: lanes@1c0e200 { 1570 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1571 <0 0x1c0e400 0 0x200>, /* rx0 */ 1572 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1573 <0 0x1c0e600 0 0x170>, /* tx1 */ 1574 <0 0x1c0e800 0 0x200>, /* rx1 */ 1575 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1576 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1577 clock-names = "pipe0"; 1578 1579 #phy-cells = <0>; 1580 clock-output-names = "pcie_1_pipe_clk"; 1581 }; 1582 }; 1583 1584 pcie2: pci@1c10000 { 1585 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1586 reg = <0 0x01c10000 0 0x3000>, 1587 <0 0x64000000 0 0xf1d>, 1588 <0 0x64000f20 0 0xa8>, 1589 <0 0x64001000 0 0x1000>, 1590 <0 0x64100000 0 0x100000>; 1591 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1592 device_type = "pci"; 1593 linux,pci-domain = <2>; 1594 bus-range = <0x00 0xff>; 1595 num-lanes = <2>; 1596 1597 #address-cells = <3>; 1598 #size-cells = <2>; 1599 1600 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1601 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1602 1603 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1604 interrupt-names = "msi"; 1605 #interrupt-cells = <1>; 1606 interrupt-map-mask = <0 0 0 0x7>; 1607 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1608 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1609 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1610 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1611 1612 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1613 <&gcc GCC_PCIE_2_AUX_CLK>, 1614 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1615 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1616 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1617 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1618 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1619 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1620 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1621 clock-names = "pipe", 1622 "aux", 1623 "cfg", 1624 "bus_master", 1625 "bus_slave", 1626 "slave_q2a", 1627 "ref", 1628 "tbu", 1629 "ddrss_sf_tbu"; 1630 1631 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1632 assigned-clock-rates = <19200000>; 1633 1634 iommus = <&apps_smmu 0x1d00 0x7f>; 1635 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1636 <0x100 &apps_smmu 0x1d01 0x1>; 1637 1638 resets = <&gcc GCC_PCIE_2_BCR>; 1639 reset-names = "pci"; 1640 1641 power-domains = <&gcc PCIE_2_GDSC>; 1642 1643 phys = <&pcie2_lane>; 1644 phy-names = "pciephy"; 1645 1646 perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; 1647 enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; 1648 1649 pinctrl-names = "default"; 1650 pinctrl-0 = <&pcie2_default_state>; 1651 1652 status = "disabled"; 1653 }; 1654 1655 pcie2_phy: phy@1c16000 { 1656 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1657 reg = <0 0x1c16000 0 0x1c0>; 1658 #address-cells = <2>; 1659 #size-cells = <2>; 1660 ranges; 1661 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1662 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1663 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1664 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1665 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1666 1667 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1668 reset-names = "phy"; 1669 1670 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1671 assigned-clock-rates = <100000000>; 1672 1673 status = "disabled"; 1674 1675 pcie2_lane: lanes@1c16200 { 1676 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1677 <0 0x1c16400 0 0x200>, /* rx0 */ 1678 <0 0x1c16a00 0 0x1f0>, /* pcs */ 1679 <0 0x1c16600 0 0x170>, /* tx1 */ 1680 <0 0x1c16800 0 0x200>, /* rx1 */ 1681 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1682 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1683 clock-names = "pipe0"; 1684 1685 #phy-cells = <0>; 1686 clock-output-names = "pcie_2_pipe_clk"; 1687 }; 1688 }; 1689 1690 ufs_mem_hc: ufshc@1d84000 { 1691 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1692 "jedec,ufs-2.0"; 1693 reg = <0 0x01d84000 0 0x3000>; 1694 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1695 phys = <&ufs_mem_phy_lanes>; 1696 phy-names = "ufsphy"; 1697 lanes-per-direction = <2>; 1698 #reset-cells = <1>; 1699 resets = <&gcc GCC_UFS_PHY_BCR>; 1700 reset-names = "rst"; 1701 1702 power-domains = <&gcc UFS_PHY_GDSC>; 1703 1704 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1705 1706 clock-names = 1707 "core_clk", 1708 "bus_aggr_clk", 1709 "iface_clk", 1710 "core_clk_unipro", 1711 "ref_clk", 1712 "tx_lane0_sync_clk", 1713 "rx_lane0_sync_clk", 1714 "rx_lane1_sync_clk"; 1715 clocks = 1716 <&gcc GCC_UFS_PHY_AXI_CLK>, 1717 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1718 <&gcc GCC_UFS_PHY_AHB_CLK>, 1719 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1720 <&rpmhcc RPMH_CXO_CLK>, 1721 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1722 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1723 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1724 freq-table-hz = 1725 <37500000 300000000>, 1726 <0 0>, 1727 <0 0>, 1728 <37500000 300000000>, 1729 <0 0>, 1730 <0 0>, 1731 <0 0>, 1732 <0 0>; 1733 1734 status = "disabled"; 1735 }; 1736 1737 ufs_mem_phy: phy@1d87000 { 1738 compatible = "qcom,sm8250-qmp-ufs-phy"; 1739 reg = <0 0x01d87000 0 0x1c0>; 1740 #address-cells = <2>; 1741 #size-cells = <2>; 1742 ranges; 1743 clock-names = "ref", 1744 "ref_aux"; 1745 clocks = <&rpmhcc RPMH_CXO_CLK>, 1746 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1747 1748 resets = <&ufs_mem_hc 0>; 1749 reset-names = "ufsphy"; 1750 status = "disabled"; 1751 1752 ufs_mem_phy_lanes: lanes@1d87400 { 1753 reg = <0 0x01d87400 0 0x108>, 1754 <0 0x01d87600 0 0x1e0>, 1755 <0 0x01d87c00 0 0x1dc>, 1756 <0 0x01d87800 0 0x108>, 1757 <0 0x01d87a00 0 0x1e0>; 1758 #phy-cells = <0>; 1759 }; 1760 }; 1761 1762 ipa_virt: interconnect@1e00000 { 1763 compatible = "qcom,sm8250-ipa-virt"; 1764 reg = <0 0x01e00000 0 0x1000>; 1765 #interconnect-cells = <1>; 1766 qcom,bcm-voters = <&apps_bcm_voter>; 1767 }; 1768 1769 tcsr_mutex: hwlock@1f40000 { 1770 compatible = "qcom,tcsr-mutex"; 1771 reg = <0x0 0x01f40000 0x0 0x40000>; 1772 #hwlock-cells = <1>; 1773 }; 1774 1775 wsamacro: codec@3240000 { 1776 compatible = "qcom,sm8250-lpass-wsa-macro"; 1777 reg = <0 0x03240000 0 0x1000>; 1778 clocks = <&audiocc 1>, 1779 <&audiocc 0>, 1780 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1781 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1782 <&aoncc 0>, 1783 <&vamacro>; 1784 1785 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1786 1787 #clock-cells = <0>; 1788 clock-frequency = <9600000>; 1789 clock-output-names = "mclk"; 1790 #sound-dai-cells = <1>; 1791 1792 pinctrl-names = "default"; 1793 pinctrl-0 = <&wsa_swr_active>; 1794 }; 1795 1796 swr0: soundwire-controller@3250000 { 1797 reg = <0 0x03250000 0 0x2000>; 1798 compatible = "qcom,soundwire-v1.5.1"; 1799 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1800 clocks = <&wsamacro>; 1801 clock-names = "iface"; 1802 1803 qcom,din-ports = <2>; 1804 qcom,dout-ports = <6>; 1805 1806 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1807 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1808 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1809 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1810 1811 #sound-dai-cells = <1>; 1812 #address-cells = <2>; 1813 #size-cells = <0>; 1814 }; 1815 1816 audiocc: clock-controller@3300000 { 1817 compatible = "qcom,sm8250-lpass-audiocc"; 1818 reg = <0 0x03300000 0 0x30000>; 1819 #clock-cells = <1>; 1820 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1821 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1822 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1823 clock-names = "core", "audio", "bus"; 1824 }; 1825 1826 vamacro: codec@3370000 { 1827 compatible = "qcom,sm8250-lpass-va-macro"; 1828 reg = <0 0x03370000 0 0x1000>; 1829 clocks = <&aoncc 0>, 1830 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1831 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1832 1833 clock-names = "mclk", "macro", "dcodec"; 1834 1835 #clock-cells = <0>; 1836 clock-frequency = <9600000>; 1837 clock-output-names = "fsgen"; 1838 #sound-dai-cells = <1>; 1839 }; 1840 1841 aoncc: clock-controller@3380000 { 1842 compatible = "qcom,sm8250-lpass-aoncc"; 1843 reg = <0 0x03380000 0 0x40000>; 1844 #clock-cells = <1>; 1845 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1846 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1847 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1848 clock-names = "core", "audio", "bus"; 1849 }; 1850 1851 lpass_tlmm: pinctrl@33c0000{ 1852 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 1853 reg = <0 0x033c0000 0x0 0x20000>, 1854 <0 0x03550000 0x0 0x10000>; 1855 gpio-controller; 1856 #gpio-cells = <2>; 1857 gpio-ranges = <&lpass_tlmm 0 0 14>; 1858 1859 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1860 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1861 clock-names = "core", "audio"; 1862 1863 wsa_swr_active: wsa-swr-active-pins { 1864 clk { 1865 pins = "gpio10"; 1866 function = "wsa_swr_clk"; 1867 drive-strength = <2>; 1868 slew-rate = <1>; 1869 bias-disable; 1870 }; 1871 1872 data { 1873 pins = "gpio11"; 1874 function = "wsa_swr_data"; 1875 drive-strength = <2>; 1876 slew-rate = <1>; 1877 bias-bus-hold; 1878 1879 }; 1880 }; 1881 1882 wsa_swr_sleep: wsa-swr-sleep-pins { 1883 clk { 1884 pins = "gpio10"; 1885 function = "wsa_swr_clk"; 1886 drive-strength = <2>; 1887 input-enable; 1888 bias-pull-down; 1889 }; 1890 1891 data { 1892 pins = "gpio11"; 1893 function = "wsa_swr_data"; 1894 drive-strength = <2>; 1895 input-enable; 1896 bias-pull-down; 1897 1898 }; 1899 }; 1900 1901 dmic01_active: dmic01-active-pins { 1902 clk { 1903 pins = "gpio6"; 1904 function = "dmic1_clk"; 1905 drive-strength = <8>; 1906 output-high; 1907 }; 1908 data { 1909 pins = "gpio7"; 1910 function = "dmic1_data"; 1911 drive-strength = <8>; 1912 input-enable; 1913 }; 1914 }; 1915 1916 dmic01_sleep: dmic01-sleep-pins { 1917 clk { 1918 pins = "gpio6"; 1919 function = "dmic1_clk"; 1920 drive-strength = <2>; 1921 bias-disable; 1922 output-low; 1923 }; 1924 1925 data { 1926 pins = "gpio7"; 1927 function = "dmic1_data"; 1928 drive-strength = <2>; 1929 pull-down; 1930 input-enable; 1931 }; 1932 }; 1933 }; 1934 1935 gpu: gpu@3d00000 { 1936 compatible = "qcom,adreno-650.2", 1937 "qcom,adreno"; 1938 #stream-id-cells = <16>; 1939 1940 reg = <0 0x03d00000 0 0x40000>; 1941 reg-names = "kgsl_3d0_reg_memory"; 1942 1943 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1944 1945 iommus = <&adreno_smmu 0 0x401>; 1946 1947 operating-points-v2 = <&gpu_opp_table>; 1948 1949 qcom,gmu = <&gmu>; 1950 1951 status = "disabled"; 1952 1953 zap-shader { 1954 memory-region = <&gpu_mem>; 1955 }; 1956 1957 /* note: downstream checks gpu binning for 670 Mhz */ 1958 gpu_opp_table: opp-table { 1959 compatible = "operating-points-v2"; 1960 1961 opp-670000000 { 1962 opp-hz = /bits/ 64 <670000000>; 1963 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1964 }; 1965 1966 opp-587000000 { 1967 opp-hz = /bits/ 64 <587000000>; 1968 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1969 }; 1970 1971 opp-525000000 { 1972 opp-hz = /bits/ 64 <525000000>; 1973 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1974 }; 1975 1976 opp-490000000 { 1977 opp-hz = /bits/ 64 <490000000>; 1978 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1979 }; 1980 1981 opp-441600000 { 1982 opp-hz = /bits/ 64 <441600000>; 1983 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1984 }; 1985 1986 opp-400000000 { 1987 opp-hz = /bits/ 64 <400000000>; 1988 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1989 }; 1990 1991 opp-305000000 { 1992 opp-hz = /bits/ 64 <305000000>; 1993 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1994 }; 1995 }; 1996 }; 1997 1998 gmu: gmu@3d6a000 { 1999 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2000 2001 reg = <0 0x03d6a000 0 0x30000>, 2002 <0 0x3de0000 0 0x10000>, 2003 <0 0xb290000 0 0x10000>, 2004 <0 0xb490000 0 0x10000>; 2005 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2006 2007 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2009 interrupt-names = "hfi", "gmu"; 2010 2011 clocks = <&gpucc GPU_CC_AHB_CLK>, 2012 <&gpucc GPU_CC_CX_GMU_CLK>, 2013 <&gpucc GPU_CC_CXO_CLK>, 2014 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2015 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2016 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2017 2018 power-domains = <&gpucc GPU_CX_GDSC>, 2019 <&gpucc GPU_GX_GDSC>; 2020 power-domain-names = "cx", "gx"; 2021 2022 iommus = <&adreno_smmu 5 0x400>; 2023 2024 operating-points-v2 = <&gmu_opp_table>; 2025 2026 status = "disabled"; 2027 2028 gmu_opp_table: opp-table { 2029 compatible = "operating-points-v2"; 2030 2031 opp-200000000 { 2032 opp-hz = /bits/ 64 <200000000>; 2033 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2034 }; 2035 }; 2036 }; 2037 2038 gpucc: clock-controller@3d90000 { 2039 compatible = "qcom,sm8250-gpucc"; 2040 reg = <0 0x03d90000 0 0x9000>; 2041 clocks = <&rpmhcc RPMH_CXO_CLK>, 2042 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2043 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2044 clock-names = "bi_tcxo", 2045 "gcc_gpu_gpll0_clk_src", 2046 "gcc_gpu_gpll0_div_clk_src"; 2047 #clock-cells = <1>; 2048 #reset-cells = <1>; 2049 #power-domain-cells = <1>; 2050 }; 2051 2052 adreno_smmu: iommu@3da0000 { 2053 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2054 reg = <0 0x03da0000 0 0x10000>; 2055 #iommu-cells = <2>; 2056 #global-interrupts = <2>; 2057 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2067 clocks = <&gpucc GPU_CC_AHB_CLK>, 2068 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2069 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2070 clock-names = "ahb", "bus", "iface"; 2071 2072 power-domains = <&gpucc GPU_CX_GDSC>; 2073 }; 2074 2075 slpi: remoteproc@5c00000 { 2076 compatible = "qcom,sm8250-slpi-pas"; 2077 reg = <0 0x05c00000 0 0x4000>; 2078 2079 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2080 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2081 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2082 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2083 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2084 interrupt-names = "wdog", "fatal", "ready", 2085 "handover", "stop-ack"; 2086 2087 clocks = <&rpmhcc RPMH_CXO_CLK>; 2088 clock-names = "xo"; 2089 2090 power-domains = <&rpmhpd SM8250_LCX>, 2091 <&rpmhpd SM8250_LMX>; 2092 power-domain-names = "lcx", "lmx"; 2093 2094 memory-region = <&slpi_mem>; 2095 2096 qcom,qmp = <&aoss_qmp>; 2097 2098 qcom,smem-states = <&smp2p_slpi_out 0>; 2099 qcom,smem-state-names = "stop"; 2100 2101 status = "disabled"; 2102 2103 glink-edge { 2104 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2105 IPCC_MPROC_SIGNAL_GLINK_QMP 2106 IRQ_TYPE_EDGE_RISING>; 2107 mboxes = <&ipcc IPCC_CLIENT_SLPI 2108 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2109 2110 label = "slpi"; 2111 qcom,remote-pid = <3>; 2112 2113 fastrpc { 2114 compatible = "qcom,fastrpc"; 2115 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2116 label = "sdsp"; 2117 #address-cells = <1>; 2118 #size-cells = <0>; 2119 2120 compute-cb@1 { 2121 compatible = "qcom,fastrpc-compute-cb"; 2122 reg = <1>; 2123 iommus = <&apps_smmu 0x0541 0x0>; 2124 }; 2125 2126 compute-cb@2 { 2127 compatible = "qcom,fastrpc-compute-cb"; 2128 reg = <2>; 2129 iommus = <&apps_smmu 0x0542 0x0>; 2130 }; 2131 2132 compute-cb@3 { 2133 compatible = "qcom,fastrpc-compute-cb"; 2134 reg = <3>; 2135 iommus = <&apps_smmu 0x0543 0x0>; 2136 /* note: shared-cb = <4> in downstream */ 2137 }; 2138 }; 2139 }; 2140 }; 2141 2142 cdsp: remoteproc@8300000 { 2143 compatible = "qcom,sm8250-cdsp-pas"; 2144 reg = <0 0x08300000 0 0x10000>; 2145 2146 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2147 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2148 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2149 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2150 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2151 interrupt-names = "wdog", "fatal", "ready", 2152 "handover", "stop-ack"; 2153 2154 clocks = <&rpmhcc RPMH_CXO_CLK>; 2155 clock-names = "xo"; 2156 2157 power-domains = <&rpmhpd SM8250_CX>; 2158 2159 memory-region = <&cdsp_mem>; 2160 2161 qcom,qmp = <&aoss_qmp>; 2162 2163 qcom,smem-states = <&smp2p_cdsp_out 0>; 2164 qcom,smem-state-names = "stop"; 2165 2166 status = "disabled"; 2167 2168 glink-edge { 2169 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2170 IPCC_MPROC_SIGNAL_GLINK_QMP 2171 IRQ_TYPE_EDGE_RISING>; 2172 mboxes = <&ipcc IPCC_CLIENT_CDSP 2173 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2174 2175 label = "cdsp"; 2176 qcom,remote-pid = <5>; 2177 2178 fastrpc { 2179 compatible = "qcom,fastrpc"; 2180 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2181 label = "cdsp"; 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 2185 compute-cb@1 { 2186 compatible = "qcom,fastrpc-compute-cb"; 2187 reg = <1>; 2188 iommus = <&apps_smmu 0x1001 0x0460>; 2189 }; 2190 2191 compute-cb@2 { 2192 compatible = "qcom,fastrpc-compute-cb"; 2193 reg = <2>; 2194 iommus = <&apps_smmu 0x1002 0x0460>; 2195 }; 2196 2197 compute-cb@3 { 2198 compatible = "qcom,fastrpc-compute-cb"; 2199 reg = <3>; 2200 iommus = <&apps_smmu 0x1003 0x0460>; 2201 }; 2202 2203 compute-cb@4 { 2204 compatible = "qcom,fastrpc-compute-cb"; 2205 reg = <4>; 2206 iommus = <&apps_smmu 0x1004 0x0460>; 2207 }; 2208 2209 compute-cb@5 { 2210 compatible = "qcom,fastrpc-compute-cb"; 2211 reg = <5>; 2212 iommus = <&apps_smmu 0x1005 0x0460>; 2213 }; 2214 2215 compute-cb@6 { 2216 compatible = "qcom,fastrpc-compute-cb"; 2217 reg = <6>; 2218 iommus = <&apps_smmu 0x1006 0x0460>; 2219 }; 2220 2221 compute-cb@7 { 2222 compatible = "qcom,fastrpc-compute-cb"; 2223 reg = <7>; 2224 iommus = <&apps_smmu 0x1007 0x0460>; 2225 }; 2226 2227 compute-cb@8 { 2228 compatible = "qcom,fastrpc-compute-cb"; 2229 reg = <8>; 2230 iommus = <&apps_smmu 0x1008 0x0460>; 2231 }; 2232 2233 /* note: secure cb9 in downstream */ 2234 }; 2235 }; 2236 }; 2237 2238 sound: sound { 2239 }; 2240 2241 usb_1_hsphy: phy@88e3000 { 2242 compatible = "qcom,sm8250-usb-hs-phy", 2243 "qcom,usb-snps-hs-7nm-phy"; 2244 reg = <0 0x088e3000 0 0x400>; 2245 status = "disabled"; 2246 #phy-cells = <0>; 2247 2248 clocks = <&rpmhcc RPMH_CXO_CLK>; 2249 clock-names = "ref"; 2250 2251 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2252 }; 2253 2254 usb_2_hsphy: phy@88e4000 { 2255 compatible = "qcom,sm8250-usb-hs-phy", 2256 "qcom,usb-snps-hs-7nm-phy"; 2257 reg = <0 0x088e4000 0 0x400>; 2258 status = "disabled"; 2259 #phy-cells = <0>; 2260 2261 clocks = <&rpmhcc RPMH_CXO_CLK>; 2262 clock-names = "ref"; 2263 2264 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2265 }; 2266 2267 usb_1_qmpphy: phy@88e9000 { 2268 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2269 reg = <0 0x088e9000 0 0x200>, 2270 <0 0x088e8000 0 0x40>, 2271 <0 0x088ea000 0 0x200>; 2272 status = "disabled"; 2273 #address-cells = <2>; 2274 #size-cells = <2>; 2275 ranges; 2276 2277 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2278 <&rpmhcc RPMH_CXO_CLK>, 2279 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2280 clock-names = "aux", "ref_clk_src", "com_aux"; 2281 2282 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2283 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2284 reset-names = "phy", "common"; 2285 2286 usb_1_ssphy: usb3-phy@88e9200 { 2287 reg = <0 0x088e9200 0 0x200>, 2288 <0 0x088e9400 0 0x200>, 2289 <0 0x088e9c00 0 0x400>, 2290 <0 0x088e9600 0 0x200>, 2291 <0 0x088e9800 0 0x200>, 2292 <0 0x088e9a00 0 0x100>; 2293 #clock-cells = <0>; 2294 #phy-cells = <0>; 2295 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2296 clock-names = "pipe0"; 2297 clock-output-names = "usb3_phy_pipe_clk_src"; 2298 }; 2299 2300 dp_phy: dp-phy@88ea200 { 2301 reg = <0 0x088ea200 0 0x200>, 2302 <0 0x088ea400 0 0x200>, 2303 <0 0x088eac00 0 0x400>, 2304 <0 0x088ea600 0 0x200>, 2305 <0 0x088ea800 0 0x200>, 2306 <0 0x088eaa00 0 0x100>; 2307 #phy-cells = <0>; 2308 #clock-cells = <1>; 2309 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2310 clock-names = "pipe0"; 2311 clock-output-names = "usb3_phy_pipe_clk_src"; 2312 }; 2313 }; 2314 2315 usb_2_qmpphy: phy@88eb000 { 2316 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2317 reg = <0 0x088eb000 0 0x200>; 2318 status = "disabled"; 2319 #address-cells = <2>; 2320 #size-cells = <2>; 2321 ranges; 2322 2323 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2324 <&rpmhcc RPMH_CXO_CLK>, 2325 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2326 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2327 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2328 2329 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2330 <&gcc GCC_USB3_PHY_SEC_BCR>; 2331 reset-names = "phy", "common"; 2332 2333 usb_2_ssphy: lanes@88eb200 { 2334 reg = <0 0x088eb200 0 0x200>, 2335 <0 0x088eb400 0 0x200>, 2336 <0 0x088eb800 0 0x800>; 2337 #clock-cells = <0>; 2338 #phy-cells = <0>; 2339 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2340 clock-names = "pipe0"; 2341 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2342 }; 2343 }; 2344 2345 sdhc_2: sdhci@8804000 { 2346 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2347 reg = <0 0x08804000 0 0x1000>; 2348 2349 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2351 interrupt-names = "hc_irq", "pwr_irq"; 2352 2353 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2354 <&gcc GCC_SDCC2_APPS_CLK>, 2355 <&rpmhcc RPMH_CXO_CLK>; 2356 clock-names = "iface", "core", "xo"; 2357 iommus = <&apps_smmu 0x4a0 0x0>; 2358 qcom,dll-config = <0x0007642c>; 2359 qcom,ddr-config = <0x80040868>; 2360 power-domains = <&rpmhpd SM8250_CX>; 2361 operating-points-v2 = <&sdhc2_opp_table>; 2362 2363 status = "disabled"; 2364 2365 sdhc2_opp_table: sdhc2-opp-table { 2366 compatible = "operating-points-v2"; 2367 2368 opp-19200000 { 2369 opp-hz = /bits/ 64 <19200000>; 2370 required-opps = <&rpmhpd_opp_min_svs>; 2371 }; 2372 2373 opp-50000000 { 2374 opp-hz = /bits/ 64 <50000000>; 2375 required-opps = <&rpmhpd_opp_low_svs>; 2376 }; 2377 2378 opp-100000000 { 2379 opp-hz = /bits/ 64 <100000000>; 2380 required-opps = <&rpmhpd_opp_svs>; 2381 }; 2382 2383 opp-202000000 { 2384 opp-hz = /bits/ 64 <202000000>; 2385 required-opps = <&rpmhpd_opp_svs_l1>; 2386 }; 2387 }; 2388 }; 2389 2390 dc_noc: interconnect@90c0000 { 2391 compatible = "qcom,sm8250-dc-noc"; 2392 reg = <0 0x090c0000 0 0x4200>; 2393 #interconnect-cells = <1>; 2394 qcom,bcm-voters = <&apps_bcm_voter>; 2395 }; 2396 2397 gem_noc: interconnect@9100000 { 2398 compatible = "qcom,sm8250-gem-noc"; 2399 reg = <0 0x09100000 0 0xb4000>; 2400 #interconnect-cells = <1>; 2401 qcom,bcm-voters = <&apps_bcm_voter>; 2402 }; 2403 2404 npu_noc: interconnect@9990000 { 2405 compatible = "qcom,sm8250-npu-noc"; 2406 reg = <0 0x09990000 0 0x1600>; 2407 #interconnect-cells = <1>; 2408 qcom,bcm-voters = <&apps_bcm_voter>; 2409 }; 2410 2411 usb_1: usb@a6f8800 { 2412 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2413 reg = <0 0x0a6f8800 0 0x400>; 2414 status = "disabled"; 2415 #address-cells = <2>; 2416 #size-cells = <2>; 2417 ranges; 2418 dma-ranges; 2419 2420 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2421 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2422 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2423 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2424 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2425 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2426 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2427 "sleep", "xo"; 2428 2429 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2430 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2431 assigned-clock-rates = <19200000>, <200000000>; 2432 2433 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2434 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2435 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2436 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2437 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2438 "dm_hs_phy_irq", "ss_phy_irq"; 2439 2440 power-domains = <&gcc USB30_PRIM_GDSC>; 2441 2442 resets = <&gcc GCC_USB30_PRIM_BCR>; 2443 2444 usb_1_dwc3: usb@a600000 { 2445 compatible = "snps,dwc3"; 2446 reg = <0 0x0a600000 0 0xcd00>; 2447 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2448 iommus = <&apps_smmu 0x0 0x0>; 2449 snps,dis_u2_susphy_quirk; 2450 snps,dis_enblslpm_quirk; 2451 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2452 phy-names = "usb2-phy", "usb3-phy"; 2453 }; 2454 }; 2455 2456 system-cache-controller@9200000 { 2457 compatible = "qcom,sm8250-llcc"; 2458 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2459 reg-names = "llcc_base", "llcc_broadcast_base"; 2460 }; 2461 2462 usb_2: usb@a8f8800 { 2463 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2464 reg = <0 0x0a8f8800 0 0x400>; 2465 status = "disabled"; 2466 #address-cells = <2>; 2467 #size-cells = <2>; 2468 ranges; 2469 dma-ranges; 2470 2471 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2472 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2473 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2474 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2475 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2476 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2477 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2478 "sleep", "xo"; 2479 2480 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2481 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2482 assigned-clock-rates = <19200000>, <200000000>; 2483 2484 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2485 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2486 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2487 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2488 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2489 "dm_hs_phy_irq", "ss_phy_irq"; 2490 2491 power-domains = <&gcc USB30_SEC_GDSC>; 2492 2493 resets = <&gcc GCC_USB30_SEC_BCR>; 2494 2495 usb_2_dwc3: usb@a800000 { 2496 compatible = "snps,dwc3"; 2497 reg = <0 0x0a800000 0 0xcd00>; 2498 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2499 iommus = <&apps_smmu 0x20 0>; 2500 snps,dis_u2_susphy_quirk; 2501 snps,dis_enblslpm_quirk; 2502 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2503 phy-names = "usb2-phy", "usb3-phy"; 2504 }; 2505 }; 2506 2507 venus: video-codec@aa00000 { 2508 compatible = "qcom,sm8250-venus"; 2509 reg = <0 0x0aa00000 0 0x100000>; 2510 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2511 power-domains = <&videocc MVS0C_GDSC>, 2512 <&videocc MVS0_GDSC>, 2513 <&rpmhpd SM8250_MX>; 2514 power-domain-names = "venus", "vcodec0", "mx"; 2515 operating-points-v2 = <&venus_opp_table>; 2516 2517 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2518 <&videocc VIDEO_CC_MVS0C_CLK>, 2519 <&videocc VIDEO_CC_MVS0_CLK>; 2520 clock-names = "iface", "core", "vcodec0_core"; 2521 2522 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2523 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2524 interconnect-names = "cpu-cfg", "video-mem"; 2525 2526 iommus = <&apps_smmu 0x2100 0x0400>; 2527 memory-region = <&video_mem>; 2528 2529 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2530 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2531 reset-names = "bus", "core"; 2532 2533 status = "disabled"; 2534 2535 video-decoder { 2536 compatible = "venus-decoder"; 2537 }; 2538 2539 video-encoder { 2540 compatible = "venus-encoder"; 2541 }; 2542 2543 venus_opp_table: venus-opp-table { 2544 compatible = "operating-points-v2"; 2545 2546 opp-720000000 { 2547 opp-hz = /bits/ 64 <720000000>; 2548 required-opps = <&rpmhpd_opp_low_svs>; 2549 }; 2550 2551 opp-1014000000 { 2552 opp-hz = /bits/ 64 <1014000000>; 2553 required-opps = <&rpmhpd_opp_svs>; 2554 }; 2555 2556 opp-1098000000 { 2557 opp-hz = /bits/ 64 <1098000000>; 2558 required-opps = <&rpmhpd_opp_svs_l1>; 2559 }; 2560 2561 opp-1332000000 { 2562 opp-hz = /bits/ 64 <1332000000>; 2563 required-opps = <&rpmhpd_opp_nom>; 2564 }; 2565 }; 2566 }; 2567 2568 videocc: clock-controller@abf0000 { 2569 compatible = "qcom,sm8250-videocc"; 2570 reg = <0 0x0abf0000 0 0x10000>; 2571 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2572 <&rpmhcc RPMH_CXO_CLK>, 2573 <&rpmhcc RPMH_CXO_CLK_A>; 2574 mmcx-supply = <&mmcx_reg>; 2575 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 2576 #clock-cells = <1>; 2577 #reset-cells = <1>; 2578 #power-domain-cells = <1>; 2579 }; 2580 2581 mdss: mdss@ae00000 { 2582 compatible = "qcom,sm8250-mdss"; 2583 reg = <0 0x0ae00000 0 0x1000>; 2584 reg-names = "mdss"; 2585 2586 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 2587 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2588 interconnect-names = "mdp0-mem", "mdp1-mem"; 2589 2590 power-domains = <&dispcc MDSS_GDSC>; 2591 2592 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2593 <&gcc GCC_DISP_SF_AXI_CLK>, 2594 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2595 clock-names = "iface", "nrt_bus", "core"; 2596 2597 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2598 assigned-clock-rates = <460000000>; 2599 2600 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2601 interrupt-controller; 2602 #interrupt-cells = <1>; 2603 2604 iommus = <&apps_smmu 0x820 0x402>; 2605 2606 status = "disabled"; 2607 2608 #address-cells = <2>; 2609 #size-cells = <2>; 2610 ranges; 2611 2612 mdss_mdp: mdp@ae01000 { 2613 compatible = "qcom,sm8250-dpu"; 2614 reg = <0 0x0ae01000 0 0x8f000>, 2615 <0 0x0aeb0000 0 0x2008>; 2616 reg-names = "mdp", "vbif"; 2617 2618 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2619 <&gcc GCC_DISP_HF_AXI_CLK>, 2620 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2621 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2622 clock-names = "iface", "bus", "core", "vsync"; 2623 2624 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2625 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2626 assigned-clock-rates = <460000000>, 2627 <19200000>; 2628 2629 operating-points-v2 = <&mdp_opp_table>; 2630 power-domains = <&rpmhpd SM8250_MMCX>; 2631 2632 interrupt-parent = <&mdss>; 2633 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2634 2635 ports { 2636 #address-cells = <1>; 2637 #size-cells = <0>; 2638 2639 port@0 { 2640 reg = <0>; 2641 dpu_intf1_out: endpoint { 2642 remote-endpoint = <&dsi0_in>; 2643 }; 2644 }; 2645 2646 port@1 { 2647 reg = <1>; 2648 dpu_intf2_out: endpoint { 2649 remote-endpoint = <&dsi1_in>; 2650 }; 2651 }; 2652 }; 2653 2654 mdp_opp_table: mdp-opp-table { 2655 compatible = "operating-points-v2"; 2656 2657 opp-200000000 { 2658 opp-hz = /bits/ 64 <200000000>; 2659 required-opps = <&rpmhpd_opp_low_svs>; 2660 }; 2661 2662 opp-300000000 { 2663 opp-hz = /bits/ 64 <300000000>; 2664 required-opps = <&rpmhpd_opp_svs>; 2665 }; 2666 2667 opp-345000000 { 2668 opp-hz = /bits/ 64 <345000000>; 2669 required-opps = <&rpmhpd_opp_svs_l1>; 2670 }; 2671 2672 opp-460000000 { 2673 opp-hz = /bits/ 64 <460000000>; 2674 required-opps = <&rpmhpd_opp_nom>; 2675 }; 2676 }; 2677 }; 2678 2679 dsi0: dsi@ae94000 { 2680 compatible = "qcom,mdss-dsi-ctrl"; 2681 reg = <0 0x0ae94000 0 0x400>; 2682 reg-names = "dsi_ctrl"; 2683 2684 interrupt-parent = <&mdss>; 2685 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2686 2687 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2688 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2689 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2690 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2691 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2692 <&gcc GCC_DISP_HF_AXI_CLK>; 2693 clock-names = "byte", 2694 "byte_intf", 2695 "pixel", 2696 "core", 2697 "iface", 2698 "bus"; 2699 2700 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2701 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 2702 2703 operating-points-v2 = <&dsi_opp_table>; 2704 power-domains = <&rpmhpd SM8250_MMCX>; 2705 2706 phys = <&dsi0_phy>; 2707 phy-names = "dsi"; 2708 2709 status = "disabled"; 2710 2711 #address-cells = <1>; 2712 #size-cells = <0>; 2713 2714 ports { 2715 #address-cells = <1>; 2716 #size-cells = <0>; 2717 2718 port@0 { 2719 reg = <0>; 2720 dsi0_in: endpoint { 2721 remote-endpoint = <&dpu_intf1_out>; 2722 }; 2723 }; 2724 2725 port@1 { 2726 reg = <1>; 2727 dsi0_out: endpoint { 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 dsi0_phy: dsi-phy@ae94400 { 2734 compatible = "qcom,dsi-phy-7nm"; 2735 reg = <0 0x0ae94400 0 0x200>, 2736 <0 0x0ae94600 0 0x280>, 2737 <0 0x0ae94900 0 0x260>; 2738 reg-names = "dsi_phy", 2739 "dsi_phy_lane", 2740 "dsi_pll"; 2741 2742 #clock-cells = <1>; 2743 #phy-cells = <0>; 2744 2745 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2746 <&rpmhcc RPMH_CXO_CLK>; 2747 clock-names = "iface", "ref"; 2748 2749 status = "disabled"; 2750 }; 2751 2752 dsi1: dsi@ae96000 { 2753 compatible = "qcom,mdss-dsi-ctrl"; 2754 reg = <0 0x0ae96000 0 0x400>; 2755 reg-names = "dsi_ctrl"; 2756 2757 interrupt-parent = <&mdss>; 2758 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2759 2760 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2761 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2762 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2763 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2764 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2765 <&gcc GCC_DISP_HF_AXI_CLK>; 2766 clock-names = "byte", 2767 "byte_intf", 2768 "pixel", 2769 "core", 2770 "iface", 2771 "bus"; 2772 2773 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2774 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 2775 2776 operating-points-v2 = <&dsi_opp_table>; 2777 power-domains = <&rpmhpd SM8250_MMCX>; 2778 2779 phys = <&dsi1_phy>; 2780 phy-names = "dsi"; 2781 2782 status = "disabled"; 2783 2784 #address-cells = <1>; 2785 #size-cells = <0>; 2786 2787 ports { 2788 #address-cells = <1>; 2789 #size-cells = <0>; 2790 2791 port@0 { 2792 reg = <0>; 2793 dsi1_in: endpoint { 2794 remote-endpoint = <&dpu_intf2_out>; 2795 }; 2796 }; 2797 2798 port@1 { 2799 reg = <1>; 2800 dsi1_out: endpoint { 2801 }; 2802 }; 2803 }; 2804 }; 2805 2806 dsi1_phy: dsi-phy@ae96400 { 2807 compatible = "qcom,dsi-phy-7nm"; 2808 reg = <0 0x0ae96400 0 0x200>, 2809 <0 0x0ae96600 0 0x280>, 2810 <0 0x0ae96900 0 0x260>; 2811 reg-names = "dsi_phy", 2812 "dsi_phy_lane", 2813 "dsi_pll"; 2814 2815 #clock-cells = <1>; 2816 #phy-cells = <0>; 2817 2818 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2819 <&rpmhcc RPMH_CXO_CLK>; 2820 clock-names = "iface", "ref"; 2821 2822 status = "disabled"; 2823 2824 dsi_opp_table: dsi-opp-table { 2825 compatible = "operating-points-v2"; 2826 2827 opp-187500000 { 2828 opp-hz = /bits/ 64 <187500000>; 2829 required-opps = <&rpmhpd_opp_low_svs>; 2830 }; 2831 2832 opp-300000000 { 2833 opp-hz = /bits/ 64 <300000000>; 2834 required-opps = <&rpmhpd_opp_svs>; 2835 }; 2836 2837 opp-358000000 { 2838 opp-hz = /bits/ 64 <358000000>; 2839 required-opps = <&rpmhpd_opp_svs_l1>; 2840 }; 2841 }; 2842 }; 2843 }; 2844 2845 dispcc: clock-controller@af00000 { 2846 compatible = "qcom,sm8250-dispcc"; 2847 reg = <0 0x0af00000 0 0x10000>; 2848 mmcx-supply = <&mmcx_reg>; 2849 clocks = <&rpmhcc RPMH_CXO_CLK>, 2850 <&dsi0_phy 0>, 2851 <&dsi0_phy 1>, 2852 <&dsi1_phy 0>, 2853 <&dsi1_phy 1>, 2854 <&dp_phy 0>, 2855 <&dp_phy 1>; 2856 clock-names = "bi_tcxo", 2857 "dsi0_phy_pll_out_byteclk", 2858 "dsi0_phy_pll_out_dsiclk", 2859 "dsi1_phy_pll_out_byteclk", 2860 "dsi1_phy_pll_out_dsiclk", 2861 "dp_phy_pll_link_clk", 2862 "dp_phy_pll_vco_div_clk"; 2863 #clock-cells = <1>; 2864 #reset-cells = <1>; 2865 #power-domain-cells = <1>; 2866 }; 2867 2868 pdc: interrupt-controller@b220000 { 2869 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 2870 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2871 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2872 <125 63 1>, <126 716 12>; 2873 #interrupt-cells = <2>; 2874 interrupt-parent = <&intc>; 2875 interrupt-controller; 2876 }; 2877 2878 tsens0: thermal-sensor@c263000 { 2879 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2880 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2881 <0 0x0c222000 0 0x1ff>; /* SROT */ 2882 #qcom,sensors = <16>; 2883 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2885 interrupt-names = "uplow", "critical"; 2886 #thermal-sensor-cells = <1>; 2887 }; 2888 2889 tsens1: thermal-sensor@c265000 { 2890 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2891 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2892 <0 0x0c223000 0 0x1ff>; /* SROT */ 2893 #qcom,sensors = <9>; 2894 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2896 interrupt-names = "uplow", "critical"; 2897 #thermal-sensor-cells = <1>; 2898 }; 2899 2900 aoss_qmp: power-controller@c300000 { 2901 compatible = "qcom,sm8250-aoss-qmp"; 2902 reg = <0 0x0c300000 0 0x100000>; 2903 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2904 IPCC_MPROC_SIGNAL_GLINK_QMP 2905 IRQ_TYPE_EDGE_RISING>; 2906 mboxes = <&ipcc IPCC_CLIENT_AOP 2907 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2908 2909 #clock-cells = <0>; 2910 }; 2911 2912 spmi_bus: spmi@c440000 { 2913 compatible = "qcom,spmi-pmic-arb"; 2914 reg = <0x0 0x0c440000 0x0 0x0001100>, 2915 <0x0 0x0c600000 0x0 0x2000000>, 2916 <0x0 0x0e600000 0x0 0x0100000>, 2917 <0x0 0x0e700000 0x0 0x00a0000>, 2918 <0x0 0x0c40a000 0x0 0x0026000>; 2919 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2920 interrupt-names = "periph_irq"; 2921 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2922 qcom,ee = <0>; 2923 qcom,channel = <0>; 2924 #address-cells = <2>; 2925 #size-cells = <0>; 2926 interrupt-controller; 2927 #interrupt-cells = <4>; 2928 }; 2929 2930 tlmm: pinctrl@f100000 { 2931 compatible = "qcom,sm8250-pinctrl"; 2932 reg = <0 0x0f100000 0 0x300000>, 2933 <0 0x0f500000 0 0x300000>, 2934 <0 0x0f900000 0 0x300000>; 2935 reg-names = "west", "south", "north"; 2936 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2937 gpio-controller; 2938 #gpio-cells = <2>; 2939 interrupt-controller; 2940 #interrupt-cells = <2>; 2941 gpio-ranges = <&tlmm 0 0 181>; 2942 wakeup-parent = <&pdc>; 2943 2944 pri_mi2s_active: pri-mi2s-active { 2945 sclk { 2946 pins = "gpio138"; 2947 function = "mi2s0_sck"; 2948 drive-strength = <8>; 2949 bias-disable; 2950 }; 2951 2952 ws { 2953 pins = "gpio141"; 2954 function = "mi2s0_ws"; 2955 drive-strength = <8>; 2956 output-high; 2957 }; 2958 2959 data0 { 2960 pins = "gpio139"; 2961 function = "mi2s0_data0"; 2962 drive-strength = <8>; 2963 bias-disable; 2964 output-high; 2965 }; 2966 2967 data1 { 2968 pins = "gpio140"; 2969 function = "mi2s0_data1"; 2970 drive-strength = <8>; 2971 output-high; 2972 }; 2973 }; 2974 2975 qup_i2c0_default: qup-i2c0-default { 2976 mux { 2977 pins = "gpio28", "gpio29"; 2978 function = "qup0"; 2979 }; 2980 2981 config { 2982 pins = "gpio28", "gpio29"; 2983 drive-strength = <2>; 2984 bias-disable; 2985 }; 2986 }; 2987 2988 qup_i2c1_default: qup-i2c1-default { 2989 pinmux { 2990 pins = "gpio4", "gpio5"; 2991 function = "qup1"; 2992 }; 2993 2994 config { 2995 pins = "gpio4", "gpio5"; 2996 drive-strength = <2>; 2997 bias-disable; 2998 }; 2999 }; 3000 3001 qup_i2c2_default: qup-i2c2-default { 3002 mux { 3003 pins = "gpio115", "gpio116"; 3004 function = "qup2"; 3005 }; 3006 3007 config { 3008 pins = "gpio115", "gpio116"; 3009 drive-strength = <2>; 3010 bias-disable; 3011 }; 3012 }; 3013 3014 qup_i2c3_default: qup-i2c3-default { 3015 mux { 3016 pins = "gpio119", "gpio120"; 3017 function = "qup3"; 3018 }; 3019 3020 config { 3021 pins = "gpio119", "gpio120"; 3022 drive-strength = <2>; 3023 bias-disable; 3024 }; 3025 }; 3026 3027 qup_i2c4_default: qup-i2c4-default { 3028 mux { 3029 pins = "gpio8", "gpio9"; 3030 function = "qup4"; 3031 }; 3032 3033 config { 3034 pins = "gpio8", "gpio9"; 3035 drive-strength = <2>; 3036 bias-disable; 3037 }; 3038 }; 3039 3040 qup_i2c5_default: qup-i2c5-default { 3041 mux { 3042 pins = "gpio12", "gpio13"; 3043 function = "qup5"; 3044 }; 3045 3046 config { 3047 pins = "gpio12", "gpio13"; 3048 drive-strength = <2>; 3049 bias-disable; 3050 }; 3051 }; 3052 3053 qup_i2c6_default: qup-i2c6-default { 3054 mux { 3055 pins = "gpio16", "gpio17"; 3056 function = "qup6"; 3057 }; 3058 3059 config { 3060 pins = "gpio16", "gpio17"; 3061 drive-strength = <2>; 3062 bias-disable; 3063 }; 3064 }; 3065 3066 qup_i2c7_default: qup-i2c7-default { 3067 mux { 3068 pins = "gpio20", "gpio21"; 3069 function = "qup7"; 3070 }; 3071 3072 config { 3073 pins = "gpio20", "gpio21"; 3074 drive-strength = <2>; 3075 bias-disable; 3076 }; 3077 }; 3078 3079 qup_i2c8_default: qup-i2c8-default { 3080 mux { 3081 pins = "gpio24", "gpio25"; 3082 function = "qup8"; 3083 }; 3084 3085 config { 3086 pins = "gpio24", "gpio25"; 3087 drive-strength = <2>; 3088 bias-disable; 3089 }; 3090 }; 3091 3092 qup_i2c9_default: qup-i2c9-default { 3093 mux { 3094 pins = "gpio125", "gpio126"; 3095 function = "qup9"; 3096 }; 3097 3098 config { 3099 pins = "gpio125", "gpio126"; 3100 drive-strength = <2>; 3101 bias-disable; 3102 }; 3103 }; 3104 3105 qup_i2c10_default: qup-i2c10-default { 3106 mux { 3107 pins = "gpio129", "gpio130"; 3108 function = "qup10"; 3109 }; 3110 3111 config { 3112 pins = "gpio129", "gpio130"; 3113 drive-strength = <2>; 3114 bias-disable; 3115 }; 3116 }; 3117 3118 qup_i2c11_default: qup-i2c11-default { 3119 mux { 3120 pins = "gpio60", "gpio61"; 3121 function = "qup11"; 3122 }; 3123 3124 config { 3125 pins = "gpio60", "gpio61"; 3126 drive-strength = <2>; 3127 bias-disable; 3128 }; 3129 }; 3130 3131 qup_i2c12_default: qup-i2c12-default { 3132 mux { 3133 pins = "gpio32", "gpio33"; 3134 function = "qup12"; 3135 }; 3136 3137 config { 3138 pins = "gpio32", "gpio33"; 3139 drive-strength = <2>; 3140 bias-disable; 3141 }; 3142 }; 3143 3144 qup_i2c13_default: qup-i2c13-default { 3145 mux { 3146 pins = "gpio36", "gpio37"; 3147 function = "qup13"; 3148 }; 3149 3150 config { 3151 pins = "gpio36", "gpio37"; 3152 drive-strength = <2>; 3153 bias-disable; 3154 }; 3155 }; 3156 3157 qup_i2c14_default: qup-i2c14-default { 3158 mux { 3159 pins = "gpio40", "gpio41"; 3160 function = "qup14"; 3161 }; 3162 3163 config { 3164 pins = "gpio40", "gpio41"; 3165 drive-strength = <2>; 3166 bias-disable; 3167 }; 3168 }; 3169 3170 qup_i2c15_default: qup-i2c15-default { 3171 mux { 3172 pins = "gpio44", "gpio45"; 3173 function = "qup15"; 3174 }; 3175 3176 config { 3177 pins = "gpio44", "gpio45"; 3178 drive-strength = <2>; 3179 bias-disable; 3180 }; 3181 }; 3182 3183 qup_i2c16_default: qup-i2c16-default { 3184 mux { 3185 pins = "gpio48", "gpio49"; 3186 function = "qup16"; 3187 }; 3188 3189 config { 3190 pins = "gpio48", "gpio49"; 3191 drive-strength = <2>; 3192 bias-disable; 3193 }; 3194 }; 3195 3196 qup_i2c17_default: qup-i2c17-default { 3197 mux { 3198 pins = "gpio52", "gpio53"; 3199 function = "qup17"; 3200 }; 3201 3202 config { 3203 pins = "gpio52", "gpio53"; 3204 drive-strength = <2>; 3205 bias-disable; 3206 }; 3207 }; 3208 3209 qup_i2c18_default: qup-i2c18-default { 3210 mux { 3211 pins = "gpio56", "gpio57"; 3212 function = "qup18"; 3213 }; 3214 3215 config { 3216 pins = "gpio56", "gpio57"; 3217 drive-strength = <2>; 3218 bias-disable; 3219 }; 3220 }; 3221 3222 qup_i2c19_default: qup-i2c19-default { 3223 mux { 3224 pins = "gpio0", "gpio1"; 3225 function = "qup19"; 3226 }; 3227 3228 config { 3229 pins = "gpio0", "gpio1"; 3230 drive-strength = <2>; 3231 bias-disable; 3232 }; 3233 }; 3234 3235 qup_spi0_cs: qup-spi0-cs { 3236 pins = "gpio31"; 3237 function = "qup0"; 3238 }; 3239 3240 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3241 pins = "gpio31"; 3242 function = "gpio"; 3243 }; 3244 3245 qup_spi0_data_clk: qup-spi0-data-clk { 3246 pins = "gpio28", "gpio29", 3247 "gpio30"; 3248 function = "qup0"; 3249 }; 3250 3251 qup_spi1_cs: qup-spi1-cs { 3252 pins = "gpio7"; 3253 function = "qup1"; 3254 }; 3255 3256 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3257 pins = "gpio7"; 3258 function = "gpio"; 3259 }; 3260 3261 qup_spi1_data_clk: qup-spi1-data-clk { 3262 pins = "gpio4", "gpio5", 3263 "gpio6"; 3264 function = "qup1"; 3265 }; 3266 3267 qup_spi2_cs: qup-spi2-cs { 3268 pins = "gpio118"; 3269 function = "qup2"; 3270 }; 3271 3272 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3273 pins = "gpio118"; 3274 function = "gpio"; 3275 }; 3276 3277 qup_spi2_data_clk: qup-spi2-data-clk { 3278 pins = "gpio115", "gpio116", 3279 "gpio117"; 3280 function = "qup2"; 3281 }; 3282 3283 qup_spi3_cs: qup-spi3-cs { 3284 pins = "gpio122"; 3285 function = "qup3"; 3286 }; 3287 3288 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3289 pins = "gpio122"; 3290 function = "gpio"; 3291 }; 3292 3293 qup_spi3_data_clk: qup-spi3-data-clk { 3294 pins = "gpio119", "gpio120", 3295 "gpio121"; 3296 function = "qup3"; 3297 }; 3298 3299 qup_spi4_cs: qup-spi4-cs { 3300 pins = "gpio11"; 3301 function = "qup4"; 3302 }; 3303 3304 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3305 pins = "gpio11"; 3306 function = "gpio"; 3307 }; 3308 3309 qup_spi4_data_clk: qup-spi4-data-clk { 3310 pins = "gpio8", "gpio9", 3311 "gpio10"; 3312 function = "qup4"; 3313 }; 3314 3315 qup_spi5_cs: qup-spi5-cs { 3316 pins = "gpio15"; 3317 function = "qup5"; 3318 }; 3319 3320 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3321 pins = "gpio15"; 3322 function = "gpio"; 3323 }; 3324 3325 qup_spi5_data_clk: qup-spi5-data-clk { 3326 pins = "gpio12", "gpio13", 3327 "gpio14"; 3328 function = "qup5"; 3329 }; 3330 3331 qup_spi6_cs: qup-spi6-cs { 3332 pins = "gpio19"; 3333 function = "qup6"; 3334 }; 3335 3336 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3337 pins = "gpio19"; 3338 function = "gpio"; 3339 }; 3340 3341 qup_spi6_data_clk: qup-spi6-data-clk { 3342 pins = "gpio16", "gpio17", 3343 "gpio18"; 3344 function = "qup6"; 3345 }; 3346 3347 qup_spi7_cs: qup-spi7-cs { 3348 pins = "gpio23"; 3349 function = "qup7"; 3350 }; 3351 3352 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3353 pins = "gpio23"; 3354 function = "gpio"; 3355 }; 3356 3357 qup_spi7_data_clk: qup-spi7-data-clk { 3358 pins = "gpio20", "gpio21", 3359 "gpio22"; 3360 function = "qup7"; 3361 }; 3362 3363 qup_spi8_cs: qup-spi8-cs { 3364 pins = "gpio27"; 3365 function = "qup8"; 3366 }; 3367 3368 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3369 pins = "gpio27"; 3370 function = "gpio"; 3371 }; 3372 3373 qup_spi8_data_clk: qup-spi8-data-clk { 3374 pins = "gpio24", "gpio25", 3375 "gpio26"; 3376 function = "qup8"; 3377 }; 3378 3379 qup_spi9_cs: qup-spi9-cs { 3380 pins = "gpio128"; 3381 function = "qup9"; 3382 }; 3383 3384 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3385 pins = "gpio128"; 3386 function = "gpio"; 3387 }; 3388 3389 qup_spi9_data_clk: qup-spi9-data-clk { 3390 pins = "gpio125", "gpio126", 3391 "gpio127"; 3392 function = "qup9"; 3393 }; 3394 3395 qup_spi10_cs: qup-spi10-cs { 3396 pins = "gpio132"; 3397 function = "qup10"; 3398 }; 3399 3400 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3401 pins = "gpio132"; 3402 function = "gpio"; 3403 }; 3404 3405 qup_spi10_data_clk: qup-spi10-data-clk { 3406 pins = "gpio129", "gpio130", 3407 "gpio131"; 3408 function = "qup10"; 3409 }; 3410 3411 qup_spi11_cs: qup-spi11-cs { 3412 pins = "gpio63"; 3413 function = "qup11"; 3414 }; 3415 3416 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3417 pins = "gpio63"; 3418 function = "gpio"; 3419 }; 3420 3421 qup_spi11_data_clk: qup-spi11-data-clk { 3422 pins = "gpio60", "gpio61", 3423 "gpio62"; 3424 function = "qup11"; 3425 }; 3426 3427 qup_spi12_cs: qup-spi12-cs { 3428 pins = "gpio35"; 3429 function = "qup12"; 3430 }; 3431 3432 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3433 pins = "gpio35"; 3434 function = "gpio"; 3435 }; 3436 3437 qup_spi12_data_clk: qup-spi12-data-clk { 3438 pins = "gpio32", "gpio33", 3439 "gpio34"; 3440 function = "qup12"; 3441 }; 3442 3443 qup_spi13_cs: qup-spi13-cs { 3444 pins = "gpio39"; 3445 function = "qup13"; 3446 }; 3447 3448 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3449 pins = "gpio39"; 3450 function = "gpio"; 3451 }; 3452 3453 qup_spi13_data_clk: qup-spi13-data-clk { 3454 pins = "gpio36", "gpio37", 3455 "gpio38"; 3456 function = "qup13"; 3457 }; 3458 3459 qup_spi14_cs: qup-spi14-cs { 3460 pins = "gpio43"; 3461 function = "qup14"; 3462 }; 3463 3464 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3465 pins = "gpio43"; 3466 function = "gpio"; 3467 }; 3468 3469 qup_spi14_data_clk: qup-spi14-data-clk { 3470 pins = "gpio40", "gpio41", 3471 "gpio42"; 3472 function = "qup14"; 3473 }; 3474 3475 qup_spi15_cs: qup-spi15-cs { 3476 pins = "gpio47"; 3477 function = "qup15"; 3478 }; 3479 3480 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3481 pins = "gpio47"; 3482 function = "gpio"; 3483 }; 3484 3485 qup_spi15_data_clk: qup-spi15-data-clk { 3486 pins = "gpio44", "gpio45", 3487 "gpio46"; 3488 function = "qup15"; 3489 }; 3490 3491 qup_spi16_cs: qup-spi16-cs { 3492 pins = "gpio51"; 3493 function = "qup16"; 3494 }; 3495 3496 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3497 pins = "gpio51"; 3498 function = "gpio"; 3499 }; 3500 3501 qup_spi16_data_clk: qup-spi16-data-clk { 3502 pins = "gpio48", "gpio49", 3503 "gpio50"; 3504 function = "qup16"; 3505 }; 3506 3507 qup_spi17_cs: qup-spi17-cs { 3508 pins = "gpio55"; 3509 function = "qup17"; 3510 }; 3511 3512 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3513 pins = "gpio55"; 3514 function = "gpio"; 3515 }; 3516 3517 qup_spi17_data_clk: qup-spi17-data-clk { 3518 pins = "gpio52", "gpio53", 3519 "gpio54"; 3520 function = "qup17"; 3521 }; 3522 3523 qup_spi18_cs: qup-spi18-cs { 3524 pins = "gpio59"; 3525 function = "qup18"; 3526 }; 3527 3528 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 3529 pins = "gpio59"; 3530 function = "gpio"; 3531 }; 3532 3533 qup_spi18_data_clk: qup-spi18-data-clk { 3534 pins = "gpio56", "gpio57", 3535 "gpio58"; 3536 function = "qup18"; 3537 }; 3538 3539 qup_spi19_cs: qup-spi19-cs { 3540 pins = "gpio3"; 3541 function = "qup19"; 3542 }; 3543 3544 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 3545 pins = "gpio3"; 3546 function = "gpio"; 3547 }; 3548 3549 qup_spi19_data_clk: qup-spi19-data-clk { 3550 pins = "gpio0", "gpio1", 3551 "gpio2"; 3552 function = "qup19"; 3553 }; 3554 3555 qup_uart2_default: qup-uart2-default { 3556 mux { 3557 pins = "gpio117", "gpio118"; 3558 function = "qup2"; 3559 }; 3560 }; 3561 3562 qup_uart6_default: qup-uart6-default { 3563 mux { 3564 pins = "gpio16", "gpio17", 3565 "gpio18", "gpio19"; 3566 function = "qup6"; 3567 }; 3568 }; 3569 3570 qup_uart12_default: qup-uart12-default { 3571 mux { 3572 pins = "gpio34", "gpio35"; 3573 function = "qup12"; 3574 }; 3575 }; 3576 3577 qup_uart17_default: qup-uart17-default { 3578 mux { 3579 pins = "gpio52", "gpio53", 3580 "gpio54", "gpio55"; 3581 function = "qup17"; 3582 }; 3583 }; 3584 3585 qup_uart18_default: qup-uart18-default { 3586 mux { 3587 pins = "gpio58", "gpio59"; 3588 function = "qup18"; 3589 }; 3590 }; 3591 3592 tert_mi2s_active: tert-mi2s-active { 3593 sck { 3594 pins = "gpio133"; 3595 function = "mi2s2_sck"; 3596 drive-strength = <8>; 3597 bias-disable; 3598 }; 3599 3600 data0 { 3601 pins = "gpio134"; 3602 function = "mi2s2_data0"; 3603 drive-strength = <8>; 3604 bias-disable; 3605 output-high; 3606 }; 3607 3608 ws { 3609 pins = "gpio135"; 3610 function = "mi2s2_ws"; 3611 drive-strength = <8>; 3612 output-high; 3613 }; 3614 }; 3615 3616 sdc2_sleep_state: sdc2-sleep { 3617 clk { 3618 pins = "sdc2_clk"; 3619 drive-strength = <2>; 3620 bias-disable; 3621 }; 3622 3623 cmd { 3624 pins = "sdc2_cmd"; 3625 drive-strength = <2>; 3626 bias-pull-up; 3627 }; 3628 3629 data { 3630 pins = "sdc2_data"; 3631 drive-strength = <2>; 3632 bias-pull-up; 3633 }; 3634 }; 3635 3636 pcie0_default_state: pcie0-default { 3637 perst { 3638 pins = "gpio79"; 3639 function = "gpio"; 3640 drive-strength = <2>; 3641 bias-pull-down; 3642 }; 3643 3644 clkreq { 3645 pins = "gpio80"; 3646 function = "pci_e0"; 3647 drive-strength = <2>; 3648 bias-pull-up; 3649 }; 3650 3651 wake { 3652 pins = "gpio81"; 3653 function = "gpio"; 3654 drive-strength = <2>; 3655 bias-pull-up; 3656 }; 3657 }; 3658 3659 pcie1_default_state: pcie1-default { 3660 perst { 3661 pins = "gpio82"; 3662 function = "gpio"; 3663 drive-strength = <2>; 3664 bias-pull-down; 3665 }; 3666 3667 clkreq { 3668 pins = "gpio83"; 3669 function = "pci_e1"; 3670 drive-strength = <2>; 3671 bias-pull-up; 3672 }; 3673 3674 wake { 3675 pins = "gpio84"; 3676 function = "gpio"; 3677 drive-strength = <2>; 3678 bias-pull-up; 3679 }; 3680 }; 3681 3682 pcie2_default_state: pcie2-default { 3683 perst { 3684 pins = "gpio85"; 3685 function = "gpio"; 3686 drive-strength = <2>; 3687 bias-pull-down; 3688 }; 3689 3690 clkreq { 3691 pins = "gpio86"; 3692 function = "pci_e2"; 3693 drive-strength = <2>; 3694 bias-pull-up; 3695 }; 3696 3697 wake { 3698 pins = "gpio87"; 3699 function = "gpio"; 3700 drive-strength = <2>; 3701 bias-pull-up; 3702 }; 3703 }; 3704 }; 3705 3706 apps_smmu: iommu@15000000 { 3707 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3708 reg = <0 0x15000000 0 0x100000>; 3709 #iommu-cells = <2>; 3710 #global-interrupts = <2>; 3711 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3809 }; 3810 3811 adsp: remoteproc@17300000 { 3812 compatible = "qcom,sm8250-adsp-pas"; 3813 reg = <0 0x17300000 0 0x100>; 3814 3815 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3816 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3817 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3818 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3819 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3820 interrupt-names = "wdog", "fatal", "ready", 3821 "handover", "stop-ack"; 3822 3823 clocks = <&rpmhcc RPMH_CXO_CLK>; 3824 clock-names = "xo"; 3825 3826 power-domains = <&rpmhpd SM8250_LCX>, 3827 <&rpmhpd SM8250_LMX>; 3828 power-domain-names = "lcx", "lmx"; 3829 3830 memory-region = <&adsp_mem>; 3831 3832 qcom,qmp = <&aoss_qmp>; 3833 3834 qcom,smem-states = <&smp2p_adsp_out 0>; 3835 qcom,smem-state-names = "stop"; 3836 3837 status = "disabled"; 3838 3839 glink-edge { 3840 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3841 IPCC_MPROC_SIGNAL_GLINK_QMP 3842 IRQ_TYPE_EDGE_RISING>; 3843 mboxes = <&ipcc IPCC_CLIENT_LPASS 3844 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3845 3846 label = "lpass"; 3847 qcom,remote-pid = <2>; 3848 3849 apr { 3850 compatible = "qcom,apr-v2"; 3851 qcom,glink-channels = "apr_audio_svc"; 3852 qcom,apr-domain = <APR_DOMAIN_ADSP>; 3853 #address-cells = <1>; 3854 #size-cells = <0>; 3855 3856 apr-service@3 { 3857 reg = <APR_SVC_ADSP_CORE>; 3858 compatible = "qcom,q6core"; 3859 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3860 }; 3861 3862 q6afe: apr-service@4 { 3863 compatible = "qcom,q6afe"; 3864 reg = <APR_SVC_AFE>; 3865 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3866 q6afedai: dais { 3867 compatible = "qcom,q6afe-dais"; 3868 #address-cells = <1>; 3869 #size-cells = <0>; 3870 #sound-dai-cells = <1>; 3871 }; 3872 3873 q6afecc: cc { 3874 compatible = "qcom,q6afe-clocks"; 3875 #clock-cells = <2>; 3876 }; 3877 }; 3878 3879 q6asm: apr-service@7 { 3880 compatible = "qcom,q6asm"; 3881 reg = <APR_SVC_ASM>; 3882 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3883 q6asmdai: dais { 3884 compatible = "qcom,q6asm-dais"; 3885 #address-cells = <1>; 3886 #size-cells = <0>; 3887 #sound-dai-cells = <1>; 3888 iommus = <&apps_smmu 0x1801 0x0>; 3889 }; 3890 }; 3891 3892 q6adm: apr-service@8 { 3893 compatible = "qcom,q6adm"; 3894 reg = <APR_SVC_ADM>; 3895 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3896 q6routing: routing { 3897 compatible = "qcom,q6adm-routing"; 3898 #sound-dai-cells = <0>; 3899 }; 3900 }; 3901 }; 3902 3903 fastrpc { 3904 compatible = "qcom,fastrpc"; 3905 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3906 label = "adsp"; 3907 #address-cells = <1>; 3908 #size-cells = <0>; 3909 3910 compute-cb@3 { 3911 compatible = "qcom,fastrpc-compute-cb"; 3912 reg = <3>; 3913 iommus = <&apps_smmu 0x1803 0x0>; 3914 }; 3915 3916 compute-cb@4 { 3917 compatible = "qcom,fastrpc-compute-cb"; 3918 reg = <4>; 3919 iommus = <&apps_smmu 0x1804 0x0>; 3920 }; 3921 3922 compute-cb@5 { 3923 compatible = "qcom,fastrpc-compute-cb"; 3924 reg = <5>; 3925 iommus = <&apps_smmu 0x1805 0x0>; 3926 }; 3927 }; 3928 }; 3929 }; 3930 3931 intc: interrupt-controller@17a00000 { 3932 compatible = "arm,gic-v3"; 3933 #interrupt-cells = <3>; 3934 interrupt-controller; 3935 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3936 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3937 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3938 }; 3939 3940 watchdog@17c10000 { 3941 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3942 reg = <0 0x17c10000 0 0x1000>; 3943 clocks = <&sleep_clk>; 3944 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3945 }; 3946 3947 timer@17c20000 { 3948 #address-cells = <2>; 3949 #size-cells = <2>; 3950 ranges; 3951 compatible = "arm,armv7-timer-mem"; 3952 reg = <0x0 0x17c20000 0x0 0x1000>; 3953 clock-frequency = <19200000>; 3954 3955 frame@17c21000 { 3956 frame-number = <0>; 3957 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3959 reg = <0x0 0x17c21000 0x0 0x1000>, 3960 <0x0 0x17c22000 0x0 0x1000>; 3961 }; 3962 3963 frame@17c23000 { 3964 frame-number = <1>; 3965 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3966 reg = <0x0 0x17c23000 0x0 0x1000>; 3967 status = "disabled"; 3968 }; 3969 3970 frame@17c25000 { 3971 frame-number = <2>; 3972 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3973 reg = <0x0 0x17c25000 0x0 0x1000>; 3974 status = "disabled"; 3975 }; 3976 3977 frame@17c27000 { 3978 frame-number = <3>; 3979 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3980 reg = <0x0 0x17c27000 0x0 0x1000>; 3981 status = "disabled"; 3982 }; 3983 3984 frame@17c29000 { 3985 frame-number = <4>; 3986 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3987 reg = <0x0 0x17c29000 0x0 0x1000>; 3988 status = "disabled"; 3989 }; 3990 3991 frame@17c2b000 { 3992 frame-number = <5>; 3993 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3994 reg = <0x0 0x17c2b000 0x0 0x1000>; 3995 status = "disabled"; 3996 }; 3997 3998 frame@17c2d000 { 3999 frame-number = <6>; 4000 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4001 reg = <0x0 0x17c2d000 0x0 0x1000>; 4002 status = "disabled"; 4003 }; 4004 }; 4005 4006 apps_rsc: rsc@18200000 { 4007 label = "apps_rsc"; 4008 compatible = "qcom,rpmh-rsc"; 4009 reg = <0x0 0x18200000 0x0 0x10000>, 4010 <0x0 0x18210000 0x0 0x10000>, 4011 <0x0 0x18220000 0x0 0x10000>; 4012 reg-names = "drv-0", "drv-1", "drv-2"; 4013 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4016 qcom,tcs-offset = <0xd00>; 4017 qcom,drv-id = <2>; 4018 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4019 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4020 4021 rpmhcc: clock-controller { 4022 compatible = "qcom,sm8250-rpmh-clk"; 4023 #clock-cells = <1>; 4024 clock-names = "xo"; 4025 clocks = <&xo_board>; 4026 }; 4027 4028 rpmhpd: power-controller { 4029 compatible = "qcom,sm8250-rpmhpd"; 4030 #power-domain-cells = <1>; 4031 operating-points-v2 = <&rpmhpd_opp_table>; 4032 4033 rpmhpd_opp_table: opp-table { 4034 compatible = "operating-points-v2"; 4035 4036 rpmhpd_opp_ret: opp1 { 4037 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4038 }; 4039 4040 rpmhpd_opp_min_svs: opp2 { 4041 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4042 }; 4043 4044 rpmhpd_opp_low_svs: opp3 { 4045 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4046 }; 4047 4048 rpmhpd_opp_svs: opp4 { 4049 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4050 }; 4051 4052 rpmhpd_opp_svs_l1: opp5 { 4053 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4054 }; 4055 4056 rpmhpd_opp_nom: opp6 { 4057 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4058 }; 4059 4060 rpmhpd_opp_nom_l1: opp7 { 4061 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4062 }; 4063 4064 rpmhpd_opp_nom_l2: opp8 { 4065 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4066 }; 4067 4068 rpmhpd_opp_turbo: opp9 { 4069 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4070 }; 4071 4072 rpmhpd_opp_turbo_l1: opp10 { 4073 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4074 }; 4075 }; 4076 }; 4077 4078 apps_bcm_voter: bcm_voter { 4079 compatible = "qcom,bcm-voter"; 4080 }; 4081 }; 4082 4083 epss_l3: interconnect@18590000 { 4084 compatible = "qcom,sm8250-epss-l3"; 4085 reg = <0 0x18590000 0 0x1000>; 4086 4087 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4088 clock-names = "xo", "alternate"; 4089 4090 #interconnect-cells = <1>; 4091 }; 4092 4093 cpufreq_hw: cpufreq@18591000 { 4094 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 4095 reg = <0 0x18591000 0 0x1000>, 4096 <0 0x18592000 0 0x1000>, 4097 <0 0x18593000 0 0x1000>; 4098 reg-names = "freq-domain0", "freq-domain1", 4099 "freq-domain2"; 4100 4101 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4102 clock-names = "xo", "alternate"; 4103 4104 #freq-domain-cells = <1>; 4105 }; 4106 }; 4107 4108 timer { 4109 compatible = "arm,armv8-timer"; 4110 interrupts = <GIC_PPI 13 4111 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4112 <GIC_PPI 14 4113 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4114 <GIC_PPI 11 4115 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4116 <GIC_PPI 10 4117 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4118 }; 4119 4120 thermal-zones { 4121 cpu0-thermal { 4122 polling-delay-passive = <250>; 4123 polling-delay = <1000>; 4124 4125 thermal-sensors = <&tsens0 1>; 4126 4127 trips { 4128 cpu0_alert0: trip-point0 { 4129 temperature = <90000>; 4130 hysteresis = <2000>; 4131 type = "passive"; 4132 }; 4133 4134 cpu0_alert1: trip-point1 { 4135 temperature = <95000>; 4136 hysteresis = <2000>; 4137 type = "passive"; 4138 }; 4139 4140 cpu0_crit: cpu_crit { 4141 temperature = <110000>; 4142 hysteresis = <1000>; 4143 type = "critical"; 4144 }; 4145 }; 4146 4147 cooling-maps { 4148 map0 { 4149 trip = <&cpu0_alert0>; 4150 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4151 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4154 }; 4155 map1 { 4156 trip = <&cpu0_alert1>; 4157 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4161 }; 4162 }; 4163 }; 4164 4165 cpu1-thermal { 4166 polling-delay-passive = <250>; 4167 polling-delay = <1000>; 4168 4169 thermal-sensors = <&tsens0 2>; 4170 4171 trips { 4172 cpu1_alert0: trip-point0 { 4173 temperature = <90000>; 4174 hysteresis = <2000>; 4175 type = "passive"; 4176 }; 4177 4178 cpu1_alert1: trip-point1 { 4179 temperature = <95000>; 4180 hysteresis = <2000>; 4181 type = "passive"; 4182 }; 4183 4184 cpu1_crit: cpu_crit { 4185 temperature = <110000>; 4186 hysteresis = <1000>; 4187 type = "critical"; 4188 }; 4189 }; 4190 4191 cooling-maps { 4192 map0 { 4193 trip = <&cpu1_alert0>; 4194 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4195 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4198 }; 4199 map1 { 4200 trip = <&cpu1_alert1>; 4201 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4205 }; 4206 }; 4207 }; 4208 4209 cpu2-thermal { 4210 polling-delay-passive = <250>; 4211 polling-delay = <1000>; 4212 4213 thermal-sensors = <&tsens0 3>; 4214 4215 trips { 4216 cpu2_alert0: trip-point0 { 4217 temperature = <90000>; 4218 hysteresis = <2000>; 4219 type = "passive"; 4220 }; 4221 4222 cpu2_alert1: trip-point1 { 4223 temperature = <95000>; 4224 hysteresis = <2000>; 4225 type = "passive"; 4226 }; 4227 4228 cpu2_crit: cpu_crit { 4229 temperature = <110000>; 4230 hysteresis = <1000>; 4231 type = "critical"; 4232 }; 4233 }; 4234 4235 cooling-maps { 4236 map0 { 4237 trip = <&cpu2_alert0>; 4238 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4239 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4242 }; 4243 map1 { 4244 trip = <&cpu2_alert1>; 4245 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4246 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4249 }; 4250 }; 4251 }; 4252 4253 cpu3-thermal { 4254 polling-delay-passive = <250>; 4255 polling-delay = <1000>; 4256 4257 thermal-sensors = <&tsens0 4>; 4258 4259 trips { 4260 cpu3_alert0: trip-point0 { 4261 temperature = <90000>; 4262 hysteresis = <2000>; 4263 type = "passive"; 4264 }; 4265 4266 cpu3_alert1: trip-point1 { 4267 temperature = <95000>; 4268 hysteresis = <2000>; 4269 type = "passive"; 4270 }; 4271 4272 cpu3_crit: cpu_crit { 4273 temperature = <110000>; 4274 hysteresis = <1000>; 4275 type = "critical"; 4276 }; 4277 }; 4278 4279 cooling-maps { 4280 map0 { 4281 trip = <&cpu3_alert0>; 4282 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4283 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4286 }; 4287 map1 { 4288 trip = <&cpu3_alert1>; 4289 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4290 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4292 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4293 }; 4294 }; 4295 }; 4296 4297 cpu4-top-thermal { 4298 polling-delay-passive = <250>; 4299 polling-delay = <1000>; 4300 4301 thermal-sensors = <&tsens0 7>; 4302 4303 trips { 4304 cpu4_top_alert0: trip-point0 { 4305 temperature = <90000>; 4306 hysteresis = <2000>; 4307 type = "passive"; 4308 }; 4309 4310 cpu4_top_alert1: trip-point1 { 4311 temperature = <95000>; 4312 hysteresis = <2000>; 4313 type = "passive"; 4314 }; 4315 4316 cpu4_top_crit: cpu_crit { 4317 temperature = <110000>; 4318 hysteresis = <1000>; 4319 type = "critical"; 4320 }; 4321 }; 4322 4323 cooling-maps { 4324 map0 { 4325 trip = <&cpu4_top_alert0>; 4326 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4327 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4328 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4330 }; 4331 map1 { 4332 trip = <&cpu4_top_alert1>; 4333 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4334 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4337 }; 4338 }; 4339 }; 4340 4341 cpu5-top-thermal { 4342 polling-delay-passive = <250>; 4343 polling-delay = <1000>; 4344 4345 thermal-sensors = <&tsens0 8>; 4346 4347 trips { 4348 cpu5_top_alert0: trip-point0 { 4349 temperature = <90000>; 4350 hysteresis = <2000>; 4351 type = "passive"; 4352 }; 4353 4354 cpu5_top_alert1: trip-point1 { 4355 temperature = <95000>; 4356 hysteresis = <2000>; 4357 type = "passive"; 4358 }; 4359 4360 cpu5_top_crit: cpu_crit { 4361 temperature = <110000>; 4362 hysteresis = <1000>; 4363 type = "critical"; 4364 }; 4365 }; 4366 4367 cooling-maps { 4368 map0 { 4369 trip = <&cpu5_top_alert0>; 4370 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4371 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4374 }; 4375 map1 { 4376 trip = <&cpu5_top_alert1>; 4377 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4378 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4381 }; 4382 }; 4383 }; 4384 4385 cpu6-top-thermal { 4386 polling-delay-passive = <250>; 4387 polling-delay = <1000>; 4388 4389 thermal-sensors = <&tsens0 9>; 4390 4391 trips { 4392 cpu6_top_alert0: trip-point0 { 4393 temperature = <90000>; 4394 hysteresis = <2000>; 4395 type = "passive"; 4396 }; 4397 4398 cpu6_top_alert1: trip-point1 { 4399 temperature = <95000>; 4400 hysteresis = <2000>; 4401 type = "passive"; 4402 }; 4403 4404 cpu6_top_crit: cpu_crit { 4405 temperature = <110000>; 4406 hysteresis = <1000>; 4407 type = "critical"; 4408 }; 4409 }; 4410 4411 cooling-maps { 4412 map0 { 4413 trip = <&cpu6_top_alert0>; 4414 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4415 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4418 }; 4419 map1 { 4420 trip = <&cpu6_top_alert1>; 4421 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4422 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4425 }; 4426 }; 4427 }; 4428 4429 cpu7-top-thermal { 4430 polling-delay-passive = <250>; 4431 polling-delay = <1000>; 4432 4433 thermal-sensors = <&tsens0 10>; 4434 4435 trips { 4436 cpu7_top_alert0: trip-point0 { 4437 temperature = <90000>; 4438 hysteresis = <2000>; 4439 type = "passive"; 4440 }; 4441 4442 cpu7_top_alert1: trip-point1 { 4443 temperature = <95000>; 4444 hysteresis = <2000>; 4445 type = "passive"; 4446 }; 4447 4448 cpu7_top_crit: cpu_crit { 4449 temperature = <110000>; 4450 hysteresis = <1000>; 4451 type = "critical"; 4452 }; 4453 }; 4454 4455 cooling-maps { 4456 map0 { 4457 trip = <&cpu7_top_alert0>; 4458 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4459 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4460 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4462 }; 4463 map1 { 4464 trip = <&cpu7_top_alert1>; 4465 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4466 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4468 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4469 }; 4470 }; 4471 }; 4472 4473 cpu4-bottom-thermal { 4474 polling-delay-passive = <250>; 4475 polling-delay = <1000>; 4476 4477 thermal-sensors = <&tsens0 11>; 4478 4479 trips { 4480 cpu4_bottom_alert0: trip-point0 { 4481 temperature = <90000>; 4482 hysteresis = <2000>; 4483 type = "passive"; 4484 }; 4485 4486 cpu4_bottom_alert1: trip-point1 { 4487 temperature = <95000>; 4488 hysteresis = <2000>; 4489 type = "passive"; 4490 }; 4491 4492 cpu4_bottom_crit: cpu_crit { 4493 temperature = <110000>; 4494 hysteresis = <1000>; 4495 type = "critical"; 4496 }; 4497 }; 4498 4499 cooling-maps { 4500 map0 { 4501 trip = <&cpu4_bottom_alert0>; 4502 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4503 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4504 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4506 }; 4507 map1 { 4508 trip = <&cpu4_bottom_alert1>; 4509 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4510 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4512 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4513 }; 4514 }; 4515 }; 4516 4517 cpu5-bottom-thermal { 4518 polling-delay-passive = <250>; 4519 polling-delay = <1000>; 4520 4521 thermal-sensors = <&tsens0 12>; 4522 4523 trips { 4524 cpu5_bottom_alert0: trip-point0 { 4525 temperature = <90000>; 4526 hysteresis = <2000>; 4527 type = "passive"; 4528 }; 4529 4530 cpu5_bottom_alert1: trip-point1 { 4531 temperature = <95000>; 4532 hysteresis = <2000>; 4533 type = "passive"; 4534 }; 4535 4536 cpu5_bottom_crit: cpu_crit { 4537 temperature = <110000>; 4538 hysteresis = <1000>; 4539 type = "critical"; 4540 }; 4541 }; 4542 4543 cooling-maps { 4544 map0 { 4545 trip = <&cpu5_bottom_alert0>; 4546 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4547 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4548 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4550 }; 4551 map1 { 4552 trip = <&cpu5_bottom_alert1>; 4553 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4554 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4556 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4557 }; 4558 }; 4559 }; 4560 4561 cpu6-bottom-thermal { 4562 polling-delay-passive = <250>; 4563 polling-delay = <1000>; 4564 4565 thermal-sensors = <&tsens0 13>; 4566 4567 trips { 4568 cpu6_bottom_alert0: trip-point0 { 4569 temperature = <90000>; 4570 hysteresis = <2000>; 4571 type = "passive"; 4572 }; 4573 4574 cpu6_bottom_alert1: trip-point1 { 4575 temperature = <95000>; 4576 hysteresis = <2000>; 4577 type = "passive"; 4578 }; 4579 4580 cpu6_bottom_crit: cpu_crit { 4581 temperature = <110000>; 4582 hysteresis = <1000>; 4583 type = "critical"; 4584 }; 4585 }; 4586 4587 cooling-maps { 4588 map0 { 4589 trip = <&cpu6_bottom_alert0>; 4590 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4591 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4592 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4594 }; 4595 map1 { 4596 trip = <&cpu6_bottom_alert1>; 4597 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4598 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4599 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4600 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4601 }; 4602 }; 4603 }; 4604 4605 cpu7-bottom-thermal { 4606 polling-delay-passive = <250>; 4607 polling-delay = <1000>; 4608 4609 thermal-sensors = <&tsens0 14>; 4610 4611 trips { 4612 cpu7_bottom_alert0: trip-point0 { 4613 temperature = <90000>; 4614 hysteresis = <2000>; 4615 type = "passive"; 4616 }; 4617 4618 cpu7_bottom_alert1: trip-point1 { 4619 temperature = <95000>; 4620 hysteresis = <2000>; 4621 type = "passive"; 4622 }; 4623 4624 cpu7_bottom_crit: cpu_crit { 4625 temperature = <110000>; 4626 hysteresis = <1000>; 4627 type = "critical"; 4628 }; 4629 }; 4630 4631 cooling-maps { 4632 map0 { 4633 trip = <&cpu7_bottom_alert0>; 4634 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4635 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4638 }; 4639 map1 { 4640 trip = <&cpu7_bottom_alert1>; 4641 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4642 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4644 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4645 }; 4646 }; 4647 }; 4648 4649 aoss0-thermal { 4650 polling-delay-passive = <250>; 4651 polling-delay = <1000>; 4652 4653 thermal-sensors = <&tsens0 0>; 4654 4655 trips { 4656 aoss0_alert0: trip-point0 { 4657 temperature = <90000>; 4658 hysteresis = <2000>; 4659 type = "hot"; 4660 }; 4661 }; 4662 }; 4663 4664 cluster0-thermal { 4665 polling-delay-passive = <250>; 4666 polling-delay = <1000>; 4667 4668 thermal-sensors = <&tsens0 5>; 4669 4670 trips { 4671 cluster0_alert0: trip-point0 { 4672 temperature = <90000>; 4673 hysteresis = <2000>; 4674 type = "hot"; 4675 }; 4676 cluster0_crit: cluster0_crit { 4677 temperature = <110000>; 4678 hysteresis = <2000>; 4679 type = "critical"; 4680 }; 4681 }; 4682 }; 4683 4684 cluster1-thermal { 4685 polling-delay-passive = <250>; 4686 polling-delay = <1000>; 4687 4688 thermal-sensors = <&tsens0 6>; 4689 4690 trips { 4691 cluster1_alert0: trip-point0 { 4692 temperature = <90000>; 4693 hysteresis = <2000>; 4694 type = "hot"; 4695 }; 4696 cluster1_crit: cluster1_crit { 4697 temperature = <110000>; 4698 hysteresis = <2000>; 4699 type = "critical"; 4700 }; 4701 }; 4702 }; 4703 4704 gpu-thermal-top { 4705 polling-delay-passive = <250>; 4706 polling-delay = <1000>; 4707 4708 thermal-sensors = <&tsens0 15>; 4709 4710 trips { 4711 gpu1_alert0: trip-point0 { 4712 temperature = <90000>; 4713 hysteresis = <2000>; 4714 type = "hot"; 4715 }; 4716 }; 4717 }; 4718 4719 aoss1-thermal { 4720 polling-delay-passive = <250>; 4721 polling-delay = <1000>; 4722 4723 thermal-sensors = <&tsens1 0>; 4724 4725 trips { 4726 aoss1_alert0: trip-point0 { 4727 temperature = <90000>; 4728 hysteresis = <2000>; 4729 type = "hot"; 4730 }; 4731 }; 4732 }; 4733 4734 wlan-thermal { 4735 polling-delay-passive = <250>; 4736 polling-delay = <1000>; 4737 4738 thermal-sensors = <&tsens1 1>; 4739 4740 trips { 4741 wlan_alert0: trip-point0 { 4742 temperature = <90000>; 4743 hysteresis = <2000>; 4744 type = "hot"; 4745 }; 4746 }; 4747 }; 4748 4749 video-thermal { 4750 polling-delay-passive = <250>; 4751 polling-delay = <1000>; 4752 4753 thermal-sensors = <&tsens1 2>; 4754 4755 trips { 4756 video_alert0: trip-point0 { 4757 temperature = <90000>; 4758 hysteresis = <2000>; 4759 type = "hot"; 4760 }; 4761 }; 4762 }; 4763 4764 mem-thermal { 4765 polling-delay-passive = <250>; 4766 polling-delay = <1000>; 4767 4768 thermal-sensors = <&tsens1 3>; 4769 4770 trips { 4771 mem_alert0: trip-point0 { 4772 temperature = <90000>; 4773 hysteresis = <2000>; 4774 type = "hot"; 4775 }; 4776 }; 4777 }; 4778 4779 q6-hvx-thermal { 4780 polling-delay-passive = <250>; 4781 polling-delay = <1000>; 4782 4783 thermal-sensors = <&tsens1 4>; 4784 4785 trips { 4786 q6_hvx_alert0: trip-point0 { 4787 temperature = <90000>; 4788 hysteresis = <2000>; 4789 type = "hot"; 4790 }; 4791 }; 4792 }; 4793 4794 camera-thermal { 4795 polling-delay-passive = <250>; 4796 polling-delay = <1000>; 4797 4798 thermal-sensors = <&tsens1 5>; 4799 4800 trips { 4801 camera_alert0: trip-point0 { 4802 temperature = <90000>; 4803 hysteresis = <2000>; 4804 type = "hot"; 4805 }; 4806 }; 4807 }; 4808 4809 compute-thermal { 4810 polling-delay-passive = <250>; 4811 polling-delay = <1000>; 4812 4813 thermal-sensors = <&tsens1 6>; 4814 4815 trips { 4816 compute_alert0: trip-point0 { 4817 temperature = <90000>; 4818 hysteresis = <2000>; 4819 type = "hot"; 4820 }; 4821 }; 4822 }; 4823 4824 npu-thermal { 4825 polling-delay-passive = <250>; 4826 polling-delay = <1000>; 4827 4828 thermal-sensors = <&tsens1 7>; 4829 4830 trips { 4831 npu_alert0: trip-point0 { 4832 temperature = <90000>; 4833 hysteresis = <2000>; 4834 type = "hot"; 4835 }; 4836 }; 4837 }; 4838 4839 gpu-thermal-bottom { 4840 polling-delay-passive = <250>; 4841 polling-delay = <1000>; 4842 4843 thermal-sensors = <&tsens1 8>; 4844 4845 trips { 4846 gpu2_alert0: trip-point0 { 4847 temperature = <90000>; 4848 hysteresis = <2000>; 4849 type = "hot"; 4850 }; 4851 }; 4852 }; 4853 }; 4854}; 4855