1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn20_dsc.h" 28 #include "dsc/dscc_types.h" 29 30 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); 31 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 32 struct dsc_optc_config *dsc_optc_cfg); 33 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals); 34 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params); 35 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 36 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple); 37 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth); 38 39 /* Object I/F functions */ 40 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 41 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 42 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 43 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 44 struct dsc_optc_config *dsc_optc_cfg); 45 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); 46 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); 47 static void dsc2_disable(struct display_stream_compressor *dsc); 48 49 const struct dsc_funcs dcn20_dsc_funcs = { 50 .dsc_get_enc_caps = dsc2_get_enc_caps, 51 .dsc_read_state = dsc2_read_state, 52 .dsc_validate_stream = dsc2_validate_stream, 53 .dsc_set_config = dsc2_set_config, 54 .dsc_get_packed_pps = dsc2_get_packed_pps, 55 .dsc_enable = dsc2_enable, 56 .dsc_disable = dsc2_disable, 57 }; 58 59 /* Macro definitios for REG_SET macros*/ 60 #define CTX \ 61 dsc20->base.ctx 62 63 #define REG(reg)\ 64 dsc20->dsc_regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name 69 #define DC_LOGGER \ 70 dsc->ctx->logger 71 72 enum dsc_bits_per_comp { 73 DSC_BPC_8 = 8, 74 DSC_BPC_10 = 10, 75 DSC_BPC_12 = 12, 76 DSC_BPC_UNKNOWN 77 }; 78 79 /* API functions (external or via structure->function_pointer) */ 80 81 void dsc2_construct(struct dcn20_dsc *dsc, 82 struct dc_context *ctx, 83 int inst, 84 const struct dcn20_dsc_registers *dsc_regs, 85 const struct dcn20_dsc_shift *dsc_shift, 86 const struct dcn20_dsc_mask *dsc_mask) 87 { 88 dsc->base.ctx = ctx; 89 dsc->base.inst = inst; 90 dsc->base.funcs = &dcn20_dsc_funcs; 91 92 dsc->dsc_regs = dsc_regs; 93 dsc->dsc_shift = dsc_shift; 94 dsc->dsc_mask = dsc_mask; 95 96 dsc->max_image_width = 5184; 97 } 98 99 100 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188 101 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200 102 103 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput 104 * can be doubled, tripled etc. by using additional DSC engines. 105 */ 106 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 107 { 108 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 109 110 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 111 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 112 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 113 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 114 115 dsc_enc_caps->lb_bit_depth = 13; 116 dsc_enc_caps->is_block_pred_supported = true; 117 118 dsc_enc_caps->color_formats.bits.RGB = 1; 119 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 120 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 121 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 122 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 123 124 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 125 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 126 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 127 128 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. 129 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. 130 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always 131 * be sufficient to process the input pixel rate fed into a single DSC engine. 132 */ 133 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; 134 135 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our 136 * throughput and number of slices, but also introduces a lower limit of 2 slices 137 */ 138 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) { 139 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0; 140 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 141 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 142 } 143 144 // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM. 145 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 146 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 147 } 148 149 150 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 151 * into a dcn_dsc_state struct. 152 */ 153 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 154 { 155 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 156 157 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 158 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 159 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); 160 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); 161 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); 162 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); 163 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); 164 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); 165 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en, 166 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source); 167 } 168 169 170 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 171 { 172 struct dsc_optc_config dsc_optc_cfg; 173 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 174 175 if (dsc_cfg->pic_width > dsc20->max_image_width) 176 return false; 177 178 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); 179 } 180 181 182 static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) 183 { 184 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); 185 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); 186 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", 187 config->dc_dsc_cfg.bits_per_pixel, 188 config->dc_dsc_cfg.bits_per_pixel / 16, 189 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); 190 DC_LOG_DSC("\tcolor_depth %d", config->color_depth); 191 } 192 193 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 194 struct dsc_optc_config *dsc_optc_cfg) 195 { 196 bool is_config_ok; 197 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 198 199 DC_LOG_DSC(" "); 200 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 201 dsc_config_log(dsc, dsc_cfg); 202 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); 203 ASSERT(is_config_ok); 204 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 205 dsc_log_pps(dsc, &dsc20->reg_vals.pps); 206 dsc_write_to_registers(dsc, &dsc20->reg_vals); 207 } 208 209 210 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) 211 { 212 bool is_config_ok; 213 struct dsc_reg_values dsc_reg_vals; 214 struct dsc_optc_config dsc_optc_cfg; 215 216 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals)); 217 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg)); 218 219 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); 220 dsc_config_log(dsc, dsc_cfg); 221 DC_LOG_DSC("DSC Picture Parameter Set (PPS):"); 222 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); 223 ASSERT(is_config_ok); 224 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); 225 dsc_log_pps(dsc, &dsc_reg_vals.pps); 226 227 return is_config_ok; 228 } 229 230 231 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) 232 { 233 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 234 int dsc_clock_en; 235 int dsc_fw_config; 236 int enabled_opp_pipe; 237 238 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 239 240 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 241 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 242 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 243 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 244 ASSERT(0); 245 } 246 247 REG_UPDATE(DSC_TOP_CONTROL, 248 DSC_CLOCK_EN, 1); 249 250 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 251 DSCRM_DSC_FORWARD_EN, 1, 252 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 253 } 254 255 256 static void dsc2_disable(struct display_stream_compressor *dsc) 257 { 258 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 259 int dsc_clock_en; 260 int dsc_fw_config; 261 int enabled_opp_pipe; 262 263 DC_LOG_DSC("disable DSC %d", dsc->inst); 264 265 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 266 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 267 if (!dsc_clock_en || !dsc_fw_config) { 268 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe); 269 ASSERT(0); 270 } 271 272 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 273 DSCRM_DSC_FORWARD_EN, 0); 274 275 REG_UPDATE(DSC_TOP_CONTROL, 276 DSC_CLOCK_EN, 0); 277 } 278 279 280 /* This module's internal functions */ 281 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) 282 { 283 int i; 284 int bits_per_pixel = pps->bits_per_pixel; 285 286 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); 287 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); 288 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); 289 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); 290 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); 291 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); 292 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); 293 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); 294 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); 295 DC_LOG_DSC("\tpic_height %d", pps->pic_height); 296 DC_LOG_DSC("\tpic_width %d", pps->pic_width); 297 DC_LOG_DSC("\tslice_height %d", pps->slice_height); 298 DC_LOG_DSC("\tslice_width %d", pps->slice_width); 299 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); 300 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); 301 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); 302 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); 303 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); 304 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); 305 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); 306 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); 307 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); 308 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); 309 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); 310 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); 311 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); 312 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */ 313 DC_LOG_DSC("\tnative_420 %d", pps->native_420); 314 DC_LOG_DSC("\tnative_422 %d", pps->native_422); 315 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); 316 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); 317 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); 318 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); 319 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); 320 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); 321 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); 322 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); 323 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); 324 325 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 326 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); 327 328 for (i = 0; i < NUM_BUF_RANGES; i++) { 329 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); 330 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); 331 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); 332 } 333 } 334 335 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 336 struct dsc_optc_config *dsc_optc_cfg) 337 { 338 struct dsc_parameters dsc_params; 339 340 /* Validate input parameters */ 341 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); 342 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); 343 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); 344 ASSERT(dsc_cfg->pic_width); 345 ASSERT(dsc_cfg->pic_height); 346 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && 347 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || 348 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && 349 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 350 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); 351 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 352 353 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || 354 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || 355 !dsc_cfg->pic_width || !dsc_cfg->pic_height || 356 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: 357 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || 358 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: 359 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 360 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || 361 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { 362 dm_output_to_console("%s: Invalid parameters\n", __func__); 363 return false; 364 } 365 366 dsc_init_reg_values(dsc_reg_vals); 367 368 /* Copy input config */ 369 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); 370 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; 371 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; 372 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; 373 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; 374 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; 375 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); 376 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; 377 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; 378 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; 379 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; 380 381 // TODO: in addition to validating slice height (pic height must be divisible by slice height), 382 // see what happens when the same condition doesn't apply for slice_width/pic_width. 383 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; 384 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; 385 386 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); 387 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { 388 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); 389 return false; 390 } 391 392 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; 393 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 394 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; 395 else 396 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; 397 398 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; 399 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); 400 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); 401 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); 402 403 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) { 404 dm_output_to_console("%s: DSC config failed\n", __func__); 405 return false; 406 } 407 408 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); 409 410 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; 411 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; 412 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || 413 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || 414 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; 415 416 return true; 417 } 418 419 420 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple) 421 { 422 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 423 424 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */ 425 426 switch (dc_pix_enc) { 427 case PIXEL_ENCODING_RGB: 428 dsc_pix_fmt = DSC_PIXFMT_RGB; 429 break; 430 case PIXEL_ENCODING_YCBCR422: 431 if (is_ycbcr422_simple) 432 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422; 433 else 434 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422; 435 break; 436 case PIXEL_ENCODING_YCBCR444: 437 dsc_pix_fmt = DSC_PIXFMT_YCBCR444; 438 break; 439 case PIXEL_ENCODING_YCBCR420: 440 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420; 441 break; 442 default: 443 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 444 break; 445 } 446 447 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN); 448 return dsc_pix_fmt; 449 } 450 451 452 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth) 453 { 454 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; 455 456 switch (dc_color_depth) { 457 case COLOR_DEPTH_888: 458 bpc = DSC_BPC_8; 459 break; 460 case COLOR_DEPTH_101010: 461 bpc = DSC_BPC_10; 462 break; 463 case COLOR_DEPTH_121212: 464 bpc = DSC_BPC_12; 465 break; 466 default: 467 bpc = DSC_BPC_UNKNOWN; 468 break; 469 } 470 471 return bpc; 472 } 473 474 475 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) 476 { 477 int i; 478 479 memset(reg_vals, 0, sizeof(struct dsc_reg_values)); 480 481 /* Non-PPS values */ 482 reg_vals->dsc_clock_enable = 1; 483 reg_vals->dsc_clock_gating_disable = 0; 484 reg_vals->underflow_recovery_en = 0; 485 reg_vals->underflow_occurred_int_en = 0; 486 reg_vals->underflow_occurred_status = 0; 487 reg_vals->ich_reset_at_eol = 0; 488 reg_vals->alternate_ich_encoding_en = 0; 489 reg_vals->rc_buffer_model_size = 0; 490 /*reg_vals->disable_ich = 0;*/ 491 reg_vals->dsc_dbg_en = 0; 492 493 for (i = 0; i < 4; i++) 494 reg_vals->rc_buffer_model_overflow_int_en[i] = 0; 495 496 /* PPS values */ 497 reg_vals->pps.dsc_version_minor = 2; 498 reg_vals->pps.dsc_version_major = 1; 499 reg_vals->pps.line_buf_depth = 9; 500 reg_vals->pps.bits_per_component = 8; 501 reg_vals->pps.block_pred_enable = 1; 502 reg_vals->pps.slice_chunk_size = 0; 503 reg_vals->pps.pic_width = 0; 504 reg_vals->pps.pic_height = 0; 505 reg_vals->pps.slice_width = 0; 506 reg_vals->pps.slice_height = 0; 507 reg_vals->pps.initial_xmit_delay = 170; 508 reg_vals->pps.initial_dec_delay = 0; 509 reg_vals->pps.initial_scale_value = 0; 510 reg_vals->pps.scale_increment_interval = 0; 511 reg_vals->pps.scale_decrement_interval = 0; 512 reg_vals->pps.nfl_bpg_offset = 0; 513 reg_vals->pps.slice_bpg_offset = 0; 514 reg_vals->pps.nsl_bpg_offset = 0; 515 reg_vals->pps.initial_offset = 6144; 516 reg_vals->pps.final_offset = 0; 517 reg_vals->pps.flatness_min_qp = 3; 518 reg_vals->pps.flatness_max_qp = 12; 519 reg_vals->pps.rc_model_size = 8192; 520 reg_vals->pps.rc_edge_factor = 6; 521 reg_vals->pps.rc_quant_incr_limit0 = 11; 522 reg_vals->pps.rc_quant_incr_limit1 = 11; 523 reg_vals->pps.rc_tgt_offset_low = 3; 524 reg_vals->pps.rc_tgt_offset_high = 3; 525 } 526 527 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params. 528 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn 529 * affects non-PPS register values. 530 */ 531 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) 532 { 533 int i; 534 535 reg_vals->pps = dsc_params->pps; 536 537 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs. 538 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 539 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; 540 541 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; 542 } 543 544 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 545 { 546 uint32_t temp_int; 547 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 548 549 REG_SET(DSC_DEBUG_CONTROL, 0, 550 DSC_DBG_EN, reg_vals->dsc_dbg_en); 551 552 // dsccif registers 553 REG_SET_5(DSCCIF_CONFIG0, 0, 554 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 555 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 556 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 557 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 558 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 559 560 REG_SET_2(DSCCIF_CONFIG1, 0, 561 PIC_WIDTH, reg_vals->pps.pic_width, 562 PIC_HEIGHT, reg_vals->pps.pic_height); 563 564 // dscc registers 565 REG_SET_4(DSCC_CONFIG0, 0, 566 ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol, 567 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 568 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 569 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 570 571 REG_SET(DSCC_CONFIG1, 0, 572 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 573 /*REG_SET_2(DSCC_CONFIG1, 0, 574 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 575 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 576 577 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, 578 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], 579 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], 580 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], 581 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); 582 583 REG_SET_3(DSCC_PPS_CONFIG0, 0, 584 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 585 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 586 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 587 588 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 589 temp_int = reg_vals->bpp_x32; 590 else 591 temp_int = reg_vals->bpp_x32 >> 1; 592 593 REG_SET_7(DSCC_PPS_CONFIG1, 0, 594 BITS_PER_PIXEL, temp_int, 595 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 596 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 597 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 598 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 599 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 600 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 601 602 REG_SET_2(DSCC_PPS_CONFIG2, 0, 603 PIC_WIDTH, reg_vals->pps.pic_width, 604 PIC_HEIGHT, reg_vals->pps.pic_height); 605 606 REG_SET_2(DSCC_PPS_CONFIG3, 0, 607 SLICE_WIDTH, reg_vals->pps.slice_width, 608 SLICE_HEIGHT, reg_vals->pps.slice_height); 609 610 REG_SET(DSCC_PPS_CONFIG4, 0, 611 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 612 613 REG_SET_2(DSCC_PPS_CONFIG5, 0, 614 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 615 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 616 617 REG_SET_3(DSCC_PPS_CONFIG6, 0, 618 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 619 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 620 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 621 622 REG_SET_2(DSCC_PPS_CONFIG7, 0, 623 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 624 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 625 626 REG_SET_2(DSCC_PPS_CONFIG8, 0, 627 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 628 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 629 630 REG_SET_2(DSCC_PPS_CONFIG9, 0, 631 INITIAL_OFFSET, reg_vals->pps.initial_offset, 632 FINAL_OFFSET, reg_vals->pps.final_offset); 633 634 REG_SET_3(DSCC_PPS_CONFIG10, 0, 635 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 636 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 637 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 638 639 REG_SET_5(DSCC_PPS_CONFIG11, 0, 640 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 641 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 642 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 643 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 644 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 645 646 REG_SET_4(DSCC_PPS_CONFIG12, 0, 647 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 648 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 649 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 650 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 651 652 REG_SET_4(DSCC_PPS_CONFIG13, 0, 653 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 654 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 655 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 656 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 657 658 REG_SET_4(DSCC_PPS_CONFIG14, 0, 659 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 660 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 661 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 662 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 663 664 REG_SET_5(DSCC_PPS_CONFIG15, 0, 665 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 666 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 667 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 668 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 669 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 670 671 REG_SET_6(DSCC_PPS_CONFIG16, 0, 672 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 673 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 674 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 675 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 676 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 677 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 678 679 REG_SET_6(DSCC_PPS_CONFIG17, 0, 680 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 681 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 682 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 683 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 684 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 685 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 686 687 REG_SET_6(DSCC_PPS_CONFIG18, 0, 688 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 689 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 690 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 691 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 692 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 693 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 694 695 REG_SET_6(DSCC_PPS_CONFIG19, 0, 696 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 697 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 698 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 699 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 700 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 701 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 702 703 REG_SET_6(DSCC_PPS_CONFIG20, 0, 704 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 705 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 706 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 707 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 708 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 709 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 710 711 REG_SET_6(DSCC_PPS_CONFIG21, 0, 712 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 713 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 714 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 715 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 716 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 717 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 718 719 REG_SET_6(DSCC_PPS_CONFIG22, 0, 720 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 721 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 722 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 723 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 724 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 725 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 726 727 } 728 729