1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADF4350/ADF4351 SPI Wideband Synthesizer driver 4 * 5 * Copyright 2012-2013 Analog Devices Inc. 6 */ 7 8 #include <linux/device.h> 9 #include <linux/kernel.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/property.h> 13 #include <linux/slab.h> 14 #include <linux/sysfs.h> 15 #include <linux/spi/spi.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/err.h> 18 #include <linux/gcd.h> 19 #include <linux/gpio/consumer.h> 20 #include <asm/div64.h> 21 #include <linux/clk.h> 22 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/frequency/adf4350.h> 26 27 enum { 28 ADF4350_FREQ, 29 ADF4350_FREQ_REFIN, 30 ADF4350_FREQ_RESOLUTION, 31 ADF4350_PWRDOWN, 32 }; 33 34 struct adf4350_state { 35 struct spi_device *spi; 36 struct regulator *reg; 37 struct gpio_desc *lock_detect_gpiod; 38 struct adf4350_platform_data *pdata; 39 struct clk *clk; 40 unsigned long clkin; 41 unsigned long chspc; /* Channel Spacing */ 42 unsigned long fpfd; /* Phase Frequency Detector */ 43 unsigned long min_out_freq; 44 unsigned r0_fract; 45 unsigned r0_int; 46 unsigned r1_mod; 47 unsigned r4_rf_div_sel; 48 unsigned long regs[6]; 49 unsigned long regs_hw[6]; 50 unsigned long long freq_req; 51 /* 52 * Lock to protect the state of the device from potential concurrent 53 * writes. The device is configured via a sequence of SPI writes, 54 * and this lock is meant to prevent the start of another sequence 55 * before another one has finished. 56 */ 57 struct mutex lock; 58 /* 59 * DMA (thus cache coherency maintenance) requires the 60 * transfer buffers to live in their own cache lines. 61 */ 62 __be32 val ____cacheline_aligned; 63 }; 64 65 static struct adf4350_platform_data default_pdata = { 66 .channel_spacing = 10000, 67 .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS | 68 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500), 69 .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0), 70 .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) | 71 ADF4350_REG4_MUTE_TILL_LOCK_EN, 72 }; 73 74 static int adf4350_sync_config(struct adf4350_state *st) 75 { 76 int ret, i, doublebuf = 0; 77 78 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { 79 if ((st->regs_hw[i] != st->regs[i]) || 80 ((i == ADF4350_REG0) && doublebuf)) { 81 switch (i) { 82 case ADF4350_REG1: 83 case ADF4350_REG4: 84 doublebuf = 1; 85 break; 86 } 87 88 st->val = cpu_to_be32(st->regs[i] | i); 89 ret = spi_write(st->spi, &st->val, 4); 90 if (ret < 0) 91 return ret; 92 st->regs_hw[i] = st->regs[i]; 93 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", 94 i, (u32)st->regs[i] | i); 95 } 96 } 97 return 0; 98 } 99 100 static int adf4350_reg_access(struct iio_dev *indio_dev, 101 unsigned reg, unsigned writeval, 102 unsigned *readval) 103 { 104 struct adf4350_state *st = iio_priv(indio_dev); 105 int ret; 106 107 if (reg > ADF4350_REG5) 108 return -EINVAL; 109 110 mutex_lock(&st->lock); 111 if (readval == NULL) { 112 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); 113 ret = adf4350_sync_config(st); 114 } else { 115 *readval = st->regs_hw[reg]; 116 ret = 0; 117 } 118 mutex_unlock(&st->lock); 119 120 return ret; 121 } 122 123 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt) 124 { 125 struct adf4350_platform_data *pdata = st->pdata; 126 127 do { 128 r_cnt++; 129 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) / 130 (r_cnt * (pdata->ref_div2_en ? 2 : 1)); 131 } while (st->fpfd > ADF4350_MAX_FREQ_PFD); 132 133 return r_cnt; 134 } 135 136 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) 137 { 138 struct adf4350_platform_data *pdata = st->pdata; 139 u64 tmp; 140 u32 div_gcd, prescaler, chspc; 141 u16 mdiv, r_cnt = 0; 142 u8 band_sel_div; 143 144 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) 145 return -EINVAL; 146 147 if (freq > ADF4350_MAX_FREQ_45_PRESC) { 148 prescaler = ADF4350_REG1_PRESCALER; 149 mdiv = 75; 150 } else { 151 prescaler = 0; 152 mdiv = 23; 153 } 154 155 st->r4_rf_div_sel = 0; 156 157 while (freq < ADF4350_MIN_VCO_FREQ) { 158 freq <<= 1; 159 st->r4_rf_div_sel++; 160 } 161 162 /* 163 * Allow a predefined reference division factor 164 * if not set, compute our own 165 */ 166 if (pdata->ref_div_factor) 167 r_cnt = pdata->ref_div_factor - 1; 168 169 chspc = st->chspc; 170 171 do { 172 do { 173 do { 174 r_cnt = adf4350_tune_r_cnt(st, r_cnt); 175 st->r1_mod = st->fpfd / chspc; 176 if (r_cnt > ADF4350_MAX_R_CNT) { 177 /* try higher spacing values */ 178 chspc++; 179 r_cnt = 0; 180 } 181 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt); 182 } while (r_cnt == 0); 183 184 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); 185 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ 186 st->r0_fract = do_div(tmp, st->r1_mod); 187 st->r0_int = tmp; 188 } while (mdiv > st->r0_int); 189 190 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK); 191 192 if (st->r0_fract && st->r1_mod) { 193 div_gcd = gcd(st->r1_mod, st->r0_fract); 194 st->r1_mod /= div_gcd; 195 st->r0_fract /= div_gcd; 196 } else { 197 st->r0_fract = 0; 198 st->r1_mod = 1; 199 } 200 201 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n" 202 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n" 203 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n", 204 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod, 205 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5", 206 band_sel_div); 207 208 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) | 209 ADF4350_REG0_FRACT(st->r0_fract); 210 211 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) | 212 ADF4350_REG1_MOD(st->r1_mod) | 213 prescaler; 214 215 st->regs[ADF4350_REG2] = 216 ADF4350_REG2_10BIT_R_CNT(r_cnt) | 217 ADF4350_REG2_DOUBLE_BUFF_EN | 218 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) | 219 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) | 220 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS | 221 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N | 222 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) | 223 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3))); 224 225 st->regs[ADF4350_REG3] = pdata->r3_user_settings & 226 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) | 227 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) | 228 ADF4350_REG3_12BIT_CSR_EN | 229 ADF4351_REG3_CHARGE_CANCELLATION_EN | 230 ADF4351_REG3_ANTI_BACKLASH_3ns_EN | 231 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH); 232 233 st->regs[ADF4350_REG4] = 234 ADF4350_REG4_FEEDBACK_FUND | 235 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | 236 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) | 237 ADF4350_REG4_RF_OUT_EN | 238 (pdata->r4_user_settings & 239 (ADF4350_REG4_OUTPUT_PWR(0x3) | 240 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) | 241 ADF4350_REG4_AUX_OUTPUT_EN | 242 ADF4350_REG4_AUX_OUTPUT_FUND | 243 ADF4350_REG4_MUTE_TILL_LOCK_EN)); 244 245 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL; 246 st->freq_req = freq; 247 248 return adf4350_sync_config(st); 249 } 250 251 static ssize_t adf4350_write(struct iio_dev *indio_dev, 252 uintptr_t private, 253 const struct iio_chan_spec *chan, 254 const char *buf, size_t len) 255 { 256 struct adf4350_state *st = iio_priv(indio_dev); 257 unsigned long long readin; 258 unsigned long tmp; 259 int ret; 260 261 ret = kstrtoull(buf, 10, &readin); 262 if (ret) 263 return ret; 264 265 mutex_lock(&st->lock); 266 switch ((u32)private) { 267 case ADF4350_FREQ: 268 ret = adf4350_set_freq(st, readin); 269 break; 270 case ADF4350_FREQ_REFIN: 271 if (readin > ADF4350_MAX_FREQ_REFIN) { 272 ret = -EINVAL; 273 break; 274 } 275 276 if (st->clk) { 277 tmp = clk_round_rate(st->clk, readin); 278 if (tmp != readin) { 279 ret = -EINVAL; 280 break; 281 } 282 ret = clk_set_rate(st->clk, tmp); 283 if (ret < 0) 284 break; 285 } 286 st->clkin = readin; 287 ret = adf4350_set_freq(st, st->freq_req); 288 break; 289 case ADF4350_FREQ_RESOLUTION: 290 if (readin == 0) 291 ret = -EINVAL; 292 else 293 st->chspc = readin; 294 break; 295 case ADF4350_PWRDOWN: 296 if (readin) 297 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 298 else 299 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; 300 301 adf4350_sync_config(st); 302 break; 303 default: 304 ret = -EINVAL; 305 } 306 mutex_unlock(&st->lock); 307 308 return ret ? ret : len; 309 } 310 311 static ssize_t adf4350_read(struct iio_dev *indio_dev, 312 uintptr_t private, 313 const struct iio_chan_spec *chan, 314 char *buf) 315 { 316 struct adf4350_state *st = iio_priv(indio_dev); 317 unsigned long long val; 318 int ret = 0; 319 320 mutex_lock(&st->lock); 321 switch ((u32)private) { 322 case ADF4350_FREQ: 323 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * 324 (u64)st->fpfd; 325 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); 326 /* PLL unlocked? return error */ 327 if (st->lock_detect_gpiod) 328 if (!gpiod_get_value(st->lock_detect_gpiod)) { 329 dev_dbg(&st->spi->dev, "PLL un-locked\n"); 330 ret = -EBUSY; 331 } 332 break; 333 case ADF4350_FREQ_REFIN: 334 if (st->clk) 335 st->clkin = clk_get_rate(st->clk); 336 337 val = st->clkin; 338 break; 339 case ADF4350_FREQ_RESOLUTION: 340 val = st->chspc; 341 break; 342 case ADF4350_PWRDOWN: 343 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); 344 break; 345 default: 346 ret = -EINVAL; 347 val = 0; 348 } 349 mutex_unlock(&st->lock); 350 351 return ret < 0 ? ret : sprintf(buf, "%llu\n", val); 352 } 353 354 #define _ADF4350_EXT_INFO(_name, _ident) { \ 355 .name = _name, \ 356 .read = adf4350_read, \ 357 .write = adf4350_write, \ 358 .private = _ident, \ 359 .shared = IIO_SEPARATE, \ 360 } 361 362 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = { 363 /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are 364 * values > 2^32 in order to support the entire frequency range 365 * in Hz. Using scale is a bit ugly. 366 */ 367 _ADF4350_EXT_INFO("frequency", ADF4350_FREQ), 368 _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION), 369 _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN), 370 _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN), 371 { }, 372 }; 373 374 static const struct iio_chan_spec adf4350_chan = { 375 .type = IIO_ALTVOLTAGE, 376 .indexed = 1, 377 .output = 1, 378 .ext_info = adf4350_ext_info, 379 }; 380 381 static const struct iio_info adf4350_info = { 382 .debugfs_reg_access = &adf4350_reg_access, 383 }; 384 385 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) 386 { 387 struct adf4350_platform_data *pdata; 388 unsigned int tmp; 389 390 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 391 if (!pdata) 392 return NULL; 393 394 snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev)); 395 396 tmp = 10000; 397 device_property_read_u32(dev, "adi,channel-spacing", &tmp); 398 pdata->channel_spacing = tmp; 399 400 tmp = 0; 401 device_property_read_u32(dev, "adi,power-up-frequency", &tmp); 402 pdata->power_up_frequency = tmp; 403 404 tmp = 0; 405 device_property_read_u32(dev, "adi,reference-div-factor", &tmp); 406 pdata->ref_div_factor = tmp; 407 408 pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable"); 409 pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable"); 410 411 /* r2_user_settings */ 412 pdata->r2_user_settings = 0; 413 if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable")) 414 pdata->r2_user_settings |= ADF4350_REG2_PD_POLARITY_POS; 415 if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable")) 416 pdata->r2_user_settings |= ADF4350_REG2_LDP_6ns; 417 if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable")) 418 pdata->r2_user_settings |= ADF4350_REG2_LDF_INT_N; 419 420 tmp = 2500; 421 device_property_read_u32(dev, "adi,charge-pump-current", &tmp); 422 pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp); 423 424 tmp = 0; 425 device_property_read_u32(dev, "adi,muxout-select", &tmp); 426 pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp); 427 428 if (device_property_read_bool(dev, "adi,low-spur-mode-enable")) 429 pdata->r2_user_settings |= ADF4350_REG2_NOISE_MODE(0x3); 430 431 /* r3_user_settings */ 432 433 pdata->r3_user_settings = 0; 434 if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable")) 435 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CSR_EN; 436 if (device_property_read_bool(dev, "adi,charge-cancellation-enable")) 437 pdata->r3_user_settings |= ADF4351_REG3_CHARGE_CANCELLATION_EN; 438 if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable")) 439 pdata->r3_user_settings |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN; 440 if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable")) 441 pdata->r3_user_settings |= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH; 442 443 tmp = 0; 444 device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp); 445 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp); 446 447 tmp = 0; 448 device_property_read_u32(dev, "adi,clk-divider-mode", &tmp); 449 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp); 450 451 /* r4_user_settings */ 452 453 pdata->r4_user_settings = 0; 454 if (device_property_read_bool(dev, "adi,aux-output-enable")) 455 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_EN; 456 if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable")) 457 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_FUND; 458 if (device_property_read_bool(dev, "adi,mute-till-lock-enable")) 459 pdata->r4_user_settings |= ADF4350_REG4_MUTE_TILL_LOCK_EN; 460 461 tmp = 0; 462 device_property_read_u32(dev, "adi,output-power", &tmp); 463 pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp); 464 465 tmp = 0; 466 device_property_read_u32(dev, "adi,aux-output-power", &tmp); 467 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp); 468 469 return pdata; 470 } 471 472 static int adf4350_probe(struct spi_device *spi) 473 { 474 struct adf4350_platform_data *pdata; 475 struct iio_dev *indio_dev; 476 struct adf4350_state *st; 477 struct clk *clk = NULL; 478 int ret; 479 480 if (dev_fwnode(&spi->dev)) { 481 pdata = adf4350_parse_dt(&spi->dev); 482 if (pdata == NULL) 483 return -EINVAL; 484 } else { 485 pdata = spi->dev.platform_data; 486 } 487 488 if (!pdata) { 489 dev_warn(&spi->dev, "no platform data? using default\n"); 490 pdata = &default_pdata; 491 } 492 493 if (!pdata->clkin) { 494 clk = devm_clk_get(&spi->dev, "clkin"); 495 if (IS_ERR(clk)) 496 return -EPROBE_DEFER; 497 498 ret = clk_prepare_enable(clk); 499 if (ret < 0) 500 return ret; 501 } 502 503 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 504 if (indio_dev == NULL) { 505 ret = -ENOMEM; 506 goto error_disable_clk; 507 } 508 509 st = iio_priv(indio_dev); 510 511 st->reg = devm_regulator_get(&spi->dev, "vcc"); 512 if (!IS_ERR(st->reg)) { 513 ret = regulator_enable(st->reg); 514 if (ret) 515 goto error_disable_clk; 516 } 517 518 spi_set_drvdata(spi, indio_dev); 519 st->spi = spi; 520 st->pdata = pdata; 521 522 indio_dev->name = (pdata->name[0] != 0) ? pdata->name : 523 spi_get_device_id(spi)->name; 524 525 indio_dev->info = &adf4350_info; 526 indio_dev->modes = INDIO_DIRECT_MODE; 527 indio_dev->channels = &adf4350_chan; 528 indio_dev->num_channels = 1; 529 530 mutex_init(&st->lock); 531 532 st->chspc = pdata->channel_spacing; 533 if (clk) { 534 st->clk = clk; 535 st->clkin = clk_get_rate(clk); 536 } else { 537 st->clkin = pdata->clkin; 538 } 539 540 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ? 541 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ; 542 543 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); 544 545 st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL, 546 GPIOD_IN); 547 if (IS_ERR(st->lock_detect_gpiod)) { 548 ret = PTR_ERR(st->lock_detect_gpiod); 549 goto error_disable_reg; 550 } 551 552 if (pdata->power_up_frequency) { 553 ret = adf4350_set_freq(st, pdata->power_up_frequency); 554 if (ret) 555 goto error_disable_reg; 556 } 557 558 ret = iio_device_register(indio_dev); 559 if (ret) 560 goto error_disable_reg; 561 562 return 0; 563 564 error_disable_reg: 565 if (!IS_ERR(st->reg)) 566 regulator_disable(st->reg); 567 error_disable_clk: 568 clk_disable_unprepare(clk); 569 570 return ret; 571 } 572 573 static void adf4350_remove(struct spi_device *spi) 574 { 575 struct iio_dev *indio_dev = spi_get_drvdata(spi); 576 struct adf4350_state *st = iio_priv(indio_dev); 577 struct regulator *reg = st->reg; 578 579 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 580 adf4350_sync_config(st); 581 582 iio_device_unregister(indio_dev); 583 584 clk_disable_unprepare(st->clk); 585 586 if (!IS_ERR(reg)) 587 regulator_disable(reg); 588 } 589 590 static const struct of_device_id adf4350_of_match[] = { 591 { .compatible = "adi,adf4350", }, 592 { .compatible = "adi,adf4351", }, 593 { /* sentinel */ }, 594 }; 595 MODULE_DEVICE_TABLE(of, adf4350_of_match); 596 597 static const struct spi_device_id adf4350_id[] = { 598 {"adf4350", 4350}, 599 {"adf4351", 4351}, 600 {} 601 }; 602 MODULE_DEVICE_TABLE(spi, adf4350_id); 603 604 static struct spi_driver adf4350_driver = { 605 .driver = { 606 .name = "adf4350", 607 .of_match_table = adf4350_of_match, 608 }, 609 .probe = adf4350_probe, 610 .remove = adf4350_remove, 611 .id_table = adf4350_id, 612 }; 613 module_spi_driver(adf4350_driver); 614 615 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 616 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL"); 617 MODULE_LICENSE("GPL v2"); 618