1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2017 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 */ 7 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include <dt-bindings/gpio/tegra186-gpio.h> 16 #include <dt-bindings/gpio/tegra194-gpio.h> 17 #include <dt-bindings/gpio/tegra234-gpio.h> 18 #include <dt-bindings/gpio/tegra241-gpio.h> 19 20 /* security registers */ 21 #define TEGRA186_GPIO_CTL_SCR 0x0c 22 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 23 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 24 25 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 26 27 /* control registers */ 28 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 29 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 30 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 35 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 36 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 37 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 38 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 39 40 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 41 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 42 43 #define TEGRA186_GPIO_INPUT 0x08 44 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) 45 46 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 47 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 48 49 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 50 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 51 52 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 53 54 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 55 56 struct tegra_gpio_port { 57 const char *name; 58 unsigned int bank; 59 unsigned int port; 60 unsigned int pins; 61 }; 62 63 struct tegra186_pin_range { 64 unsigned int offset; 65 const char *group; 66 }; 67 68 struct tegra_gpio_soc { 69 const struct tegra_gpio_port *ports; 70 unsigned int num_ports; 71 const char *name; 72 unsigned int instance; 73 74 unsigned int num_irqs_per_bank; 75 76 const struct tegra186_pin_range *pin_ranges; 77 unsigned int num_pin_ranges; 78 const char *pinmux; 79 }; 80 81 struct tegra_gpio { 82 struct gpio_chip gpio; 83 struct irq_chip intc; 84 unsigned int num_irq; 85 unsigned int *irq; 86 87 const struct tegra_gpio_soc *soc; 88 unsigned int num_irqs_per_bank; 89 unsigned int num_banks; 90 91 void __iomem *secure; 92 void __iomem *base; 93 }; 94 95 static const struct tegra_gpio_port * 96 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 97 { 98 unsigned int start = 0, i; 99 100 for (i = 0; i < gpio->soc->num_ports; i++) { 101 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 102 103 if (*pin >= start && *pin < start + port->pins) { 104 *pin -= start; 105 return port; 106 } 107 108 start += port->pins; 109 } 110 111 return NULL; 112 } 113 114 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 115 unsigned int pin) 116 { 117 const struct tegra_gpio_port *port; 118 unsigned int offset; 119 120 port = tegra186_gpio_get_port(gpio, &pin); 121 if (!port) 122 return NULL; 123 124 offset = port->bank * 0x1000 + port->port * 0x200; 125 126 return gpio->base + offset + pin * 0x20; 127 } 128 129 static int tegra186_gpio_get_direction(struct gpio_chip *chip, 130 unsigned int offset) 131 { 132 struct tegra_gpio *gpio = gpiochip_get_data(chip); 133 void __iomem *base; 134 u32 value; 135 136 base = tegra186_gpio_get_base(gpio, offset); 137 if (WARN_ON(base == NULL)) 138 return -ENODEV; 139 140 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 141 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 142 return GPIO_LINE_DIRECTION_OUT; 143 144 return GPIO_LINE_DIRECTION_IN; 145 } 146 147 static int tegra186_gpio_direction_input(struct gpio_chip *chip, 148 unsigned int offset) 149 { 150 struct tegra_gpio *gpio = gpiochip_get_data(chip); 151 void __iomem *base; 152 u32 value; 153 154 base = tegra186_gpio_get_base(gpio, offset); 155 if (WARN_ON(base == NULL)) 156 return -ENODEV; 157 158 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 159 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 160 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 161 162 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 163 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 164 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 165 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 166 167 return 0; 168 } 169 170 static int tegra186_gpio_direction_output(struct gpio_chip *chip, 171 unsigned int offset, int level) 172 { 173 struct tegra_gpio *gpio = gpiochip_get_data(chip); 174 void __iomem *base; 175 u32 value; 176 177 /* configure output level first */ 178 chip->set(chip, offset, level); 179 180 base = tegra186_gpio_get_base(gpio, offset); 181 if (WARN_ON(base == NULL)) 182 return -EINVAL; 183 184 /* set the direction */ 185 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 186 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 187 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 188 189 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 190 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 191 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 192 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 193 194 return 0; 195 } 196 197 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 198 { 199 struct tegra_gpio *gpio = gpiochip_get_data(chip); 200 void __iomem *base; 201 u32 value; 202 203 base = tegra186_gpio_get_base(gpio, offset); 204 if (WARN_ON(base == NULL)) 205 return -ENODEV; 206 207 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 208 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 209 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 210 else 211 value = readl(base + TEGRA186_GPIO_INPUT); 212 213 return value & BIT(0); 214 } 215 216 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 217 int level) 218 { 219 struct tegra_gpio *gpio = gpiochip_get_data(chip); 220 void __iomem *base; 221 u32 value; 222 223 base = tegra186_gpio_get_base(gpio, offset); 224 if (WARN_ON(base == NULL)) 225 return; 226 227 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 228 if (level == 0) 229 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 230 else 231 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 232 233 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 234 } 235 236 static int tegra186_gpio_set_config(struct gpio_chip *chip, 237 unsigned int offset, 238 unsigned long config) 239 { 240 struct tegra_gpio *gpio = gpiochip_get_data(chip); 241 u32 debounce, value; 242 void __iomem *base; 243 244 base = tegra186_gpio_get_base(gpio, offset); 245 if (base == NULL) 246 return -ENXIO; 247 248 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 249 return -ENOTSUPP; 250 251 debounce = pinconf_to_config_argument(config); 252 253 /* 254 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 255 * time. 256 */ 257 if (debounce > 255000) 258 return -EINVAL; 259 260 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 261 262 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 263 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 264 265 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 266 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 267 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 268 269 return 0; 270 } 271 272 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 273 { 274 struct tegra_gpio *gpio = gpiochip_get_data(chip); 275 struct pinctrl_dev *pctldev; 276 struct device_node *np; 277 unsigned int i, j; 278 int err; 279 280 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 281 return 0; 282 283 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 284 if (!np) 285 return -ENODEV; 286 287 pctldev = of_pinctrl_get(np); 288 of_node_put(np); 289 if (!pctldev) 290 return -EPROBE_DEFER; 291 292 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 293 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 294 const char *group = gpio->soc->pin_ranges[i].group; 295 296 port = pin / 8; 297 pin = pin % 8; 298 299 if (port >= gpio->soc->num_ports) { 300 dev_warn(chip->parent, "invalid port %u for %s\n", 301 port, group); 302 continue; 303 } 304 305 for (j = 0; j < port; j++) 306 pin += gpio->soc->ports[j].pins; 307 308 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 309 if (err < 0) 310 return err; 311 } 312 313 return 0; 314 } 315 316 static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 317 const struct of_phandle_args *spec, 318 u32 *flags) 319 { 320 struct tegra_gpio *gpio = gpiochip_get_data(chip); 321 unsigned int port, pin, i, offset = 0; 322 323 if (WARN_ON(chip->of_gpio_n_cells < 2)) 324 return -EINVAL; 325 326 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 327 return -EINVAL; 328 329 port = spec->args[0] / 8; 330 pin = spec->args[0] % 8; 331 332 if (port >= gpio->soc->num_ports) { 333 dev_err(chip->parent, "invalid port number: %u\n", port); 334 return -EINVAL; 335 } 336 337 for (i = 0; i < port; i++) 338 offset += gpio->soc->ports[i].pins; 339 340 if (flags) 341 *flags = spec->args[1]; 342 343 return offset + pin; 344 } 345 346 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio) 347 348 static void tegra186_irq_ack(struct irq_data *data) 349 { 350 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 351 struct tegra_gpio *gpio = to_tegra_gpio(gc); 352 void __iomem *base; 353 354 base = tegra186_gpio_get_base(gpio, data->hwirq); 355 if (WARN_ON(base == NULL)) 356 return; 357 358 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 359 } 360 361 static void tegra186_irq_mask(struct irq_data *data) 362 { 363 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 364 struct tegra_gpio *gpio = to_tegra_gpio(gc); 365 void __iomem *base; 366 u32 value; 367 368 base = tegra186_gpio_get_base(gpio, data->hwirq); 369 if (WARN_ON(base == NULL)) 370 return; 371 372 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 373 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 374 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 375 } 376 377 static void tegra186_irq_unmask(struct irq_data *data) 378 { 379 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 380 struct tegra_gpio *gpio = to_tegra_gpio(gc); 381 void __iomem *base; 382 u32 value; 383 384 base = tegra186_gpio_get_base(gpio, data->hwirq); 385 if (WARN_ON(base == NULL)) 386 return; 387 388 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 389 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 390 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 391 } 392 393 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 394 { 395 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 396 struct tegra_gpio *gpio = to_tegra_gpio(gc); 397 void __iomem *base; 398 u32 value; 399 400 base = tegra186_gpio_get_base(gpio, data->hwirq); 401 if (WARN_ON(base == NULL)) 402 return -ENODEV; 403 404 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 405 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 406 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 407 408 switch (type & IRQ_TYPE_SENSE_MASK) { 409 case IRQ_TYPE_NONE: 410 break; 411 412 case IRQ_TYPE_EDGE_RISING: 413 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 414 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 415 break; 416 417 case IRQ_TYPE_EDGE_FALLING: 418 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 419 break; 420 421 case IRQ_TYPE_EDGE_BOTH: 422 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 423 break; 424 425 case IRQ_TYPE_LEVEL_HIGH: 426 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 427 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 428 break; 429 430 case IRQ_TYPE_LEVEL_LOW: 431 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 432 break; 433 434 default: 435 return -EINVAL; 436 } 437 438 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 439 440 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 441 irq_set_handler_locked(data, handle_level_irq); 442 else 443 irq_set_handler_locked(data, handle_edge_irq); 444 445 if (data->parent_data) 446 return irq_chip_set_type_parent(data, type); 447 448 return 0; 449 } 450 451 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 452 { 453 if (data->parent_data) 454 return irq_chip_set_wake_parent(data, on); 455 456 return 0; 457 } 458 459 static void tegra186_gpio_irq(struct irq_desc *desc) 460 { 461 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 462 struct irq_domain *domain = gpio->gpio.irq.domain; 463 struct irq_chip *chip = irq_desc_get_chip(desc); 464 unsigned int parent = irq_desc_get_irq(desc); 465 unsigned int i, j, offset = 0; 466 467 chained_irq_enter(chip, desc); 468 469 for (i = 0; i < gpio->soc->num_ports; i++) { 470 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 471 unsigned int pin; 472 unsigned long value; 473 void __iomem *base; 474 475 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 476 477 /* skip ports that are not associated with this bank */ 478 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 479 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) 480 break; 481 } 482 483 if (j == gpio->num_irqs_per_bank) 484 goto skip; 485 486 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 487 488 for_each_set_bit(pin, &value, port->pins) { 489 int ret = generic_handle_domain_irq(domain, offset + pin); 490 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); 491 } 492 493 skip: 494 offset += port->pins; 495 } 496 497 chained_irq_exit(chip, desc); 498 } 499 500 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 501 struct irq_fwspec *fwspec, 502 unsigned long *hwirq, 503 unsigned int *type) 504 { 505 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 506 unsigned int port, pin, i, offset = 0; 507 508 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 509 return -EINVAL; 510 511 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 512 return -EINVAL; 513 514 port = fwspec->param[0] / 8; 515 pin = fwspec->param[0] % 8; 516 517 if (port >= gpio->soc->num_ports) 518 return -EINVAL; 519 520 for (i = 0; i < port; i++) 521 offset += gpio->soc->ports[i].pins; 522 523 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 524 *hwirq = offset + pin; 525 526 return 0; 527 } 528 529 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 530 unsigned int parent_hwirq, 531 unsigned int parent_type) 532 { 533 struct tegra_gpio *gpio = gpiochip_get_data(chip); 534 struct irq_fwspec *fwspec; 535 536 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); 537 if (!fwspec) 538 return NULL; 539 540 fwspec->fwnode = chip->irq.parent_domain->fwnode; 541 fwspec->param_count = 3; 542 fwspec->param[0] = gpio->soc->instance; 543 fwspec->param[1] = parent_hwirq; 544 fwspec->param[2] = parent_type; 545 546 return fwspec; 547 } 548 549 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 550 unsigned int hwirq, 551 unsigned int type, 552 unsigned int *parent_hwirq, 553 unsigned int *parent_type) 554 { 555 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 556 *parent_type = type; 557 558 return 0; 559 } 560 561 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 562 unsigned int offset) 563 { 564 struct tegra_gpio *gpio = gpiochip_get_data(chip); 565 unsigned int i; 566 567 for (i = 0; i < gpio->soc->num_ports; i++) { 568 if (offset < gpio->soc->ports[i].pins) 569 break; 570 571 offset -= gpio->soc->ports[i].pins; 572 } 573 574 return offset + i * 8; 575 } 576 577 static const struct of_device_id tegra186_pmc_of_match[] = { 578 { .compatible = "nvidia,tegra186-pmc" }, 579 { .compatible = "nvidia,tegra194-pmc" }, 580 { /* sentinel */ } 581 }; 582 583 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 584 { 585 struct device *dev = gpio->gpio.parent; 586 unsigned int i, j; 587 u32 value; 588 589 for (i = 0; i < gpio->soc->num_ports; i++) { 590 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 591 unsigned int offset, p = port->port; 592 void __iomem *base; 593 594 base = gpio->secure + port->bank * 0x1000 + 0x800; 595 596 value = readl(base + TEGRA186_GPIO_CTL_SCR); 597 598 /* 599 * For controllers that haven't been locked down yet, make 600 * sure to program the default interrupt route mapping. 601 */ 602 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 603 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 604 /* 605 * On Tegra194 and later, each pin can be routed to one or more 606 * interrupts. 607 */ 608 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 609 dev_dbg(dev, "programming default interrupt routing for port %s\n", 610 port->name); 611 612 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); 613 614 /* 615 * By default we only want to route GPIO pins to IRQ 0. This works 616 * only under the assumption that we're running as the host kernel 617 * and hence all GPIO pins are owned by Linux. 618 * 619 * For cases where Linux is the guest OS, the hypervisor will have 620 * to configure the interrupt routing and pass only the valid 621 * interrupts via device tree. 622 */ 623 if (j == 0) { 624 value = readl(base + offset); 625 value = BIT(port->pins) - 1; 626 writel(value, base + offset); 627 } 628 } 629 } 630 } 631 } 632 633 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) 634 { 635 struct device *dev = gpio->gpio.parent; 636 637 if (gpio->num_irq > gpio->num_banks) { 638 if (gpio->num_irq % gpio->num_banks != 0) 639 goto error; 640 } 641 642 if (gpio->num_irq < gpio->num_banks) 643 goto error; 644 645 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; 646 647 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) 648 goto error; 649 650 return 0; 651 652 error: 653 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", 654 gpio->num_irq, gpio->num_banks); 655 return -EINVAL; 656 } 657 658 static int tegra186_gpio_probe(struct platform_device *pdev) 659 { 660 unsigned int i, j, offset; 661 struct gpio_irq_chip *irq; 662 struct tegra_gpio *gpio; 663 struct device_node *np; 664 char **names; 665 int err; 666 667 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 668 if (!gpio) 669 return -ENOMEM; 670 671 gpio->soc = device_get_match_data(&pdev->dev); 672 gpio->gpio.label = gpio->soc->name; 673 gpio->gpio.parent = &pdev->dev; 674 675 /* count the number of banks in the controller */ 676 for (i = 0; i < gpio->soc->num_ports; i++) 677 if (gpio->soc->ports[i].bank > gpio->num_banks) 678 gpio->num_banks = gpio->soc->ports[i].bank; 679 680 gpio->num_banks++; 681 682 /* get register apertures */ 683 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); 684 if (IS_ERR(gpio->secure)) { 685 gpio->secure = devm_platform_ioremap_resource(pdev, 0); 686 if (IS_ERR(gpio->secure)) 687 return PTR_ERR(gpio->secure); 688 } 689 690 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); 691 if (IS_ERR(gpio->base)) { 692 gpio->base = devm_platform_ioremap_resource(pdev, 1); 693 if (IS_ERR(gpio->base)) 694 return PTR_ERR(gpio->base); 695 } 696 697 err = platform_irq_count(pdev); 698 if (err < 0) 699 return err; 700 701 gpio->num_irq = err; 702 703 err = tegra186_gpio_irqs_per_bank(gpio); 704 if (err < 0) 705 return err; 706 707 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 708 GFP_KERNEL); 709 if (!gpio->irq) 710 return -ENOMEM; 711 712 for (i = 0; i < gpio->num_irq; i++) { 713 err = platform_get_irq(pdev, i); 714 if (err < 0) 715 return err; 716 717 gpio->irq[i] = err; 718 } 719 720 gpio->gpio.request = gpiochip_generic_request; 721 gpio->gpio.free = gpiochip_generic_free; 722 gpio->gpio.get_direction = tegra186_gpio_get_direction; 723 gpio->gpio.direction_input = tegra186_gpio_direction_input; 724 gpio->gpio.direction_output = tegra186_gpio_direction_output; 725 gpio->gpio.get = tegra186_gpio_get; 726 gpio->gpio.set = tegra186_gpio_set; 727 gpio->gpio.set_config = tegra186_gpio_set_config; 728 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 729 730 gpio->gpio.base = -1; 731 732 for (i = 0; i < gpio->soc->num_ports; i++) 733 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 734 735 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 736 sizeof(*names), GFP_KERNEL); 737 if (!names) 738 return -ENOMEM; 739 740 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 741 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 742 char *name; 743 744 for (j = 0; j < port->pins; j++) { 745 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 746 "P%s.%02x", port->name, j); 747 if (!name) 748 return -ENOMEM; 749 750 names[offset + j] = name; 751 } 752 753 offset += port->pins; 754 } 755 756 gpio->gpio.names = (const char * const *)names; 757 758 #if defined(CONFIG_OF_GPIO) 759 gpio->gpio.of_gpio_n_cells = 2; 760 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 761 #endif /* CONFIG_OF_GPIO */ 762 763 gpio->intc.name = dev_name(&pdev->dev); 764 gpio->intc.irq_ack = tegra186_irq_ack; 765 gpio->intc.irq_mask = tegra186_irq_mask; 766 gpio->intc.irq_unmask = tegra186_irq_unmask; 767 gpio->intc.irq_set_type = tegra186_irq_set_type; 768 gpio->intc.irq_set_wake = tegra186_irq_set_wake; 769 770 irq = &gpio->gpio.irq; 771 irq->chip = &gpio->intc; 772 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); 773 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 774 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 775 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 776 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 777 irq->handler = handle_simple_irq; 778 irq->default_type = IRQ_TYPE_NONE; 779 irq->parent_handler = tegra186_gpio_irq; 780 irq->parent_handler_data = gpio; 781 irq->num_parents = gpio->num_irq; 782 783 /* 784 * To simplify things, use a single interrupt per bank for now. Some 785 * chips support up to 8 interrupts per bank, which can be useful to 786 * distribute the load and decrease the processing latency for GPIOs 787 * but it also requires a more complicated interrupt routing than we 788 * currently program. 789 */ 790 if (gpio->num_irqs_per_bank > 1) { 791 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, 792 sizeof(*irq->parents), GFP_KERNEL); 793 if (!irq->parents) 794 return -ENOMEM; 795 796 for (i = 0; i < gpio->num_banks; i++) 797 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; 798 799 irq->num_parents = gpio->num_banks; 800 } else { 801 irq->num_parents = gpio->num_irq; 802 irq->parents = gpio->irq; 803 } 804 805 if (gpio->soc->num_irqs_per_bank > 1) 806 tegra186_gpio_init_route_mapping(gpio); 807 808 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 809 if (np) { 810 irq->parent_domain = irq_find_host(np); 811 of_node_put(np); 812 813 if (!irq->parent_domain) 814 return -EPROBE_DEFER; 815 } 816 817 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 818 sizeof(*irq->map), GFP_KERNEL); 819 if (!irq->map) 820 return -ENOMEM; 821 822 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 823 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 824 825 for (j = 0; j < port->pins; j++) 826 irq->map[offset + j] = irq->parents[port->bank]; 827 828 offset += port->pins; 829 } 830 831 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 832 } 833 834 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 835 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ 836 .name = #_name, \ 837 .bank = _bank, \ 838 .port = _port, \ 839 .pins = _pins, \ 840 } 841 842 static const struct tegra_gpio_port tegra186_main_ports[] = { 843 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 844 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 845 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 846 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 847 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 848 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 849 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 850 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 851 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 852 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 853 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 854 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 855 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 856 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 857 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 858 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 859 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 860 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 861 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 862 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 863 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 864 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 865 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 866 }; 867 868 static const struct tegra_gpio_soc tegra186_main_soc = { 869 .num_ports = ARRAY_SIZE(tegra186_main_ports), 870 .ports = tegra186_main_ports, 871 .name = "tegra186-gpio", 872 .instance = 0, 873 .num_irqs_per_bank = 1, 874 }; 875 876 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 877 [TEGRA186_AON_GPIO_PORT_##_name] = { \ 878 .name = #_name, \ 879 .bank = _bank, \ 880 .port = _port, \ 881 .pins = _pins, \ 882 } 883 884 static const struct tegra_gpio_port tegra186_aon_ports[] = { 885 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 886 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 887 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 888 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 889 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 890 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 891 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 892 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 893 }; 894 895 static const struct tegra_gpio_soc tegra186_aon_soc = { 896 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 897 .ports = tegra186_aon_ports, 898 .name = "tegra186-gpio-aon", 899 .instance = 1, 900 .num_irqs_per_bank = 1, 901 }; 902 903 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 904 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ 905 .name = #_name, \ 906 .bank = _bank, \ 907 .port = _port, \ 908 .pins = _pins, \ 909 } 910 911 static const struct tegra_gpio_port tegra194_main_ports[] = { 912 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 913 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 914 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 915 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 916 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 917 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 918 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 919 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 920 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 921 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 922 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 923 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 924 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 925 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 926 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 927 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 928 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 929 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 930 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 931 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 932 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 933 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 934 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 935 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 936 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 937 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 938 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 939 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 940 }; 941 942 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 943 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 944 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 945 }; 946 947 static const struct tegra_gpio_soc tegra194_main_soc = { 948 .num_ports = ARRAY_SIZE(tegra194_main_ports), 949 .ports = tegra194_main_ports, 950 .name = "tegra194-gpio", 951 .instance = 0, 952 .num_irqs_per_bank = 8, 953 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 954 .pin_ranges = tegra194_main_pin_ranges, 955 .pinmux = "nvidia,tegra194-pinmux", 956 }; 957 958 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 959 [TEGRA194_AON_GPIO_PORT_##_name] = { \ 960 .name = #_name, \ 961 .bank = _bank, \ 962 .port = _port, \ 963 .pins = _pins, \ 964 } 965 966 static const struct tegra_gpio_port tegra194_aon_ports[] = { 967 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 968 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 969 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 970 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 971 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 972 }; 973 974 static const struct tegra_gpio_soc tegra194_aon_soc = { 975 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 976 .ports = tegra194_aon_ports, 977 .name = "tegra194-gpio-aon", 978 .instance = 1, 979 .num_irqs_per_bank = 8, 980 }; 981 982 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 983 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \ 984 .name = #_name, \ 985 .bank = _bank, \ 986 .port = _port, \ 987 .pins = _pins, \ 988 } 989 990 static const struct tegra_gpio_port tegra234_main_ports[] = { 991 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8), 992 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1), 993 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8), 994 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4), 995 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8), 996 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6), 997 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8), 998 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8), 999 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7), 1000 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6), 1001 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8), 1002 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4), 1003 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8), 1004 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8), 1005 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8), 1006 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8), 1007 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6), 1008 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8), 1009 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8), 1010 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8), 1011 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8), 1012 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4), 1013 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2), 1014 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4), 1015 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8), 1016 }; 1017 1018 static const struct tegra_gpio_soc tegra234_main_soc = { 1019 .num_ports = ARRAY_SIZE(tegra234_main_ports), 1020 .ports = tegra234_main_ports, 1021 .name = "tegra234-gpio", 1022 .instance = 0, 1023 .num_irqs_per_bank = 8, 1024 }; 1025 1026 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1027 [TEGRA234_AON_GPIO_PORT_##_name] = { \ 1028 .name = #_name, \ 1029 .bank = _bank, \ 1030 .port = _port, \ 1031 .pins = _pins, \ 1032 } 1033 1034 static const struct tegra_gpio_port tegra234_aon_ports[] = { 1035 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8), 1036 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4), 1037 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8), 1038 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3), 1039 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8), 1040 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1), 1041 }; 1042 1043 static const struct tegra_gpio_soc tegra234_aon_soc = { 1044 .num_ports = ARRAY_SIZE(tegra234_aon_ports), 1045 .ports = tegra234_aon_ports, 1046 .name = "tegra234-gpio-aon", 1047 .instance = 1, 1048 .num_irqs_per_bank = 8, 1049 }; 1050 1051 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1052 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \ 1053 .name = #_name, \ 1054 .bank = _bank, \ 1055 .port = _port, \ 1056 .pins = _pins, \ 1057 } 1058 1059 static const struct tegra_gpio_port tegra241_main_ports[] = { 1060 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8), 1061 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8), 1062 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2), 1063 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6), 1064 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8), 1065 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8), 1066 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8), 1067 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8), 1068 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8), 1069 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4), 1070 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6), 1071 }; 1072 1073 static const struct tegra_gpio_soc tegra241_main_soc = { 1074 .num_ports = ARRAY_SIZE(tegra241_main_ports), 1075 .ports = tegra241_main_ports, 1076 .name = "tegra241-gpio", 1077 .instance = 0, 1078 .num_irqs_per_bank = 8, 1079 }; 1080 1081 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1082 [TEGRA241_AON_GPIO_PORT_##_name] = { \ 1083 .name = #_name, \ 1084 .bank = _bank, \ 1085 .port = _port, \ 1086 .pins = _pins, \ 1087 } 1088 1089 static const struct tegra_gpio_port tegra241_aon_ports[] = { 1090 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8), 1091 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4), 1092 }; 1093 1094 static const struct tegra_gpio_soc tegra241_aon_soc = { 1095 .num_ports = ARRAY_SIZE(tegra241_aon_ports), 1096 .ports = tegra241_aon_ports, 1097 .name = "tegra241-gpio-aon", 1098 .instance = 1, 1099 .num_irqs_per_bank = 8, 1100 }; 1101 1102 static const struct of_device_id tegra186_gpio_of_match[] = { 1103 { 1104 .compatible = "nvidia,tegra186-gpio", 1105 .data = &tegra186_main_soc 1106 }, { 1107 .compatible = "nvidia,tegra186-gpio-aon", 1108 .data = &tegra186_aon_soc 1109 }, { 1110 .compatible = "nvidia,tegra194-gpio", 1111 .data = &tegra194_main_soc 1112 }, { 1113 .compatible = "nvidia,tegra194-gpio-aon", 1114 .data = &tegra194_aon_soc 1115 }, { 1116 .compatible = "nvidia,tegra234-gpio", 1117 .data = &tegra234_main_soc 1118 }, { 1119 .compatible = "nvidia,tegra234-gpio-aon", 1120 .data = &tegra234_aon_soc 1121 }, { 1122 /* sentinel */ 1123 } 1124 }; 1125 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 1126 1127 static const struct acpi_device_id tegra186_gpio_acpi_match[] = { 1128 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc }, 1129 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc }, 1130 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc }, 1131 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, 1132 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, 1133 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, 1134 {} 1135 }; 1136 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); 1137 1138 static struct platform_driver tegra186_gpio_driver = { 1139 .driver = { 1140 .name = "tegra186-gpio", 1141 .of_match_table = tegra186_gpio_of_match, 1142 .acpi_match_table = tegra186_gpio_acpi_match, 1143 }, 1144 .probe = tegra186_gpio_probe, 1145 }; 1146 module_platform_driver(tegra186_gpio_driver); 1147 1148 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 1149 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1150 MODULE_LICENSE("GPL v2"); 1151