1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <asm/cpu.h> 77 #include <asm/cpufeature.h> 78 #include <asm/cpu_ops.h> 79 #include <asm/fpsimd.h> 80 #include <asm/insn.h> 81 #include <asm/kvm_host.h> 82 #include <asm/mmu_context.h> 83 #include <asm/mte.h> 84 #include <asm/processor.h> 85 #include <asm/smp.h> 86 #include <asm/sysreg.h> 87 #include <asm/traps.h> 88 #include <asm/virt.h> 89 90 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 91 static unsigned long elf_hwcap __read_mostly; 92 93 #ifdef CONFIG_COMPAT 94 #define COMPAT_ELF_HWCAP_DEFAULT \ 95 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 96 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 97 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 98 COMPAT_HWCAP_LPAE) 99 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 100 unsigned int compat_elf_hwcap2 __read_mostly; 101 #endif 102 103 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 104 EXPORT_SYMBOL(cpu_hwcaps); 105 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 106 107 /* Need also bit for ARM64_CB_PATCH */ 108 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 109 110 bool arm64_use_ng_mappings = false; 111 EXPORT_SYMBOL(arm64_use_ng_mappings); 112 113 /* 114 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 115 * support it? 116 */ 117 static bool __read_mostly allow_mismatched_32bit_el0; 118 119 /* 120 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 121 * seen at least one CPU capable of 32-bit EL0. 122 */ 123 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 124 125 /* 126 * Mask of CPUs supporting 32-bit EL0. 127 * Only valid if arm64_mismatched_32bit_el0 is enabled. 128 */ 129 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 130 131 /* 132 * Flag to indicate if we have computed the system wide 133 * capabilities based on the boot time active CPUs. This 134 * will be used to determine if a new booting CPU should 135 * go through the verification process to make sure that it 136 * supports the system capabilities, without using a hotplug 137 * notifier. This is also used to decide if we could use 138 * the fast path for checking constant CPU caps. 139 */ 140 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 141 EXPORT_SYMBOL(arm64_const_caps_ready); 142 static inline void finalize_system_capabilities(void) 143 { 144 static_branch_enable(&arm64_const_caps_ready); 145 } 146 147 void dump_cpu_features(void) 148 { 149 /* file-wide pr_fmt adds "CPU features: " prefix */ 150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 151 } 152 153 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 154 EXPORT_SYMBOL(cpu_hwcap_keys); 155 156 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 157 { \ 158 .sign = SIGNED, \ 159 .visible = VISIBLE, \ 160 .strict = STRICT, \ 161 .type = TYPE, \ 162 .shift = SHIFT, \ 163 .width = WIDTH, \ 164 .safe_val = SAFE_VAL, \ 165 } 166 167 /* Define a feature with unsigned values */ 168 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 169 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 170 171 /* Define a feature with a signed value */ 172 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 173 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 174 175 #define ARM64_FTR_END \ 176 { \ 177 .width = 0, \ 178 } 179 180 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 181 182 static bool __system_matches_cap(unsigned int n); 183 184 /* 185 * NOTE: Any changes to the visibility of features should be kept in 186 * sync with the documentation of the CPU feature register ABI. 187 */ 188 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 203 ARM64_FTR_END, 204 }; 205 206 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 216 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 221 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 223 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 225 ARM64_FTR_END, 226 }; 227 228 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), 230 ARM64_FTR_END, 231 }; 232 233 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 241 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 244 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 245 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 250 ARM64_FTR_END, 251 }; 252 253 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 257 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 259 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 260 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 261 ARM64_FTR_END, 262 }; 263 264 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 268 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 270 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 283 ARM64_FTR_END, 284 }; 285 286 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 287 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 290 /* 291 * Page size not being supported at Stage-2 is not fatal. You 292 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 293 * your favourite nesting hypervisor. 294 * 295 * There is a small corner case where the hypervisor explicitly 296 * advertises a given granule size at Stage-2 (value 2) on some 297 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 298 * vCPUs. Although this is not forbidden by the architecture, it 299 * indicates that the hypervisor is being silly (or buggy). 300 * 301 * We make no effort to cope with this and pretend that if these 302 * fields are inconsistent across vCPUs, then it isn't worth 303 * trying to bring KVM up. 304 */ 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 308 /* 309 * We already refuse to boot CPUs that don't support our configured 310 * page size, so we can only detect mismatches for a page size other 311 * than the one we're currently using. Unfortunately, SoCs like this 312 * exist in the wild so, even though we don't like it, we'll have to go 313 * along with it and treat them as non-strict. 314 */ 315 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 316 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 318 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 320 /* Linux shouldn't care about secure memory */ 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 324 /* 325 * Differing PARange is fine as long as all peripherals and memory are mapped 326 * within the minimum PARange of all CPUs 327 */ 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 329 ARM64_FTR_END, 330 }; 331 332 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 333 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 344 ARM64_FTR_END, 345 }; 346 347 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 363 ARM64_FTR_END, 364 }; 365 366 static const struct arm64_ftr_bits ftr_ctr[] = { 367 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 368 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 369 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 370 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 373 /* 374 * Linux can handle differing I-cache policies. Userspace JITs will 375 * make use of *minLine. 376 * If we have differing I-cache policies, report it as the weakest - VIPT. 377 */ 378 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 379 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 380 ARM64_FTR_END, 381 }; 382 383 static struct arm64_ftr_override __ro_after_init no_override = { }; 384 385 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 386 .name = "SYS_CTR_EL0", 387 .ftr_bits = ftr_ctr, 388 .override = &no_override, 389 }; 390 391 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 392 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 396 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 397 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 398 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 400 ARM64_FTR_END, 401 }; 402 403 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 404 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 409 /* 410 * We can instantiate multiple PMU instances with different levels 411 * of support. 412 */ 413 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 415 ARM64_FTR_END, 416 }; 417 418 static const struct arm64_ftr_bits ftr_mvfr2[] = { 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 421 ARM64_FTR_END, 422 }; 423 424 static const struct arm64_ftr_bits ftr_dczid[] = { 425 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 426 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 427 ARM64_FTR_END, 428 }; 429 430 static const struct arm64_ftr_bits ftr_gmid[] = { 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0), 432 ARM64_FTR_END, 433 }; 434 435 static const struct arm64_ftr_bits ftr_id_isar0[] = { 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 443 ARM64_FTR_END, 444 }; 445 446 static const struct arm64_ftr_bits ftr_id_isar5[] = { 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 453 ARM64_FTR_END, 454 }; 455 456 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 464 465 /* 466 * SpecSEI = 1 indicates that the PE might generate an SError on an 467 * external abort on speculative read. It is safe to assume that an 468 * SError might be generated than it will not be. Hence it has been 469 * classified as FTR_HIGHER_SAFE. 470 */ 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 472 ARM64_FTR_END, 473 }; 474 475 static const struct arm64_ftr_bits ftr_id_isar4[] = { 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 484 ARM64_FTR_END, 485 }; 486 487 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 489 ARM64_FTR_END, 490 }; 491 492 static const struct arm64_ftr_bits ftr_id_isar6[] = { 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 500 ARM64_FTR_END, 501 }; 502 503 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 510 ARM64_FTR_END, 511 }; 512 513 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 522 ARM64_FTR_END, 523 }; 524 525 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 528 ARM64_FTR_END, 529 }; 530 531 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 532 /* [31:28] TraceFilt */ 533 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 540 ARM64_FTR_END, 541 }; 542 543 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 544 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 545 ARM64_FTR_END, 546 }; 547 548 static const struct arm64_ftr_bits ftr_zcr[] = { 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 550 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 551 ARM64_FTR_END, 552 }; 553 554 /* 555 * Common ftr bits for a 32bit register with all hidden, strict 556 * attributes, with 4bit feature fields and a default safe value of 557 * 0. Covers the following 32bit registers: 558 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 559 */ 560 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 569 ARM64_FTR_END, 570 }; 571 572 /* Table for a single 32bit feature value */ 573 static const struct arm64_ftr_bits ftr_single32[] = { 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 575 ARM64_FTR_END, 576 }; 577 578 static const struct arm64_ftr_bits ftr_raz[] = { 579 ARM64_FTR_END, 580 }; 581 582 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 583 .sys_id = id, \ 584 .reg = &(struct arm64_ftr_reg){ \ 585 .name = id_str, \ 586 .override = (ovr), \ 587 .ftr_bits = &((table)[0]), \ 588 }} 589 590 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 591 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 592 593 #define ARM64_FTR_REG(id, table) \ 594 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 595 596 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 597 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 598 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 599 600 static const struct __ftr_reg_entry { 601 u32 sys_id; 602 struct arm64_ftr_reg *reg; 603 } arm64_ftr_regs[] = { 604 605 /* Op1 = 0, CRn = 0, CRm = 1 */ 606 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 607 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 608 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 609 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 610 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 611 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 612 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 613 614 /* Op1 = 0, CRn = 0, CRm = 2 */ 615 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 616 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 617 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 618 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 619 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 620 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 621 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 622 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 623 624 /* Op1 = 0, CRn = 0, CRm = 3 */ 625 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 626 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 627 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 628 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 629 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 630 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 631 632 /* Op1 = 0, CRn = 0, CRm = 4 */ 633 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 634 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 635 &id_aa64pfr1_override), 636 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 637 638 /* Op1 = 0, CRn = 0, CRm = 5 */ 639 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 640 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 641 642 /* Op1 = 0, CRn = 0, CRm = 6 */ 643 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 644 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 645 &id_aa64isar1_override), 646 ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2), 647 648 /* Op1 = 0, CRn = 0, CRm = 7 */ 649 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 650 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 651 &id_aa64mmfr1_override), 652 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 653 654 /* Op1 = 0, CRn = 1, CRm = 2 */ 655 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 656 657 /* Op1 = 1, CRn = 0, CRm = 0 */ 658 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 659 660 /* Op1 = 3, CRn = 0, CRm = 0 */ 661 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 662 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 663 664 /* Op1 = 3, CRn = 14, CRm = 0 */ 665 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 666 }; 667 668 static int search_cmp_ftr_reg(const void *id, const void *regp) 669 { 670 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 671 } 672 673 /* 674 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 675 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 676 * ascending order of sys_id, we use binary search to find a matching 677 * entry. 678 * 679 * returns - Upon success, matching ftr_reg entry for id. 680 * - NULL on failure. It is upto the caller to decide 681 * the impact of a failure. 682 */ 683 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 684 { 685 const struct __ftr_reg_entry *ret; 686 687 ret = bsearch((const void *)(unsigned long)sys_id, 688 arm64_ftr_regs, 689 ARRAY_SIZE(arm64_ftr_regs), 690 sizeof(arm64_ftr_regs[0]), 691 search_cmp_ftr_reg); 692 if (ret) 693 return ret->reg; 694 return NULL; 695 } 696 697 /* 698 * get_arm64_ftr_reg - Looks up a feature register entry using 699 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 700 * 701 * returns - Upon success, matching ftr_reg entry for id. 702 * - NULL on failure but with an WARN_ON(). 703 */ 704 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 705 { 706 struct arm64_ftr_reg *reg; 707 708 reg = get_arm64_ftr_reg_nowarn(sys_id); 709 710 /* 711 * Requesting a non-existent register search is an error. Warn 712 * and let the caller handle it. 713 */ 714 WARN_ON(!reg); 715 return reg; 716 } 717 718 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 719 s64 ftr_val) 720 { 721 u64 mask = arm64_ftr_mask(ftrp); 722 723 reg &= ~mask; 724 reg |= (ftr_val << ftrp->shift) & mask; 725 return reg; 726 } 727 728 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 729 s64 cur) 730 { 731 s64 ret = 0; 732 733 switch (ftrp->type) { 734 case FTR_EXACT: 735 ret = ftrp->safe_val; 736 break; 737 case FTR_LOWER_SAFE: 738 ret = min(new, cur); 739 break; 740 case FTR_HIGHER_OR_ZERO_SAFE: 741 if (!cur || !new) 742 break; 743 fallthrough; 744 case FTR_HIGHER_SAFE: 745 ret = max(new, cur); 746 break; 747 default: 748 BUG(); 749 } 750 751 return ret; 752 } 753 754 static void __init sort_ftr_regs(void) 755 { 756 unsigned int i; 757 758 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 759 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 760 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 761 unsigned int j = 0; 762 763 /* 764 * Features here must be sorted in descending order with respect 765 * to their shift values and should not overlap with each other. 766 */ 767 for (; ftr_bits->width != 0; ftr_bits++, j++) { 768 unsigned int width = ftr_reg->ftr_bits[j].width; 769 unsigned int shift = ftr_reg->ftr_bits[j].shift; 770 unsigned int prev_shift; 771 772 WARN((shift + width) > 64, 773 "%s has invalid feature at shift %d\n", 774 ftr_reg->name, shift); 775 776 /* 777 * Skip the first feature. There is nothing to 778 * compare against for now. 779 */ 780 if (j == 0) 781 continue; 782 783 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 784 WARN((shift + width) > prev_shift, 785 "%s has feature overlap at shift %d\n", 786 ftr_reg->name, shift); 787 } 788 789 /* 790 * Skip the first register. There is nothing to 791 * compare against for now. 792 */ 793 if (i == 0) 794 continue; 795 /* 796 * Registers here must be sorted in ascending order with respect 797 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 798 * to work correctly. 799 */ 800 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 801 } 802 } 803 804 /* 805 * Initialise the CPU feature register from Boot CPU values. 806 * Also initiliases the strict_mask for the register. 807 * Any bits that are not covered by an arm64_ftr_bits entry are considered 808 * RES0 for the system-wide value, and must strictly match. 809 */ 810 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 811 { 812 u64 val = 0; 813 u64 strict_mask = ~0x0ULL; 814 u64 user_mask = 0; 815 u64 valid_mask = 0; 816 817 const struct arm64_ftr_bits *ftrp; 818 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 819 820 if (!reg) 821 return; 822 823 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 824 u64 ftr_mask = arm64_ftr_mask(ftrp); 825 s64 ftr_new = arm64_ftr_value(ftrp, new); 826 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 827 828 if ((ftr_mask & reg->override->mask) == ftr_mask) { 829 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 830 char *str = NULL; 831 832 if (ftr_ovr != tmp) { 833 /* Unsafe, remove the override */ 834 reg->override->mask &= ~ftr_mask; 835 reg->override->val &= ~ftr_mask; 836 tmp = ftr_ovr; 837 str = "ignoring override"; 838 } else if (ftr_new != tmp) { 839 /* Override was valid */ 840 ftr_new = tmp; 841 str = "forced"; 842 } else if (ftr_ovr == tmp) { 843 /* Override was the safe value */ 844 str = "already set"; 845 } 846 847 if (str) 848 pr_warn("%s[%d:%d]: %s to %llx\n", 849 reg->name, 850 ftrp->shift + ftrp->width - 1, 851 ftrp->shift, str, tmp); 852 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 853 reg->override->val &= ~ftr_mask; 854 pr_warn("%s[%d:%d]: impossible override, ignored\n", 855 reg->name, 856 ftrp->shift + ftrp->width - 1, 857 ftrp->shift); 858 } 859 860 val = arm64_ftr_set_value(ftrp, val, ftr_new); 861 862 valid_mask |= ftr_mask; 863 if (!ftrp->strict) 864 strict_mask &= ~ftr_mask; 865 if (ftrp->visible) 866 user_mask |= ftr_mask; 867 else 868 reg->user_val = arm64_ftr_set_value(ftrp, 869 reg->user_val, 870 ftrp->safe_val); 871 } 872 873 val &= valid_mask; 874 875 reg->sys_val = val; 876 reg->strict_mask = strict_mask; 877 reg->user_mask = user_mask; 878 } 879 880 extern const struct arm64_cpu_capabilities arm64_errata[]; 881 static const struct arm64_cpu_capabilities arm64_features[]; 882 883 static void __init 884 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 885 { 886 for (; caps->matches; caps++) { 887 if (WARN(caps->capability >= ARM64_NCAPS, 888 "Invalid capability %d\n", caps->capability)) 889 continue; 890 if (WARN(cpu_hwcaps_ptrs[caps->capability], 891 "Duplicate entry for capability %d\n", 892 caps->capability)) 893 continue; 894 cpu_hwcaps_ptrs[caps->capability] = caps; 895 } 896 } 897 898 static void __init init_cpu_hwcaps_indirect_list(void) 899 { 900 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 901 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 902 } 903 904 static void __init setup_boot_cpu_capabilities(void); 905 906 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 907 { 908 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 909 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 910 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 911 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 912 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 913 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 914 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 915 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 916 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 917 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 918 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 919 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 920 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 921 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 922 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 923 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 924 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 925 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 926 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 927 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 928 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 929 } 930 931 void __init init_cpu_features(struct cpuinfo_arm64 *info) 932 { 933 /* Before we start using the tables, make sure it is sorted */ 934 sort_ftr_regs(); 935 936 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 937 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 938 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 939 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 940 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 941 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 942 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 943 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 944 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 945 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 946 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 947 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 948 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 949 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 950 951 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 952 init_32bit_cpu_features(&info->aarch32); 953 954 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 955 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 956 vec_init_vq_map(ARM64_VEC_SVE); 957 } 958 959 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 960 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 961 962 /* 963 * Initialize the indirect array of CPU hwcaps capabilities pointers 964 * before we handle the boot CPU below. 965 */ 966 init_cpu_hwcaps_indirect_list(); 967 968 /* 969 * Detect and enable early CPU capabilities based on the boot CPU, 970 * after we have initialised the CPU feature infrastructure. 971 */ 972 setup_boot_cpu_capabilities(); 973 } 974 975 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 976 { 977 const struct arm64_ftr_bits *ftrp; 978 979 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 980 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 981 s64 ftr_new = arm64_ftr_value(ftrp, new); 982 983 if (ftr_cur == ftr_new) 984 continue; 985 /* Find a safe value */ 986 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 987 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 988 } 989 990 } 991 992 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 993 { 994 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 995 996 if (!regp) 997 return 0; 998 999 update_cpu_ftr_reg(regp, val); 1000 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1001 return 0; 1002 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1003 regp->name, boot, cpu, val); 1004 return 1; 1005 } 1006 1007 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1008 { 1009 const struct arm64_ftr_bits *ftrp; 1010 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1011 1012 if (!regp) 1013 return; 1014 1015 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1016 if (ftrp->shift == field) { 1017 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1018 break; 1019 } 1020 } 1021 1022 /* Bogus field? */ 1023 WARN_ON(!ftrp->width); 1024 } 1025 1026 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1027 struct cpuinfo_arm64 *boot) 1028 { 1029 static bool boot_cpu_32bit_regs_overridden = false; 1030 1031 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1032 return; 1033 1034 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1035 return; 1036 1037 boot->aarch32 = info->aarch32; 1038 init_32bit_cpu_features(&boot->aarch32); 1039 boot_cpu_32bit_regs_overridden = true; 1040 } 1041 1042 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1043 struct cpuinfo_32bit *boot) 1044 { 1045 int taint = 0; 1046 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1047 1048 /* 1049 * If we don't have AArch32 at EL1, then relax the strictness of 1050 * EL1-dependent register fields to avoid spurious sanity check fails. 1051 */ 1052 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1053 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 1054 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 1055 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1056 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1057 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1058 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1059 } 1060 1061 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1062 info->reg_id_dfr0, boot->reg_id_dfr0); 1063 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1064 info->reg_id_dfr1, boot->reg_id_dfr1); 1065 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1066 info->reg_id_isar0, boot->reg_id_isar0); 1067 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1068 info->reg_id_isar1, boot->reg_id_isar1); 1069 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1070 info->reg_id_isar2, boot->reg_id_isar2); 1071 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1072 info->reg_id_isar3, boot->reg_id_isar3); 1073 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1074 info->reg_id_isar4, boot->reg_id_isar4); 1075 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1076 info->reg_id_isar5, boot->reg_id_isar5); 1077 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1078 info->reg_id_isar6, boot->reg_id_isar6); 1079 1080 /* 1081 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1082 * ACTLR formats could differ across CPUs and therefore would have to 1083 * be trapped for virtualization anyway. 1084 */ 1085 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1086 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1087 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1088 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1089 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1090 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1091 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1092 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1093 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1094 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1095 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1096 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1097 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1098 info->reg_id_pfr0, boot->reg_id_pfr0); 1099 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1100 info->reg_id_pfr1, boot->reg_id_pfr1); 1101 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1102 info->reg_id_pfr2, boot->reg_id_pfr2); 1103 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1104 info->reg_mvfr0, boot->reg_mvfr0); 1105 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1106 info->reg_mvfr1, boot->reg_mvfr1); 1107 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1108 info->reg_mvfr2, boot->reg_mvfr2); 1109 1110 return taint; 1111 } 1112 1113 /* 1114 * Update system wide CPU feature registers with the values from a 1115 * non-boot CPU. Also performs SANITY checks to make sure that there 1116 * aren't any insane variations from that of the boot CPU. 1117 */ 1118 void update_cpu_features(int cpu, 1119 struct cpuinfo_arm64 *info, 1120 struct cpuinfo_arm64 *boot) 1121 { 1122 int taint = 0; 1123 1124 /* 1125 * The kernel can handle differing I-cache policies, but otherwise 1126 * caches should look identical. Userspace JITs will make use of 1127 * *minLine. 1128 */ 1129 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1130 info->reg_ctr, boot->reg_ctr); 1131 1132 /* 1133 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1134 * could result in too much or too little memory being zeroed if a 1135 * process is preempted and migrated between CPUs. 1136 */ 1137 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1138 info->reg_dczid, boot->reg_dczid); 1139 1140 /* If different, timekeeping will be broken (especially with KVM) */ 1141 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1142 info->reg_cntfrq, boot->reg_cntfrq); 1143 1144 /* 1145 * The kernel uses self-hosted debug features and expects CPUs to 1146 * support identical debug features. We presently need CTX_CMPs, WRPs, 1147 * and BRPs to be identical. 1148 * ID_AA64DFR1 is currently RES0. 1149 */ 1150 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1151 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1152 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1153 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1154 /* 1155 * Even in big.LITTLE, processors should be identical instruction-set 1156 * wise. 1157 */ 1158 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1159 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1160 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1161 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1162 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1163 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1164 1165 /* 1166 * Differing PARange support is fine as long as all peripherals and 1167 * memory are mapped within the minimum PARange of all CPUs. 1168 * Linux should not care about secure memory. 1169 */ 1170 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1171 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1172 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1173 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1174 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1175 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1176 1177 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1178 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1179 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1180 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1181 1182 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1183 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1184 1185 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1186 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1187 info->reg_zcr, boot->reg_zcr); 1188 1189 /* Probe vector lengths, unless we already gave up on SVE */ 1190 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1191 !system_capabilities_finalized()) 1192 vec_update_vq_map(ARM64_VEC_SVE); 1193 } 1194 1195 /* 1196 * The kernel uses the LDGM/STGM instructions and the number of tags 1197 * they read/write depends on the GMID_EL1.BS field. Check that the 1198 * value is the same on all CPUs. 1199 */ 1200 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1201 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1202 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1203 info->reg_gmid, boot->reg_gmid); 1204 } 1205 1206 /* 1207 * If we don't have AArch32 at all then skip the checks entirely 1208 * as the register values may be UNKNOWN and we're not going to be 1209 * using them for anything. 1210 * 1211 * This relies on a sanitised view of the AArch64 ID registers 1212 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1213 */ 1214 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1215 lazy_init_32bit_cpu_features(info, boot); 1216 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1217 &boot->aarch32); 1218 } 1219 1220 /* 1221 * Mismatched CPU features are a recipe for disaster. Don't even 1222 * pretend to support them. 1223 */ 1224 if (taint) { 1225 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1226 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1227 } 1228 } 1229 1230 u64 read_sanitised_ftr_reg(u32 id) 1231 { 1232 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1233 1234 if (!regp) 1235 return 0; 1236 return regp->sys_val; 1237 } 1238 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1239 1240 #define read_sysreg_case(r) \ 1241 case r: val = read_sysreg_s(r); break; 1242 1243 /* 1244 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1245 * Read the system register on the current CPU 1246 */ 1247 u64 __read_sysreg_by_encoding(u32 sys_id) 1248 { 1249 struct arm64_ftr_reg *regp; 1250 u64 val; 1251 1252 switch (sys_id) { 1253 read_sysreg_case(SYS_ID_PFR0_EL1); 1254 read_sysreg_case(SYS_ID_PFR1_EL1); 1255 read_sysreg_case(SYS_ID_PFR2_EL1); 1256 read_sysreg_case(SYS_ID_DFR0_EL1); 1257 read_sysreg_case(SYS_ID_DFR1_EL1); 1258 read_sysreg_case(SYS_ID_MMFR0_EL1); 1259 read_sysreg_case(SYS_ID_MMFR1_EL1); 1260 read_sysreg_case(SYS_ID_MMFR2_EL1); 1261 read_sysreg_case(SYS_ID_MMFR3_EL1); 1262 read_sysreg_case(SYS_ID_MMFR4_EL1); 1263 read_sysreg_case(SYS_ID_MMFR5_EL1); 1264 read_sysreg_case(SYS_ID_ISAR0_EL1); 1265 read_sysreg_case(SYS_ID_ISAR1_EL1); 1266 read_sysreg_case(SYS_ID_ISAR2_EL1); 1267 read_sysreg_case(SYS_ID_ISAR3_EL1); 1268 read_sysreg_case(SYS_ID_ISAR4_EL1); 1269 read_sysreg_case(SYS_ID_ISAR5_EL1); 1270 read_sysreg_case(SYS_ID_ISAR6_EL1); 1271 read_sysreg_case(SYS_MVFR0_EL1); 1272 read_sysreg_case(SYS_MVFR1_EL1); 1273 read_sysreg_case(SYS_MVFR2_EL1); 1274 1275 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1276 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1277 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1278 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1279 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1280 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1281 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1282 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1283 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1284 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1285 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1286 1287 read_sysreg_case(SYS_CNTFRQ_EL0); 1288 read_sysreg_case(SYS_CTR_EL0); 1289 read_sysreg_case(SYS_DCZID_EL0); 1290 1291 default: 1292 BUG(); 1293 return 0; 1294 } 1295 1296 regp = get_arm64_ftr_reg(sys_id); 1297 if (regp) { 1298 val &= ~regp->override->mask; 1299 val |= (regp->override->val & regp->override->mask); 1300 } 1301 1302 return val; 1303 } 1304 1305 #include <linux/irqchip/arm-gic-v3.h> 1306 1307 static bool 1308 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1309 { 1310 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1311 1312 return val >= entry->min_field_value; 1313 } 1314 1315 static bool 1316 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1317 { 1318 u64 val; 1319 1320 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1321 if (scope == SCOPE_SYSTEM) 1322 val = read_sanitised_ftr_reg(entry->sys_reg); 1323 else 1324 val = __read_sysreg_by_encoding(entry->sys_reg); 1325 1326 return feature_matches(val, entry); 1327 } 1328 1329 const struct cpumask *system_32bit_el0_cpumask(void) 1330 { 1331 if (!system_supports_32bit_el0()) 1332 return cpu_none_mask; 1333 1334 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1335 return cpu_32bit_el0_mask; 1336 1337 return cpu_possible_mask; 1338 } 1339 1340 static int __init parse_32bit_el0_param(char *str) 1341 { 1342 allow_mismatched_32bit_el0 = true; 1343 return 0; 1344 } 1345 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1346 1347 static ssize_t aarch32_el0_show(struct device *dev, 1348 struct device_attribute *attr, char *buf) 1349 { 1350 const struct cpumask *mask = system_32bit_el0_cpumask(); 1351 1352 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1353 } 1354 static const DEVICE_ATTR_RO(aarch32_el0); 1355 1356 static int __init aarch32_el0_sysfs_init(void) 1357 { 1358 if (!allow_mismatched_32bit_el0) 1359 return 0; 1360 1361 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1362 } 1363 device_initcall(aarch32_el0_sysfs_init); 1364 1365 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1366 { 1367 if (!has_cpuid_feature(entry, scope)) 1368 return allow_mismatched_32bit_el0; 1369 1370 if (scope == SCOPE_SYSTEM) 1371 pr_info("detected: 32-bit EL0 Support\n"); 1372 1373 return true; 1374 } 1375 1376 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1377 { 1378 bool has_sre; 1379 1380 if (!has_cpuid_feature(entry, scope)) 1381 return false; 1382 1383 has_sre = gic_enable_sre(); 1384 if (!has_sre) 1385 pr_warn_once("%s present but disabled by higher exception level\n", 1386 entry->desc); 1387 1388 return has_sre; 1389 } 1390 1391 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1392 { 1393 u32 midr = read_cpuid_id(); 1394 1395 /* Cavium ThunderX pass 1.x and 2.x */ 1396 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1397 MIDR_CPU_VAR_REV(0, 0), 1398 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1399 } 1400 1401 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1402 { 1403 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1404 1405 return cpuid_feature_extract_signed_field(pfr0, 1406 ID_AA64PFR0_FP_SHIFT) < 0; 1407 } 1408 1409 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1410 int scope) 1411 { 1412 u64 ctr; 1413 1414 if (scope == SCOPE_SYSTEM) 1415 ctr = arm64_ftr_reg_ctrel0.sys_val; 1416 else 1417 ctr = read_cpuid_effective_cachetype(); 1418 1419 return ctr & BIT(CTR_IDC_SHIFT); 1420 } 1421 1422 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1423 { 1424 /* 1425 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1426 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1427 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1428 * value. 1429 */ 1430 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1431 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1432 } 1433 1434 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1435 int scope) 1436 { 1437 u64 ctr; 1438 1439 if (scope == SCOPE_SYSTEM) 1440 ctr = arm64_ftr_reg_ctrel0.sys_val; 1441 else 1442 ctr = read_cpuid_cachetype(); 1443 1444 return ctr & BIT(CTR_DIC_SHIFT); 1445 } 1446 1447 static bool __maybe_unused 1448 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1449 { 1450 /* 1451 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1452 * may share TLB entries with a CPU stuck in the crashed 1453 * kernel. 1454 */ 1455 if (is_kdump_kernel()) 1456 return false; 1457 1458 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1459 return false; 1460 1461 return has_cpuid_feature(entry, scope); 1462 } 1463 1464 /* 1465 * This check is triggered during the early boot before the cpufeature 1466 * is initialised. Checking the status on the local CPU allows the boot 1467 * CPU to detect the need for non-global mappings and thus avoiding a 1468 * pagetable re-write after all the CPUs are booted. This check will be 1469 * anyway run on individual CPUs, allowing us to get the consistent 1470 * state once the SMP CPUs are up and thus make the switch to non-global 1471 * mappings if required. 1472 */ 1473 bool kaslr_requires_kpti(void) 1474 { 1475 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1476 return false; 1477 1478 /* 1479 * E0PD does a similar job to KPTI so can be used instead 1480 * where available. 1481 */ 1482 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1483 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1484 if (cpuid_feature_extract_unsigned_field(mmfr2, 1485 ID_AA64MMFR2_E0PD_SHIFT)) 1486 return false; 1487 } 1488 1489 /* 1490 * Systems affected by Cavium erratum 24756 are incompatible 1491 * with KPTI. 1492 */ 1493 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1494 extern const struct midr_range cavium_erratum_27456_cpus[]; 1495 1496 if (is_midr_in_range_list(read_cpuid_id(), 1497 cavium_erratum_27456_cpus)) 1498 return false; 1499 } 1500 1501 return kaslr_offset() > 0; 1502 } 1503 1504 static bool __meltdown_safe = true; 1505 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1506 1507 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1508 int scope) 1509 { 1510 /* List of CPUs that are not vulnerable and don't need KPTI */ 1511 static const struct midr_range kpti_safe_list[] = { 1512 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1513 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1514 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1515 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1516 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1517 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1518 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1519 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1520 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1521 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1522 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1523 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1524 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1525 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1526 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1527 { /* sentinel */ } 1528 }; 1529 char const *str = "kpti command line option"; 1530 bool meltdown_safe; 1531 1532 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1533 1534 /* Defer to CPU feature registers */ 1535 if (has_cpuid_feature(entry, scope)) 1536 meltdown_safe = true; 1537 1538 if (!meltdown_safe) 1539 __meltdown_safe = false; 1540 1541 /* 1542 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1543 * ThunderX leads to apparent I-cache corruption of kernel text, which 1544 * ends as well as you might imagine. Don't even try. We cannot rely 1545 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1546 * because cpucap detection order may change. However, since we know 1547 * affected CPUs are always in a homogeneous configuration, it is 1548 * safe to rely on this_cpu_has_cap() here. 1549 */ 1550 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1551 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1552 __kpti_forced = -1; 1553 } 1554 1555 /* Useful for KASLR robustness */ 1556 if (kaslr_requires_kpti()) { 1557 if (!__kpti_forced) { 1558 str = "KASLR"; 1559 __kpti_forced = 1; 1560 } 1561 } 1562 1563 if (cpu_mitigations_off() && !__kpti_forced) { 1564 str = "mitigations=off"; 1565 __kpti_forced = -1; 1566 } 1567 1568 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1569 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1570 return false; 1571 } 1572 1573 /* Forced? */ 1574 if (__kpti_forced) { 1575 pr_info_once("kernel page table isolation forced %s by %s\n", 1576 __kpti_forced > 0 ? "ON" : "OFF", str); 1577 return __kpti_forced > 0; 1578 } 1579 1580 return !meltdown_safe; 1581 } 1582 1583 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1584 static void __nocfi 1585 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1586 { 1587 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1588 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1589 kpti_remap_fn *remap_fn; 1590 1591 int cpu = smp_processor_id(); 1592 1593 /* 1594 * We don't need to rewrite the page-tables if either we've done 1595 * it already or we have KASLR enabled and therefore have not 1596 * created any global mappings at all. 1597 */ 1598 if (arm64_use_ng_mappings) 1599 return; 1600 1601 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings)); 1602 1603 cpu_install_idmap(); 1604 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1605 cpu_uninstall_idmap(); 1606 1607 if (!cpu) 1608 arm64_use_ng_mappings = true; 1609 } 1610 #else 1611 static void 1612 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1613 { 1614 } 1615 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1616 1617 static int __init parse_kpti(char *str) 1618 { 1619 bool enabled; 1620 int ret = strtobool(str, &enabled); 1621 1622 if (ret) 1623 return ret; 1624 1625 __kpti_forced = enabled ? 1 : -1; 1626 return 0; 1627 } 1628 early_param("kpti", parse_kpti); 1629 1630 #ifdef CONFIG_ARM64_HW_AFDBM 1631 static inline void __cpu_enable_hw_dbm(void) 1632 { 1633 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1634 1635 write_sysreg(tcr, tcr_el1); 1636 isb(); 1637 local_flush_tlb_all(); 1638 } 1639 1640 static bool cpu_has_broken_dbm(void) 1641 { 1642 /* List of CPUs which have broken DBM support. */ 1643 static const struct midr_range cpus[] = { 1644 #ifdef CONFIG_ARM64_ERRATUM_1024718 1645 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1646 /* Kryo4xx Silver (rdpe => r1p0) */ 1647 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1648 #endif 1649 {}, 1650 }; 1651 1652 return is_midr_in_range_list(read_cpuid_id(), cpus); 1653 } 1654 1655 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1656 { 1657 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1658 !cpu_has_broken_dbm(); 1659 } 1660 1661 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1662 { 1663 if (cpu_can_use_dbm(cap)) 1664 __cpu_enable_hw_dbm(); 1665 } 1666 1667 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1668 int __unused) 1669 { 1670 static bool detected = false; 1671 /* 1672 * DBM is a non-conflicting feature. i.e, the kernel can safely 1673 * run a mix of CPUs with and without the feature. So, we 1674 * unconditionally enable the capability to allow any late CPU 1675 * to use the feature. We only enable the control bits on the 1676 * CPU, if it actually supports. 1677 * 1678 * We have to make sure we print the "feature" detection only 1679 * when at least one CPU actually uses it. So check if this CPU 1680 * can actually use it and print the message exactly once. 1681 * 1682 * This is safe as all CPUs (including secondary CPUs - due to the 1683 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1684 * goes through the "matches" check exactly once. Also if a CPU 1685 * matches the criteria, it is guaranteed that the CPU will turn 1686 * the DBM on, as the capability is unconditionally enabled. 1687 */ 1688 if (!detected && cpu_can_use_dbm(cap)) { 1689 detected = true; 1690 pr_info("detected: Hardware dirty bit management\n"); 1691 } 1692 1693 return true; 1694 } 1695 1696 #endif 1697 1698 #ifdef CONFIG_ARM64_AMU_EXTN 1699 1700 /* 1701 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1702 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1703 * information regarding all the events that it supports. When a CPU bit is 1704 * set in the cpumask, the user of this feature can only rely on the presence 1705 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1706 * counters are enabled or access to these counters is enabled by code 1707 * executed at higher exception levels (firmware). 1708 */ 1709 static struct cpumask amu_cpus __read_mostly; 1710 1711 bool cpu_has_amu_feat(int cpu) 1712 { 1713 return cpumask_test_cpu(cpu, &amu_cpus); 1714 } 1715 1716 int get_cpu_with_amu_feat(void) 1717 { 1718 return cpumask_any(&amu_cpus); 1719 } 1720 1721 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1722 { 1723 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1724 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1725 smp_processor_id()); 1726 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1727 update_freq_counters_refs(); 1728 } 1729 } 1730 1731 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1732 int __unused) 1733 { 1734 /* 1735 * The AMU extension is a non-conflicting feature: the kernel can 1736 * safely run a mix of CPUs with and without support for the 1737 * activity monitors extension. Therefore, unconditionally enable 1738 * the capability to allow any late CPU to use the feature. 1739 * 1740 * With this feature unconditionally enabled, the cpu_enable 1741 * function will be called for all CPUs that match the criteria, 1742 * including secondary and hotplugged, marking this feature as 1743 * present on that respective CPU. The enable function will also 1744 * print a detection message. 1745 */ 1746 1747 return true; 1748 } 1749 #else 1750 int get_cpu_with_amu_feat(void) 1751 { 1752 return nr_cpu_ids; 1753 } 1754 #endif 1755 1756 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1757 { 1758 return is_kernel_in_hyp_mode(); 1759 } 1760 1761 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1762 { 1763 /* 1764 * Copy register values that aren't redirected by hardware. 1765 * 1766 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1767 * this value to tpidr_el2 before we patch the code. Once we've done 1768 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1769 * do anything here. 1770 */ 1771 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1772 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1773 } 1774 1775 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1776 { 1777 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1778 1779 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1780 WARN_ON(CLIDR_LOUU(val) || CLIDR_LOUIS(val)); 1781 } 1782 1783 #ifdef CONFIG_ARM64_PAN 1784 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1785 { 1786 /* 1787 * We modify PSTATE. This won't work from irq context as the PSTATE 1788 * is discarded once we return from the exception. 1789 */ 1790 WARN_ON_ONCE(in_interrupt()); 1791 1792 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1793 set_pstate_pan(1); 1794 } 1795 #endif /* CONFIG_ARM64_PAN */ 1796 1797 #ifdef CONFIG_ARM64_RAS_EXTN 1798 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1799 { 1800 /* Firmware may have left a deferred SError in this register. */ 1801 write_sysreg_s(0, SYS_DISR_EL1); 1802 } 1803 #endif /* CONFIG_ARM64_RAS_EXTN */ 1804 1805 #ifdef CONFIG_ARM64_PTR_AUTH 1806 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1807 { 1808 int boot_val, sec_val; 1809 1810 /* We don't expect to be called with SCOPE_SYSTEM */ 1811 WARN_ON(scope == SCOPE_SYSTEM); 1812 /* 1813 * The ptr-auth feature levels are not intercompatible with lower 1814 * levels. Hence we must match ptr-auth feature level of the secondary 1815 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1816 * from the sanitised register whereas direct register read is done for 1817 * the secondary CPUs. 1818 * The sanitised feature state is guaranteed to match that of the 1819 * boot CPU as a mismatched secondary CPU is parked before it gets 1820 * a chance to update the state, with the capability. 1821 */ 1822 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1823 entry->field_pos, entry->sign); 1824 if (scope & SCOPE_BOOT_CPU) 1825 return boot_val >= entry->min_field_value; 1826 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1827 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1828 entry->field_pos, entry->sign); 1829 return sec_val == boot_val; 1830 } 1831 1832 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1833 int scope) 1834 { 1835 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1836 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1837 } 1838 1839 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1840 int __unused) 1841 { 1842 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1843 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1844 } 1845 #endif /* CONFIG_ARM64_PTR_AUTH */ 1846 1847 #ifdef CONFIG_ARM64_E0PD 1848 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1849 { 1850 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1851 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1852 } 1853 #endif /* CONFIG_ARM64_E0PD */ 1854 1855 #ifdef CONFIG_ARM64_PSEUDO_NMI 1856 static bool enable_pseudo_nmi; 1857 1858 static int __init early_enable_pseudo_nmi(char *p) 1859 { 1860 return strtobool(p, &enable_pseudo_nmi); 1861 } 1862 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1863 1864 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1865 int scope) 1866 { 1867 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1868 } 1869 #endif 1870 1871 #ifdef CONFIG_ARM64_BTI 1872 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1873 { 1874 /* 1875 * Use of X16/X17 for tail-calls and trampolines that jump to 1876 * function entry points using BR is a requirement for 1877 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1878 * So, be strict and forbid other BRs using other registers to 1879 * jump onto a PACIxSP instruction: 1880 */ 1881 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1882 isb(); 1883 } 1884 #endif /* CONFIG_ARM64_BTI */ 1885 1886 #ifdef CONFIG_ARM64_MTE 1887 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1888 { 1889 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 1890 isb(); 1891 1892 /* 1893 * Clear the tags in the zero page. This needs to be done via the 1894 * linear map which has the Tagged attribute. 1895 */ 1896 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1897 mte_clear_page_tags(lm_alias(empty_zero_page)); 1898 1899 kasan_init_hw_tags_cpu(); 1900 } 1901 #endif /* CONFIG_ARM64_MTE */ 1902 1903 #ifdef CONFIG_KVM 1904 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1905 { 1906 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1907 return false; 1908 1909 if (is_kernel_in_hyp_mode()) { 1910 pr_warn("Protected KVM not available with VHE\n"); 1911 return false; 1912 } 1913 1914 return true; 1915 } 1916 #endif /* CONFIG_KVM */ 1917 1918 /* Internal helper functions to match cpu capability type */ 1919 static bool 1920 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1921 { 1922 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1923 } 1924 1925 static bool 1926 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1927 { 1928 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1929 } 1930 1931 static bool 1932 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1933 { 1934 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1935 } 1936 1937 static const struct arm64_cpu_capabilities arm64_features[] = { 1938 { 1939 .desc = "GIC system register CPU interface", 1940 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1941 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1942 .matches = has_useable_gicv3_cpuif, 1943 .sys_reg = SYS_ID_AA64PFR0_EL1, 1944 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1945 .sign = FTR_UNSIGNED, 1946 .min_field_value = 1, 1947 }, 1948 { 1949 .desc = "Enhanced Counter Virtualization", 1950 .capability = ARM64_HAS_ECV, 1951 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1952 .matches = has_cpuid_feature, 1953 .sys_reg = SYS_ID_AA64MMFR0_EL1, 1954 .field_pos = ID_AA64MMFR0_ECV_SHIFT, 1955 .sign = FTR_UNSIGNED, 1956 .min_field_value = 1, 1957 }, 1958 #ifdef CONFIG_ARM64_PAN 1959 { 1960 .desc = "Privileged Access Never", 1961 .capability = ARM64_HAS_PAN, 1962 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1963 .matches = has_cpuid_feature, 1964 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1965 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1966 .sign = FTR_UNSIGNED, 1967 .min_field_value = 1, 1968 .cpu_enable = cpu_enable_pan, 1969 }, 1970 #endif /* CONFIG_ARM64_PAN */ 1971 #ifdef CONFIG_ARM64_EPAN 1972 { 1973 .desc = "Enhanced Privileged Access Never", 1974 .capability = ARM64_HAS_EPAN, 1975 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1976 .matches = has_cpuid_feature, 1977 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1978 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1979 .sign = FTR_UNSIGNED, 1980 .min_field_value = 3, 1981 }, 1982 #endif /* CONFIG_ARM64_EPAN */ 1983 #ifdef CONFIG_ARM64_LSE_ATOMICS 1984 { 1985 .desc = "LSE atomic instructions", 1986 .capability = ARM64_HAS_LSE_ATOMICS, 1987 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1988 .matches = has_cpuid_feature, 1989 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1990 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1991 .sign = FTR_UNSIGNED, 1992 .min_field_value = 2, 1993 }, 1994 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1995 { 1996 .desc = "Software prefetching using PRFM", 1997 .capability = ARM64_HAS_NO_HW_PREFETCH, 1998 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1999 .matches = has_no_hw_prefetch, 2000 }, 2001 { 2002 .desc = "Virtualization Host Extensions", 2003 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2004 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2005 .matches = runs_at_el2, 2006 .cpu_enable = cpu_copy_el2regs, 2007 }, 2008 { 2009 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2010 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2011 .matches = has_32bit_el0, 2012 .sys_reg = SYS_ID_AA64PFR0_EL1, 2013 .sign = FTR_UNSIGNED, 2014 .field_pos = ID_AA64PFR0_EL0_SHIFT, 2015 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2016 }, 2017 #ifdef CONFIG_KVM 2018 { 2019 .desc = "32-bit EL1 Support", 2020 .capability = ARM64_HAS_32BIT_EL1, 2021 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2022 .matches = has_cpuid_feature, 2023 .sys_reg = SYS_ID_AA64PFR0_EL1, 2024 .sign = FTR_UNSIGNED, 2025 .field_pos = ID_AA64PFR0_EL1_SHIFT, 2026 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2027 }, 2028 { 2029 .desc = "Protected KVM", 2030 .capability = ARM64_KVM_PROTECTED_MODE, 2031 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2032 .matches = is_kvm_protected_mode, 2033 }, 2034 #endif 2035 { 2036 .desc = "Kernel page table isolation (KPTI)", 2037 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2038 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2039 /* 2040 * The ID feature fields below are used to indicate that 2041 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2042 * more details. 2043 */ 2044 .sys_reg = SYS_ID_AA64PFR0_EL1, 2045 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 2046 .min_field_value = 1, 2047 .matches = unmap_kernel_at_el0, 2048 .cpu_enable = kpti_install_ng_mappings, 2049 }, 2050 { 2051 /* FP/SIMD is not implemented */ 2052 .capability = ARM64_HAS_NO_FPSIMD, 2053 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2054 .min_field_value = 0, 2055 .matches = has_no_fpsimd, 2056 }, 2057 #ifdef CONFIG_ARM64_PMEM 2058 { 2059 .desc = "Data cache clean to Point of Persistence", 2060 .capability = ARM64_HAS_DCPOP, 2061 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2062 .matches = has_cpuid_feature, 2063 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2064 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2065 .min_field_value = 1, 2066 }, 2067 { 2068 .desc = "Data cache clean to Point of Deep Persistence", 2069 .capability = ARM64_HAS_DCPODP, 2070 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2071 .matches = has_cpuid_feature, 2072 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2073 .sign = FTR_UNSIGNED, 2074 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2075 .min_field_value = 2, 2076 }, 2077 #endif 2078 #ifdef CONFIG_ARM64_SVE 2079 { 2080 .desc = "Scalable Vector Extension", 2081 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2082 .capability = ARM64_SVE, 2083 .sys_reg = SYS_ID_AA64PFR0_EL1, 2084 .sign = FTR_UNSIGNED, 2085 .field_pos = ID_AA64PFR0_SVE_SHIFT, 2086 .min_field_value = ID_AA64PFR0_SVE, 2087 .matches = has_cpuid_feature, 2088 .cpu_enable = sve_kernel_enable, 2089 }, 2090 #endif /* CONFIG_ARM64_SVE */ 2091 #ifdef CONFIG_ARM64_RAS_EXTN 2092 { 2093 .desc = "RAS Extension Support", 2094 .capability = ARM64_HAS_RAS_EXTN, 2095 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2096 .matches = has_cpuid_feature, 2097 .sys_reg = SYS_ID_AA64PFR0_EL1, 2098 .sign = FTR_UNSIGNED, 2099 .field_pos = ID_AA64PFR0_RAS_SHIFT, 2100 .min_field_value = ID_AA64PFR0_RAS_V1, 2101 .cpu_enable = cpu_clear_disr, 2102 }, 2103 #endif /* CONFIG_ARM64_RAS_EXTN */ 2104 #ifdef CONFIG_ARM64_AMU_EXTN 2105 { 2106 /* 2107 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2108 * Therefore, don't provide .desc as we don't want the detection 2109 * message to be shown until at least one CPU is detected to 2110 * support the feature. 2111 */ 2112 .capability = ARM64_HAS_AMU_EXTN, 2113 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2114 .matches = has_amu, 2115 .sys_reg = SYS_ID_AA64PFR0_EL1, 2116 .sign = FTR_UNSIGNED, 2117 .field_pos = ID_AA64PFR0_AMU_SHIFT, 2118 .min_field_value = ID_AA64PFR0_AMU, 2119 .cpu_enable = cpu_amu_enable, 2120 }, 2121 #endif /* CONFIG_ARM64_AMU_EXTN */ 2122 { 2123 .desc = "Data cache clean to the PoU not required for I/D coherence", 2124 .capability = ARM64_HAS_CACHE_IDC, 2125 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2126 .matches = has_cache_idc, 2127 .cpu_enable = cpu_emulate_effective_ctr, 2128 }, 2129 { 2130 .desc = "Instruction cache invalidation not required for I/D coherence", 2131 .capability = ARM64_HAS_CACHE_DIC, 2132 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2133 .matches = has_cache_dic, 2134 }, 2135 { 2136 .desc = "Stage-2 Force Write-Back", 2137 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2138 .capability = ARM64_HAS_STAGE2_FWB, 2139 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2140 .sign = FTR_UNSIGNED, 2141 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 2142 .min_field_value = 1, 2143 .matches = has_cpuid_feature, 2144 .cpu_enable = cpu_has_fwb, 2145 }, 2146 { 2147 .desc = "ARMv8.4 Translation Table Level", 2148 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2149 .capability = ARM64_HAS_ARMv8_4_TTL, 2150 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2151 .sign = FTR_UNSIGNED, 2152 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 2153 .min_field_value = 1, 2154 .matches = has_cpuid_feature, 2155 }, 2156 { 2157 .desc = "TLB range maintenance instructions", 2158 .capability = ARM64_HAS_TLB_RANGE, 2159 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2160 .matches = has_cpuid_feature, 2161 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2162 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 2163 .sign = FTR_UNSIGNED, 2164 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 2165 }, 2166 #ifdef CONFIG_ARM64_HW_AFDBM 2167 { 2168 /* 2169 * Since we turn this on always, we don't want the user to 2170 * think that the feature is available when it may not be. 2171 * So hide the description. 2172 * 2173 * .desc = "Hardware pagetable Dirty Bit Management", 2174 * 2175 */ 2176 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2177 .capability = ARM64_HW_DBM, 2178 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2179 .sign = FTR_UNSIGNED, 2180 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2181 .min_field_value = 2, 2182 .matches = has_hw_dbm, 2183 .cpu_enable = cpu_enable_hw_dbm, 2184 }, 2185 #endif 2186 { 2187 .desc = "CRC32 instructions", 2188 .capability = ARM64_HAS_CRC32, 2189 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2190 .matches = has_cpuid_feature, 2191 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2192 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 2193 .min_field_value = 1, 2194 }, 2195 { 2196 .desc = "Speculative Store Bypassing Safe (SSBS)", 2197 .capability = ARM64_SSBS, 2198 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2199 .matches = has_cpuid_feature, 2200 .sys_reg = SYS_ID_AA64PFR1_EL1, 2201 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2202 .sign = FTR_UNSIGNED, 2203 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2204 }, 2205 #ifdef CONFIG_ARM64_CNP 2206 { 2207 .desc = "Common not Private translations", 2208 .capability = ARM64_HAS_CNP, 2209 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2210 .matches = has_useable_cnp, 2211 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2212 .sign = FTR_UNSIGNED, 2213 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2214 .min_field_value = 1, 2215 .cpu_enable = cpu_enable_cnp, 2216 }, 2217 #endif 2218 { 2219 .desc = "Speculation barrier (SB)", 2220 .capability = ARM64_HAS_SB, 2221 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2222 .matches = has_cpuid_feature, 2223 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2224 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2225 .sign = FTR_UNSIGNED, 2226 .min_field_value = 1, 2227 }, 2228 #ifdef CONFIG_ARM64_PTR_AUTH 2229 { 2230 .desc = "Address authentication (architected algorithm)", 2231 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2232 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2233 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2234 .sign = FTR_UNSIGNED, 2235 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2236 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2237 .matches = has_address_auth_cpucap, 2238 }, 2239 { 2240 .desc = "Address authentication (IMP DEF algorithm)", 2241 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2242 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2243 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2244 .sign = FTR_UNSIGNED, 2245 .field_pos = ID_AA64ISAR1_API_SHIFT, 2246 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2247 .matches = has_address_auth_cpucap, 2248 }, 2249 { 2250 .capability = ARM64_HAS_ADDRESS_AUTH, 2251 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2252 .matches = has_address_auth_metacap, 2253 }, 2254 { 2255 .desc = "Generic authentication (architected algorithm)", 2256 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2257 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2258 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2259 .sign = FTR_UNSIGNED, 2260 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2261 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2262 .matches = has_cpuid_feature, 2263 }, 2264 { 2265 .desc = "Generic authentication (IMP DEF algorithm)", 2266 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2267 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2268 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2269 .sign = FTR_UNSIGNED, 2270 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2271 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2272 .matches = has_cpuid_feature, 2273 }, 2274 { 2275 .capability = ARM64_HAS_GENERIC_AUTH, 2276 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2277 .matches = has_generic_auth, 2278 }, 2279 #endif /* CONFIG_ARM64_PTR_AUTH */ 2280 #ifdef CONFIG_ARM64_PSEUDO_NMI 2281 { 2282 /* 2283 * Depends on having GICv3 2284 */ 2285 .desc = "IRQ priority masking", 2286 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2287 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2288 .matches = can_use_gic_priorities, 2289 .sys_reg = SYS_ID_AA64PFR0_EL1, 2290 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2291 .sign = FTR_UNSIGNED, 2292 .min_field_value = 1, 2293 }, 2294 #endif 2295 #ifdef CONFIG_ARM64_E0PD 2296 { 2297 .desc = "E0PD", 2298 .capability = ARM64_HAS_E0PD, 2299 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2300 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2301 .sign = FTR_UNSIGNED, 2302 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2303 .matches = has_cpuid_feature, 2304 .min_field_value = 1, 2305 .cpu_enable = cpu_enable_e0pd, 2306 }, 2307 #endif 2308 #ifdef CONFIG_ARCH_RANDOM 2309 { 2310 .desc = "Random Number Generator", 2311 .capability = ARM64_HAS_RNG, 2312 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2313 .matches = has_cpuid_feature, 2314 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2315 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2316 .sign = FTR_UNSIGNED, 2317 .min_field_value = 1, 2318 }, 2319 #endif 2320 #ifdef CONFIG_ARM64_BTI 2321 { 2322 .desc = "Branch Target Identification", 2323 .capability = ARM64_BTI, 2324 #ifdef CONFIG_ARM64_BTI_KERNEL 2325 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2326 #else 2327 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2328 #endif 2329 .matches = has_cpuid_feature, 2330 .cpu_enable = bti_enable, 2331 .sys_reg = SYS_ID_AA64PFR1_EL1, 2332 .field_pos = ID_AA64PFR1_BT_SHIFT, 2333 .min_field_value = ID_AA64PFR1_BT_BTI, 2334 .sign = FTR_UNSIGNED, 2335 }, 2336 #endif 2337 #ifdef CONFIG_ARM64_MTE 2338 { 2339 .desc = "Memory Tagging Extension", 2340 .capability = ARM64_MTE, 2341 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2342 .matches = has_cpuid_feature, 2343 .sys_reg = SYS_ID_AA64PFR1_EL1, 2344 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2345 .min_field_value = ID_AA64PFR1_MTE, 2346 .sign = FTR_UNSIGNED, 2347 .cpu_enable = cpu_enable_mte, 2348 }, 2349 { 2350 .desc = "Asymmetric MTE Tag Check Fault", 2351 .capability = ARM64_MTE_ASYMM, 2352 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2353 .matches = has_cpuid_feature, 2354 .sys_reg = SYS_ID_AA64PFR1_EL1, 2355 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2356 .min_field_value = ID_AA64PFR1_MTE_ASYMM, 2357 .sign = FTR_UNSIGNED, 2358 }, 2359 #endif /* CONFIG_ARM64_MTE */ 2360 { 2361 .desc = "RCpc load-acquire (LDAPR)", 2362 .capability = ARM64_HAS_LDAPR, 2363 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2364 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2365 .sign = FTR_UNSIGNED, 2366 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2367 .matches = has_cpuid_feature, 2368 .min_field_value = 1, 2369 }, 2370 {}, 2371 }; 2372 2373 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2374 .matches = has_cpuid_feature, \ 2375 .sys_reg = reg, \ 2376 .field_pos = field, \ 2377 .sign = s, \ 2378 .min_field_value = min_value, 2379 2380 #define __HWCAP_CAP(name, cap_type, cap) \ 2381 .desc = name, \ 2382 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2383 .hwcap_type = cap_type, \ 2384 .hwcap = cap, \ 2385 2386 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2387 { \ 2388 __HWCAP_CAP(#cap, cap_type, cap) \ 2389 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2390 } 2391 2392 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2393 { \ 2394 __HWCAP_CAP(#cap, cap_type, cap) \ 2395 .matches = cpucap_multi_entry_cap_matches, \ 2396 .match_list = list, \ 2397 } 2398 2399 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2400 { \ 2401 __HWCAP_CAP(#cap, cap_type, cap) \ 2402 .matches = match, \ 2403 } 2404 2405 #ifdef CONFIG_ARM64_PTR_AUTH 2406 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2407 { 2408 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2409 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2410 }, 2411 { 2412 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2413 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2414 }, 2415 {}, 2416 }; 2417 2418 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2419 { 2420 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2421 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2422 }, 2423 { 2424 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2425 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2426 }, 2427 {}, 2428 }; 2429 #endif 2430 2431 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2432 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2433 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2434 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2435 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2436 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2437 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2438 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2439 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2440 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2441 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2442 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2443 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2444 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2445 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2446 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2447 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2448 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2449 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2450 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2451 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2452 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2453 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2454 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2455 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2456 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2457 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2458 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2459 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2460 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2461 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2462 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2463 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2464 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2465 #ifdef CONFIG_ARM64_SVE 2466 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2467 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2468 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2469 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2470 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2471 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2472 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2473 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2474 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2475 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2476 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2477 #endif 2478 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2479 #ifdef CONFIG_ARM64_BTI 2480 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2481 #endif 2482 #ifdef CONFIG_ARM64_PTR_AUTH 2483 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2484 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2485 #endif 2486 #ifdef CONFIG_ARM64_MTE 2487 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2488 #endif /* CONFIG_ARM64_MTE */ 2489 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), 2490 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), 2491 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2492 {}, 2493 }; 2494 2495 #ifdef CONFIG_COMPAT 2496 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2497 { 2498 /* 2499 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2500 * in line with that of arm32 as in vfp_init(). We make sure that the 2501 * check is future proof, by making sure value is non-zero. 2502 */ 2503 u32 mvfr1; 2504 2505 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2506 if (scope == SCOPE_SYSTEM) 2507 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2508 else 2509 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2510 2511 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2512 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2513 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2514 } 2515 #endif 2516 2517 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2518 #ifdef CONFIG_COMPAT 2519 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2520 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2521 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2522 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2523 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2524 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2525 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2526 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2527 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2528 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2529 #endif 2530 {}, 2531 }; 2532 2533 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2534 { 2535 switch (cap->hwcap_type) { 2536 case CAP_HWCAP: 2537 cpu_set_feature(cap->hwcap); 2538 break; 2539 #ifdef CONFIG_COMPAT 2540 case CAP_COMPAT_HWCAP: 2541 compat_elf_hwcap |= (u32)cap->hwcap; 2542 break; 2543 case CAP_COMPAT_HWCAP2: 2544 compat_elf_hwcap2 |= (u32)cap->hwcap; 2545 break; 2546 #endif 2547 default: 2548 WARN_ON(1); 2549 break; 2550 } 2551 } 2552 2553 /* Check if we have a particular HWCAP enabled */ 2554 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2555 { 2556 bool rc; 2557 2558 switch (cap->hwcap_type) { 2559 case CAP_HWCAP: 2560 rc = cpu_have_feature(cap->hwcap); 2561 break; 2562 #ifdef CONFIG_COMPAT 2563 case CAP_COMPAT_HWCAP: 2564 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2565 break; 2566 case CAP_COMPAT_HWCAP2: 2567 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2568 break; 2569 #endif 2570 default: 2571 WARN_ON(1); 2572 rc = false; 2573 } 2574 2575 return rc; 2576 } 2577 2578 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2579 { 2580 /* We support emulation of accesses to CPU ID feature registers */ 2581 cpu_set_named_feature(CPUID); 2582 for (; hwcaps->matches; hwcaps++) 2583 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2584 cap_set_elf_hwcap(hwcaps); 2585 } 2586 2587 static void update_cpu_capabilities(u16 scope_mask) 2588 { 2589 int i; 2590 const struct arm64_cpu_capabilities *caps; 2591 2592 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2593 for (i = 0; i < ARM64_NCAPS; i++) { 2594 caps = cpu_hwcaps_ptrs[i]; 2595 if (!caps || !(caps->type & scope_mask) || 2596 cpus_have_cap(caps->capability) || 2597 !caps->matches(caps, cpucap_default_scope(caps))) 2598 continue; 2599 2600 if (caps->desc) 2601 pr_info("detected: %s\n", caps->desc); 2602 cpus_set_cap(caps->capability); 2603 2604 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2605 set_bit(caps->capability, boot_capabilities); 2606 } 2607 } 2608 2609 /* 2610 * Enable all the available capabilities on this CPU. The capabilities 2611 * with BOOT_CPU scope are handled separately and hence skipped here. 2612 */ 2613 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2614 { 2615 int i; 2616 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2617 2618 for_each_available_cap(i) { 2619 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2620 2621 if (WARN_ON(!cap)) 2622 continue; 2623 2624 if (!(cap->type & non_boot_scope)) 2625 continue; 2626 2627 if (cap->cpu_enable) 2628 cap->cpu_enable(cap); 2629 } 2630 return 0; 2631 } 2632 2633 /* 2634 * Run through the enabled capabilities and enable() it on all active 2635 * CPUs 2636 */ 2637 static void __init enable_cpu_capabilities(u16 scope_mask) 2638 { 2639 int i; 2640 const struct arm64_cpu_capabilities *caps; 2641 bool boot_scope; 2642 2643 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2644 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2645 2646 for (i = 0; i < ARM64_NCAPS; i++) { 2647 unsigned int num; 2648 2649 caps = cpu_hwcaps_ptrs[i]; 2650 if (!caps || !(caps->type & scope_mask)) 2651 continue; 2652 num = caps->capability; 2653 if (!cpus_have_cap(num)) 2654 continue; 2655 2656 /* Ensure cpus_have_const_cap(num) works */ 2657 static_branch_enable(&cpu_hwcap_keys[num]); 2658 2659 if (boot_scope && caps->cpu_enable) 2660 /* 2661 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2662 * before any secondary CPU boots. Thus, each secondary 2663 * will enable the capability as appropriate via 2664 * check_local_cpu_capabilities(). The only exception is 2665 * the boot CPU, for which the capability must be 2666 * enabled here. This approach avoids costly 2667 * stop_machine() calls for this case. 2668 */ 2669 caps->cpu_enable(caps); 2670 } 2671 2672 /* 2673 * For all non-boot scope capabilities, use stop_machine() 2674 * as it schedules the work allowing us to modify PSTATE, 2675 * instead of on_each_cpu() which uses an IPI, giving us a 2676 * PSTATE that disappears when we return. 2677 */ 2678 if (!boot_scope) 2679 stop_machine(cpu_enable_non_boot_scope_capabilities, 2680 NULL, cpu_online_mask); 2681 } 2682 2683 /* 2684 * Run through the list of capabilities to check for conflicts. 2685 * If the system has already detected a capability, take necessary 2686 * action on this CPU. 2687 */ 2688 static void verify_local_cpu_caps(u16 scope_mask) 2689 { 2690 int i; 2691 bool cpu_has_cap, system_has_cap; 2692 const struct arm64_cpu_capabilities *caps; 2693 2694 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2695 2696 for (i = 0; i < ARM64_NCAPS; i++) { 2697 caps = cpu_hwcaps_ptrs[i]; 2698 if (!caps || !(caps->type & scope_mask)) 2699 continue; 2700 2701 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2702 system_has_cap = cpus_have_cap(caps->capability); 2703 2704 if (system_has_cap) { 2705 /* 2706 * Check if the new CPU misses an advertised feature, 2707 * which is not safe to miss. 2708 */ 2709 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2710 break; 2711 /* 2712 * We have to issue cpu_enable() irrespective of 2713 * whether the CPU has it or not, as it is enabeld 2714 * system wide. It is upto the call back to take 2715 * appropriate action on this CPU. 2716 */ 2717 if (caps->cpu_enable) 2718 caps->cpu_enable(caps); 2719 } else { 2720 /* 2721 * Check if the CPU has this capability if it isn't 2722 * safe to have when the system doesn't. 2723 */ 2724 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2725 break; 2726 } 2727 } 2728 2729 if (i < ARM64_NCAPS) { 2730 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2731 smp_processor_id(), caps->capability, 2732 caps->desc, system_has_cap, cpu_has_cap); 2733 2734 if (cpucap_panic_on_conflict(caps)) 2735 cpu_panic_kernel(); 2736 else 2737 cpu_die_early(); 2738 } 2739 } 2740 2741 /* 2742 * Check for CPU features that are used in early boot 2743 * based on the Boot CPU value. 2744 */ 2745 static void check_early_cpu_features(void) 2746 { 2747 verify_cpu_asid_bits(); 2748 2749 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2750 } 2751 2752 static void 2753 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2754 { 2755 2756 for (; caps->matches; caps++) 2757 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2758 pr_crit("CPU%d: missing HWCAP: %s\n", 2759 smp_processor_id(), caps->desc); 2760 cpu_die_early(); 2761 } 2762 } 2763 2764 static void verify_local_elf_hwcaps(void) 2765 { 2766 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 2767 2768 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 2769 __verify_local_elf_hwcaps(compat_elf_hwcaps); 2770 } 2771 2772 static void verify_sve_features(void) 2773 { 2774 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2775 u64 zcr = read_zcr_features(); 2776 2777 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2778 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2779 2780 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 2781 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2782 smp_processor_id()); 2783 cpu_die_early(); 2784 } 2785 2786 /* Add checks on other ZCR bits here if necessary */ 2787 } 2788 2789 static void verify_hyp_capabilities(void) 2790 { 2791 u64 safe_mmfr1, mmfr0, mmfr1; 2792 int parange, ipa_max; 2793 unsigned int safe_vmid_bits, vmid_bits; 2794 2795 if (!IS_ENABLED(CONFIG_KVM)) 2796 return; 2797 2798 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2799 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2800 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2801 2802 /* Verify VMID bits */ 2803 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2804 vmid_bits = get_vmid_bits(mmfr1); 2805 if (vmid_bits < safe_vmid_bits) { 2806 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2807 cpu_die_early(); 2808 } 2809 2810 /* Verify IPA range */ 2811 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2812 ID_AA64MMFR0_PARANGE_SHIFT); 2813 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2814 if (ipa_max < get_kvm_ipa_limit()) { 2815 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2816 cpu_die_early(); 2817 } 2818 } 2819 2820 /* 2821 * Run through the enabled system capabilities and enable() it on this CPU. 2822 * The capabilities were decided based on the available CPUs at the boot time. 2823 * Any new CPU should match the system wide status of the capability. If the 2824 * new CPU doesn't have a capability which the system now has enabled, we 2825 * cannot do anything to fix it up and could cause unexpected failures. So 2826 * we park the CPU. 2827 */ 2828 static void verify_local_cpu_capabilities(void) 2829 { 2830 /* 2831 * The capabilities with SCOPE_BOOT_CPU are checked from 2832 * check_early_cpu_features(), as they need to be verified 2833 * on all secondary CPUs. 2834 */ 2835 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2836 verify_local_elf_hwcaps(); 2837 2838 if (system_supports_sve()) 2839 verify_sve_features(); 2840 2841 if (is_hyp_mode_available()) 2842 verify_hyp_capabilities(); 2843 } 2844 2845 void check_local_cpu_capabilities(void) 2846 { 2847 /* 2848 * All secondary CPUs should conform to the early CPU features 2849 * in use by the kernel based on boot CPU. 2850 */ 2851 check_early_cpu_features(); 2852 2853 /* 2854 * If we haven't finalised the system capabilities, this CPU gets 2855 * a chance to update the errata work arounds and local features. 2856 * Otherwise, this CPU should verify that it has all the system 2857 * advertised capabilities. 2858 */ 2859 if (!system_capabilities_finalized()) 2860 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2861 else 2862 verify_local_cpu_capabilities(); 2863 } 2864 2865 static void __init setup_boot_cpu_capabilities(void) 2866 { 2867 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2868 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2869 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2870 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2871 } 2872 2873 bool this_cpu_has_cap(unsigned int n) 2874 { 2875 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2876 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2877 2878 if (cap) 2879 return cap->matches(cap, SCOPE_LOCAL_CPU); 2880 } 2881 2882 return false; 2883 } 2884 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 2885 2886 /* 2887 * This helper function is used in a narrow window when, 2888 * - The system wide safe registers are set with all the SMP CPUs and, 2889 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2890 * In all other cases cpus_have_{const_}cap() should be used. 2891 */ 2892 static bool __maybe_unused __system_matches_cap(unsigned int n) 2893 { 2894 if (n < ARM64_NCAPS) { 2895 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2896 2897 if (cap) 2898 return cap->matches(cap, SCOPE_SYSTEM); 2899 } 2900 return false; 2901 } 2902 2903 void cpu_set_feature(unsigned int num) 2904 { 2905 WARN_ON(num >= MAX_CPU_FEATURES); 2906 elf_hwcap |= BIT(num); 2907 } 2908 EXPORT_SYMBOL_GPL(cpu_set_feature); 2909 2910 bool cpu_have_feature(unsigned int num) 2911 { 2912 WARN_ON(num >= MAX_CPU_FEATURES); 2913 return elf_hwcap & BIT(num); 2914 } 2915 EXPORT_SYMBOL_GPL(cpu_have_feature); 2916 2917 unsigned long cpu_get_elf_hwcap(void) 2918 { 2919 /* 2920 * We currently only populate the first 32 bits of AT_HWCAP. Please 2921 * note that for userspace compatibility we guarantee that bits 62 2922 * and 63 will always be returned as 0. 2923 */ 2924 return lower_32_bits(elf_hwcap); 2925 } 2926 2927 unsigned long cpu_get_elf_hwcap2(void) 2928 { 2929 return upper_32_bits(elf_hwcap); 2930 } 2931 2932 static void __init setup_system_capabilities(void) 2933 { 2934 /* 2935 * We have finalised the system-wide safe feature 2936 * registers, finalise the capabilities that depend 2937 * on it. Also enable all the available capabilities, 2938 * that are not enabled already. 2939 */ 2940 update_cpu_capabilities(SCOPE_SYSTEM); 2941 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2942 } 2943 2944 void __init setup_cpu_features(void) 2945 { 2946 u32 cwg; 2947 2948 setup_system_capabilities(); 2949 setup_elf_hwcaps(arm64_elf_hwcaps); 2950 2951 if (system_supports_32bit_el0()) 2952 setup_elf_hwcaps(compat_elf_hwcaps); 2953 2954 if (system_uses_ttbr0_pan()) 2955 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2956 2957 sve_setup(); 2958 minsigstksz_setup(); 2959 2960 /* Advertise that we have computed the system capabilities */ 2961 finalize_system_capabilities(); 2962 2963 /* 2964 * Check for sane CTR_EL0.CWG value. 2965 */ 2966 cwg = cache_type_cwg(); 2967 if (!cwg) 2968 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2969 ARCH_DMA_MINALIGN); 2970 } 2971 2972 static int enable_mismatched_32bit_el0(unsigned int cpu) 2973 { 2974 /* 2975 * The first 32-bit-capable CPU we detected and so can no longer 2976 * be offlined by userspace. -1 indicates we haven't yet onlined 2977 * a 32-bit-capable CPU. 2978 */ 2979 static int lucky_winner = -1; 2980 2981 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 2982 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 2983 2984 if (cpu_32bit) { 2985 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 2986 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 2987 } 2988 2989 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 2990 return 0; 2991 2992 if (lucky_winner >= 0) 2993 return 0; 2994 2995 /* 2996 * We've detected a mismatch. We need to keep one of our CPUs with 2997 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 2998 * every CPU in the system for a 32-bit task. 2999 */ 3000 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3001 cpu_active_mask); 3002 get_cpu_device(lucky_winner)->offline_disabled = true; 3003 setup_elf_hwcaps(compat_elf_hwcaps); 3004 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3005 cpu, lucky_winner); 3006 return 0; 3007 } 3008 3009 static int __init init_32bit_el0_mask(void) 3010 { 3011 if (!allow_mismatched_32bit_el0) 3012 return 0; 3013 3014 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3015 return -ENOMEM; 3016 3017 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3018 "arm64/mismatched_32bit_el0:online", 3019 enable_mismatched_32bit_el0, NULL); 3020 } 3021 subsys_initcall_sync(init_32bit_el0_mask); 3022 3023 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3024 { 3025 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 3026 } 3027 3028 /* 3029 * We emulate only the following system register space. 3030 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 3031 * See Table C5-6 System instruction encodings for System register accesses, 3032 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3033 */ 3034 static inline bool __attribute_const__ is_emulated(u32 id) 3035 { 3036 return (sys_reg_Op0(id) == 0x3 && 3037 sys_reg_CRn(id) == 0x0 && 3038 sys_reg_Op1(id) == 0x0 && 3039 (sys_reg_CRm(id) == 0 || 3040 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 3041 } 3042 3043 /* 3044 * With CRm == 0, reg should be one of : 3045 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3046 */ 3047 static inline int emulate_id_reg(u32 id, u64 *valp) 3048 { 3049 switch (id) { 3050 case SYS_MIDR_EL1: 3051 *valp = read_cpuid_id(); 3052 break; 3053 case SYS_MPIDR_EL1: 3054 *valp = SYS_MPIDR_SAFE_VAL; 3055 break; 3056 case SYS_REVIDR_EL1: 3057 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3058 *valp = 0; 3059 break; 3060 default: 3061 return -EINVAL; 3062 } 3063 3064 return 0; 3065 } 3066 3067 static int emulate_sys_reg(u32 id, u64 *valp) 3068 { 3069 struct arm64_ftr_reg *regp; 3070 3071 if (!is_emulated(id)) 3072 return -EINVAL; 3073 3074 if (sys_reg_CRm(id) == 0) 3075 return emulate_id_reg(id, valp); 3076 3077 regp = get_arm64_ftr_reg_nowarn(id); 3078 if (regp) 3079 *valp = arm64_ftr_reg_user_value(regp); 3080 else 3081 /* 3082 * The untracked registers are either IMPLEMENTATION DEFINED 3083 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3084 */ 3085 *valp = 0; 3086 return 0; 3087 } 3088 3089 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3090 { 3091 int rc; 3092 u64 val; 3093 3094 rc = emulate_sys_reg(sys_reg, &val); 3095 if (!rc) { 3096 pt_regs_write_reg(regs, rt, val); 3097 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3098 } 3099 return rc; 3100 } 3101 3102 static int emulate_mrs(struct pt_regs *regs, u32 insn) 3103 { 3104 u32 sys_reg, rt; 3105 3106 /* 3107 * sys_reg values are defined as used in mrs/msr instruction. 3108 * shift the imm value to get the encoding. 3109 */ 3110 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3111 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3112 return do_emulate_mrs(regs, sys_reg, rt); 3113 } 3114 3115 static struct undef_hook mrs_hook = { 3116 .instr_mask = 0xffff0000, 3117 .instr_val = 0xd5380000, 3118 .pstate_mask = PSR_AA32_MODE_MASK, 3119 .pstate_val = PSR_MODE_EL0t, 3120 .fn = emulate_mrs, 3121 }; 3122 3123 static int __init enable_mrs_emulation(void) 3124 { 3125 register_undef_hook(&mrs_hook); 3126 return 0; 3127 } 3128 3129 core_initcall(enable_mrs_emulation); 3130 3131 enum mitigation_state arm64_get_meltdown_state(void) 3132 { 3133 if (__meltdown_safe) 3134 return SPECTRE_UNAFFECTED; 3135 3136 if (arm64_kernel_unmapped_at_el0()) 3137 return SPECTRE_MITIGATED; 3138 3139 return SPECTRE_VULNERABLE; 3140 } 3141 3142 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3143 char *buf) 3144 { 3145 switch (arm64_get_meltdown_state()) { 3146 case SPECTRE_UNAFFECTED: 3147 return sprintf(buf, "Not affected\n"); 3148 3149 case SPECTRE_MITIGATED: 3150 return sprintf(buf, "Mitigation: PTI\n"); 3151 3152 default: 3153 return sprintf(buf, "Vulnerable\n"); 3154 } 3155 } 3156