1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx SERDES manipulation, via SMI bus 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 */ 9 10 #ifndef _MV88E6XXX_SERDES_H 11 #define _MV88E6XXX_SERDES_H 12 13 #include "chip.h" 14 15 #define MV88E6352_ADDR_SERDES 0x0f 16 #define MV88E6352_SERDES_PAGE_FIBER 0x01 17 #define MV88E6352_SERDES_IRQ 0x0b 18 #define MV88E6352_SERDES_INT_ENABLE 0x12 19 #define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14) 20 #define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13) 21 #define MV88E6352_SERDES_INT_PAGE_RX BIT(12) 22 #define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11) 23 #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10) 24 #define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9) 25 #define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8) 26 #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7) 27 #define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4) 28 #define MV88E6352_SERDES_INT_STATUS 0x13 29 30 31 #define MV88E6341_PORT5_LANE 0x15 32 33 #define MV88E6390_PORT9_LANE0 0x09 34 #define MV88E6390_PORT9_LANE1 0x12 35 #define MV88E6390_PORT9_LANE2 0x13 36 #define MV88E6390_PORT9_LANE3 0x14 37 #define MV88E6390_PORT10_LANE0 0x0a 38 #define MV88E6390_PORT10_LANE1 0x15 39 #define MV88E6390_PORT10_LANE2 0x16 40 #define MV88E6390_PORT10_LANE3 0x17 41 42 /* 10GBASE-R and 10GBASE-X4/X2 */ 43 #define MV88E6390_10G_CTRL1 (0x1000 + MDIO_CTRL1) 44 #define MV88E6390_10G_STAT1 (0x1000 + MDIO_STAT1) 45 #define MV88E6393X_10G_INT_ENABLE 0x9000 46 #define MV88E6393X_10G_INT_LINK_CHANGE BIT(2) 47 #define MV88E6393X_10G_INT_STATUS 0x9001 48 49 /* 1000BASE-X and SGMII */ 50 #define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR) 51 #define MV88E6390_SGMII_BMSR (0x2000 + MII_BMSR) 52 #define MV88E6390_SGMII_ADVERTISE (0x2000 + MII_ADVERTISE) 53 #define MV88E6390_SGMII_LPA (0x2000 + MII_LPA) 54 #define MV88E6390_SGMII_INT_ENABLE 0xa001 55 #define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14) 56 #define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13) 57 #define MV88E6390_SGMII_INT_PAGE_RX BIT(12) 58 #define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11) 59 #define MV88E6390_SGMII_INT_LINK_DOWN BIT(10) 60 #define MV88E6390_SGMII_INT_LINK_UP BIT(9) 61 #define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8) 62 #define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7) 63 #define MV88E6390_SGMII_INT_STATUS 0xa002 64 #define MV88E6390_SGMII_PHY_STATUS 0xa003 65 #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14) 66 #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000 67 #define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000 68 #define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000 69 #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13) 70 #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11) 71 #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10) 72 #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3) 73 #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2) 74 75 /* Packet generator pad packet checker */ 76 #define MV88E6390_PG_CONTROL 0xf010 77 #define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0) 78 79 #define MV88E6393X_PORT0_LANE 0x00 80 #define MV88E6393X_PORT9_LANE 0x09 81 #define MV88E6393X_PORT10_LANE 0x0a 82 83 /* Port Operational Configuration */ 84 #define MV88E6393X_SERDES_POC 0xf002 85 #define MV88E6393X_SERDES_POC_PCS_1000BASEX 0x0000 86 #define MV88E6393X_SERDES_POC_PCS_2500BASEX 0x0001 87 #define MV88E6393X_SERDES_POC_PCS_SGMII_PHY 0x0002 88 #define MV88E6393X_SERDES_POC_PCS_SGMII_MAC 0x0003 89 #define MV88E6393X_SERDES_POC_PCS_5GBASER 0x0004 90 #define MV88E6393X_SERDES_POC_PCS_10GBASER 0x0005 91 #define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY 0x0006 92 #define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC 0x0007 93 #define MV88E6393X_SERDES_POC_PCS_MASK 0x0007 94 #define MV88E6393X_SERDES_POC_RESET BIT(15) 95 #define MV88E6393X_SERDES_POC_PDOWN BIT(5) 96 #define MV88E6393X_SERDES_POC_AN BIT(3) 97 #define MV88E6393X_SERDES_CTRL1 0xf003 98 #define MV88E6393X_SERDES_CTRL1_TX_PDOWN BIT(9) 99 #define MV88E6393X_SERDES_CTRL1_RX_PDOWN BIT(8) 100 101 #define MV88E6393X_ERRATA_4_8_REG 0xF074 102 #define MV88E6393X_ERRATA_4_8_BIT BIT(14) 103 104 int mv88e6185_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 105 int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 106 int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 107 int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 108 int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 109 int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 110 int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 111 int lane, unsigned int mode, 112 phy_interface_t interface, 113 const unsigned long *advertise); 114 int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 115 int lane, unsigned int mode, 116 phy_interface_t interface, 117 const unsigned long *advertise); 118 int mv88e6185_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 119 int lane, struct phylink_link_state *state); 120 int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 121 int lane, struct phylink_link_state *state); 122 int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 123 int lane, struct phylink_link_state *state); 124 int mv88e6393x_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 125 int lane, struct phylink_link_state *state); 126 int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, 127 int lane); 128 int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, 129 int lane); 130 int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 131 int lane, int speed, int duplex); 132 int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 133 int lane, int speed, int duplex); 134 unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip, 135 int port); 136 unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip, 137 int port); 138 int mv88e6185_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, 139 bool up); 140 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, 141 bool on); 142 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, 143 bool on); 144 int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, 145 bool on); 146 int mv88e6393x_serdes_setup_errata(struct mv88e6xxx_chip *chip); 147 int mv88e6097_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, 148 bool enable); 149 int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, 150 bool enable); 151 int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, 152 bool enable); 153 int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, 154 int lane, bool enable); 155 irqreturn_t mv88e6097_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 156 int lane); 157 irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 158 int lane); 159 irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 160 int lane); 161 irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 162 int lane); 163 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); 164 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip, 165 int port, uint8_t *data); 166 int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, 167 uint64_t *data); 168 int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); 169 int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip, 170 int port, uint8_t *data); 171 int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, 172 uint64_t *data); 173 174 int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); 175 void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); 176 int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); 177 void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); 178 179 /* Return the (first) SERDES lane address a port is using, -errno otherwise. */ 180 static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip, 181 int port) 182 { 183 if (!chip->info->ops->serdes_get_lane) 184 return -EOPNOTSUPP; 185 186 return chip->info->ops->serdes_get_lane(chip, port); 187 } 188 189 static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip, 190 int port, int lane) 191 { 192 if (!chip->info->ops->serdes_power) 193 return -EOPNOTSUPP; 194 195 return chip->info->ops->serdes_power(chip, port, lane, true); 196 } 197 198 static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip, 199 int port, int lane) 200 { 201 if (!chip->info->ops->serdes_power) 202 return -EOPNOTSUPP; 203 204 return chip->info->ops->serdes_power(chip, port, lane, false); 205 } 206 207 static inline unsigned int 208 mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port) 209 { 210 if (!chip->info->ops->serdes_irq_mapping) 211 return 0; 212 213 return chip->info->ops->serdes_irq_mapping(chip, port); 214 } 215 216 static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip, 217 int port, int lane) 218 { 219 if (!chip->info->ops->serdes_irq_enable) 220 return -EOPNOTSUPP; 221 222 return chip->info->ops->serdes_irq_enable(chip, port, lane, true); 223 } 224 225 static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip, 226 int port, int lane) 227 { 228 if (!chip->info->ops->serdes_irq_enable) 229 return -EOPNOTSUPP; 230 231 return chip->info->ops->serdes_irq_enable(chip, port, lane, false); 232 } 233 234 static inline irqreturn_t 235 mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, int lane) 236 { 237 if (!chip->info->ops->serdes_irq_status) 238 return IRQ_NONE; 239 240 return chip->info->ops->serdes_irq_status(chip, port, lane); 241 } 242 243 #endif 244