1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-gcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 11#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 21#include <dt-bindings/phy/phy-qcom-qmp.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 bi_tcxo_div2: bi-tcxo-div2-clk { 44 #clock-cells = <0>; 45 compatible = "fixed-factor-clock"; 46 clocks = <&rpmhcc RPMH_CXO_CLK>; 47 clock-mult = <1>; 48 clock-div = <2>; 49 }; 50 51 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 52 #clock-cells = <0>; 53 compatible = "fixed-factor-clock"; 54 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 55 clock-mult = <1>; 56 clock-div = <2>; 57 }; 58 59 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 CPU0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a510"; 72 reg = <0 0>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 next-level-cache = <&L2_0>; 76 power-domains = <&CPU_PD0>; 77 power-domain-names = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 #cooling-cells = <2>; 82 L2_0: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 next-level-cache = <&L3_0>; 86 L3_0: l3-cache { 87 compatible = "cache"; 88 cache-level = <3>; 89 }; 90 }; 91 }; 92 93 CPU1: cpu@100 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a510"; 96 reg = <0 0x100>; 97 clocks = <&cpufreq_hw 0>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_100>; 100 power-domains = <&CPU_PD1>; 101 power-domain-names = "psci"; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 capacity-dmips-mhz = <1024>; 104 dynamic-power-coefficient = <100>; 105 #cooling-cells = <2>; 106 L2_100: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU2: cpu@200 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a510"; 116 reg = <0 0x200>; 117 clocks = <&cpufreq_hw 0>; 118 enable-method = "psci"; 119 next-level-cache = <&L2_200>; 120 power-domains = <&CPU_PD2>; 121 power-domain-names = "psci"; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 capacity-dmips-mhz = <1024>; 124 dynamic-power-coefficient = <100>; 125 #cooling-cells = <2>; 126 L2_200: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 next-level-cache = <&L3_0>; 130 }; 131 }; 132 133 CPU3: cpu@300 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a715"; 136 reg = <0 0x300>; 137 clocks = <&cpufreq_hw 1>; 138 enable-method = "psci"; 139 next-level-cache = <&L2_300>; 140 power-domains = <&CPU_PD3>; 141 power-domain-names = "psci"; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 capacity-dmips-mhz = <1792>; 144 dynamic-power-coefficient = <270>; 145 #cooling-cells = <2>; 146 L2_300: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU4: cpu@400 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a715"; 156 reg = <0 0x400>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_400>; 160 power-domains = <&CPU_PD4>; 161 power-domain-names = "psci"; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 capacity-dmips-mhz = <1792>; 164 dynamic-power-coefficient = <270>; 165 #cooling-cells = <2>; 166 L2_400: l2-cache { 167 compatible = "cache"; 168 cache-level = <2>; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 CPU5: cpu@500 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a710"; 176 reg = <0 0x500>; 177 clocks = <&cpufreq_hw 1>; 178 enable-method = "psci"; 179 next-level-cache = <&L2_500>; 180 power-domains = <&CPU_PD5>; 181 power-domain-names = "psci"; 182 qcom,freq-domain = <&cpufreq_hw 1>; 183 capacity-dmips-mhz = <1792>; 184 dynamic-power-coefficient = <270>; 185 #cooling-cells = <2>; 186 L2_500: l2-cache { 187 compatible = "cache"; 188 cache-level = <2>; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU6: cpu@600 { 194 device_type = "cpu"; 195 compatible = "arm,cortex-a710"; 196 reg = <0 0x600>; 197 clocks = <&cpufreq_hw 1>; 198 enable-method = "psci"; 199 next-level-cache = <&L2_600>; 200 power-domains = <&CPU_PD6>; 201 power-domain-names = "psci"; 202 qcom,freq-domain = <&cpufreq_hw 1>; 203 capacity-dmips-mhz = <1792>; 204 dynamic-power-coefficient = <270>; 205 #cooling-cells = <2>; 206 L2_600: l2-cache { 207 compatible = "cache"; 208 cache-level = <2>; 209 next-level-cache = <&L3_0>; 210 }; 211 }; 212 213 CPU7: cpu@700 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-x3"; 216 reg = <0 0x700>; 217 clocks = <&cpufreq_hw 2>; 218 enable-method = "psci"; 219 next-level-cache = <&L2_700>; 220 power-domains = <&CPU_PD7>; 221 power-domain-names = "psci"; 222 qcom,freq-domain = <&cpufreq_hw 2>; 223 capacity-dmips-mhz = <1894>; 224 dynamic-power-coefficient = <588>; 225 #cooling-cells = <2>; 226 L2_700: l2-cache { 227 compatible = "cache"; 228 cache-level = <2>; 229 next-level-cache = <&L3_0>; 230 }; 231 }; 232 233 cpu-map { 234 cluster0 { 235 core0 { 236 cpu = <&CPU0>; 237 }; 238 239 core1 { 240 cpu = <&CPU1>; 241 }; 242 243 core2 { 244 cpu = <&CPU2>; 245 }; 246 247 core3 { 248 cpu = <&CPU3>; 249 }; 250 251 core4 { 252 cpu = <&CPU4>; 253 }; 254 255 core5 { 256 cpu = <&CPU5>; 257 }; 258 259 core6 { 260 cpu = <&CPU6>; 261 }; 262 263 core7 { 264 cpu = <&CPU7>; 265 }; 266 }; 267 }; 268 269 idle-states { 270 entry-method = "psci"; 271 272 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 273 compatible = "arm,idle-state"; 274 idle-state-name = "silver-rail-power-collapse"; 275 arm,psci-suspend-param = <0x40000004>; 276 entry-latency-us = <800>; 277 exit-latency-us = <750>; 278 min-residency-us = <4090>; 279 local-timer-stop; 280 }; 281 282 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "gold-rail-power-collapse"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <600>; 287 exit-latency-us = <1550>; 288 min-residency-us = <4791>; 289 local-timer-stop; 290 }; 291 }; 292 293 domain-idle-states { 294 CLUSTER_SLEEP_0: cluster-sleep-0 { 295 compatible = "domain-idle-state"; 296 arm,psci-suspend-param = <0x41000044>; 297 entry-latency-us = <1050>; 298 exit-latency-us = <2500>; 299 min-residency-us = <5309>; 300 }; 301 302 CLUSTER_SLEEP_1: cluster-sleep-1 { 303 compatible = "domain-idle-state"; 304 arm,psci-suspend-param = <0x4100c344>; 305 entry-latency-us = <2700>; 306 exit-latency-us = <3500>; 307 min-residency-us = <13959>; 308 }; 309 }; 310 }; 311 312 firmware { 313 scm: scm { 314 compatible = "qcom,scm-sm8550", "qcom,scm"; 315 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 316 }; 317 }; 318 319 clk_virt: interconnect-0 { 320 compatible = "qcom,sm8550-clk-virt"; 321 #interconnect-cells = <2>; 322 qcom,bcm-voters = <&apps_bcm_voter>; 323 }; 324 325 mc_virt: interconnect-1 { 326 compatible = "qcom,sm8550-mc-virt"; 327 #interconnect-cells = <2>; 328 qcom,bcm-voters = <&apps_bcm_voter>; 329 }; 330 331 memory@a0000000 { 332 device_type = "memory"; 333 /* We expect the bootloader to fill in the size */ 334 reg = <0 0xa0000000 0 0>; 335 }; 336 337 pmu { 338 compatible = "arm,armv8-pmuv3"; 339 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 340 }; 341 342 psci { 343 compatible = "arm,psci-1.0"; 344 method = "smc"; 345 346 CPU_PD0: power-domain-cpu0 { 347 #power-domain-cells = <0>; 348 power-domains = <&CLUSTER_PD>; 349 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 350 }; 351 352 CPU_PD1: power-domain-cpu1 { 353 #power-domain-cells = <0>; 354 power-domains = <&CLUSTER_PD>; 355 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 356 }; 357 358 CPU_PD2: power-domain-cpu2 { 359 #power-domain-cells = <0>; 360 power-domains = <&CLUSTER_PD>; 361 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 362 }; 363 364 CPU_PD3: power-domain-cpu3 { 365 #power-domain-cells = <0>; 366 power-domains = <&CLUSTER_PD>; 367 domain-idle-states = <&BIG_CPU_SLEEP_0>; 368 }; 369 370 CPU_PD4: power-domain-cpu4 { 371 #power-domain-cells = <0>; 372 power-domains = <&CLUSTER_PD>; 373 domain-idle-states = <&BIG_CPU_SLEEP_0>; 374 }; 375 376 CPU_PD5: power-domain-cpu5 { 377 #power-domain-cells = <0>; 378 power-domains = <&CLUSTER_PD>; 379 domain-idle-states = <&BIG_CPU_SLEEP_0>; 380 }; 381 382 CPU_PD6: power-domain-cpu6 { 383 #power-domain-cells = <0>; 384 power-domains = <&CLUSTER_PD>; 385 domain-idle-states = <&BIG_CPU_SLEEP_0>; 386 }; 387 388 CPU_PD7: power-domain-cpu7 { 389 #power-domain-cells = <0>; 390 power-domains = <&CLUSTER_PD>; 391 domain-idle-states = <&BIG_CPU_SLEEP_0>; 392 }; 393 394 CLUSTER_PD: power-domain-cluster { 395 #power-domain-cells = <0>; 396 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 397 }; 398 }; 399 400 reserved_memory: reserved-memory { 401 #address-cells = <2>; 402 #size-cells = <2>; 403 ranges; 404 405 hyp_mem: hyp-region@80000000 { 406 reg = <0 0x80000000 0 0xa00000>; 407 no-map; 408 }; 409 410 cpusys_vm_mem: cpusys-vm-region@80a00000 { 411 reg = <0 0x80a00000 0 0x400000>; 412 no-map; 413 }; 414 415 hyp_tags_mem: hyp-tags-region@80e00000 { 416 reg = <0 0x80e00000 0 0x3d0000>; 417 no-map; 418 }; 419 420 xbl_sc_mem: xbl-sc-region@d8100000 { 421 reg = <0 0xd8100000 0 0x40000>; 422 no-map; 423 }; 424 425 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 426 reg = <0 0x811d0000 0 0x30000>; 427 no-map; 428 }; 429 430 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 431 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 432 reg = <0 0x81a00000 0 0x260000>; 433 no-map; 434 }; 435 436 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 437 compatible = "qcom,cmd-db"; 438 reg = <0 0x81c60000 0 0x20000>; 439 no-map; 440 }; 441 442 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 443 aop_config_merged_mem: aop-config-merged-region@81c80000 { 444 reg = <0 0x81c80000 0 0x74000>; 445 no-map; 446 }; 447 448 /* secdata region can be reused by apps */ 449 smem: smem@81d00000 { 450 compatible = "qcom,smem"; 451 reg = <0 0x81d00000 0 0x200000>; 452 hwlocks = <&tcsr_mutex 3>; 453 no-map; 454 }; 455 456 adsp_mhi_mem: adsp-mhi-region@81f00000 { 457 reg = <0 0x81f00000 0 0x20000>; 458 no-map; 459 }; 460 461 global_sync_mem: global-sync-region@82600000 { 462 reg = <0 0x82600000 0 0x100000>; 463 no-map; 464 }; 465 466 tz_stat_mem: tz-stat-region@82700000 { 467 reg = <0 0x82700000 0 0x100000>; 468 no-map; 469 }; 470 471 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 472 reg = <0 0x82800000 0 0x4600000>; 473 no-map; 474 }; 475 476 mpss_mem: mpss-region@8a800000 { 477 reg = <0 0x8a800000 0 0x10800000>; 478 no-map; 479 }; 480 481 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 482 reg = <0 0x9b000000 0 0x80000>; 483 no-map; 484 }; 485 486 ipa_fw_mem: ipa-fw-region@9b080000 { 487 reg = <0 0x9b080000 0 0x10000>; 488 no-map; 489 }; 490 491 ipa_gsi_mem: ipa-gsi-region@9b090000 { 492 reg = <0 0x9b090000 0 0xa000>; 493 no-map; 494 }; 495 496 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 497 reg = <0 0x9b09a000 0 0x2000>; 498 no-map; 499 }; 500 501 spss_region_mem: spss-region@9b100000 { 502 reg = <0 0x9b100000 0 0x180000>; 503 no-map; 504 }; 505 506 /* First part of the "SPU secure shared memory" region */ 507 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 508 reg = <0 0x9b280000 0 0x60000>; 509 no-map; 510 }; 511 512 /* Second part of the "SPU secure shared memory" region */ 513 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 514 reg = <0 0x9b2e0000 0 0x20000>; 515 no-map; 516 }; 517 518 camera_mem: camera-region@9b300000 { 519 reg = <0 0x9b300000 0 0x800000>; 520 no-map; 521 }; 522 523 video_mem: video-region@9bb00000 { 524 reg = <0 0x9bb00000 0 0x700000>; 525 no-map; 526 }; 527 528 cvp_mem: cvp-region@9c200000 { 529 reg = <0 0x9c200000 0 0x700000>; 530 no-map; 531 }; 532 533 cdsp_mem: cdsp-region@9c900000 { 534 reg = <0 0x9c900000 0 0x2000000>; 535 no-map; 536 }; 537 538 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 539 reg = <0 0x9e900000 0 0x80000>; 540 no-map; 541 }; 542 543 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 544 reg = <0 0x9e980000 0 0x80000>; 545 no-map; 546 }; 547 548 adspslpi_mem: adspslpi-region@9ea00000 { 549 reg = <0 0x9ea00000 0 0x4080000>; 550 no-map; 551 }; 552 553 /* uefi region can be reused by apps */ 554 555 /* Linux kernel image is loaded at 0xa8000000 */ 556 557 rmtfs_mem: rmtfs-region@d4a80000 { 558 compatible = "qcom,rmtfs-mem"; 559 reg = <0x0 0xd4a80000 0x0 0x280000>; 560 no-map; 561 562 qcom,client-id = <1>; 563 qcom,vmid = <15>; 564 }; 565 566 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 567 reg = <0 0xd4d00000 0 0x3300000>; 568 no-map; 569 }; 570 571 tz_reserved_mem: tz-reserved-region@d8000000 { 572 reg = <0 0xd8000000 0 0x100000>; 573 no-map; 574 }; 575 576 cpucp_fw_mem: cpucp-fw-region@d8140000 { 577 reg = <0 0xd8140000 0 0x1c0000>; 578 no-map; 579 }; 580 581 qtee_mem: qtee-region@d8300000 { 582 reg = <0 0xd8300000 0 0x500000>; 583 no-map; 584 }; 585 586 ta_mem: ta-region@d8800000 { 587 reg = <0 0xd8800000 0 0x8a00000>; 588 no-map; 589 }; 590 591 tz_tags_mem: tz-tags-region@e1200000 { 592 reg = <0 0xe1200000 0 0x2740000>; 593 no-map; 594 }; 595 596 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 597 reg = <0 0xe6440000 0 0x279000>; 598 no-map; 599 }; 600 601 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 602 reg = <0 0xf3600000 0 0x4aee000>; 603 no-map; 604 }; 605 606 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 607 reg = <0 0xf80ee000 0 0x1000>; 608 no-map; 609 }; 610 611 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 612 reg = <0 0xf80ef000 0 0x9000>; 613 no-map; 614 }; 615 616 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 617 reg = <0 0xf80f8000 0 0x4000>; 618 no-map; 619 }; 620 621 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 622 reg = <0 0xf80fc000 0 0x4000>; 623 no-map; 624 }; 625 626 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 627 reg = <0 0xf8100000 0 0x100000>; 628 no-map; 629 }; 630 631 oem_vm_mem: oem-vm-region@f8400000 { 632 reg = <0 0xf8400000 0 0x4800000>; 633 no-map; 634 }; 635 636 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 637 reg = <0 0xfcc00000 0 0x4000>; 638 no-map; 639 }; 640 641 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 642 reg = <0 0xfcc04000 0 0x100000>; 643 no-map; 644 }; 645 646 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 647 reg = <0 0xfce00000 0 0x2900000>; 648 no-map; 649 }; 650 651 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 652 reg = <0 0xff700000 0 0x100000>; 653 no-map; 654 }; 655 }; 656 657 smp2p-adsp { 658 compatible = "qcom,smp2p"; 659 qcom,smem = <443>, <429>; 660 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 661 IPCC_MPROC_SIGNAL_SMP2P 662 IRQ_TYPE_EDGE_RISING>; 663 mboxes = <&ipcc IPCC_CLIENT_LPASS 664 IPCC_MPROC_SIGNAL_SMP2P>; 665 666 qcom,local-pid = <0>; 667 qcom,remote-pid = <2>; 668 669 smp2p_adsp_out: master-kernel { 670 qcom,entry-name = "master-kernel"; 671 #qcom,smem-state-cells = <1>; 672 }; 673 674 smp2p_adsp_in: slave-kernel { 675 qcom,entry-name = "slave-kernel"; 676 interrupt-controller; 677 #interrupt-cells = <2>; 678 }; 679 }; 680 681 smp2p-cdsp { 682 compatible = "qcom,smp2p"; 683 qcom,smem = <94>, <432>; 684 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 685 IPCC_MPROC_SIGNAL_SMP2P 686 IRQ_TYPE_EDGE_RISING>; 687 mboxes = <&ipcc IPCC_CLIENT_CDSP 688 IPCC_MPROC_SIGNAL_SMP2P>; 689 690 qcom,local-pid = <0>; 691 qcom,remote-pid = <5>; 692 693 smp2p_cdsp_out: master-kernel { 694 qcom,entry-name = "master-kernel"; 695 #qcom,smem-state-cells = <1>; 696 }; 697 698 smp2p_cdsp_in: slave-kernel { 699 qcom,entry-name = "slave-kernel"; 700 interrupt-controller; 701 #interrupt-cells = <2>; 702 }; 703 }; 704 705 smp2p-modem { 706 compatible = "qcom,smp2p"; 707 qcom,smem = <435>, <428>; 708 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 709 IPCC_MPROC_SIGNAL_SMP2P 710 IRQ_TYPE_EDGE_RISING>; 711 mboxes = <&ipcc IPCC_CLIENT_MPSS 712 IPCC_MPROC_SIGNAL_SMP2P>; 713 714 qcom,local-pid = <0>; 715 qcom,remote-pid = <1>; 716 717 smp2p_modem_out: master-kernel { 718 qcom,entry-name = "master-kernel"; 719 #qcom,smem-state-cells = <1>; 720 }; 721 722 smp2p_modem_in: slave-kernel { 723 qcom,entry-name = "slave-kernel"; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 }; 727 728 ipa_smp2p_out: ipa-ap-to-modem { 729 qcom,entry-name = "ipa"; 730 #qcom,smem-state-cells = <1>; 731 }; 732 733 ipa_smp2p_in: ipa-modem-to-ap { 734 qcom,entry-name = "ipa"; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 }; 738 }; 739 740 soc: soc@0 { 741 compatible = "simple-bus"; 742 ranges = <0 0 0 0 0x10 0>; 743 dma-ranges = <0 0 0 0 0x10 0>; 744 745 #address-cells = <2>; 746 #size-cells = <2>; 747 748 gcc: clock-controller@100000 { 749 compatible = "qcom,sm8550-gcc"; 750 reg = <0 0x00100000 0 0x1f4200>; 751 #clock-cells = <1>; 752 #reset-cells = <1>; 753 #power-domain-cells = <1>; 754 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 755 <&pcie0_phy>, 756 <&pcie1_phy>, 757 <&pcie_1_phy_aux_clk>, 758 <&ufs_mem_phy 0>, 759 <&ufs_mem_phy 1>, 760 <&ufs_mem_phy 2>, 761 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 762 }; 763 764 ipcc: mailbox@408000 { 765 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 766 reg = <0 0x00408000 0 0x1000>; 767 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-controller; 769 #interrupt-cells = <3>; 770 #mbox-cells = <2>; 771 }; 772 773 gpi_dma2: dma-controller@800000 { 774 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 775 #dma-cells = <3>; 776 reg = <0 0x00800000 0 0x60000>; 777 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 789 dma-channels = <12>; 790 dma-channel-mask = <0x3e>; 791 iommus = <&apps_smmu 0x436 0>; 792 status = "disabled"; 793 }; 794 795 qupv3_id_1: geniqup@8c0000 { 796 compatible = "qcom,geni-se-qup"; 797 reg = <0 0x008c0000 0 0x2000>; 798 ranges; 799 clock-names = "m-ahb", "s-ahb"; 800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 802 iommus = <&apps_smmu 0x423 0>; 803 #address-cells = <2>; 804 #size-cells = <2>; 805 status = "disabled"; 806 807 i2c8: i2c@880000 { 808 compatible = "qcom,geni-i2c"; 809 reg = <0 0x00880000 0 0x4000>; 810 clock-names = "se"; 811 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&qup_i2c8_data_clk>; 814 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 818 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 819 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 820 interconnect-names = "qup-core", "qup-config", "qup-memory"; 821 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 822 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 823 dma-names = "tx", "rx"; 824 status = "disabled"; 825 }; 826 827 spi8: spi@880000 { 828 compatible = "qcom,geni-spi"; 829 reg = <0 0x00880000 0 0x4000>; 830 clock-names = "se"; 831 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 832 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 833 pinctrl-names = "default"; 834 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 835 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 836 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 837 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 838 interconnect-names = "qup-core", "qup-config", "qup-memory"; 839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 840 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 841 dma-names = "tx", "rx"; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 status = "disabled"; 845 }; 846 847 i2c9: i2c@884000 { 848 compatible = "qcom,geni-i2c"; 849 reg = <0 0x00884000 0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&qup_i2c9_data_clk>; 854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 858 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 860 interconnect-names = "qup-core", "qup-config", "qup-memory"; 861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 862 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 863 dma-names = "tx", "rx"; 864 status = "disabled"; 865 }; 866 867 spi9: spi@884000 { 868 compatible = "qcom,geni-spi"; 869 reg = <0 0x00884000 0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 876 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 877 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 878 interconnect-names = "qup-core", "qup-config", "qup-memory"; 879 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 880 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 881 dma-names = "tx", "rx"; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 status = "disabled"; 885 }; 886 887 i2c10: i2c@888000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00888000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c10_data_clk>; 894 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 898 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 899 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 900 interconnect-names = "qup-core", "qup-config", "qup-memory"; 901 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 902 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 903 dma-names = "tx", "rx"; 904 status = "disabled"; 905 }; 906 907 spi10: spi@888000 { 908 compatible = "qcom,geni-spi"; 909 reg = <0 0x00888000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 912 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 915 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 916 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 917 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 918 interconnect-names = "qup-core", "qup-config", "qup-memory"; 919 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 920 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 921 dma-names = "tx", "rx"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 status = "disabled"; 925 }; 926 927 i2c11: i2c@88c000 { 928 compatible = "qcom,geni-i2c"; 929 reg = <0 0x0088c000 0 0x4000>; 930 clock-names = "se"; 931 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 932 pinctrl-names = "default"; 933 pinctrl-0 = <&qup_i2c11_data_clk>; 934 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 938 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 939 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 940 interconnect-names = "qup-core", "qup-config", "qup-memory"; 941 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 942 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 943 dma-names = "tx", "rx"; 944 status = "disabled"; 945 }; 946 947 spi11: spi@88c000 { 948 compatible = "qcom,geni-spi"; 949 reg = <0 0x0088c000 0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 952 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 953 pinctrl-names = "default"; 954 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 955 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 956 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 957 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 958 interconnect-names = "qup-core", "qup-config", "qup-memory"; 959 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 960 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 961 dma-names = "tx", "rx"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 i2c12: i2c@890000 { 968 compatible = "qcom,geni-i2c"; 969 reg = <0 0x00890000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_i2c12_data_clk>; 974 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 978 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 979 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 980 interconnect-names = "qup-core", "qup-config", "qup-memory"; 981 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 982 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 983 dma-names = "tx", "rx"; 984 status = "disabled"; 985 }; 986 987 spi12: spi@890000 { 988 compatible = "qcom,geni-spi"; 989 reg = <0 0x00890000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 992 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 995 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 996 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 997 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 998 interconnect-names = "qup-core", "qup-config", "qup-memory"; 999 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1000 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1001 dma-names = "tx", "rx"; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 i2c13: i2c@894000 { 1008 compatible = "qcom,geni-i2c"; 1009 reg = <0 0x00894000 0 0x4000>; 1010 clock-names = "se"; 1011 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&qup_i2c13_data_clk>; 1014 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1018 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1019 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1020 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1021 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1022 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1023 dma-names = "tx", "rx"; 1024 status = "disabled"; 1025 }; 1026 1027 spi13: spi@894000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x00894000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1032 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1035 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1036 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1037 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1038 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1039 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1040 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1041 dma-names = "tx", "rx"; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 i2c15: i2c@89c000 { 1048 compatible = "qcom,geni-i2c"; 1049 reg = <0 0x0089c000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_i2c15_data_clk>; 1054 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1058 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1059 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1060 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1061 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1062 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1063 dma-names = "tx", "rx"; 1064 status = "disabled"; 1065 }; 1066 1067 spi15: spi@89c000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0 0x0089c000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1072 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1075 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1076 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1077 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1078 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1079 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1080 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1081 dma-names = "tx", "rx"; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 }; 1087 1088 i2c_master_hub_0: geniqup@9c0000 { 1089 compatible = "qcom,geni-se-i2c-master-hub"; 1090 reg = <0x0 0x009c0000 0x0 0x2000>; 1091 clock-names = "s-ahb"; 1092 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1093 #address-cells = <2>; 1094 #size-cells = <2>; 1095 ranges; 1096 status = "disabled"; 1097 1098 i2c_hub_0: i2c@980000 { 1099 compatible = "qcom,geni-i2c-master-hub"; 1100 reg = <0x0 0x00980000 0x0 0x4000>; 1101 clock-names = "se", "core"; 1102 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1103 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&hub_i2c0_data_clk>; 1106 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1111 interconnect-names = "qup-core", "qup-config"; 1112 status = "disabled"; 1113 }; 1114 1115 i2c_hub_1: i2c@984000 { 1116 compatible = "qcom,geni-i2c-master-hub"; 1117 reg = <0x0 0x00984000 0x0 0x4000>; 1118 clock-names = "se", "core"; 1119 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1120 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&hub_i2c1_data_clk>; 1123 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1127 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1128 interconnect-names = "qup-core", "qup-config"; 1129 status = "disabled"; 1130 }; 1131 1132 i2c_hub_2: i2c@988000 { 1133 compatible = "qcom,geni-i2c-master-hub"; 1134 reg = <0x0 0x00988000 0x0 0x4000>; 1135 clock-names = "se", "core"; 1136 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1137 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&hub_i2c2_data_clk>; 1140 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1145 interconnect-names = "qup-core", "qup-config"; 1146 status = "disabled"; 1147 }; 1148 1149 i2c_hub_3: i2c@98c000 { 1150 compatible = "qcom,geni-i2c-master-hub"; 1151 reg = <0x0 0x0098c000 0x0 0x4000>; 1152 clock-names = "se", "core"; 1153 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1154 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&hub_i2c3_data_clk>; 1157 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1161 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1162 interconnect-names = "qup-core", "qup-config"; 1163 status = "disabled"; 1164 }; 1165 1166 i2c_hub_4: i2c@990000 { 1167 compatible = "qcom,geni-i2c-master-hub"; 1168 reg = <0x0 0x00990000 0x0 0x4000>; 1169 clock-names = "se", "core"; 1170 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1171 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&hub_i2c4_data_clk>; 1174 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1178 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1179 interconnect-names = "qup-core", "qup-config"; 1180 status = "disabled"; 1181 }; 1182 1183 i2c_hub_5: i2c@994000 { 1184 compatible = "qcom,geni-i2c-master-hub"; 1185 reg = <0 0x00994000 0 0x4000>; 1186 clock-names = "se", "core"; 1187 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1188 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&hub_i2c5_data_clk>; 1191 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1196 interconnect-names = "qup-core", "qup-config"; 1197 status = "disabled"; 1198 }; 1199 1200 i2c_hub_6: i2c@998000 { 1201 compatible = "qcom,geni-i2c-master-hub"; 1202 reg = <0 0x00998000 0 0x4000>; 1203 clock-names = "se", "core"; 1204 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1205 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&hub_i2c6_data_clk>; 1208 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1212 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1213 interconnect-names = "qup-core", "qup-config"; 1214 status = "disabled"; 1215 }; 1216 1217 i2c_hub_7: i2c@99c000 { 1218 compatible = "qcom,geni-i2c-master-hub"; 1219 reg = <0 0x0099c000 0 0x4000>; 1220 clock-names = "se", "core"; 1221 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1222 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&hub_i2c7_data_clk>; 1225 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1230 interconnect-names = "qup-core", "qup-config"; 1231 status = "disabled"; 1232 }; 1233 1234 i2c_hub_8: i2c@9a0000 { 1235 compatible = "qcom,geni-i2c-master-hub"; 1236 reg = <0 0x009a0000 0 0x4000>; 1237 clock-names = "se", "core"; 1238 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1239 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&hub_i2c8_data_clk>; 1242 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1246 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1247 interconnect-names = "qup-core", "qup-config"; 1248 status = "disabled"; 1249 }; 1250 1251 i2c_hub_9: i2c@9a4000 { 1252 compatible = "qcom,geni-i2c-master-hub"; 1253 reg = <0 0x009a4000 0 0x4000>; 1254 clock-names = "se", "core"; 1255 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1256 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&hub_i2c9_data_clk>; 1259 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1263 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1264 interconnect-names = "qup-core", "qup-config"; 1265 status = "disabled"; 1266 }; 1267 }; 1268 1269 gpi_dma1: dma-controller@a00000 { 1270 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1271 #dma-cells = <3>; 1272 reg = <0 0x00a00000 0 0x60000>; 1273 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1285 dma-channels = <12>; 1286 dma-channel-mask = <0x1e>; 1287 iommus = <&apps_smmu 0xb6 0>; 1288 status = "disabled"; 1289 }; 1290 1291 qupv3_id_0: geniqup@ac0000 { 1292 compatible = "qcom,geni-se-qup"; 1293 reg = <0 0x00ac0000 0 0x2000>; 1294 ranges; 1295 clock-names = "m-ahb", "s-ahb"; 1296 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1297 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1298 iommus = <&apps_smmu 0xa3 0>; 1299 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1300 interconnect-names = "qup-core"; 1301 #address-cells = <2>; 1302 #size-cells = <2>; 1303 status = "disabled"; 1304 1305 i2c0: i2c@a80000 { 1306 compatible = "qcom,geni-i2c"; 1307 reg = <0 0x00a80000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_i2c0_data_clk>; 1312 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1316 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1317 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1318 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1319 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1320 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1321 dma-names = "tx", "rx"; 1322 status = "disabled"; 1323 }; 1324 1325 spi0: spi@a80000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0 0x00a80000 0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1330 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1333 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1334 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1335 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1336 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1337 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1338 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1339 dma-names = "tx", "rx"; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 status = "disabled"; 1343 }; 1344 1345 i2c1: i2c@a84000 { 1346 compatible = "qcom,geni-i2c"; 1347 reg = <0 0x00a84000 0 0x4000>; 1348 clock-names = "se"; 1349 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&qup_i2c1_data_clk>; 1352 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1356 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1357 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1358 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1359 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1360 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1361 dma-names = "tx", "rx"; 1362 status = "disabled"; 1363 }; 1364 1365 spi1: spi@a84000 { 1366 compatible = "qcom,geni-spi"; 1367 reg = <0 0x00a84000 0 0x4000>; 1368 clock-names = "se"; 1369 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1370 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1373 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1374 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1375 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1376 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1377 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1378 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1379 dma-names = "tx", "rx"; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 i2c2: i2c@a88000 { 1386 compatible = "qcom,geni-i2c"; 1387 reg = <0 0x00a88000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&qup_i2c2_data_clk>; 1392 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1396 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1397 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1398 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1399 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1400 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1401 dma-names = "tx", "rx"; 1402 status = "disabled"; 1403 }; 1404 1405 spi2: spi@a88000 { 1406 compatible = "qcom,geni-spi"; 1407 reg = <0 0x00a88000 0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1410 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1414 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1415 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1416 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1417 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1418 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1419 dma-names = "tx", "rx"; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 i2c3: i2c@a8c000 { 1426 compatible = "qcom,geni-i2c"; 1427 reg = <0 0x00a8c000 0 0x4000>; 1428 clock-names = "se"; 1429 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1430 pinctrl-names = "default"; 1431 pinctrl-0 = <&qup_i2c3_data_clk>; 1432 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1436 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1437 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1438 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1439 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1440 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1441 dma-names = "tx", "rx"; 1442 status = "disabled"; 1443 }; 1444 1445 spi3: spi@a8c000 { 1446 compatible = "qcom,geni-spi"; 1447 reg = <0 0x00a8c000 0 0x4000>; 1448 clock-names = "se"; 1449 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1450 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1453 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1454 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1455 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1456 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1457 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1458 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1459 dma-names = "tx", "rx"; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 status = "disabled"; 1463 }; 1464 1465 i2c4: i2c@a90000 { 1466 compatible = "qcom,geni-i2c"; 1467 reg = <0 0x00a90000 0 0x4000>; 1468 clock-names = "se"; 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1470 pinctrl-names = "default"; 1471 pinctrl-0 = <&qup_i2c4_data_clk>; 1472 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1476 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1477 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1478 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1479 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1480 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1481 dma-names = "tx", "rx"; 1482 status = "disabled"; 1483 }; 1484 1485 spi4: spi@a90000 { 1486 compatible = "qcom,geni-spi"; 1487 reg = <0 0x00a90000 0 0x4000>; 1488 clock-names = "se"; 1489 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1490 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1491 pinctrl-names = "default"; 1492 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1493 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1494 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1495 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1496 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1497 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1498 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1499 dma-names = "tx", "rx"; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 i2c5: i2c@a94000 { 1506 compatible = "qcom,geni-i2c"; 1507 reg = <0 0x00a94000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_i2c5_data_clk>; 1512 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1513 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1514 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1515 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1516 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1517 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1518 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1519 dma-names = "tx", "rx"; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 status = "disabled"; 1523 }; 1524 1525 spi5: spi@a94000 { 1526 compatible = "qcom,geni-spi"; 1527 reg = <0 0x00a94000 0 0x4000>; 1528 clock-names = "se"; 1529 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1530 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1531 pinctrl-names = "default"; 1532 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1533 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1534 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1535 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1536 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1537 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1538 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1539 dma-names = "tx", "rx"; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 status = "disabled"; 1543 }; 1544 1545 i2c6: i2c@a98000 { 1546 compatible = "qcom,geni-i2c"; 1547 reg = <0 0x00a98000 0 0x4000>; 1548 clock-names = "se"; 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1550 pinctrl-names = "default"; 1551 pinctrl-0 = <&qup_i2c6_data_clk>; 1552 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1556 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1557 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1558 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1559 dma-names = "tx", "rx"; 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 status = "disabled"; 1563 }; 1564 1565 spi6: spi@a98000 { 1566 compatible = "qcom,geni-spi"; 1567 reg = <0 0x00a98000 0 0x4000>; 1568 clock-names = "se"; 1569 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1570 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1573 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1574 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1575 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1576 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1577 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1578 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1579 dma-names = "tx", "rx"; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 status = "disabled"; 1583 }; 1584 1585 uart7: serial@a9c000 { 1586 compatible = "qcom,geni-debug-uart"; 1587 reg = <0 0x00a9c000 0 0x4000>; 1588 clock-names = "se"; 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&qup_uart7_default>; 1592 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1593 interconnect-names = "qup-core", "qup-config"; 1594 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1595 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1596 status = "disabled"; 1597 }; 1598 }; 1599 1600 cnoc_main: interconnect@1500000 { 1601 compatible = "qcom,sm8550-cnoc-main"; 1602 reg = <0 0x01500000 0 0x13080>; 1603 #interconnect-cells = <2>; 1604 qcom,bcm-voters = <&apps_bcm_voter>; 1605 }; 1606 1607 config_noc: interconnect@1600000 { 1608 compatible = "qcom,sm8550-config-noc"; 1609 reg = <0 0x01600000 0 0x6200>; 1610 #interconnect-cells = <2>; 1611 qcom,bcm-voters = <&apps_bcm_voter>; 1612 }; 1613 1614 system_noc: interconnect@1680000 { 1615 compatible = "qcom,sm8550-system-noc"; 1616 reg = <0 0x01680000 0 0x1d080>; 1617 #interconnect-cells = <2>; 1618 qcom,bcm-voters = <&apps_bcm_voter>; 1619 }; 1620 1621 pcie_noc: interconnect@16c0000 { 1622 compatible = "qcom,sm8550-pcie-anoc"; 1623 reg = <0 0x016c0000 0 0x12200>; 1624 #interconnect-cells = <2>; 1625 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1626 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1627 qcom,bcm-voters = <&apps_bcm_voter>; 1628 }; 1629 1630 aggre1_noc: interconnect@16e0000 { 1631 compatible = "qcom,sm8550-aggre1-noc"; 1632 reg = <0 0x016e0000 0 0x14400>; 1633 #interconnect-cells = <2>; 1634 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1635 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1636 qcom,bcm-voters = <&apps_bcm_voter>; 1637 }; 1638 1639 aggre2_noc: interconnect@1700000 { 1640 compatible = "qcom,sm8550-aggre2-noc"; 1641 reg = <0 0x01700000 0 0x1e400>; 1642 #interconnect-cells = <2>; 1643 clocks = <&rpmhcc RPMH_IPA_CLK>; 1644 qcom,bcm-voters = <&apps_bcm_voter>; 1645 }; 1646 1647 mmss_noc: interconnect@1780000 { 1648 compatible = "qcom,sm8550-mmss-noc"; 1649 reg = <0 0x01780000 0 0x5b800>; 1650 #interconnect-cells = <2>; 1651 qcom,bcm-voters = <&apps_bcm_voter>; 1652 }; 1653 1654 pcie0: pci@1c00000 { 1655 device_type = "pci"; 1656 compatible = "qcom,pcie-sm8550"; 1657 reg = <0 0x01c00000 0 0x3000>, 1658 <0 0x60000000 0 0xf1d>, 1659 <0 0x60000f20 0 0xa8>, 1660 <0 0x60001000 0 0x1000>, 1661 <0 0x60100000 0 0x100000>; 1662 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1663 #address-cells = <3>; 1664 #size-cells = <2>; 1665 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1666 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1667 bus-range = <0x00 0xff>; 1668 1669 dma-coherent; 1670 1671 linux,pci-domain = <0>; 1672 num-lanes = <2>; 1673 1674 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1675 interrupt-names = "msi"; 1676 1677 #interrupt-cells = <1>; 1678 interrupt-map-mask = <0 0 0 0x7>; 1679 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1680 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1681 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1682 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1683 1684 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1685 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1686 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1687 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1688 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1689 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1690 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1691 clock-names = "aux", 1692 "cfg", 1693 "bus_master", 1694 "bus_slave", 1695 "slave_q2a", 1696 "ddrss_sf_tbu", 1697 "noc_aggr"; 1698 1699 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1700 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1701 interconnect-names = "pcie-mem", "cpu-pcie"; 1702 1703 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1704 <0x100 &apps_smmu 0x1401 0x1>; 1705 1706 resets = <&gcc GCC_PCIE_0_BCR>; 1707 reset-names = "pci"; 1708 1709 power-domains = <&gcc PCIE_0_GDSC>; 1710 1711 phys = <&pcie0_phy>; 1712 phy-names = "pciephy"; 1713 1714 status = "disabled"; 1715 }; 1716 1717 pcie0_phy: phy@1c06000 { 1718 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1719 reg = <0 0x01c06000 0 0x2000>; 1720 1721 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1722 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1723 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1724 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1725 <&gcc GCC_PCIE_0_PIPE_CLK>; 1726 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1727 "pipe"; 1728 1729 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1730 reset-names = "phy"; 1731 1732 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1733 assigned-clock-rates = <100000000>; 1734 1735 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1736 1737 #clock-cells = <0>; 1738 clock-output-names = "pcie0_pipe_clk"; 1739 1740 #phy-cells = <0>; 1741 1742 status = "disabled"; 1743 }; 1744 1745 pcie1: pci@1c08000 { 1746 device_type = "pci"; 1747 compatible = "qcom,pcie-sm8550"; 1748 reg = <0x0 0x01c08000 0x0 0x3000>, 1749 <0x0 0x40000000 0x0 0xf1d>, 1750 <0x0 0x40000f20 0x0 0xa8>, 1751 <0x0 0x40001000 0x0 0x1000>, 1752 <0x0 0x40100000 0x0 0x100000>; 1753 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1754 #address-cells = <3>; 1755 #size-cells = <2>; 1756 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1757 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1758 bus-range = <0x00 0xff>; 1759 1760 dma-coherent; 1761 1762 linux,pci-domain = <1>; 1763 num-lanes = <2>; 1764 1765 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1766 interrupt-names = "msi"; 1767 1768 #interrupt-cells = <1>; 1769 interrupt-map-mask = <0 0 0 0x7>; 1770 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1771 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1772 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1773 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1774 1775 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1776 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1777 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1778 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1779 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1780 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1781 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1782 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1783 clock-names = "aux", 1784 "cfg", 1785 "bus_master", 1786 "bus_slave", 1787 "slave_q2a", 1788 "ddrss_sf_tbu", 1789 "noc_aggr", 1790 "cnoc_sf_axi"; 1791 1792 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1793 assigned-clock-rates = <19200000>; 1794 1795 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1796 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1797 interconnect-names = "pcie-mem", "cpu-pcie"; 1798 1799 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1800 <0x100 &apps_smmu 0x1481 0x1>; 1801 1802 resets = <&gcc GCC_PCIE_1_BCR>, 1803 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1804 reset-names = "pci", "link_down"; 1805 1806 power-domains = <&gcc PCIE_1_GDSC>; 1807 1808 phys = <&pcie1_phy>; 1809 phy-names = "pciephy"; 1810 1811 status = "disabled"; 1812 }; 1813 1814 pcie1_phy: phy@1c0e000 { 1815 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1816 reg = <0x0 0x01c0e000 0x0 0x2000>; 1817 1818 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1819 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1820 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1821 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1822 <&gcc GCC_PCIE_1_PIPE_CLK>; 1823 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1824 "pipe"; 1825 1826 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1827 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1828 reset-names = "phy", "phy_nocsr"; 1829 1830 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1831 assigned-clock-rates = <100000000>; 1832 1833 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1834 1835 #clock-cells = <0>; 1836 clock-output-names = "pcie1_pipe_clk"; 1837 1838 #phy-cells = <0>; 1839 1840 status = "disabled"; 1841 }; 1842 1843 cryptobam: dma-controller@1dc4000 { 1844 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1845 reg = <0x0 0x01dc4000 0x0 0x28000>; 1846 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1847 #dma-cells = <1>; 1848 qcom,ee = <0>; 1849 qcom,controlled-remotely; 1850 iommus = <&apps_smmu 0x480 0x0>, 1851 <&apps_smmu 0x481 0x0>; 1852 }; 1853 1854 crypto: crypto@1dfa000 { 1855 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1856 reg = <0x0 0x01dfa000 0x0 0x6000>; 1857 dmas = <&cryptobam 4>, <&cryptobam 5>; 1858 dma-names = "rx", "tx"; 1859 iommus = <&apps_smmu 0x480 0x0>, 1860 <&apps_smmu 0x481 0x0>; 1861 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1862 interconnect-names = "memory"; 1863 }; 1864 1865 ufs_mem_phy: phy@1d80000 { 1866 compatible = "qcom,sm8550-qmp-ufs-phy"; 1867 reg = <0x0 0x01d80000 0x0 0x2000>; 1868 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1869 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1870 clock-names = "ref", "ref_aux"; 1871 1872 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1873 1874 resets = <&ufs_mem_hc 0>; 1875 reset-names = "ufsphy"; 1876 1877 #clock-cells = <1>; 1878 #phy-cells = <0>; 1879 1880 status = "disabled"; 1881 }; 1882 1883 ufs_mem_hc: ufs@1d84000 { 1884 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1885 "jedec,ufs-2.0"; 1886 reg = <0x0 0x01d84000 0x0 0x3000>; 1887 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1888 phys = <&ufs_mem_phy>; 1889 phy-names = "ufsphy"; 1890 lanes-per-direction = <2>; 1891 #reset-cells = <1>; 1892 resets = <&gcc GCC_UFS_PHY_BCR>; 1893 reset-names = "rst"; 1894 1895 power-domains = <&gcc UFS_PHY_GDSC>; 1896 required-opps = <&rpmhpd_opp_nom>; 1897 1898 iommus = <&apps_smmu 0x60 0x0>; 1899 dma-coherent; 1900 1901 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1902 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1903 1904 interconnect-names = "ufs-ddr", "cpu-ufs"; 1905 clock-names = "core_clk", 1906 "bus_aggr_clk", 1907 "iface_clk", 1908 "core_clk_unipro", 1909 "ref_clk", 1910 "tx_lane0_sync_clk", 1911 "rx_lane0_sync_clk", 1912 "rx_lane1_sync_clk"; 1913 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1914 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1915 <&gcc GCC_UFS_PHY_AHB_CLK>, 1916 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1917 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1918 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1919 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1920 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1921 freq-table-hz = 1922 <75000000 300000000>, 1923 <0 0>, 1924 <0 0>, 1925 <75000000 300000000>, 1926 <100000000 403000000>, 1927 <0 0>, 1928 <0 0>, 1929 <0 0>; 1930 qcom,ice = <&ice>; 1931 1932 status = "disabled"; 1933 }; 1934 1935 ice: crypto@1d88000 { 1936 compatible = "qcom,sm8550-inline-crypto-engine", 1937 "qcom,inline-crypto-engine"; 1938 reg = <0 0x01d88000 0 0x8000>; 1939 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1940 }; 1941 1942 tcsr_mutex: hwlock@1f40000 { 1943 compatible = "qcom,tcsr-mutex"; 1944 reg = <0 0x01f40000 0 0x20000>; 1945 #hwlock-cells = <1>; 1946 }; 1947 1948 tcsr: clock-controller@1fc0000 { 1949 compatible = "qcom,sm8550-tcsr", "syscon"; 1950 reg = <0 0x01fc0000 0 0x30000>; 1951 clocks = <&rpmhcc RPMH_CXO_CLK>; 1952 #clock-cells = <1>; 1953 #reset-cells = <1>; 1954 }; 1955 1956 gpucc: clock-controller@3d90000 { 1957 compatible = "qcom,sm8550-gpucc"; 1958 reg = <0 0x03d90000 0 0xa000>; 1959 clocks = <&bi_tcxo_div2>, 1960 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1961 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1962 #clock-cells = <1>; 1963 #reset-cells = <1>; 1964 #power-domain-cells = <1>; 1965 }; 1966 1967 remoteproc_mpss: remoteproc@4080000 { 1968 compatible = "qcom,sm8550-mpss-pas"; 1969 reg = <0x0 0x04080000 0x0 0x4040>; 1970 1971 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1972 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1973 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1974 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1975 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1976 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1977 interrupt-names = "wdog", "fatal", "ready", "handover", 1978 "stop-ack", "shutdown-ack"; 1979 1980 clocks = <&rpmhcc RPMH_CXO_CLK>; 1981 clock-names = "xo"; 1982 1983 power-domains = <&rpmhpd SM8550_CX>, 1984 <&rpmhpd SM8550_MSS>; 1985 power-domain-names = "cx", "mss"; 1986 1987 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1988 1989 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 1990 1991 qcom,qmp = <&aoss_qmp>; 1992 1993 qcom,smem-states = <&smp2p_modem_out 0>; 1994 qcom,smem-state-names = "stop"; 1995 1996 status = "disabled"; 1997 1998 glink-edge { 1999 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2000 IPCC_MPROC_SIGNAL_GLINK_QMP 2001 IRQ_TYPE_EDGE_RISING>; 2002 mboxes = <&ipcc IPCC_CLIENT_MPSS 2003 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2004 label = "mpss"; 2005 qcom,remote-pid = <1>; 2006 }; 2007 }; 2008 2009 lpass_wsa2macro: codec@6aa0000 { 2010 compatible = "qcom,sm8550-lpass-wsa-macro"; 2011 reg = <0 0x06aa0000 0 0x1000>; 2012 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2013 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2014 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2015 <&lpass_vamacro>; 2016 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2017 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2018 assigned-clock-rates = <19200000>; 2019 2020 #clock-cells = <0>; 2021 clock-output-names = "wsa2-mclk"; 2022 pinctrl-names = "default"; 2023 pinctrl-0 = <&wsa2_swr_active>; 2024 #sound-dai-cells = <1>; 2025 }; 2026 2027 swr3: soundwire-controller@6ab0000 { 2028 compatible = "qcom,soundwire-v2.0.0"; 2029 reg = <0 0x06ab0000 0 0x10000>; 2030 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2031 clocks = <&lpass_wsa2macro>; 2032 clock-names = "iface"; 2033 label = "WSA2"; 2034 2035 qcom,din-ports = <4>; 2036 qcom,dout-ports = <9>; 2037 2038 qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2039 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2040 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2041 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2042 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2043 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2044 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2045 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2046 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2047 2048 #address-cells = <2>; 2049 #size-cells = <0>; 2050 #sound-dai-cells = <1>; 2051 status = "disabled"; 2052 }; 2053 2054 lpass_rxmacro: codec@6ac0000 { 2055 compatible = "qcom,sm8550-lpass-rx-macro"; 2056 reg = <0 0x06ac0000 0 0x1000>; 2057 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2058 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2059 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2060 <&lpass_vamacro>; 2061 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2062 2063 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2064 assigned-clock-rates = <19200000>; 2065 2066 #clock-cells = <0>; 2067 clock-output-names = "mclk"; 2068 pinctrl-names = "default"; 2069 pinctrl-0 = <&rx_swr_active>; 2070 #sound-dai-cells = <1>; 2071 }; 2072 2073 swr1: soundwire-controller@6ad0000 { 2074 compatible = "qcom,soundwire-v2.0.0"; 2075 reg = <0 0x06ad0000 0 0x10000>; 2076 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2077 clocks = <&lpass_rxmacro>; 2078 clock-names = "iface"; 2079 label = "RX"; 2080 2081 qcom,din-ports = <0>; 2082 qcom,dout-ports = <10>; 2083 2084 qcom,ports-sinterval = <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2085 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; 2086 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2087 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2088 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2089 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; 2090 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 2091 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2092 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2093 2094 #address-cells = <2>; 2095 #size-cells = <0>; 2096 #sound-dai-cells = <1>; 2097 status = "disabled"; 2098 }; 2099 2100 lpass_txmacro: codec@6ae0000 { 2101 compatible = "qcom,sm8550-lpass-tx-macro"; 2102 reg = <0 0x06ae0000 0 0x1000>; 2103 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2104 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2105 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2106 <&lpass_vamacro>; 2107 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2108 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2109 2110 assigned-clock-rates = <19200000>; 2111 2112 #clock-cells = <0>; 2113 clock-output-names = "mclk"; 2114 pinctrl-names = "default"; 2115 pinctrl-0 = <&tx_swr_active>; 2116 #sound-dai-cells = <1>; 2117 }; 2118 2119 lpass_wsamacro: codec@6b00000 { 2120 compatible = "qcom,sm8550-lpass-wsa-macro"; 2121 reg = <0 0x06b00000 0 0x1000>; 2122 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2123 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2124 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2125 <&lpass_vamacro>; 2126 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2127 2128 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2129 assigned-clock-rates = <19200000>; 2130 2131 #clock-cells = <0>; 2132 clock-output-names = "mclk"; 2133 pinctrl-names = "default"; 2134 pinctrl-0 = <&wsa_swr_active>; 2135 #sound-dai-cells = <1>; 2136 }; 2137 2138 swr0: soundwire-controller@6b10000 { 2139 compatible = "qcom,soundwire-v2.0.0"; 2140 reg = <0 0x06b10000 0 0x10000>; 2141 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2142 clocks = <&lpass_wsamacro>; 2143 clock-names = "iface"; 2144 label = "WSA"; 2145 2146 qcom,din-ports = <4>; 2147 qcom,dout-ports = <9>; 2148 2149 qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2150 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2151 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2152 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2153 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2154 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2155 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2156 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2157 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2158 2159 #address-cells = <2>; 2160 #size-cells = <0>; 2161 #sound-dai-cells = <1>; 2162 status = "disabled"; 2163 }; 2164 2165 swr2: soundwire-controller@6d30000 { 2166 compatible = "qcom,soundwire-v2.0.0"; 2167 reg = <0 0x06d30000 0 0x10000>; 2168 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2170 interrupt-names = "core", "wakeup"; 2171 clocks = <&lpass_vamacro>; 2172 clock-names = "iface"; 2173 label = "TX"; 2174 2175 qcom,din-ports = <4>; 2176 qcom,dout-ports = <0>; 2177 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2178 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2179 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2180 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2181 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2182 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2183 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2184 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2185 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2186 2187 #address-cells = <2>; 2188 #size-cells = <0>; 2189 #sound-dai-cells = <1>; 2190 status = "disabled"; 2191 }; 2192 2193 lpass_vamacro: codec@6d44000 { 2194 compatible = "qcom,sm8550-lpass-va-macro"; 2195 reg = <0 0x06d44000 0 0x1000>; 2196 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2197 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2198 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2199 clock-names = "mclk", "macro", "dcodec"; 2200 2201 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2202 assigned-clock-rates = <19200000>; 2203 2204 #clock-cells = <0>; 2205 clock-output-names = "fsgen"; 2206 #sound-dai-cells = <1>; 2207 }; 2208 2209 lpass_tlmm: pinctrl@6e80000 { 2210 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2211 reg = <0 0x06e80000 0 0x20000>, 2212 <0 0x07250000 0 0x10000>; 2213 gpio-controller; 2214 #gpio-cells = <2>; 2215 gpio-ranges = <&lpass_tlmm 0 0 23>; 2216 2217 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2218 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2219 clock-names = "core", "audio"; 2220 2221 tx_swr_active: tx-swr-active-state { 2222 clk-pins { 2223 pins = "gpio0"; 2224 function = "swr_tx_clk"; 2225 drive-strength = <2>; 2226 slew-rate = <1>; 2227 bias-disable; 2228 }; 2229 2230 data-pins { 2231 pins = "gpio1", "gpio2", "gpio14"; 2232 function = "swr_tx_data"; 2233 drive-strength = <2>; 2234 slew-rate = <1>; 2235 bias-bus-hold; 2236 }; 2237 }; 2238 2239 rx_swr_active: rx-swr-active-state { 2240 clk-pins { 2241 pins = "gpio3"; 2242 function = "swr_rx_clk"; 2243 drive-strength = <2>; 2244 slew-rate = <1>; 2245 bias-disable; 2246 }; 2247 2248 data-pins { 2249 pins = "gpio4", "gpio5"; 2250 function = "swr_rx_data"; 2251 drive-strength = <2>; 2252 slew-rate = <1>; 2253 bias-bus-hold; 2254 }; 2255 }; 2256 2257 dmic01_default: dmic01-default-state { 2258 clk-pins { 2259 pins = "gpio6"; 2260 function = "dmic1_clk"; 2261 drive-strength = <8>; 2262 output-high; 2263 }; 2264 2265 data-pins { 2266 pins = "gpio7"; 2267 function = "dmic1_data"; 2268 drive-strength = <8>; 2269 input-enable; 2270 }; 2271 }; 2272 2273 dmic02_default: dmic02-default-state { 2274 clk-pins { 2275 pins = "gpio8"; 2276 function = "dmic2_clk"; 2277 drive-strength = <8>; 2278 output-high; 2279 }; 2280 2281 data-pins { 2282 pins = "gpio9"; 2283 function = "dmic2_data"; 2284 drive-strength = <8>; 2285 input-enable; 2286 }; 2287 }; 2288 2289 wsa_swr_active: wsa-swr-active-state { 2290 clk-pins { 2291 pins = "gpio10"; 2292 function = "wsa_swr_clk"; 2293 drive-strength = <2>; 2294 slew-rate = <1>; 2295 bias-disable; 2296 }; 2297 2298 data-pins { 2299 pins = "gpio11"; 2300 function = "wsa_swr_data"; 2301 drive-strength = <2>; 2302 slew-rate = <1>; 2303 bias-bus-hold; 2304 }; 2305 }; 2306 2307 wsa2_swr_active: wsa2-swr-active-state { 2308 clk-pins { 2309 pins = "gpio15"; 2310 function = "wsa2_swr_clk"; 2311 drive-strength = <2>; 2312 slew-rate = <1>; 2313 bias-disable; 2314 }; 2315 2316 data-pins { 2317 pins = "gpio16"; 2318 function = "wsa2_swr_data"; 2319 drive-strength = <2>; 2320 slew-rate = <1>; 2321 bias-bus-hold; 2322 }; 2323 }; 2324 }; 2325 2326 lpass_lpiaon_noc: interconnect@7400000 { 2327 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2328 reg = <0 0x07400000 0 0x19080>; 2329 #interconnect-cells = <2>; 2330 qcom,bcm-voters = <&apps_bcm_voter>; 2331 }; 2332 2333 lpass_lpicx_noc: interconnect@7430000 { 2334 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2335 reg = <0 0x07430000 0 0x3a200>; 2336 #interconnect-cells = <2>; 2337 qcom,bcm-voters = <&apps_bcm_voter>; 2338 }; 2339 2340 lpass_ag_noc: interconnect@7e40000 { 2341 compatible = "qcom,sm8550-lpass-ag-noc"; 2342 reg = <0 0x07e40000 0 0xe080>; 2343 #interconnect-cells = <2>; 2344 qcom,bcm-voters = <&apps_bcm_voter>; 2345 }; 2346 2347 sdhc_2: mmc@8804000 { 2348 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2349 reg = <0 0x08804000 0 0x1000>; 2350 2351 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2352 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2353 interrupt-names = "hc_irq", "pwr_irq"; 2354 2355 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2356 <&gcc GCC_SDCC2_APPS_CLK>, 2357 <&rpmhcc RPMH_CXO_CLK>; 2358 clock-names = "iface", "core", "xo"; 2359 iommus = <&apps_smmu 0x540 0>; 2360 qcom,dll-config = <0x0007642c>; 2361 qcom,ddr-config = <0x80040868>; 2362 power-domains = <&rpmhpd SM8550_CX>; 2363 operating-points-v2 = <&sdhc2_opp_table>; 2364 2365 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2366 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2367 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2368 bus-width = <4>; 2369 dma-coherent; 2370 2371 /* Forbid SDR104/SDR50 - broken hw! */ 2372 sdhci-caps-mask = <0x3 0>; 2373 2374 status = "disabled"; 2375 2376 sdhc2_opp_table: opp-table { 2377 compatible = "operating-points-v2"; 2378 2379 opp-19200000 { 2380 opp-hz = /bits/ 64 <19200000>; 2381 required-opps = <&rpmhpd_opp_min_svs>; 2382 }; 2383 2384 opp-50000000 { 2385 opp-hz = /bits/ 64 <50000000>; 2386 required-opps = <&rpmhpd_opp_low_svs>; 2387 }; 2388 2389 opp-100000000 { 2390 opp-hz = /bits/ 64 <100000000>; 2391 required-opps = <&rpmhpd_opp_svs>; 2392 }; 2393 2394 opp-202000000 { 2395 opp-hz = /bits/ 64 <202000000>; 2396 required-opps = <&rpmhpd_opp_svs_l1>; 2397 }; 2398 }; 2399 }; 2400 2401 videocc: clock-controller@aaf0000 { 2402 compatible = "qcom,sm8550-videocc"; 2403 reg = <0 0x0aaf0000 0 0x10000>; 2404 clocks = <&bi_tcxo_div2>, 2405 <&gcc GCC_VIDEO_AHB_CLK>; 2406 power-domains = <&rpmhpd SM8550_MMCX>; 2407 required-opps = <&rpmhpd_opp_low_svs>; 2408 #clock-cells = <1>; 2409 #reset-cells = <1>; 2410 #power-domain-cells = <1>; 2411 }; 2412 2413 mdss: display-subsystem@ae00000 { 2414 compatible = "qcom,sm8550-mdss"; 2415 reg = <0 0x0ae00000 0 0x1000>; 2416 reg-names = "mdss"; 2417 2418 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2419 interrupt-controller; 2420 #interrupt-cells = <1>; 2421 2422 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2423 <&gcc GCC_DISP_AHB_CLK>, 2424 <&gcc GCC_DISP_HF_AXI_CLK>, 2425 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2426 2427 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2428 2429 power-domains = <&dispcc MDSS_GDSC>; 2430 2431 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2432 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2433 interconnect-names = "mdp0-mem", "mdp1-mem"; 2434 2435 iommus = <&apps_smmu 0x1c00 0x2>; 2436 2437 #address-cells = <2>; 2438 #size-cells = <2>; 2439 ranges; 2440 2441 status = "disabled"; 2442 2443 mdss_mdp: display-controller@ae01000 { 2444 compatible = "qcom,sm8550-dpu"; 2445 reg = <0 0x0ae01000 0 0x8f000>, 2446 <0 0x0aeb0000 0 0x2008>; 2447 reg-names = "mdp", "vbif"; 2448 2449 interrupt-parent = <&mdss>; 2450 interrupts = <0>; 2451 2452 clocks = <&gcc GCC_DISP_AHB_CLK>, 2453 <&gcc GCC_DISP_HF_AXI_CLK>, 2454 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2455 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2456 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2457 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2458 clock-names = "bus", 2459 "nrt_bus", 2460 "iface", 2461 "lut", 2462 "core", 2463 "vsync"; 2464 2465 power-domains = <&rpmhpd SM8550_MMCX>; 2466 2467 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2468 assigned-clock-rates = <19200000>; 2469 2470 operating-points-v2 = <&mdp_opp_table>; 2471 2472 ports { 2473 #address-cells = <1>; 2474 #size-cells = <0>; 2475 2476 port@0 { 2477 reg = <0>; 2478 dpu_intf1_out: endpoint { 2479 remote-endpoint = <&mdss_dsi0_in>; 2480 }; 2481 }; 2482 2483 port@1 { 2484 reg = <1>; 2485 dpu_intf2_out: endpoint { 2486 remote-endpoint = <&mdss_dsi1_in>; 2487 }; 2488 }; 2489 2490 port@2 { 2491 reg = <2>; 2492 dpu_intf0_out: endpoint { 2493 remote-endpoint = <&mdss_dp0_in>; 2494 }; 2495 }; 2496 }; 2497 2498 mdp_opp_table: opp-table { 2499 compatible = "operating-points-v2"; 2500 2501 opp-200000000 { 2502 opp-hz = /bits/ 64 <200000000>; 2503 required-opps = <&rpmhpd_opp_low_svs>; 2504 }; 2505 2506 opp-325000000 { 2507 opp-hz = /bits/ 64 <325000000>; 2508 required-opps = <&rpmhpd_opp_svs>; 2509 }; 2510 2511 opp-375000000 { 2512 opp-hz = /bits/ 64 <375000000>; 2513 required-opps = <&rpmhpd_opp_svs_l1>; 2514 }; 2515 2516 opp-514000000 { 2517 opp-hz = /bits/ 64 <514000000>; 2518 required-opps = <&rpmhpd_opp_nom>; 2519 }; 2520 }; 2521 }; 2522 2523 mdss_dp0: displayport-controller@ae90000 { 2524 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2525 reg = <0 0xae90000 0 0x200>, 2526 <0 0xae90200 0 0x200>, 2527 <0 0xae90400 0 0xc00>, 2528 <0 0xae91000 0 0x400>, 2529 <0 0xae91400 0 0x400>; 2530 interrupt-parent = <&mdss>; 2531 interrupts = <12>; 2532 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2533 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2534 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2535 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2536 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2537 clock-names = "core_iface", 2538 "core_aux", 2539 "ctrl_link", 2540 "ctrl_link_iface", 2541 "stream_pixel"; 2542 2543 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2544 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2545 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2546 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2547 2548 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2549 phy-names = "dp"; 2550 2551 #sound-dai-cells = <0>; 2552 2553 operating-points-v2 = <&dp_opp_table>; 2554 power-domains = <&rpmhpd SM8550_MMCX>; 2555 2556 status = "disabled"; 2557 2558 ports { 2559 #address-cells = <1>; 2560 #size-cells = <0>; 2561 2562 port@0 { 2563 reg = <0>; 2564 mdss_dp0_in: endpoint { 2565 remote-endpoint = <&dpu_intf0_out>; 2566 }; 2567 }; 2568 2569 port@1 { 2570 reg = <1>; 2571 mdss_dp0_out: endpoint { 2572 }; 2573 }; 2574 }; 2575 2576 dp_opp_table: opp-table { 2577 compatible = "operating-points-v2"; 2578 2579 opp-162000000 { 2580 opp-hz = /bits/ 64 <162000000>; 2581 required-opps = <&rpmhpd_opp_low_svs_d1>; 2582 }; 2583 2584 opp-270000000 { 2585 opp-hz = /bits/ 64 <270000000>; 2586 required-opps = <&rpmhpd_opp_low_svs>; 2587 }; 2588 2589 opp-540000000 { 2590 opp-hz = /bits/ 64 <540000000>; 2591 required-opps = <&rpmhpd_opp_svs_l1>; 2592 }; 2593 2594 opp-810000000 { 2595 opp-hz = /bits/ 64 <810000000>; 2596 required-opps = <&rpmhpd_opp_nom>; 2597 }; 2598 }; 2599 }; 2600 2601 mdss_dsi0: dsi@ae94000 { 2602 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2603 reg = <0 0x0ae94000 0 0x400>; 2604 reg-names = "dsi_ctrl"; 2605 2606 interrupt-parent = <&mdss>; 2607 interrupts = <4>; 2608 2609 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2610 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2611 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2612 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2613 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2614 <&gcc GCC_DISP_HF_AXI_CLK>; 2615 clock-names = "byte", 2616 "byte_intf", 2617 "pixel", 2618 "core", 2619 "iface", 2620 "bus"; 2621 2622 power-domains = <&rpmhpd SM8550_MMCX>; 2623 2624 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2625 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2626 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2627 <&mdss_dsi0_phy 1>; 2628 2629 operating-points-v2 = <&mdss_dsi_opp_table>; 2630 2631 phys = <&mdss_dsi0_phy>; 2632 phy-names = "dsi"; 2633 2634 #address-cells = <1>; 2635 #size-cells = <0>; 2636 2637 status = "disabled"; 2638 2639 ports { 2640 #address-cells = <1>; 2641 #size-cells = <0>; 2642 2643 port@0 { 2644 reg = <0>; 2645 mdss_dsi0_in: endpoint { 2646 remote-endpoint = <&dpu_intf1_out>; 2647 }; 2648 }; 2649 2650 port@1 { 2651 reg = <1>; 2652 mdss_dsi0_out: endpoint { 2653 }; 2654 }; 2655 }; 2656 2657 mdss_dsi_opp_table: opp-table { 2658 compatible = "operating-points-v2"; 2659 2660 opp-187500000 { 2661 opp-hz = /bits/ 64 <187500000>; 2662 required-opps = <&rpmhpd_opp_low_svs>; 2663 }; 2664 2665 opp-300000000 { 2666 opp-hz = /bits/ 64 <300000000>; 2667 required-opps = <&rpmhpd_opp_svs>; 2668 }; 2669 2670 opp-358000000 { 2671 opp-hz = /bits/ 64 <358000000>; 2672 required-opps = <&rpmhpd_opp_svs_l1>; 2673 }; 2674 }; 2675 }; 2676 2677 mdss_dsi0_phy: phy@ae95000 { 2678 compatible = "qcom,sm8550-dsi-phy-4nm"; 2679 reg = <0 0x0ae95000 0 0x200>, 2680 <0 0x0ae95200 0 0x280>, 2681 <0 0x0ae95500 0 0x400>; 2682 reg-names = "dsi_phy", 2683 "dsi_phy_lane", 2684 "dsi_pll"; 2685 2686 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2687 <&rpmhcc RPMH_CXO_CLK>; 2688 clock-names = "iface", "ref"; 2689 2690 #clock-cells = <1>; 2691 #phy-cells = <0>; 2692 2693 status = "disabled"; 2694 }; 2695 2696 mdss_dsi1: dsi@ae96000 { 2697 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2698 reg = <0 0x0ae96000 0 0x400>; 2699 reg-names = "dsi_ctrl"; 2700 2701 interrupt-parent = <&mdss>; 2702 interrupts = <5>; 2703 2704 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2705 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2706 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2707 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2708 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2709 <&gcc GCC_DISP_HF_AXI_CLK>; 2710 clock-names = "byte", 2711 "byte_intf", 2712 "pixel", 2713 "core", 2714 "iface", 2715 "bus"; 2716 2717 power-domains = <&rpmhpd SM8550_MMCX>; 2718 2719 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2720 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2721 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2722 <&mdss_dsi1_phy 1>; 2723 2724 operating-points-v2 = <&mdss_dsi_opp_table>; 2725 2726 phys = <&mdss_dsi1_phy>; 2727 phy-names = "dsi"; 2728 2729 #address-cells = <1>; 2730 #size-cells = <0>; 2731 2732 status = "disabled"; 2733 2734 ports { 2735 #address-cells = <1>; 2736 #size-cells = <0>; 2737 2738 port@0 { 2739 reg = <0>; 2740 mdss_dsi1_in: endpoint { 2741 remote-endpoint = <&dpu_intf2_out>; 2742 }; 2743 }; 2744 2745 port@1 { 2746 reg = <1>; 2747 mdss_dsi1_out: endpoint { 2748 }; 2749 }; 2750 }; 2751 }; 2752 2753 mdss_dsi1_phy: phy@ae97000 { 2754 compatible = "qcom,sm8550-dsi-phy-4nm"; 2755 reg = <0 0x0ae97000 0 0x200>, 2756 <0 0x0ae97200 0 0x280>, 2757 <0 0x0ae97500 0 0x400>; 2758 reg-names = "dsi_phy", 2759 "dsi_phy_lane", 2760 "dsi_pll"; 2761 2762 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2763 <&rpmhcc RPMH_CXO_CLK>; 2764 clock-names = "iface", "ref"; 2765 2766 #clock-cells = <1>; 2767 #phy-cells = <0>; 2768 2769 status = "disabled"; 2770 }; 2771 }; 2772 2773 dispcc: clock-controller@af00000 { 2774 compatible = "qcom,sm8550-dispcc"; 2775 reg = <0 0x0af00000 0 0x20000>; 2776 clocks = <&bi_tcxo_div2>, 2777 <&bi_tcxo_ao_div2>, 2778 <&gcc GCC_DISP_AHB_CLK>, 2779 <&sleep_clk>, 2780 <&mdss_dsi0_phy 0>, 2781 <&mdss_dsi0_phy 1>, 2782 <&mdss_dsi1_phy 0>, 2783 <&mdss_dsi1_phy 1>, 2784 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2785 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2786 <0>, /* dp1 */ 2787 <0>, 2788 <0>, /* dp2 */ 2789 <0>, 2790 <0>, /* dp3 */ 2791 <0>; 2792 power-domains = <&rpmhpd SM8550_MMCX>; 2793 required-opps = <&rpmhpd_opp_low_svs>; 2794 #clock-cells = <1>; 2795 #reset-cells = <1>; 2796 #power-domain-cells = <1>; 2797 }; 2798 2799 usb_1_hsphy: phy@88e3000 { 2800 compatible = "qcom,sm8550-snps-eusb2-phy"; 2801 reg = <0x0 0x088e3000 0x0 0x154>; 2802 #phy-cells = <0>; 2803 2804 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2805 clock-names = "ref"; 2806 2807 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2808 2809 status = "disabled"; 2810 }; 2811 2812 usb_dp_qmpphy: phy@88e8000 { 2813 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2814 reg = <0x0 0x088e8000 0x0 0x3000>; 2815 2816 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2817 <&rpmhcc RPMH_CXO_CLK>, 2818 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2819 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2820 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2821 2822 power-domains = <&gcc USB3_PHY_GDSC>; 2823 2824 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2825 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2826 reset-names = "phy", "common"; 2827 2828 #clock-cells = <1>; 2829 #phy-cells = <1>; 2830 2831 status = "disabled"; 2832 }; 2833 2834 usb_1: usb@a6f8800 { 2835 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 2836 reg = <0x0 0x0a6f8800 0x0 0x400>; 2837 #address-cells = <2>; 2838 #size-cells = <2>; 2839 ranges; 2840 2841 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2842 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2843 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2844 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2845 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2846 <&tcsr TCSR_USB3_CLKREF_EN>; 2847 clock-names = "cfg_noc", 2848 "core", 2849 "iface", 2850 "sleep", 2851 "mock_utmi", 2852 "xo"; 2853 2854 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2855 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2856 assigned-clock-rates = <19200000>, <200000000>; 2857 2858 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2859 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2860 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 2861 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 2862 interrupt-names = "hs_phy_irq", 2863 "ss_phy_irq", 2864 "dm_hs_phy_irq", 2865 "dp_hs_phy_irq"; 2866 2867 power-domains = <&gcc USB30_PRIM_GDSC>; 2868 required-opps = <&rpmhpd_opp_nom>; 2869 2870 resets = <&gcc GCC_USB30_PRIM_BCR>; 2871 2872 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2873 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2874 interconnect-names = "usb-ddr", "apps-usb"; 2875 2876 status = "disabled"; 2877 2878 usb_1_dwc3: usb@a600000 { 2879 compatible = "snps,dwc3"; 2880 reg = <0x0 0x0a600000 0x0 0xcd00>; 2881 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2882 iommus = <&apps_smmu 0x40 0x0>; 2883 snps,dis_u2_susphy_quirk; 2884 snps,dis_enblslpm_quirk; 2885 snps,usb3_lpm_capable; 2886 phys = <&usb_1_hsphy>, 2887 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2888 phy-names = "usb2-phy", "usb3-phy"; 2889 2890 ports { 2891 #address-cells = <1>; 2892 #size-cells = <0>; 2893 2894 port@0 { 2895 reg = <0>; 2896 2897 usb_1_dwc3_hs: endpoint { 2898 }; 2899 }; 2900 2901 port@1 { 2902 reg = <1>; 2903 2904 usb_1_dwc3_ss: endpoint { 2905 }; 2906 }; 2907 }; 2908 }; 2909 }; 2910 2911 pdc: interrupt-controller@b220000 { 2912 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 2913 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2914 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2915 <125 63 1>, <126 716 12>, 2916 <138 251 5>; 2917 #interrupt-cells = <2>; 2918 interrupt-parent = <&intc>; 2919 interrupt-controller; 2920 }; 2921 2922 tsens0: thermal-sensor@c271000 { 2923 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2924 reg = <0 0x0c271000 0 0x1000>, /* TM */ 2925 <0 0x0c222000 0 0x1000>; /* SROT */ 2926 #qcom,sensors = <16>; 2927 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2929 interrupt-names = "uplow", "critical"; 2930 #thermal-sensor-cells = <1>; 2931 }; 2932 2933 tsens1: thermal-sensor@c272000 { 2934 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2935 reg = <0 0x0c272000 0 0x1000>, /* TM */ 2936 <0 0x0c223000 0 0x1000>; /* SROT */ 2937 #qcom,sensors = <16>; 2938 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2940 interrupt-names = "uplow", "critical"; 2941 #thermal-sensor-cells = <1>; 2942 }; 2943 2944 tsens2: thermal-sensor@c273000 { 2945 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2946 reg = <0 0x0c273000 0 0x1000>, /* TM */ 2947 <0 0x0c224000 0 0x1000>; /* SROT */ 2948 #qcom,sensors = <16>; 2949 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2951 interrupt-names = "uplow", "critical"; 2952 #thermal-sensor-cells = <1>; 2953 }; 2954 2955 aoss_qmp: power-management@c300000 { 2956 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 2957 reg = <0 0x0c300000 0 0x400>; 2958 interrupt-parent = <&ipcc>; 2959 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2960 IRQ_TYPE_EDGE_RISING>; 2961 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2962 2963 #clock-cells = <0>; 2964 }; 2965 2966 sram@c3f0000 { 2967 compatible = "qcom,rpmh-stats"; 2968 reg = <0 0x0c3f0000 0 0x400>; 2969 }; 2970 2971 spmi_bus: spmi@c400000 { 2972 compatible = "qcom,spmi-pmic-arb"; 2973 reg = <0 0x0c400000 0 0x3000>, 2974 <0 0x0c500000 0 0x4000000>, 2975 <0 0x0c440000 0 0x80000>, 2976 <0 0x0c4c0000 0 0x20000>, 2977 <0 0x0c42d000 0 0x4000>; 2978 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2979 interrupt-names = "periph_irq"; 2980 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2981 qcom,ee = <0>; 2982 qcom,channel = <0>; 2983 qcom,bus-id = <0>; 2984 #address-cells = <2>; 2985 #size-cells = <0>; 2986 interrupt-controller; 2987 #interrupt-cells = <4>; 2988 }; 2989 2990 tlmm: pinctrl@f100000 { 2991 compatible = "qcom,sm8550-tlmm"; 2992 reg = <0 0x0f100000 0 0x300000>; 2993 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2994 gpio-controller; 2995 #gpio-cells = <2>; 2996 interrupt-controller; 2997 #interrupt-cells = <2>; 2998 gpio-ranges = <&tlmm 0 0 211>; 2999 wakeup-parent = <&pdc>; 3000 3001 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3002 /* SDA, SCL */ 3003 pins = "gpio16", "gpio17"; 3004 function = "i2chub0_se0"; 3005 drive-strength = <2>; 3006 bias-pull-up; 3007 }; 3008 3009 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3010 /* SDA, SCL */ 3011 pins = "gpio18", "gpio19"; 3012 function = "i2chub0_se1"; 3013 drive-strength = <2>; 3014 bias-pull-up; 3015 }; 3016 3017 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3018 /* SDA, SCL */ 3019 pins = "gpio20", "gpio21"; 3020 function = "i2chub0_se2"; 3021 drive-strength = <2>; 3022 bias-pull-up; 3023 }; 3024 3025 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3026 /* SDA, SCL */ 3027 pins = "gpio22", "gpio23"; 3028 function = "i2chub0_se3"; 3029 drive-strength = <2>; 3030 bias-pull-up; 3031 }; 3032 3033 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3034 /* SDA, SCL */ 3035 pins = "gpio4", "gpio5"; 3036 function = "i2chub0_se4"; 3037 drive-strength = <2>; 3038 bias-pull-up; 3039 }; 3040 3041 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3042 /* SDA, SCL */ 3043 pins = "gpio6", "gpio7"; 3044 function = "i2chub0_se5"; 3045 drive-strength = <2>; 3046 bias-pull-up; 3047 }; 3048 3049 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3050 /* SDA, SCL */ 3051 pins = "gpio8", "gpio9"; 3052 function = "i2chub0_se6"; 3053 drive-strength = <2>; 3054 bias-pull-up; 3055 }; 3056 3057 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3058 /* SDA, SCL */ 3059 pins = "gpio10", "gpio11"; 3060 function = "i2chub0_se7"; 3061 drive-strength = <2>; 3062 bias-pull-up; 3063 }; 3064 3065 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3066 /* SDA, SCL */ 3067 pins = "gpio206", "gpio207"; 3068 function = "i2chub0_se8"; 3069 drive-strength = <2>; 3070 bias-pull-up; 3071 }; 3072 3073 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3074 /* SDA, SCL */ 3075 pins = "gpio84", "gpio85"; 3076 function = "i2chub0_se9"; 3077 drive-strength = <2>; 3078 bias-pull-up; 3079 }; 3080 3081 pcie0_default_state: pcie0-default-state { 3082 perst-pins { 3083 pins = "gpio94"; 3084 function = "gpio"; 3085 drive-strength = <2>; 3086 bias-pull-down; 3087 }; 3088 3089 clkreq-pins { 3090 pins = "gpio95"; 3091 function = "pcie0_clk_req_n"; 3092 drive-strength = <2>; 3093 bias-pull-up; 3094 }; 3095 3096 wake-pins { 3097 pins = "gpio96"; 3098 function = "gpio"; 3099 drive-strength = <2>; 3100 bias-pull-up; 3101 }; 3102 }; 3103 3104 pcie1_default_state: pcie1-default-state { 3105 perst-pins { 3106 pins = "gpio97"; 3107 function = "gpio"; 3108 drive-strength = <2>; 3109 bias-pull-down; 3110 }; 3111 3112 clkreq-pins { 3113 pins = "gpio98"; 3114 function = "pcie1_clk_req_n"; 3115 drive-strength = <2>; 3116 bias-pull-up; 3117 }; 3118 3119 wake-pins { 3120 pins = "gpio99"; 3121 function = "gpio"; 3122 drive-strength = <2>; 3123 bias-pull-up; 3124 }; 3125 }; 3126 3127 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3128 /* SDA, SCL */ 3129 pins = "gpio28", "gpio29"; 3130 function = "qup1_se0"; 3131 drive-strength = <2>; 3132 bias-pull-up = <2200>; 3133 }; 3134 3135 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3136 /* SDA, SCL */ 3137 pins = "gpio32", "gpio33"; 3138 function = "qup1_se1"; 3139 drive-strength = <2>; 3140 bias-pull-up = <2200>; 3141 }; 3142 3143 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3144 /* SDA, SCL */ 3145 pins = "gpio36", "gpio37"; 3146 function = "qup1_se2"; 3147 drive-strength = <2>; 3148 bias-pull-up = <2200>; 3149 }; 3150 3151 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3152 /* SDA, SCL */ 3153 pins = "gpio40", "gpio41"; 3154 function = "qup1_se3"; 3155 drive-strength = <2>; 3156 bias-pull-up = <2200>; 3157 }; 3158 3159 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3160 /* SDA, SCL */ 3161 pins = "gpio44", "gpio45"; 3162 function = "qup1_se4"; 3163 drive-strength = <2>; 3164 bias-pull-up = <2200>; 3165 }; 3166 3167 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3168 /* SDA, SCL */ 3169 pins = "gpio52", "gpio53"; 3170 function = "qup1_se5"; 3171 drive-strength = <2>; 3172 bias-pull-up = <2200>; 3173 }; 3174 3175 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3176 /* SDA, SCL */ 3177 pins = "gpio48", "gpio49"; 3178 function = "qup1_se6"; 3179 drive-strength = <2>; 3180 bias-pull-up = <2200>; 3181 }; 3182 3183 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3184 scl-pins { 3185 pins = "gpio57"; 3186 function = "qup2_se0_l1_mira"; 3187 drive-strength = <2>; 3188 bias-pull-up = <2200>; 3189 }; 3190 3191 sda-pins { 3192 pins = "gpio56"; 3193 function = "qup2_se0_l0_mira"; 3194 drive-strength = <2>; 3195 bias-pull-up = <2200>; 3196 }; 3197 }; 3198 3199 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3200 /* SDA, SCL */ 3201 pins = "gpio60", "gpio61"; 3202 function = "qup2_se1"; 3203 drive-strength = <2>; 3204 bias-pull-up = <2200>; 3205 }; 3206 3207 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3208 /* SDA, SCL */ 3209 pins = "gpio64", "gpio65"; 3210 function = "qup2_se2"; 3211 drive-strength = <2>; 3212 bias-pull-up = <2200>; 3213 }; 3214 3215 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3216 /* SDA, SCL */ 3217 pins = "gpio68", "gpio69"; 3218 function = "qup2_se3"; 3219 drive-strength = <2>; 3220 bias-pull-up = <2200>; 3221 }; 3222 3223 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3224 /* SDA, SCL */ 3225 pins = "gpio2", "gpio3"; 3226 function = "qup2_se4"; 3227 drive-strength = <2>; 3228 bias-pull-up = <2200>; 3229 }; 3230 3231 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3232 /* SDA, SCL */ 3233 pins = "gpio80", "gpio81"; 3234 function = "qup2_se5"; 3235 drive-strength = <2>; 3236 bias-pull-up = <2200>; 3237 }; 3238 3239 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3240 /* SDA, SCL */ 3241 pins = "gpio72", "gpio106"; 3242 function = "qup2_se7"; 3243 drive-strength = <2>; 3244 bias-pull-up = <2200>; 3245 }; 3246 3247 qup_spi0_cs: qup-spi0-cs-state { 3248 pins = "gpio31"; 3249 function = "qup1_se0"; 3250 drive-strength = <6>; 3251 bias-disable; 3252 }; 3253 3254 qup_spi0_data_clk: qup-spi0-data-clk-state { 3255 /* MISO, MOSI, CLK */ 3256 pins = "gpio28", "gpio29", "gpio30"; 3257 function = "qup1_se0"; 3258 drive-strength = <6>; 3259 bias-disable; 3260 }; 3261 3262 qup_spi1_cs: qup-spi1-cs-state { 3263 pins = "gpio35"; 3264 function = "qup1_se1"; 3265 drive-strength = <6>; 3266 bias-disable; 3267 }; 3268 3269 qup_spi1_data_clk: qup-spi1-data-clk-state { 3270 /* MISO, MOSI, CLK */ 3271 pins = "gpio32", "gpio33", "gpio34"; 3272 function = "qup1_se1"; 3273 drive-strength = <6>; 3274 bias-disable; 3275 }; 3276 3277 qup_spi2_cs: qup-spi2-cs-state { 3278 pins = "gpio39"; 3279 function = "qup1_se2"; 3280 drive-strength = <6>; 3281 bias-disable; 3282 }; 3283 3284 qup_spi2_data_clk: qup-spi2-data-clk-state { 3285 /* MISO, MOSI, CLK */ 3286 pins = "gpio36", "gpio37", "gpio38"; 3287 function = "qup1_se2"; 3288 drive-strength = <6>; 3289 bias-disable; 3290 }; 3291 3292 qup_spi3_cs: qup-spi3-cs-state { 3293 pins = "gpio43"; 3294 function = "qup1_se3"; 3295 drive-strength = <6>; 3296 bias-disable; 3297 }; 3298 3299 qup_spi3_data_clk: qup-spi3-data-clk-state { 3300 /* MISO, MOSI, CLK */ 3301 pins = "gpio40", "gpio41", "gpio42"; 3302 function = "qup1_se3"; 3303 drive-strength = <6>; 3304 bias-disable; 3305 }; 3306 3307 qup_spi4_cs: qup-spi4-cs-state { 3308 pins = "gpio47"; 3309 function = "qup1_se4"; 3310 drive-strength = <6>; 3311 bias-disable; 3312 }; 3313 3314 qup_spi4_data_clk: qup-spi4-data-clk-state { 3315 /* MISO, MOSI, CLK */ 3316 pins = "gpio44", "gpio45", "gpio46"; 3317 function = "qup1_se4"; 3318 drive-strength = <6>; 3319 bias-disable; 3320 }; 3321 3322 qup_spi5_cs: qup-spi5-cs-state { 3323 pins = "gpio55"; 3324 function = "qup1_se5"; 3325 drive-strength = <6>; 3326 bias-disable; 3327 }; 3328 3329 qup_spi5_data_clk: qup-spi5-data-clk-state { 3330 /* MISO, MOSI, CLK */ 3331 pins = "gpio52", "gpio53", "gpio54"; 3332 function = "qup1_se5"; 3333 drive-strength = <6>; 3334 bias-disable; 3335 }; 3336 3337 qup_spi6_cs: qup-spi6-cs-state { 3338 pins = "gpio51"; 3339 function = "qup1_se6"; 3340 drive-strength = <6>; 3341 bias-disable; 3342 }; 3343 3344 qup_spi6_data_clk: qup-spi6-data-clk-state { 3345 /* MISO, MOSI, CLK */ 3346 pins = "gpio48", "gpio49", "gpio50"; 3347 function = "qup1_se6"; 3348 drive-strength = <6>; 3349 bias-disable; 3350 }; 3351 3352 qup_spi8_cs: qup-spi8-cs-state { 3353 pins = "gpio59"; 3354 function = "qup2_se0_l3_mira"; 3355 drive-strength = <6>; 3356 bias-disable; 3357 }; 3358 3359 qup_spi8_data_clk: qup-spi8-data-clk-state { 3360 /* MISO, MOSI, CLK */ 3361 pins = "gpio56", "gpio57", "gpio58"; 3362 function = "qup2_se0_l2_mira"; 3363 drive-strength = <6>; 3364 bias-disable; 3365 }; 3366 3367 qup_spi9_cs: qup-spi9-cs-state { 3368 pins = "gpio63"; 3369 function = "qup2_se1"; 3370 drive-strength = <6>; 3371 bias-disable; 3372 }; 3373 3374 qup_spi9_data_clk: qup-spi9-data-clk-state { 3375 /* MISO, MOSI, CLK */ 3376 pins = "gpio60", "gpio61", "gpio62"; 3377 function = "qup2_se1"; 3378 drive-strength = <6>; 3379 bias-disable; 3380 }; 3381 3382 qup_spi10_cs: qup-spi10-cs-state { 3383 pins = "gpio67"; 3384 function = "qup2_se2"; 3385 drive-strength = <6>; 3386 bias-disable; 3387 }; 3388 3389 qup_spi10_data_clk: qup-spi10-data-clk-state { 3390 /* MISO, MOSI, CLK */ 3391 pins = "gpio64", "gpio65", "gpio66"; 3392 function = "qup2_se2"; 3393 drive-strength = <6>; 3394 bias-disable; 3395 }; 3396 3397 qup_spi11_cs: qup-spi11-cs-state { 3398 pins = "gpio71"; 3399 function = "qup2_se3"; 3400 drive-strength = <6>; 3401 bias-disable; 3402 }; 3403 3404 qup_spi11_data_clk: qup-spi11-data-clk-state { 3405 /* MISO, MOSI, CLK */ 3406 pins = "gpio68", "gpio69", "gpio70"; 3407 function = "qup2_se3"; 3408 drive-strength = <6>; 3409 bias-disable; 3410 }; 3411 3412 qup_spi12_cs: qup-spi12-cs-state { 3413 pins = "gpio119"; 3414 function = "qup2_se4"; 3415 drive-strength = <6>; 3416 bias-disable; 3417 }; 3418 3419 qup_spi12_data_clk: qup-spi12-data-clk-state { 3420 /* MISO, MOSI, CLK */ 3421 pins = "gpio2", "gpio3", "gpio118"; 3422 function = "qup2_se4"; 3423 drive-strength = <6>; 3424 bias-disable; 3425 }; 3426 3427 qup_spi13_cs: qup-spi13-cs-state { 3428 pins = "gpio83"; 3429 function = "qup2_se5"; 3430 drive-strength = <6>; 3431 bias-disable; 3432 }; 3433 3434 qup_spi13_data_clk: qup-spi13-data-clk-state { 3435 /* MISO, MOSI, CLK */ 3436 pins = "gpio80", "gpio81", "gpio82"; 3437 function = "qup2_se5"; 3438 drive-strength = <6>; 3439 bias-disable; 3440 }; 3441 3442 qup_spi15_cs: qup-spi15-cs-state { 3443 pins = "gpio75"; 3444 function = "qup2_se7"; 3445 drive-strength = <6>; 3446 bias-disable; 3447 }; 3448 3449 qup_spi15_data_clk: qup-spi15-data-clk-state { 3450 /* MISO, MOSI, CLK */ 3451 pins = "gpio72", "gpio106", "gpio74"; 3452 function = "qup2_se7"; 3453 drive-strength = <6>; 3454 bias-disable; 3455 }; 3456 3457 qup_uart7_default: qup-uart7-default-state { 3458 /* TX, RX */ 3459 pins = "gpio26", "gpio27"; 3460 function = "qup1_se7"; 3461 drive-strength = <2>; 3462 bias-disable; 3463 }; 3464 3465 sdc2_sleep: sdc2-sleep-state { 3466 clk-pins { 3467 pins = "sdc2_clk"; 3468 bias-disable; 3469 drive-strength = <2>; 3470 }; 3471 3472 cmd-pins { 3473 pins = "sdc2_cmd"; 3474 bias-pull-up; 3475 drive-strength = <2>; 3476 }; 3477 3478 data-pins { 3479 pins = "sdc2_data"; 3480 bias-pull-up; 3481 drive-strength = <2>; 3482 }; 3483 }; 3484 3485 sdc2_default: sdc2-default-state { 3486 clk-pins { 3487 pins = "sdc2_clk"; 3488 bias-disable; 3489 drive-strength = <16>; 3490 }; 3491 3492 cmd-pins { 3493 pins = "sdc2_cmd"; 3494 bias-pull-up; 3495 drive-strength = <10>; 3496 }; 3497 3498 data-pins { 3499 pins = "sdc2_data"; 3500 bias-pull-up; 3501 drive-strength = <10>; 3502 }; 3503 }; 3504 }; 3505 3506 apps_smmu: iommu@15000000 { 3507 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3508 reg = <0 0x15000000 0 0x100000>; 3509 #iommu-cells = <2>; 3510 #global-interrupts = <1>; 3511 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3553 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3557 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3558 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3559 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3560 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3561 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3564 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3565 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3566 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3571 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3577 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3582 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3583 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3584 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3608 }; 3609 3610 intc: interrupt-controller@17100000 { 3611 compatible = "arm,gic-v3"; 3612 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3613 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3614 ranges; 3615 #interrupt-cells = <3>; 3616 interrupt-controller; 3617 #redistributor-regions = <1>; 3618 redistributor-stride = <0 0x40000>; 3619 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3620 #address-cells = <2>; 3621 #size-cells = <2>; 3622 3623 gic_its: msi-controller@17140000 { 3624 compatible = "arm,gic-v3-its"; 3625 reg = <0 0x17140000 0 0x20000>; 3626 msi-controller; 3627 #msi-cells = <1>; 3628 }; 3629 }; 3630 3631 timer@17420000 { 3632 compatible = "arm,armv7-timer-mem"; 3633 reg = <0 0x17420000 0 0x1000>; 3634 ranges = <0 0 0 0x20000000>; 3635 #address-cells = <1>; 3636 #size-cells = <1>; 3637 3638 frame@17421000 { 3639 reg = <0x17421000 0x1000>, 3640 <0x17422000 0x1000>; 3641 frame-number = <0>; 3642 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3644 }; 3645 3646 frame@17423000 { 3647 reg = <0x17423000 0x1000>; 3648 frame-number = <1>; 3649 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3650 status = "disabled"; 3651 }; 3652 3653 frame@17425000 { 3654 reg = <0x17425000 0x1000>; 3655 frame-number = <2>; 3656 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3657 status = "disabled"; 3658 }; 3659 3660 frame@17427000 { 3661 reg = <0x17427000 0x1000>; 3662 frame-number = <3>; 3663 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3664 status = "disabled"; 3665 }; 3666 3667 frame@17429000 { 3668 reg = <0x17429000 0x1000>; 3669 frame-number = <4>; 3670 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3671 status = "disabled"; 3672 }; 3673 3674 frame@1742b000 { 3675 reg = <0x1742b000 0x1000>; 3676 frame-number = <5>; 3677 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3678 status = "disabled"; 3679 }; 3680 3681 frame@1742d000 { 3682 reg = <0x1742d000 0x1000>; 3683 frame-number = <6>; 3684 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3685 status = "disabled"; 3686 }; 3687 }; 3688 3689 apps_rsc: rsc@17a00000 { 3690 label = "apps_rsc"; 3691 compatible = "qcom,rpmh-rsc"; 3692 reg = <0 0x17a00000 0 0x10000>, 3693 <0 0x17a10000 0 0x10000>, 3694 <0 0x17a20000 0 0x10000>, 3695 <0 0x17a30000 0 0x10000>; 3696 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3697 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3700 qcom,tcs-offset = <0xd00>; 3701 qcom,drv-id = <2>; 3702 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3703 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3704 power-domains = <&CLUSTER_PD>; 3705 3706 apps_bcm_voter: bcm-voter { 3707 compatible = "qcom,bcm-voter"; 3708 }; 3709 3710 rpmhcc: clock-controller { 3711 compatible = "qcom,sm8550-rpmh-clk"; 3712 #clock-cells = <1>; 3713 clock-names = "xo"; 3714 clocks = <&xo_board>; 3715 }; 3716 3717 rpmhpd: power-controller { 3718 compatible = "qcom,sm8550-rpmhpd"; 3719 #power-domain-cells = <1>; 3720 operating-points-v2 = <&rpmhpd_opp_table>; 3721 3722 rpmhpd_opp_table: opp-table { 3723 compatible = "operating-points-v2"; 3724 3725 rpmhpd_opp_ret: opp-16 { 3726 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3727 }; 3728 3729 rpmhpd_opp_min_svs: opp-48 { 3730 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3731 }; 3732 3733 rpmhpd_opp_low_svs_d2: opp-52 { 3734 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3735 }; 3736 3737 rpmhpd_opp_low_svs_d1: opp-56 { 3738 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3739 }; 3740 3741 rpmhpd_opp_low_svs_d0: opp-60 { 3742 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3743 }; 3744 3745 rpmhpd_opp_low_svs: opp-64 { 3746 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3747 }; 3748 3749 rpmhpd_opp_low_svs_l1: opp-80 { 3750 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3751 }; 3752 3753 rpmhpd_opp_svs: opp-128 { 3754 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3755 }; 3756 3757 rpmhpd_opp_svs_l0: opp-144 { 3758 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3759 }; 3760 3761 rpmhpd_opp_svs_l1: opp-192 { 3762 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3763 }; 3764 3765 rpmhpd_opp_nom: opp-256 { 3766 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3767 }; 3768 3769 rpmhpd_opp_nom_l1: opp-320 { 3770 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3771 }; 3772 3773 rpmhpd_opp_nom_l2: opp-336 { 3774 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3775 }; 3776 3777 rpmhpd_opp_turbo: opp-384 { 3778 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3779 }; 3780 3781 rpmhpd_opp_turbo_l1: opp-416 { 3782 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3783 }; 3784 }; 3785 }; 3786 }; 3787 3788 cpufreq_hw: cpufreq@17d91000 { 3789 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3790 reg = <0 0x17d91000 0 0x1000>, 3791 <0 0x17d92000 0 0x1000>, 3792 <0 0x17d93000 0 0x1000>; 3793 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3794 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3795 clock-names = "xo", "alternate"; 3796 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3799 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3800 #freq-domain-cells = <1>; 3801 #clock-cells = <1>; 3802 }; 3803 3804 pmu@24091000 { 3805 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3806 reg = <0 0x24091000 0 0x1000>; 3807 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3808 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3809 3810 operating-points-v2 = <&llcc_bwmon_opp_table>; 3811 3812 llcc_bwmon_opp_table: opp-table { 3813 compatible = "operating-points-v2"; 3814 3815 opp-0 { 3816 opp-peak-kBps = <2086000>; 3817 }; 3818 3819 opp-1 { 3820 opp-peak-kBps = <2929000>; 3821 }; 3822 3823 opp-2 { 3824 opp-peak-kBps = <5931000>; 3825 }; 3826 3827 opp-3 { 3828 opp-peak-kBps = <6515000>; 3829 }; 3830 3831 opp-4 { 3832 opp-peak-kBps = <7980000>; 3833 }; 3834 3835 opp-5 { 3836 opp-peak-kBps = <10437000>; 3837 }; 3838 3839 opp-6 { 3840 opp-peak-kBps = <12157000>; 3841 }; 3842 3843 opp-7 { 3844 opp-peak-kBps = <14060000>; 3845 }; 3846 3847 opp-8 { 3848 opp-peak-kBps = <16113000>; 3849 }; 3850 }; 3851 }; 3852 3853 pmu@240b6400 { 3854 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 3855 reg = <0 0x240b6400 0 0x600>; 3856 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3857 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3858 3859 operating-points-v2 = <&cpu_bwmon_opp_table>; 3860 3861 cpu_bwmon_opp_table: opp-table { 3862 compatible = "operating-points-v2"; 3863 3864 opp-0 { 3865 opp-peak-kBps = <4577000>; 3866 }; 3867 3868 opp-1 { 3869 opp-peak-kBps = <7110000>; 3870 }; 3871 3872 opp-2 { 3873 opp-peak-kBps = <9155000>; 3874 }; 3875 3876 opp-3 { 3877 opp-peak-kBps = <12298000>; 3878 }; 3879 3880 opp-4 { 3881 opp-peak-kBps = <14236000>; 3882 }; 3883 3884 opp-5 { 3885 opp-peak-kBps = <16265000>; 3886 }; 3887 }; 3888 }; 3889 3890 gem_noc: interconnect@24100000 { 3891 compatible = "qcom,sm8550-gem-noc"; 3892 reg = <0 0x24100000 0 0xbb800>; 3893 #interconnect-cells = <2>; 3894 qcom,bcm-voters = <&apps_bcm_voter>; 3895 }; 3896 3897 system-cache-controller@25000000 { 3898 compatible = "qcom,sm8550-llcc"; 3899 reg = <0 0x25000000 0 0x800000>, 3900 <0 0x25800000 0 0x200000>; 3901 reg-names = "llcc_base", "llcc_broadcast_base"; 3902 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3903 }; 3904 3905 remoteproc_adsp: remoteproc@30000000 { 3906 compatible = "qcom,sm8550-adsp-pas"; 3907 reg = <0x0 0x30000000 0x0 0x100>; 3908 3909 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3910 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3911 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3912 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3913 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3914 interrupt-names = "wdog", "fatal", "ready", 3915 "handover", "stop-ack"; 3916 3917 clocks = <&rpmhcc RPMH_CXO_CLK>; 3918 clock-names = "xo"; 3919 3920 power-domains = <&rpmhpd SM8550_LCX>, 3921 <&rpmhpd SM8550_LMX>; 3922 power-domain-names = "lcx", "lmx"; 3923 3924 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 3925 3926 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3927 3928 qcom,qmp = <&aoss_qmp>; 3929 3930 qcom,smem-states = <&smp2p_adsp_out 0>; 3931 qcom,smem-state-names = "stop"; 3932 3933 status = "disabled"; 3934 3935 remoteproc_adsp_glink: glink-edge { 3936 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3937 IPCC_MPROC_SIGNAL_GLINK_QMP 3938 IRQ_TYPE_EDGE_RISING>; 3939 mboxes = <&ipcc IPCC_CLIENT_LPASS 3940 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3941 3942 label = "lpass"; 3943 qcom,remote-pid = <2>; 3944 3945 fastrpc { 3946 compatible = "qcom,fastrpc"; 3947 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3948 label = "adsp"; 3949 #address-cells = <1>; 3950 #size-cells = <0>; 3951 3952 compute-cb@3 { 3953 compatible = "qcom,fastrpc-compute-cb"; 3954 reg = <3>; 3955 iommus = <&apps_smmu 0x1003 0x80>, 3956 <&apps_smmu 0x1063 0x0>; 3957 }; 3958 3959 compute-cb@4 { 3960 compatible = "qcom,fastrpc-compute-cb"; 3961 reg = <4>; 3962 iommus = <&apps_smmu 0x1004 0x80>, 3963 <&apps_smmu 0x1064 0x0>; 3964 }; 3965 3966 compute-cb@5 { 3967 compatible = "qcom,fastrpc-compute-cb"; 3968 reg = <5>; 3969 iommus = <&apps_smmu 0x1005 0x80>, 3970 <&apps_smmu 0x1065 0x0>; 3971 }; 3972 3973 compute-cb@6 { 3974 compatible = "qcom,fastrpc-compute-cb"; 3975 reg = <6>; 3976 iommus = <&apps_smmu 0x1006 0x80>, 3977 <&apps_smmu 0x1066 0x0>; 3978 }; 3979 3980 compute-cb@7 { 3981 compatible = "qcom,fastrpc-compute-cb"; 3982 reg = <7>; 3983 iommus = <&apps_smmu 0x1007 0x80>, 3984 <&apps_smmu 0x1067 0x0>; 3985 }; 3986 }; 3987 3988 gpr { 3989 compatible = "qcom,gpr"; 3990 qcom,glink-channels = "adsp_apps"; 3991 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3992 qcom,intents = <512 20>; 3993 #address-cells = <1>; 3994 #size-cells = <0>; 3995 3996 q6apm: service@1 { 3997 compatible = "qcom,q6apm"; 3998 reg = <GPR_APM_MODULE_IID>; 3999 #sound-dai-cells = <0>; 4000 qcom,protection-domain = "avs/audio", 4001 "msm/adsp/audio_pd"; 4002 4003 q6apmdai: dais { 4004 compatible = "qcom,q6apm-dais"; 4005 iommus = <&apps_smmu 0x1001 0x80>, 4006 <&apps_smmu 0x1061 0x0>; 4007 }; 4008 4009 q6apmbedai: bedais { 4010 compatible = "qcom,q6apm-lpass-dais"; 4011 #sound-dai-cells = <1>; 4012 }; 4013 }; 4014 4015 q6prm: service@2 { 4016 compatible = "qcom,q6prm"; 4017 reg = <GPR_PRM_MODULE_IID>; 4018 qcom,protection-domain = "avs/audio", 4019 "msm/adsp/audio_pd"; 4020 4021 q6prmcc: clock-controller { 4022 compatible = "qcom,q6prm-lpass-clocks"; 4023 #clock-cells = <2>; 4024 }; 4025 }; 4026 }; 4027 }; 4028 }; 4029 4030 nsp_noc: interconnect@320c0000 { 4031 compatible = "qcom,sm8550-nsp-noc"; 4032 reg = <0 0x320c0000 0 0xe080>; 4033 #interconnect-cells = <2>; 4034 qcom,bcm-voters = <&apps_bcm_voter>; 4035 }; 4036 4037 remoteproc_cdsp: remoteproc@32300000 { 4038 compatible = "qcom,sm8550-cdsp-pas"; 4039 reg = <0x0 0x32300000 0x0 0x1400000>; 4040 4041 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4042 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4043 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4044 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4045 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4046 interrupt-names = "wdog", "fatal", "ready", 4047 "handover", "stop-ack"; 4048 4049 clocks = <&rpmhcc RPMH_CXO_CLK>; 4050 clock-names = "xo"; 4051 4052 power-domains = <&rpmhpd SM8550_CX>, 4053 <&rpmhpd SM8550_MXC>, 4054 <&rpmhpd SM8550_NSP>; 4055 power-domain-names = "cx", "mxc", "nsp"; 4056 4057 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4058 4059 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4060 4061 qcom,qmp = <&aoss_qmp>; 4062 4063 qcom,smem-states = <&smp2p_cdsp_out 0>; 4064 qcom,smem-state-names = "stop"; 4065 4066 status = "disabled"; 4067 4068 glink-edge { 4069 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4070 IPCC_MPROC_SIGNAL_GLINK_QMP 4071 IRQ_TYPE_EDGE_RISING>; 4072 mboxes = <&ipcc IPCC_CLIENT_CDSP 4073 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4074 4075 label = "cdsp"; 4076 qcom,remote-pid = <5>; 4077 4078 fastrpc { 4079 compatible = "qcom,fastrpc"; 4080 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4081 label = "cdsp"; 4082 #address-cells = <1>; 4083 #size-cells = <0>; 4084 4085 compute-cb@1 { 4086 compatible = "qcom,fastrpc-compute-cb"; 4087 reg = <1>; 4088 iommus = <&apps_smmu 0x1961 0x0>, 4089 <&apps_smmu 0x0c01 0x20>, 4090 <&apps_smmu 0x19c1 0x10>; 4091 }; 4092 4093 compute-cb@2 { 4094 compatible = "qcom,fastrpc-compute-cb"; 4095 reg = <2>; 4096 iommus = <&apps_smmu 0x1962 0x0>, 4097 <&apps_smmu 0x0c02 0x20>, 4098 <&apps_smmu 0x19c2 0x10>; 4099 }; 4100 4101 compute-cb@3 { 4102 compatible = "qcom,fastrpc-compute-cb"; 4103 reg = <3>; 4104 iommus = <&apps_smmu 0x1963 0x0>, 4105 <&apps_smmu 0x0c03 0x20>, 4106 <&apps_smmu 0x19c3 0x10>; 4107 }; 4108 4109 compute-cb@4 { 4110 compatible = "qcom,fastrpc-compute-cb"; 4111 reg = <4>; 4112 iommus = <&apps_smmu 0x1964 0x0>, 4113 <&apps_smmu 0x0c04 0x20>, 4114 <&apps_smmu 0x19c4 0x10>; 4115 }; 4116 4117 compute-cb@5 { 4118 compatible = "qcom,fastrpc-compute-cb"; 4119 reg = <5>; 4120 iommus = <&apps_smmu 0x1965 0x0>, 4121 <&apps_smmu 0x0c05 0x20>, 4122 <&apps_smmu 0x19c5 0x10>; 4123 }; 4124 4125 compute-cb@6 { 4126 compatible = "qcom,fastrpc-compute-cb"; 4127 reg = <6>; 4128 iommus = <&apps_smmu 0x1966 0x0>, 4129 <&apps_smmu 0x0c06 0x20>, 4130 <&apps_smmu 0x19c6 0x10>; 4131 }; 4132 4133 compute-cb@7 { 4134 compatible = "qcom,fastrpc-compute-cb"; 4135 reg = <7>; 4136 iommus = <&apps_smmu 0x1967 0x0>, 4137 <&apps_smmu 0x0c07 0x20>, 4138 <&apps_smmu 0x19c7 0x10>; 4139 }; 4140 4141 compute-cb@8 { 4142 compatible = "qcom,fastrpc-compute-cb"; 4143 reg = <8>; 4144 iommus = <&apps_smmu 0x1968 0x0>, 4145 <&apps_smmu 0x0c08 0x20>, 4146 <&apps_smmu 0x19c8 0x10>; 4147 }; 4148 4149 /* note: secure cb9 in downstream */ 4150 }; 4151 }; 4152 }; 4153 }; 4154 4155 thermal-zones { 4156 aoss0-thermal { 4157 polling-delay-passive = <0>; 4158 polling-delay = <0>; 4159 thermal-sensors = <&tsens0 0>; 4160 4161 trips { 4162 thermal-engine-config { 4163 temperature = <125000>; 4164 hysteresis = <1000>; 4165 type = "passive"; 4166 }; 4167 4168 reset-mon-config { 4169 temperature = <115000>; 4170 hysteresis = <5000>; 4171 type = "passive"; 4172 }; 4173 }; 4174 }; 4175 4176 cpuss0-thermal { 4177 polling-delay-passive = <0>; 4178 polling-delay = <0>; 4179 thermal-sensors = <&tsens0 1>; 4180 4181 trips { 4182 thermal-engine-config { 4183 temperature = <125000>; 4184 hysteresis = <1000>; 4185 type = "passive"; 4186 }; 4187 4188 reset-mon-config { 4189 temperature = <115000>; 4190 hysteresis = <5000>; 4191 type = "passive"; 4192 }; 4193 }; 4194 }; 4195 4196 cpuss1-thermal { 4197 polling-delay-passive = <0>; 4198 polling-delay = <0>; 4199 thermal-sensors = <&tsens0 2>; 4200 4201 trips { 4202 thermal-engine-config { 4203 temperature = <125000>; 4204 hysteresis = <1000>; 4205 type = "passive"; 4206 }; 4207 4208 reset-mon-config { 4209 temperature = <115000>; 4210 hysteresis = <5000>; 4211 type = "passive"; 4212 }; 4213 }; 4214 }; 4215 4216 cpuss2-thermal { 4217 polling-delay-passive = <0>; 4218 polling-delay = <0>; 4219 thermal-sensors = <&tsens0 3>; 4220 4221 trips { 4222 thermal-engine-config { 4223 temperature = <125000>; 4224 hysteresis = <1000>; 4225 type = "passive"; 4226 }; 4227 4228 reset-mon-config { 4229 temperature = <115000>; 4230 hysteresis = <5000>; 4231 type = "passive"; 4232 }; 4233 }; 4234 }; 4235 4236 cpuss3-thermal { 4237 polling-delay-passive = <0>; 4238 polling-delay = <0>; 4239 thermal-sensors = <&tsens0 4>; 4240 4241 trips { 4242 thermal-engine-config { 4243 temperature = <125000>; 4244 hysteresis = <1000>; 4245 type = "passive"; 4246 }; 4247 4248 reset-mon-config { 4249 temperature = <115000>; 4250 hysteresis = <5000>; 4251 type = "passive"; 4252 }; 4253 }; 4254 }; 4255 4256 cpu3-top-thermal { 4257 polling-delay-passive = <0>; 4258 polling-delay = <0>; 4259 thermal-sensors = <&tsens0 5>; 4260 4261 trips { 4262 cpu3_top_alert0: trip-point0 { 4263 temperature = <90000>; 4264 hysteresis = <2000>; 4265 type = "passive"; 4266 }; 4267 4268 cpu3_top_alert1: trip-point1 { 4269 temperature = <95000>; 4270 hysteresis = <2000>; 4271 type = "passive"; 4272 }; 4273 4274 cpu3_top_crit: cpu-critical { 4275 temperature = <110000>; 4276 hysteresis = <1000>; 4277 type = "critical"; 4278 }; 4279 }; 4280 }; 4281 4282 cpu3-bottom-thermal { 4283 polling-delay-passive = <0>; 4284 polling-delay = <0>; 4285 thermal-sensors = <&tsens0 6>; 4286 4287 trips { 4288 cpu3_bottom_alert0: trip-point0 { 4289 temperature = <90000>; 4290 hysteresis = <2000>; 4291 type = "passive"; 4292 }; 4293 4294 cpu3_bottom_alert1: trip-point1 { 4295 temperature = <95000>; 4296 hysteresis = <2000>; 4297 type = "passive"; 4298 }; 4299 4300 cpu3_bottom_crit: cpu-critical { 4301 temperature = <110000>; 4302 hysteresis = <1000>; 4303 type = "critical"; 4304 }; 4305 }; 4306 }; 4307 4308 cpu4-top-thermal { 4309 polling-delay-passive = <0>; 4310 polling-delay = <0>; 4311 thermal-sensors = <&tsens0 7>; 4312 4313 trips { 4314 cpu4_top_alert0: trip-point0 { 4315 temperature = <90000>; 4316 hysteresis = <2000>; 4317 type = "passive"; 4318 }; 4319 4320 cpu4_top_alert1: trip-point1 { 4321 temperature = <95000>; 4322 hysteresis = <2000>; 4323 type = "passive"; 4324 }; 4325 4326 cpu4_top_crit: cpu-critical { 4327 temperature = <110000>; 4328 hysteresis = <1000>; 4329 type = "critical"; 4330 }; 4331 }; 4332 }; 4333 4334 cpu4-bottom-thermal { 4335 polling-delay-passive = <0>; 4336 polling-delay = <0>; 4337 thermal-sensors = <&tsens0 8>; 4338 4339 trips { 4340 cpu4_bottom_alert0: trip-point0 { 4341 temperature = <90000>; 4342 hysteresis = <2000>; 4343 type = "passive"; 4344 }; 4345 4346 cpu4_bottom_alert1: trip-point1 { 4347 temperature = <95000>; 4348 hysteresis = <2000>; 4349 type = "passive"; 4350 }; 4351 4352 cpu4_bottom_crit: cpu-critical { 4353 temperature = <110000>; 4354 hysteresis = <1000>; 4355 type = "critical"; 4356 }; 4357 }; 4358 }; 4359 4360 cpu5-top-thermal { 4361 polling-delay-passive = <0>; 4362 polling-delay = <0>; 4363 thermal-sensors = <&tsens0 9>; 4364 4365 trips { 4366 cpu5_top_alert0: trip-point0 { 4367 temperature = <90000>; 4368 hysteresis = <2000>; 4369 type = "passive"; 4370 }; 4371 4372 cpu5_top_alert1: trip-point1 { 4373 temperature = <95000>; 4374 hysteresis = <2000>; 4375 type = "passive"; 4376 }; 4377 4378 cpu5_top_crit: cpu-critical { 4379 temperature = <110000>; 4380 hysteresis = <1000>; 4381 type = "critical"; 4382 }; 4383 }; 4384 }; 4385 4386 cpu5-bottom-thermal { 4387 polling-delay-passive = <0>; 4388 polling-delay = <0>; 4389 thermal-sensors = <&tsens0 10>; 4390 4391 trips { 4392 cpu5_bottom_alert0: trip-point0 { 4393 temperature = <90000>; 4394 hysteresis = <2000>; 4395 type = "passive"; 4396 }; 4397 4398 cpu5_bottom_alert1: trip-point1 { 4399 temperature = <95000>; 4400 hysteresis = <2000>; 4401 type = "passive"; 4402 }; 4403 4404 cpu5_bottom_crit: cpu-critical { 4405 temperature = <110000>; 4406 hysteresis = <1000>; 4407 type = "critical"; 4408 }; 4409 }; 4410 }; 4411 4412 cpu6-top-thermal { 4413 polling-delay-passive = <0>; 4414 polling-delay = <0>; 4415 thermal-sensors = <&tsens0 11>; 4416 4417 trips { 4418 cpu6_top_alert0: trip-point0 { 4419 temperature = <90000>; 4420 hysteresis = <2000>; 4421 type = "passive"; 4422 }; 4423 4424 cpu6_top_alert1: trip-point1 { 4425 temperature = <95000>; 4426 hysteresis = <2000>; 4427 type = "passive"; 4428 }; 4429 4430 cpu6_top_crit: cpu-critical { 4431 temperature = <110000>; 4432 hysteresis = <1000>; 4433 type = "critical"; 4434 }; 4435 }; 4436 }; 4437 4438 cpu6-bottom-thermal { 4439 polling-delay-passive = <0>; 4440 polling-delay = <0>; 4441 thermal-sensors = <&tsens0 12>; 4442 4443 trips { 4444 cpu6_bottom_alert0: trip-point0 { 4445 temperature = <90000>; 4446 hysteresis = <2000>; 4447 type = "passive"; 4448 }; 4449 4450 cpu6_bottom_alert1: trip-point1 { 4451 temperature = <95000>; 4452 hysteresis = <2000>; 4453 type = "passive"; 4454 }; 4455 4456 cpu6_bottom_crit: cpu-critical { 4457 temperature = <110000>; 4458 hysteresis = <1000>; 4459 type = "critical"; 4460 }; 4461 }; 4462 }; 4463 4464 cpu7-top-thermal { 4465 polling-delay-passive = <0>; 4466 polling-delay = <0>; 4467 thermal-sensors = <&tsens0 13>; 4468 4469 trips { 4470 cpu7_top_alert0: trip-point0 { 4471 temperature = <90000>; 4472 hysteresis = <2000>; 4473 type = "passive"; 4474 }; 4475 4476 cpu7_top_alert1: trip-point1 { 4477 temperature = <95000>; 4478 hysteresis = <2000>; 4479 type = "passive"; 4480 }; 4481 4482 cpu7_top_crit: cpu-critical { 4483 temperature = <110000>; 4484 hysteresis = <1000>; 4485 type = "critical"; 4486 }; 4487 }; 4488 }; 4489 4490 cpu7-middle-thermal { 4491 polling-delay-passive = <0>; 4492 polling-delay = <0>; 4493 thermal-sensors = <&tsens0 14>; 4494 4495 trips { 4496 cpu7_middle_alert0: trip-point0 { 4497 temperature = <90000>; 4498 hysteresis = <2000>; 4499 type = "passive"; 4500 }; 4501 4502 cpu7_middle_alert1: trip-point1 { 4503 temperature = <95000>; 4504 hysteresis = <2000>; 4505 type = "passive"; 4506 }; 4507 4508 cpu7_middle_crit: cpu-critical { 4509 temperature = <110000>; 4510 hysteresis = <1000>; 4511 type = "critical"; 4512 }; 4513 }; 4514 }; 4515 4516 cpu7-bottom-thermal { 4517 polling-delay-passive = <0>; 4518 polling-delay = <0>; 4519 thermal-sensors = <&tsens0 15>; 4520 4521 trips { 4522 cpu7_bottom_alert0: trip-point0 { 4523 temperature = <90000>; 4524 hysteresis = <2000>; 4525 type = "passive"; 4526 }; 4527 4528 cpu7_bottom_alert1: trip-point1 { 4529 temperature = <95000>; 4530 hysteresis = <2000>; 4531 type = "passive"; 4532 }; 4533 4534 cpu7_bottom_crit: cpu-critical { 4535 temperature = <110000>; 4536 hysteresis = <1000>; 4537 type = "critical"; 4538 }; 4539 }; 4540 }; 4541 4542 aoss1-thermal { 4543 polling-delay-passive = <0>; 4544 polling-delay = <0>; 4545 thermal-sensors = <&tsens1 0>; 4546 4547 trips { 4548 thermal-engine-config { 4549 temperature = <125000>; 4550 hysteresis = <1000>; 4551 type = "passive"; 4552 }; 4553 4554 reset-mon-config { 4555 temperature = <115000>; 4556 hysteresis = <5000>; 4557 type = "passive"; 4558 }; 4559 }; 4560 }; 4561 4562 cpu0-thermal { 4563 polling-delay-passive = <0>; 4564 polling-delay = <0>; 4565 thermal-sensors = <&tsens1 1>; 4566 4567 trips { 4568 cpu0_alert0: trip-point0 { 4569 temperature = <90000>; 4570 hysteresis = <2000>; 4571 type = "passive"; 4572 }; 4573 4574 cpu0_alert1: trip-point1 { 4575 temperature = <95000>; 4576 hysteresis = <2000>; 4577 type = "passive"; 4578 }; 4579 4580 cpu0_crit: cpu-critical { 4581 temperature = <110000>; 4582 hysteresis = <1000>; 4583 type = "critical"; 4584 }; 4585 }; 4586 }; 4587 4588 cpu1-thermal { 4589 polling-delay-passive = <0>; 4590 polling-delay = <0>; 4591 thermal-sensors = <&tsens1 2>; 4592 4593 trips { 4594 cpu1_alert0: trip-point0 { 4595 temperature = <90000>; 4596 hysteresis = <2000>; 4597 type = "passive"; 4598 }; 4599 4600 cpu1_alert1: trip-point1 { 4601 temperature = <95000>; 4602 hysteresis = <2000>; 4603 type = "passive"; 4604 }; 4605 4606 cpu1_crit: cpu-critical { 4607 temperature = <110000>; 4608 hysteresis = <1000>; 4609 type = "critical"; 4610 }; 4611 }; 4612 }; 4613 4614 cpu2-thermal { 4615 polling-delay-passive = <0>; 4616 polling-delay = <0>; 4617 thermal-sensors = <&tsens1 3>; 4618 4619 trips { 4620 cpu2_alert0: trip-point0 { 4621 temperature = <90000>; 4622 hysteresis = <2000>; 4623 type = "passive"; 4624 }; 4625 4626 cpu2_alert1: trip-point1 { 4627 temperature = <95000>; 4628 hysteresis = <2000>; 4629 type = "passive"; 4630 }; 4631 4632 cpu2_crit: cpu-critical { 4633 temperature = <110000>; 4634 hysteresis = <1000>; 4635 type = "critical"; 4636 }; 4637 }; 4638 }; 4639 4640 cdsp0-thermal { 4641 polling-delay-passive = <10>; 4642 polling-delay = <0>; 4643 thermal-sensors = <&tsens2 4>; 4644 4645 trips { 4646 thermal-engine-config { 4647 temperature = <125000>; 4648 hysteresis = <1000>; 4649 type = "passive"; 4650 }; 4651 4652 thermal-hal-config { 4653 temperature = <125000>; 4654 hysteresis = <1000>; 4655 type = "passive"; 4656 }; 4657 4658 reset-mon-config { 4659 temperature = <115000>; 4660 hysteresis = <5000>; 4661 type = "passive"; 4662 }; 4663 4664 cdsp0_junction_config: junction-config { 4665 temperature = <95000>; 4666 hysteresis = <5000>; 4667 type = "passive"; 4668 }; 4669 }; 4670 }; 4671 4672 cdsp1-thermal { 4673 polling-delay-passive = <10>; 4674 polling-delay = <0>; 4675 thermal-sensors = <&tsens2 5>; 4676 4677 trips { 4678 thermal-engine-config { 4679 temperature = <125000>; 4680 hysteresis = <1000>; 4681 type = "passive"; 4682 }; 4683 4684 thermal-hal-config { 4685 temperature = <125000>; 4686 hysteresis = <1000>; 4687 type = "passive"; 4688 }; 4689 4690 reset-mon-config { 4691 temperature = <115000>; 4692 hysteresis = <5000>; 4693 type = "passive"; 4694 }; 4695 4696 cdsp1_junction_config: junction-config { 4697 temperature = <95000>; 4698 hysteresis = <5000>; 4699 type = "passive"; 4700 }; 4701 }; 4702 }; 4703 4704 cdsp2-thermal { 4705 polling-delay-passive = <10>; 4706 polling-delay = <0>; 4707 thermal-sensors = <&tsens2 6>; 4708 4709 trips { 4710 thermal-engine-config { 4711 temperature = <125000>; 4712 hysteresis = <1000>; 4713 type = "passive"; 4714 }; 4715 4716 thermal-hal-config { 4717 temperature = <125000>; 4718 hysteresis = <1000>; 4719 type = "passive"; 4720 }; 4721 4722 reset-mon-config { 4723 temperature = <115000>; 4724 hysteresis = <5000>; 4725 type = "passive"; 4726 }; 4727 4728 cdsp2_junction_config: junction-config { 4729 temperature = <95000>; 4730 hysteresis = <5000>; 4731 type = "passive"; 4732 }; 4733 }; 4734 }; 4735 4736 cdsp3-thermal { 4737 polling-delay-passive = <10>; 4738 polling-delay = <0>; 4739 thermal-sensors = <&tsens2 7>; 4740 4741 trips { 4742 thermal-engine-config { 4743 temperature = <125000>; 4744 hysteresis = <1000>; 4745 type = "passive"; 4746 }; 4747 4748 thermal-hal-config { 4749 temperature = <125000>; 4750 hysteresis = <1000>; 4751 type = "passive"; 4752 }; 4753 4754 reset-mon-config { 4755 temperature = <115000>; 4756 hysteresis = <5000>; 4757 type = "passive"; 4758 }; 4759 4760 cdsp3_junction_config: junction-config { 4761 temperature = <95000>; 4762 hysteresis = <5000>; 4763 type = "passive"; 4764 }; 4765 }; 4766 }; 4767 4768 video-thermal { 4769 polling-delay-passive = <0>; 4770 polling-delay = <0>; 4771 thermal-sensors = <&tsens1 8>; 4772 4773 trips { 4774 thermal-engine-config { 4775 temperature = <125000>; 4776 hysteresis = <1000>; 4777 type = "passive"; 4778 }; 4779 4780 reset-mon-config { 4781 temperature = <115000>; 4782 hysteresis = <5000>; 4783 type = "passive"; 4784 }; 4785 }; 4786 }; 4787 4788 mem-thermal { 4789 polling-delay-passive = <10>; 4790 polling-delay = <0>; 4791 thermal-sensors = <&tsens1 9>; 4792 4793 trips { 4794 thermal-engine-config { 4795 temperature = <125000>; 4796 hysteresis = <1000>; 4797 type = "passive"; 4798 }; 4799 4800 ddr_config0: ddr0-config { 4801 temperature = <90000>; 4802 hysteresis = <5000>; 4803 type = "passive"; 4804 }; 4805 4806 reset-mon-config { 4807 temperature = <115000>; 4808 hysteresis = <5000>; 4809 type = "passive"; 4810 }; 4811 }; 4812 }; 4813 4814 modem0-thermal { 4815 polling-delay-passive = <0>; 4816 polling-delay = <0>; 4817 thermal-sensors = <&tsens1 10>; 4818 4819 trips { 4820 thermal-engine-config { 4821 temperature = <125000>; 4822 hysteresis = <1000>; 4823 type = "passive"; 4824 }; 4825 4826 mdmss0_config0: mdmss0-config0 { 4827 temperature = <102000>; 4828 hysteresis = <3000>; 4829 type = "passive"; 4830 }; 4831 4832 mdmss0_config1: mdmss0-config1 { 4833 temperature = <105000>; 4834 hysteresis = <3000>; 4835 type = "passive"; 4836 }; 4837 4838 reset-mon-config { 4839 temperature = <115000>; 4840 hysteresis = <5000>; 4841 type = "passive"; 4842 }; 4843 }; 4844 }; 4845 4846 modem1-thermal { 4847 polling-delay-passive = <0>; 4848 polling-delay = <0>; 4849 thermal-sensors = <&tsens1 11>; 4850 4851 trips { 4852 thermal-engine-config { 4853 temperature = <125000>; 4854 hysteresis = <1000>; 4855 type = "passive"; 4856 }; 4857 4858 mdmss1_config0: mdmss1-config0 { 4859 temperature = <102000>; 4860 hysteresis = <3000>; 4861 type = "passive"; 4862 }; 4863 4864 mdmss1_config1: mdmss1-config1 { 4865 temperature = <105000>; 4866 hysteresis = <3000>; 4867 type = "passive"; 4868 }; 4869 4870 reset-mon-config { 4871 temperature = <115000>; 4872 hysteresis = <5000>; 4873 type = "passive"; 4874 }; 4875 }; 4876 }; 4877 4878 modem2-thermal { 4879 polling-delay-passive = <0>; 4880 polling-delay = <0>; 4881 thermal-sensors = <&tsens1 12>; 4882 4883 trips { 4884 thermal-engine-config { 4885 temperature = <125000>; 4886 hysteresis = <1000>; 4887 type = "passive"; 4888 }; 4889 4890 mdmss2_config0: mdmss2-config0 { 4891 temperature = <102000>; 4892 hysteresis = <3000>; 4893 type = "passive"; 4894 }; 4895 4896 mdmss2_config1: mdmss2-config1 { 4897 temperature = <105000>; 4898 hysteresis = <3000>; 4899 type = "passive"; 4900 }; 4901 4902 reset-mon-config { 4903 temperature = <115000>; 4904 hysteresis = <5000>; 4905 type = "passive"; 4906 }; 4907 }; 4908 }; 4909 4910 modem3-thermal { 4911 polling-delay-passive = <0>; 4912 polling-delay = <0>; 4913 thermal-sensors = <&tsens1 13>; 4914 4915 trips { 4916 thermal-engine-config { 4917 temperature = <125000>; 4918 hysteresis = <1000>; 4919 type = "passive"; 4920 }; 4921 4922 mdmss3_config0: mdmss3-config0 { 4923 temperature = <102000>; 4924 hysteresis = <3000>; 4925 type = "passive"; 4926 }; 4927 4928 mdmss3_config1: mdmss3-config1 { 4929 temperature = <105000>; 4930 hysteresis = <3000>; 4931 type = "passive"; 4932 }; 4933 4934 reset-mon-config { 4935 temperature = <115000>; 4936 hysteresis = <5000>; 4937 type = "passive"; 4938 }; 4939 }; 4940 }; 4941 4942 camera0-thermal { 4943 polling-delay-passive = <0>; 4944 polling-delay = <0>; 4945 thermal-sensors = <&tsens1 14>; 4946 4947 trips { 4948 thermal-engine-config { 4949 temperature = <125000>; 4950 hysteresis = <1000>; 4951 type = "passive"; 4952 }; 4953 4954 reset-mon-config { 4955 temperature = <115000>; 4956 hysteresis = <5000>; 4957 type = "passive"; 4958 }; 4959 }; 4960 }; 4961 4962 camera1-thermal { 4963 polling-delay-passive = <0>; 4964 polling-delay = <0>; 4965 thermal-sensors = <&tsens1 15>; 4966 4967 trips { 4968 thermal-engine-config { 4969 temperature = <125000>; 4970 hysteresis = <1000>; 4971 type = "passive"; 4972 }; 4973 4974 reset-mon-config { 4975 temperature = <115000>; 4976 hysteresis = <5000>; 4977 type = "passive"; 4978 }; 4979 }; 4980 }; 4981 4982 aoss2-thermal { 4983 polling-delay-passive = <0>; 4984 polling-delay = <0>; 4985 thermal-sensors = <&tsens2 0>; 4986 4987 trips { 4988 thermal-engine-config { 4989 temperature = <125000>; 4990 hysteresis = <1000>; 4991 type = "passive"; 4992 }; 4993 4994 reset-mon-config { 4995 temperature = <115000>; 4996 hysteresis = <5000>; 4997 type = "passive"; 4998 }; 4999 }; 5000 }; 5001 5002 gpuss-0-thermal { 5003 polling-delay-passive = <10>; 5004 polling-delay = <0>; 5005 thermal-sensors = <&tsens2 1>; 5006 5007 trips { 5008 thermal-engine-config { 5009 temperature = <125000>; 5010 hysteresis = <1000>; 5011 type = "passive"; 5012 }; 5013 5014 thermal-hal-config { 5015 temperature = <125000>; 5016 hysteresis = <1000>; 5017 type = "passive"; 5018 }; 5019 5020 reset-mon-config { 5021 temperature = <115000>; 5022 hysteresis = <5000>; 5023 type = "passive"; 5024 }; 5025 5026 gpu0_junction_config: junction-config { 5027 temperature = <95000>; 5028 hysteresis = <5000>; 5029 type = "passive"; 5030 }; 5031 }; 5032 }; 5033 5034 gpuss-1-thermal { 5035 polling-delay-passive = <10>; 5036 polling-delay = <0>; 5037 thermal-sensors = <&tsens2 2>; 5038 5039 trips { 5040 thermal-engine-config { 5041 temperature = <125000>; 5042 hysteresis = <1000>; 5043 type = "passive"; 5044 }; 5045 5046 thermal-hal-config { 5047 temperature = <125000>; 5048 hysteresis = <1000>; 5049 type = "passive"; 5050 }; 5051 5052 reset-mon-config { 5053 temperature = <115000>; 5054 hysteresis = <5000>; 5055 type = "passive"; 5056 }; 5057 5058 gpu1_junction_config: junction-config { 5059 temperature = <95000>; 5060 hysteresis = <5000>; 5061 type = "passive"; 5062 }; 5063 }; 5064 }; 5065 5066 gpuss-2-thermal { 5067 polling-delay-passive = <10>; 5068 polling-delay = <0>; 5069 thermal-sensors = <&tsens2 3>; 5070 5071 trips { 5072 thermal-engine-config { 5073 temperature = <125000>; 5074 hysteresis = <1000>; 5075 type = "passive"; 5076 }; 5077 5078 thermal-hal-config { 5079 temperature = <125000>; 5080 hysteresis = <1000>; 5081 type = "passive"; 5082 }; 5083 5084 reset-mon-config { 5085 temperature = <115000>; 5086 hysteresis = <5000>; 5087 type = "passive"; 5088 }; 5089 5090 gpu2_junction_config: junction-config { 5091 temperature = <95000>; 5092 hysteresis = <5000>; 5093 type = "passive"; 5094 }; 5095 }; 5096 }; 5097 5098 gpuss-3-thermal { 5099 polling-delay-passive = <10>; 5100 polling-delay = <0>; 5101 thermal-sensors = <&tsens2 4>; 5102 5103 trips { 5104 thermal-engine-config { 5105 temperature = <125000>; 5106 hysteresis = <1000>; 5107 type = "passive"; 5108 }; 5109 5110 thermal-hal-config { 5111 temperature = <125000>; 5112 hysteresis = <1000>; 5113 type = "passive"; 5114 }; 5115 5116 reset-mon-config { 5117 temperature = <115000>; 5118 hysteresis = <5000>; 5119 type = "passive"; 5120 }; 5121 5122 gpu3_junction_config: junction-config { 5123 temperature = <95000>; 5124 hysteresis = <5000>; 5125 type = "passive"; 5126 }; 5127 }; 5128 }; 5129 5130 gpuss-4-thermal { 5131 polling-delay-passive = <10>; 5132 polling-delay = <0>; 5133 thermal-sensors = <&tsens2 5>; 5134 5135 trips { 5136 thermal-engine-config { 5137 temperature = <125000>; 5138 hysteresis = <1000>; 5139 type = "passive"; 5140 }; 5141 5142 thermal-hal-config { 5143 temperature = <125000>; 5144 hysteresis = <1000>; 5145 type = "passive"; 5146 }; 5147 5148 reset-mon-config { 5149 temperature = <115000>; 5150 hysteresis = <5000>; 5151 type = "passive"; 5152 }; 5153 5154 gpu4_junction_config: junction-config { 5155 temperature = <95000>; 5156 hysteresis = <5000>; 5157 type = "passive"; 5158 }; 5159 }; 5160 }; 5161 5162 gpuss-5-thermal { 5163 polling-delay-passive = <10>; 5164 polling-delay = <0>; 5165 thermal-sensors = <&tsens2 6>; 5166 5167 trips { 5168 thermal-engine-config { 5169 temperature = <125000>; 5170 hysteresis = <1000>; 5171 type = "passive"; 5172 }; 5173 5174 thermal-hal-config { 5175 temperature = <125000>; 5176 hysteresis = <1000>; 5177 type = "passive"; 5178 }; 5179 5180 reset-mon-config { 5181 temperature = <115000>; 5182 hysteresis = <5000>; 5183 type = "passive"; 5184 }; 5185 5186 gpu5_junction_config: junction-config { 5187 temperature = <95000>; 5188 hysteresis = <5000>; 5189 type = "passive"; 5190 }; 5191 }; 5192 }; 5193 5194 gpuss-6-thermal { 5195 polling-delay-passive = <10>; 5196 polling-delay = <0>; 5197 thermal-sensors = <&tsens2 7>; 5198 5199 trips { 5200 thermal-engine-config { 5201 temperature = <125000>; 5202 hysteresis = <1000>; 5203 type = "passive"; 5204 }; 5205 5206 thermal-hal-config { 5207 temperature = <125000>; 5208 hysteresis = <1000>; 5209 type = "passive"; 5210 }; 5211 5212 reset-mon-config { 5213 temperature = <115000>; 5214 hysteresis = <5000>; 5215 type = "passive"; 5216 }; 5217 5218 gpu6_junction_config: junction-config { 5219 temperature = <95000>; 5220 hysteresis = <5000>; 5221 type = "passive"; 5222 }; 5223 }; 5224 }; 5225 5226 gpuss-7-thermal { 5227 polling-delay-passive = <10>; 5228 polling-delay = <0>; 5229 thermal-sensors = <&tsens2 8>; 5230 5231 trips { 5232 thermal-engine-config { 5233 temperature = <125000>; 5234 hysteresis = <1000>; 5235 type = "passive"; 5236 }; 5237 5238 thermal-hal-config { 5239 temperature = <125000>; 5240 hysteresis = <1000>; 5241 type = "passive"; 5242 }; 5243 5244 reset-mon-config { 5245 temperature = <115000>; 5246 hysteresis = <5000>; 5247 type = "passive"; 5248 }; 5249 5250 gpu7_junction_config: junction-config { 5251 temperature = <95000>; 5252 hysteresis = <5000>; 5253 type = "passive"; 5254 }; 5255 }; 5256 }; 5257 }; 5258 5259 timer { 5260 compatible = "arm,armv8-timer"; 5261 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5262 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5263 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5264 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5265 }; 5266}; 5267