1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2017 Broadcom 4 */ 5 6 /* 7 * This file contains the Broadcom Iproc GPIO driver that supports 3 8 * GPIO controllers on Iproc including the ASIU GPIO controller, the 9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic 10 * PINCONF such as bias pull up/down, and drive strength are also supported 11 * in this driver. 12 * 13 * It provides the functionality where pins from the GPIO can be 14 * individually muxed to GPIO function, if individual pad 15 * configuration is supported, through the interaction with respective 16 * SoCs IOMUX controller. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/slab.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/ioport.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 31 #include "../pinctrl-utils.h" 32 33 #define IPROC_GPIO_DATA_IN_OFFSET 0x00 34 #define IPROC_GPIO_DATA_OUT_OFFSET 0x04 35 #define IPROC_GPIO_OUT_EN_OFFSET 0x08 36 #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c 37 #define IPROC_GPIO_INT_DE_OFFSET 0x10 38 #define IPROC_GPIO_INT_EDGE_OFFSET 0x14 39 #define IPROC_GPIO_INT_MSK_OFFSET 0x18 40 #define IPROC_GPIO_INT_STAT_OFFSET 0x1c 41 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20 42 #define IPROC_GPIO_INT_CLR_OFFSET 0x24 43 #define IPROC_GPIO_PAD_RES_OFFSET 0x34 44 #define IPROC_GPIO_RES_EN_OFFSET 0x38 45 46 /* drive strength control for ASIU GPIO */ 47 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 48 49 /* pinconf for CCM GPIO */ 50 #define IPROC_GPIO_PULL_DN_OFFSET 0x10 51 #define IPROC_GPIO_PULL_UP_OFFSET 0x14 52 53 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/ 54 #define IPROC_GPIO_DRV_CTRL_OFFSET 0x00 55 56 #define GPIO_BANK_SIZE 0x200 57 #define NGPIOS_PER_BANK 32 58 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) 59 60 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) 61 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) 62 63 #define GPIO_DRV_STRENGTH_BIT_SHIFT 20 64 #define GPIO_DRV_STRENGTH_BITS 3 65 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) 66 67 enum iproc_pinconf_param { 68 IPROC_PINCONF_DRIVE_STRENGTH = 0, 69 IPROC_PINCONF_BIAS_DISABLE, 70 IPROC_PINCONF_BIAS_PULL_UP, 71 IPROC_PINCONF_BIAS_PULL_DOWN, 72 IPROC_PINCON_MAX, 73 }; 74 75 enum iproc_pinconf_ctrl_type { 76 IOCTRL_TYPE_AON = 1, 77 IOCTRL_TYPE_CDRU, 78 IOCTRL_TYPE_INVALID, 79 }; 80 81 /* 82 * Iproc GPIO core 83 * 84 * @dev: pointer to device 85 * @base: I/O register base for Iproc GPIO controller 86 * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that 87 * has the PINCONF support implemented outside of the GPIO block 88 * @lock: lock to protect access to I/O registers 89 * @gc: GPIO chip 90 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs 91 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins 92 * that can be individually muxed to GPIO 93 * @pinconf_disable: contains a list of PINCONF parameters that need to be 94 * disabled 95 * @nr_pinconf_disable: total number of PINCONF parameters that need to be 96 * disabled 97 * @pctl: pointer to pinctrl_dev 98 * @pctldesc: pinctrl descriptor 99 */ 100 struct iproc_gpio { 101 struct device *dev; 102 103 void __iomem *base; 104 void __iomem *io_ctrl; 105 enum iproc_pinconf_ctrl_type io_ctrl_type; 106 107 raw_spinlock_t lock; 108 109 struct irq_chip irqchip; 110 struct gpio_chip gc; 111 unsigned num_banks; 112 113 bool pinmux_is_supported; 114 115 enum pin_config_param *pinconf_disable; 116 unsigned int nr_pinconf_disable; 117 118 struct pinctrl_dev *pctl; 119 struct pinctrl_desc pctldesc; 120 }; 121 122 /* 123 * Mapping from PINCONF pins to GPIO pins is 1-to-1 124 */ 125 static inline unsigned iproc_pin_to_gpio(unsigned pin) 126 { 127 return pin; 128 } 129 130 /** 131 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a 132 * Iproc GPIO register 133 * 134 * @chip: Iproc GPIO device 135 * @reg: register offset 136 * @gpio: GPIO pin 137 * @set: set or clear 138 */ 139 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, 140 unsigned gpio, bool set) 141 { 142 unsigned int offset = IPROC_GPIO_REG(gpio, reg); 143 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 144 u32 val; 145 146 val = readl(chip->base + offset); 147 if (set) 148 val |= BIT(shift); 149 else 150 val &= ~BIT(shift); 151 writel(val, chip->base + offset); 152 } 153 154 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, 155 unsigned gpio) 156 { 157 unsigned int offset = IPROC_GPIO_REG(gpio, reg); 158 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 159 160 return !!(readl(chip->base + offset) & BIT(shift)); 161 } 162 163 static void iproc_gpio_irq_handler(struct irq_desc *desc) 164 { 165 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 166 struct iproc_gpio *chip = gpiochip_get_data(gc); 167 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 168 int i, bit; 169 170 chained_irq_enter(irq_chip, desc); 171 172 /* go through the entire GPIO banks and handle all interrupts */ 173 for (i = 0; i < chip->num_banks; i++) { 174 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + 175 IPROC_GPIO_INT_MSTAT_OFFSET); 176 177 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { 178 unsigned pin = NGPIOS_PER_BANK * i + bit; 179 180 /* 181 * Clear the interrupt before invoking the 182 * handler, so we do not leave any window 183 */ 184 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + 185 IPROC_GPIO_INT_CLR_OFFSET); 186 187 generic_handle_domain_irq(gc->irq.domain, pin); 188 } 189 } 190 191 chained_irq_exit(irq_chip, desc); 192 } 193 194 195 static void iproc_gpio_irq_ack(struct irq_data *d) 196 { 197 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 198 struct iproc_gpio *chip = gpiochip_get_data(gc); 199 unsigned gpio = d->hwirq; 200 unsigned int offset = IPROC_GPIO_REG(gpio, 201 IPROC_GPIO_INT_CLR_OFFSET); 202 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 203 u32 val = BIT(shift); 204 205 writel(val, chip->base + offset); 206 } 207 208 /** 209 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt 210 * 211 * @d: IRQ chip data 212 * @unmask: mask/unmask GPIO interrupt 213 */ 214 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask) 215 { 216 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 217 struct iproc_gpio *chip = gpiochip_get_data(gc); 218 unsigned gpio = d->hwirq; 219 220 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); 221 } 222 223 static void iproc_gpio_irq_mask(struct irq_data *d) 224 { 225 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 226 struct iproc_gpio *chip = gpiochip_get_data(gc); 227 unsigned long flags; 228 229 raw_spin_lock_irqsave(&chip->lock, flags); 230 iproc_gpio_irq_set_mask(d, false); 231 raw_spin_unlock_irqrestore(&chip->lock, flags); 232 } 233 234 static void iproc_gpio_irq_unmask(struct irq_data *d) 235 { 236 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 237 struct iproc_gpio *chip = gpiochip_get_data(gc); 238 unsigned long flags; 239 240 raw_spin_lock_irqsave(&chip->lock, flags); 241 iproc_gpio_irq_set_mask(d, true); 242 raw_spin_unlock_irqrestore(&chip->lock, flags); 243 } 244 245 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) 246 { 247 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 248 struct iproc_gpio *chip = gpiochip_get_data(gc); 249 unsigned gpio = d->hwirq; 250 bool level_triggered = false; 251 bool dual_edge = false; 252 bool rising_or_high = false; 253 unsigned long flags; 254 255 switch (type & IRQ_TYPE_SENSE_MASK) { 256 case IRQ_TYPE_EDGE_RISING: 257 rising_or_high = true; 258 break; 259 260 case IRQ_TYPE_EDGE_FALLING: 261 break; 262 263 case IRQ_TYPE_EDGE_BOTH: 264 dual_edge = true; 265 break; 266 267 case IRQ_TYPE_LEVEL_HIGH: 268 level_triggered = true; 269 rising_or_high = true; 270 break; 271 272 case IRQ_TYPE_LEVEL_LOW: 273 level_triggered = true; 274 break; 275 276 default: 277 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", 278 type); 279 return -EINVAL; 280 } 281 282 raw_spin_lock_irqsave(&chip->lock, flags); 283 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio, 284 level_triggered); 285 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); 286 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, 287 rising_or_high); 288 289 if (type & IRQ_TYPE_EDGE_BOTH) 290 irq_set_handler_locked(d, handle_edge_irq); 291 else 292 irq_set_handler_locked(d, handle_level_irq); 293 294 raw_spin_unlock_irqrestore(&chip->lock, flags); 295 296 dev_dbg(chip->dev, 297 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n", 298 gpio, level_triggered, dual_edge, rising_or_high); 299 300 return 0; 301 } 302 303 /* 304 * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO 305 */ 306 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) 307 { 308 struct iproc_gpio *chip = gpiochip_get_data(gc); 309 unsigned gpio = gc->base + offset; 310 311 /* not all Iproc GPIO pins can be muxed individually */ 312 if (!chip->pinmux_is_supported) 313 return 0; 314 315 return pinctrl_gpio_request(gpio); 316 } 317 318 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) 319 { 320 struct iproc_gpio *chip = gpiochip_get_data(gc); 321 unsigned gpio = gc->base + offset; 322 323 if (!chip->pinmux_is_supported) 324 return; 325 326 pinctrl_gpio_free(gpio); 327 } 328 329 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 330 { 331 struct iproc_gpio *chip = gpiochip_get_data(gc); 332 unsigned long flags; 333 334 raw_spin_lock_irqsave(&chip->lock, flags); 335 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false); 336 raw_spin_unlock_irqrestore(&chip->lock, flags); 337 338 dev_dbg(chip->dev, "gpio:%u set input\n", gpio); 339 340 return 0; 341 } 342 343 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, 344 int val) 345 { 346 struct iproc_gpio *chip = gpiochip_get_data(gc); 347 unsigned long flags; 348 349 raw_spin_lock_irqsave(&chip->lock, flags); 350 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true); 351 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); 352 raw_spin_unlock_irqrestore(&chip->lock, flags); 353 354 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); 355 356 return 0; 357 } 358 359 static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 360 { 361 struct iproc_gpio *chip = gpiochip_get_data(gc); 362 unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET); 363 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 364 365 if (readl(chip->base + offset) & BIT(shift)) 366 return GPIO_LINE_DIRECTION_OUT; 367 368 return GPIO_LINE_DIRECTION_IN; 369 } 370 371 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) 372 { 373 struct iproc_gpio *chip = gpiochip_get_data(gc); 374 unsigned long flags; 375 376 raw_spin_lock_irqsave(&chip->lock, flags); 377 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); 378 raw_spin_unlock_irqrestore(&chip->lock, flags); 379 380 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); 381 } 382 383 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) 384 { 385 struct iproc_gpio *chip = gpiochip_get_data(gc); 386 unsigned int offset = IPROC_GPIO_REG(gpio, 387 IPROC_GPIO_DATA_IN_OFFSET); 388 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 389 390 return !!(readl(chip->base + offset) & BIT(shift)); 391 } 392 393 /* 394 * Mapping of the iProc PINCONF parameters to the generic pin configuration 395 * parameters 396 */ 397 static const enum pin_config_param iproc_pinconf_disable_map[] = { 398 [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH, 399 [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE, 400 [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP, 401 [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN, 402 }; 403 404 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip, 405 enum pin_config_param param) 406 { 407 unsigned int i; 408 409 if (!chip->nr_pinconf_disable) 410 return false; 411 412 for (i = 0; i < chip->nr_pinconf_disable; i++) 413 if (chip->pinconf_disable[i] == param) 414 return true; 415 416 return false; 417 } 418 419 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip, 420 unsigned long disable_mask) 421 { 422 unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map); 423 unsigned int bit, nbits = 0; 424 425 /* figure out total number of PINCONF parameters to disable */ 426 for_each_set_bit(bit, &disable_mask, map_size) 427 nbits++; 428 429 if (!nbits) 430 return 0; 431 432 /* 433 * Allocate an array to store PINCONF parameters that need to be 434 * disabled 435 */ 436 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits, 437 sizeof(*chip->pinconf_disable), 438 GFP_KERNEL); 439 if (!chip->pinconf_disable) 440 return -ENOMEM; 441 442 chip->nr_pinconf_disable = nbits; 443 444 /* now store these parameters */ 445 nbits = 0; 446 for_each_set_bit(bit, &disable_mask, map_size) 447 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit]; 448 449 return 0; 450 } 451 452 static int iproc_get_groups_count(struct pinctrl_dev *pctldev) 453 { 454 return 1; 455 } 456 457 /* 458 * Only one group: "gpio_grp", since this local pinctrl device only performs 459 * GPIO specific PINCONF configurations 460 */ 461 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev, 462 unsigned selector) 463 { 464 return "gpio_grp"; 465 } 466 467 static const struct pinctrl_ops iproc_pctrl_ops = { 468 .get_groups_count = iproc_get_groups_count, 469 .get_group_name = iproc_get_group_name, 470 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 471 .dt_free_map = pinctrl_utils_free_map, 472 }; 473 474 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, 475 bool disable, bool pull_up) 476 { 477 void __iomem *base; 478 unsigned long flags; 479 unsigned int shift; 480 u32 val_1, val_2; 481 482 raw_spin_lock_irqsave(&chip->lock, flags); 483 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) { 484 base = chip->io_ctrl; 485 shift = IPROC_GPIO_SHIFT(gpio); 486 487 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET); 488 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET); 489 if (disable) { 490 /* no pull-up or pull-down */ 491 val_1 &= ~BIT(shift); 492 val_2 &= ~BIT(shift); 493 } else if (pull_up) { 494 val_1 |= BIT(shift); 495 val_2 &= ~BIT(shift); 496 } else { 497 val_1 &= ~BIT(shift); 498 val_2 |= BIT(shift); 499 } 500 writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET); 501 writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET); 502 } else { 503 if (disable) { 504 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, 505 false); 506 } else { 507 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, 508 pull_up); 509 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, 510 true); 511 } 512 } 513 514 raw_spin_unlock_irqrestore(&chip->lock, flags); 515 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); 516 517 return 0; 518 } 519 520 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, 521 bool *disable, bool *pull_up) 522 { 523 void __iomem *base; 524 unsigned long flags; 525 unsigned int shift; 526 u32 val_1, val_2; 527 528 raw_spin_lock_irqsave(&chip->lock, flags); 529 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) { 530 base = chip->io_ctrl; 531 shift = IPROC_GPIO_SHIFT(gpio); 532 533 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift); 534 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift); 535 536 *pull_up = val_1 ? true : false; 537 *disable = (val_1 | val_2) ? false : true; 538 539 } else { 540 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); 541 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); 542 } 543 raw_spin_unlock_irqrestore(&chip->lock, flags); 544 } 545 546 #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \ 547 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \ 548 ((type) == IOCTRL_TYPE_CDRU) ? \ 549 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \ 550 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET))) 551 552 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, 553 unsigned strength) 554 { 555 void __iomem *base; 556 unsigned int i, offset, shift; 557 u32 val; 558 unsigned long flags; 559 560 /* make sure drive strength is supported */ 561 if (strength < 2 || strength > 16 || (strength % 2)) 562 return -ENOTSUPP; 563 564 if (chip->io_ctrl) { 565 base = chip->io_ctrl; 566 } else { 567 base = chip->base; 568 } 569 570 shift = IPROC_GPIO_SHIFT(gpio); 571 572 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, 573 strength); 574 575 raw_spin_lock_irqsave(&chip->lock, flags); 576 strength = (strength / 2) - 1; 577 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { 578 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type); 579 val = readl(base + offset); 580 val &= ~BIT(shift); 581 val |= ((strength >> i) & 0x1) << shift; 582 writel(val, base + offset); 583 } 584 raw_spin_unlock_irqrestore(&chip->lock, flags); 585 586 return 0; 587 } 588 589 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, 590 u16 *strength) 591 { 592 void __iomem *base; 593 unsigned int i, offset, shift; 594 u32 val; 595 unsigned long flags; 596 597 if (chip->io_ctrl) { 598 base = chip->io_ctrl; 599 } else { 600 base = chip->base; 601 } 602 603 shift = IPROC_GPIO_SHIFT(gpio); 604 605 raw_spin_lock_irqsave(&chip->lock, flags); 606 *strength = 0; 607 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { 608 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type); 609 val = readl(base + offset) & BIT(shift); 610 val >>= shift; 611 *strength += (val << i); 612 } 613 614 /* convert to mA */ 615 *strength = (*strength + 1) * 2; 616 raw_spin_unlock_irqrestore(&chip->lock, flags); 617 618 return 0; 619 } 620 621 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 622 unsigned long *config) 623 { 624 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 625 enum pin_config_param param = pinconf_to_config_param(*config); 626 unsigned gpio = iproc_pin_to_gpio(pin); 627 u16 arg; 628 bool disable, pull_up; 629 int ret; 630 631 if (iproc_pinconf_param_is_disabled(chip, param)) 632 return -ENOTSUPP; 633 634 switch (param) { 635 case PIN_CONFIG_BIAS_DISABLE: 636 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); 637 if (disable) 638 return 0; 639 else 640 return -EINVAL; 641 642 case PIN_CONFIG_BIAS_PULL_UP: 643 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); 644 if (!disable && pull_up) 645 return 0; 646 else 647 return -EINVAL; 648 649 case PIN_CONFIG_BIAS_PULL_DOWN: 650 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); 651 if (!disable && !pull_up) 652 return 0; 653 else 654 return -EINVAL; 655 656 case PIN_CONFIG_DRIVE_STRENGTH: 657 ret = iproc_gpio_get_strength(chip, gpio, &arg); 658 if (ret) 659 return ret; 660 *config = pinconf_to_config_packed(param, arg); 661 662 return 0; 663 664 default: 665 return -ENOTSUPP; 666 } 667 668 return -ENOTSUPP; 669 } 670 671 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 672 unsigned long *configs, unsigned num_configs) 673 { 674 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 675 enum pin_config_param param; 676 u32 arg; 677 unsigned i, gpio = iproc_pin_to_gpio(pin); 678 int ret = -ENOTSUPP; 679 680 for (i = 0; i < num_configs; i++) { 681 param = pinconf_to_config_param(configs[i]); 682 683 if (iproc_pinconf_param_is_disabled(chip, param)) 684 return -ENOTSUPP; 685 686 arg = pinconf_to_config_argument(configs[i]); 687 688 switch (param) { 689 case PIN_CONFIG_BIAS_DISABLE: 690 ret = iproc_gpio_set_pull(chip, gpio, true, false); 691 if (ret < 0) 692 goto out; 693 break; 694 695 case PIN_CONFIG_BIAS_PULL_UP: 696 ret = iproc_gpio_set_pull(chip, gpio, false, true); 697 if (ret < 0) 698 goto out; 699 break; 700 701 case PIN_CONFIG_BIAS_PULL_DOWN: 702 ret = iproc_gpio_set_pull(chip, gpio, false, false); 703 if (ret < 0) 704 goto out; 705 break; 706 707 case PIN_CONFIG_DRIVE_STRENGTH: 708 ret = iproc_gpio_set_strength(chip, gpio, arg); 709 if (ret < 0) 710 goto out; 711 break; 712 713 default: 714 dev_err(chip->dev, "invalid configuration\n"); 715 return -ENOTSUPP; 716 } 717 } /* for each config */ 718 719 out: 720 return ret; 721 } 722 723 static const struct pinconf_ops iproc_pconf_ops = { 724 .is_generic = true, 725 .pin_config_get = iproc_pin_config_get, 726 .pin_config_set = iproc_pin_config_set, 727 }; 728 729 /* 730 * Iproc GPIO controller supports some PINCONF related configurations such as 731 * pull up, pull down, and drive strength, when the pin is configured to GPIO 732 * 733 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the 734 * local GPIO pins 735 */ 736 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) 737 { 738 struct pinctrl_desc *pctldesc = &chip->pctldesc; 739 struct pinctrl_pin_desc *pins; 740 struct gpio_chip *gc = &chip->gc; 741 int i; 742 743 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); 744 if (!pins) 745 return -ENOMEM; 746 747 for (i = 0; i < gc->ngpio; i++) { 748 pins[i].number = i; 749 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, 750 "gpio-%d", i); 751 if (!pins[i].name) 752 return -ENOMEM; 753 } 754 755 pctldesc->name = dev_name(chip->dev); 756 pctldesc->pctlops = &iproc_pctrl_ops; 757 pctldesc->pins = pins; 758 pctldesc->npins = gc->ngpio; 759 pctldesc->confops = &iproc_pconf_ops; 760 761 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip); 762 if (IS_ERR(chip->pctl)) { 763 dev_err(chip->dev, "unable to register pinctrl device\n"); 764 return PTR_ERR(chip->pctl); 765 } 766 767 return 0; 768 } 769 770 static const struct of_device_id iproc_gpio_of_match[] = { 771 { .compatible = "brcm,iproc-gpio" }, 772 { .compatible = "brcm,cygnus-ccm-gpio" }, 773 { .compatible = "brcm,cygnus-asiu-gpio" }, 774 { .compatible = "brcm,cygnus-crmu-gpio" }, 775 { .compatible = "brcm,iproc-nsp-gpio" }, 776 { .compatible = "brcm,iproc-stingray-gpio" }, 777 { /* sentinel */ } 778 }; 779 780 static int iproc_gpio_probe(struct platform_device *pdev) 781 { 782 struct device *dev = &pdev->dev; 783 struct resource *res; 784 struct iproc_gpio *chip; 785 struct gpio_chip *gc; 786 u32 ngpios, pinconf_disable_mask = 0; 787 int irq, ret; 788 bool no_pinconf = false; 789 enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID; 790 791 /* NSP does not support drive strength config */ 792 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio")) 793 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH); 794 /* Stingray does not support pinconf in this controller */ 795 else if (of_device_is_compatible(dev->of_node, 796 "brcm,iproc-stingray-gpio")) 797 no_pinconf = true; 798 799 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 800 if (!chip) 801 return -ENOMEM; 802 803 chip->dev = dev; 804 platform_set_drvdata(pdev, chip); 805 806 chip->base = devm_platform_ioremap_resource(pdev, 0); 807 if (IS_ERR(chip->base)) { 808 dev_err(dev, "unable to map I/O memory\n"); 809 return PTR_ERR(chip->base); 810 } 811 812 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 813 if (res) { 814 chip->io_ctrl = devm_ioremap_resource(dev, res); 815 if (IS_ERR(chip->io_ctrl)) 816 return PTR_ERR(chip->io_ctrl); 817 if (of_device_is_compatible(dev->of_node, 818 "brcm,cygnus-ccm-gpio")) 819 io_ctrl_type = IOCTRL_TYPE_CDRU; 820 else 821 io_ctrl_type = IOCTRL_TYPE_AON; 822 } 823 824 chip->io_ctrl_type = io_ctrl_type; 825 826 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { 827 dev_err(&pdev->dev, "missing ngpios DT property\n"); 828 return -ENODEV; 829 } 830 831 raw_spin_lock_init(&chip->lock); 832 833 gc = &chip->gc; 834 gc->base = -1; 835 gc->ngpio = ngpios; 836 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; 837 gc->label = dev_name(dev); 838 gc->parent = dev; 839 gc->of_node = dev->of_node; 840 gc->request = iproc_gpio_request; 841 gc->free = iproc_gpio_free; 842 gc->direction_input = iproc_gpio_direction_input; 843 gc->direction_output = iproc_gpio_direction_output; 844 gc->get_direction = iproc_gpio_get_direction; 845 gc->set = iproc_gpio_set; 846 gc->get = iproc_gpio_get; 847 848 chip->pinmux_is_supported = of_property_read_bool(dev->of_node, 849 "gpio-ranges"); 850 851 /* optional GPIO interrupt support */ 852 irq = platform_get_irq_optional(pdev, 0); 853 if (irq > 0) { 854 struct irq_chip *irqc; 855 struct gpio_irq_chip *girq; 856 857 irqc = &chip->irqchip; 858 irqc->name = dev_name(dev); 859 irqc->irq_ack = iproc_gpio_irq_ack; 860 irqc->irq_mask = iproc_gpio_irq_mask; 861 irqc->irq_unmask = iproc_gpio_irq_unmask; 862 irqc->irq_set_type = iproc_gpio_irq_set_type; 863 irqc->irq_enable = iproc_gpio_irq_unmask; 864 irqc->irq_disable = iproc_gpio_irq_mask; 865 866 girq = &gc->irq; 867 girq->chip = irqc; 868 girq->parent_handler = iproc_gpio_irq_handler; 869 girq->num_parents = 1; 870 girq->parents = devm_kcalloc(dev, 1, 871 sizeof(*girq->parents), 872 GFP_KERNEL); 873 if (!girq->parents) 874 return -ENOMEM; 875 girq->parents[0] = irq; 876 girq->default_type = IRQ_TYPE_NONE; 877 girq->handler = handle_bad_irq; 878 } 879 880 ret = gpiochip_add_data(gc, chip); 881 if (ret < 0) { 882 dev_err(dev, "unable to add GPIO chip\n"); 883 return ret; 884 } 885 886 if (!no_pinconf) { 887 ret = iproc_gpio_register_pinconf(chip); 888 if (ret) { 889 dev_err(dev, "unable to register pinconf\n"); 890 goto err_rm_gpiochip; 891 } 892 893 if (pinconf_disable_mask) { 894 ret = iproc_pinconf_disable_map_create(chip, 895 pinconf_disable_mask); 896 if (ret) { 897 dev_err(dev, 898 "unable to create pinconf disable map\n"); 899 goto err_rm_gpiochip; 900 } 901 } 902 } 903 904 return 0; 905 906 err_rm_gpiochip: 907 gpiochip_remove(gc); 908 909 return ret; 910 } 911 912 static struct platform_driver iproc_gpio_driver = { 913 .driver = { 914 .name = "iproc-gpio", 915 .of_match_table = iproc_gpio_of_match, 916 }, 917 .probe = iproc_gpio_probe, 918 }; 919 920 static int __init iproc_gpio_init(void) 921 { 922 return platform_driver_register(&iproc_gpio_driver); 923 } 924 arch_initcall_sync(iproc_gpio_init); 925