1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/interconnect/qcom,sm8350.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <38400000>; 38 clock-output-names = "xo_board"; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 clock-frequency = <32000>; 44 #clock-cells = <0>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 CPU0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 57 enable-method = "psci"; 58 next-level-cache = <&L2_0>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 #cooling-cells = <2>; 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&L3_0>; 68 L3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 CPU1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 #cooling-cells = <2>; 87 L2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a55"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&L2_200>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 #cooling-cells = <2>; 106 L2_200: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 cache-unified; 110 next-level-cache = <&L3_0>; 111 }; 112 }; 113 114 CPU3: cpu@300 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a55"; 117 reg = <0x0 0x300>; 118 clocks = <&cpufreq_hw 0>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 power-domains = <&CPU_PD3>; 123 power-domain-names = "psci"; 124 #cooling-cells = <2>; 125 L2_300: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 cache-unified; 129 next-level-cache = <&L3_0>; 130 }; 131 }; 132 133 CPU4: cpu@400 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a78"; 136 reg = <0x0 0x400>; 137 clocks = <&cpufreq_hw 1>; 138 enable-method = "psci"; 139 next-level-cache = <&L2_400>; 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 power-domains = <&CPU_PD4>; 142 power-domain-names = "psci"; 143 #cooling-cells = <2>; 144 L2_400: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU5: cpu@500 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a78"; 155 reg = <0x0 0x500>; 156 clocks = <&cpufreq_hw 1>; 157 enable-method = "psci"; 158 next-level-cache = <&L2_500>; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 power-domains = <&CPU_PD5>; 161 power-domain-names = "psci"; 162 #cooling-cells = <2>; 163 L2_500: l2-cache { 164 compatible = "cache"; 165 cache-level = <2>; 166 cache-unified; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU6: cpu@600 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a78"; 174 reg = <0x0 0x600>; 175 clocks = <&cpufreq_hw 1>; 176 enable-method = "psci"; 177 next-level-cache = <&L2_600>; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 power-domains = <&CPU_PD6>; 180 power-domain-names = "psci"; 181 #cooling-cells = <2>; 182 L2_600: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 }; 188 }; 189 190 CPU7: cpu@700 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-x1"; 193 reg = <0x0 0x700>; 194 clocks = <&cpufreq_hw 2>; 195 enable-method = "psci"; 196 next-level-cache = <&L2_700>; 197 qcom,freq-domain = <&cpufreq_hw 2>; 198 power-domains = <&CPU_PD7>; 199 power-domain-names = "psci"; 200 #cooling-cells = <2>; 201 L2_700: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&L3_0>; 206 }; 207 }; 208 209 cpu-map { 210 cluster0 { 211 core0 { 212 cpu = <&CPU0>; 213 }; 214 215 core1 { 216 cpu = <&CPU1>; 217 }; 218 219 core2 { 220 cpu = <&CPU2>; 221 }; 222 223 core3 { 224 cpu = <&CPU3>; 225 }; 226 227 core4 { 228 cpu = <&CPU4>; 229 }; 230 231 core5 { 232 cpu = <&CPU5>; 233 }; 234 235 core6 { 236 cpu = <&CPU6>; 237 }; 238 239 core7 { 240 cpu = <&CPU7>; 241 }; 242 }; 243 }; 244 245 idle-states { 246 entry-method = "psci"; 247 248 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 249 compatible = "arm,idle-state"; 250 idle-state-name = "silver-rail-power-collapse"; 251 arm,psci-suspend-param = <0x40000004>; 252 entry-latency-us = <360>; 253 exit-latency-us = <531>; 254 min-residency-us = <3934>; 255 local-timer-stop; 256 }; 257 258 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 259 compatible = "arm,idle-state"; 260 idle-state-name = "gold-rail-power-collapse"; 261 arm,psci-suspend-param = <0x40000004>; 262 entry-latency-us = <702>; 263 exit-latency-us = <1061>; 264 min-residency-us = <4488>; 265 local-timer-stop; 266 }; 267 }; 268 269 domain-idle-states { 270 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 271 compatible = "domain-idle-state"; 272 arm,psci-suspend-param = <0x41000044>; 273 entry-latency-us = <2752>; 274 exit-latency-us = <3048>; 275 min-residency-us = <6118>; 276 }; 277 278 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 279 compatible = "domain-idle-state"; 280 arm,psci-suspend-param = <0x4100c344>; 281 entry-latency-us = <3263>; 282 exit-latency-us = <6562>; 283 min-residency-us = <9987>; 284 }; 285 }; 286 }; 287 288 firmware { 289 scm: scm { 290 compatible = "qcom,scm-sm8350", "qcom,scm"; 291 #reset-cells = <1>; 292 }; 293 }; 294 295 memory@80000000 { 296 device_type = "memory"; 297 /* We expect the bootloader to fill in the size */ 298 reg = <0x0 0x80000000 0x0 0x0>; 299 }; 300 301 pmu { 302 compatible = "arm,armv8-pmuv3"; 303 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 304 }; 305 306 psci { 307 compatible = "arm,psci-1.0"; 308 method = "smc"; 309 310 CPU_PD0: power-domain-cpu0 { 311 #power-domain-cells = <0>; 312 power-domains = <&CLUSTER_PD>; 313 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 314 }; 315 316 CPU_PD1: power-domain-cpu1 { 317 #power-domain-cells = <0>; 318 power-domains = <&CLUSTER_PD>; 319 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 320 }; 321 322 CPU_PD2: power-domain-cpu2 { 323 #power-domain-cells = <0>; 324 power-domains = <&CLUSTER_PD>; 325 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 326 }; 327 328 CPU_PD3: power-domain-cpu3 { 329 #power-domain-cells = <0>; 330 power-domains = <&CLUSTER_PD>; 331 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 332 }; 333 334 CPU_PD4: power-domain-cpu4 { 335 #power-domain-cells = <0>; 336 power-domains = <&CLUSTER_PD>; 337 domain-idle-states = <&BIG_CPU_SLEEP_0>; 338 }; 339 340 CPU_PD5: power-domain-cpu5 { 341 #power-domain-cells = <0>; 342 power-domains = <&CLUSTER_PD>; 343 domain-idle-states = <&BIG_CPU_SLEEP_0>; 344 }; 345 346 CPU_PD6: power-domain-cpu6 { 347 #power-domain-cells = <0>; 348 power-domains = <&CLUSTER_PD>; 349 domain-idle-states = <&BIG_CPU_SLEEP_0>; 350 }; 351 352 CPU_PD7: power-domain-cpu7 { 353 #power-domain-cells = <0>; 354 power-domains = <&CLUSTER_PD>; 355 domain-idle-states = <&BIG_CPU_SLEEP_0>; 356 }; 357 358 CLUSTER_PD: power-domain-cpu-cluster0 { 359 #power-domain-cells = <0>; 360 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 361 }; 362 }; 363 364 qup_opp_table_100mhz: opp-table-qup100mhz { 365 compatible = "operating-points-v2"; 366 367 opp-50000000 { 368 opp-hz = /bits/ 64 <50000000>; 369 required-opps = <&rpmhpd_opp_min_svs>; 370 }; 371 372 opp-75000000 { 373 opp-hz = /bits/ 64 <75000000>; 374 required-opps = <&rpmhpd_opp_low_svs>; 375 }; 376 377 opp-100000000 { 378 opp-hz = /bits/ 64 <100000000>; 379 required-opps = <&rpmhpd_opp_svs>; 380 }; 381 }; 382 383 qup_opp_table_120mhz: opp-table-qup120mhz { 384 compatible = "operating-points-v2"; 385 386 opp-50000000 { 387 opp-hz = /bits/ 64 <50000000>; 388 required-opps = <&rpmhpd_opp_min_svs>; 389 }; 390 391 opp-75000000 { 392 opp-hz = /bits/ 64 <75000000>; 393 required-opps = <&rpmhpd_opp_low_svs>; 394 }; 395 396 opp-120000000 { 397 opp-hz = /bits/ 64 <120000000>; 398 required-opps = <&rpmhpd_opp_svs>; 399 }; 400 }; 401 402 reserved_memory: reserved-memory { 403 #address-cells = <2>; 404 #size-cells = <2>; 405 ranges; 406 407 hyp_mem: memory@80000000 { 408 reg = <0x0 0x80000000 0x0 0x600000>; 409 no-map; 410 }; 411 412 xbl_aop_mem: memory@80700000 { 413 no-map; 414 reg = <0x0 0x80700000 0x0 0x160000>; 415 }; 416 417 cmd_db: memory@80860000 { 418 compatible = "qcom,cmd-db"; 419 reg = <0x0 0x80860000 0x0 0x20000>; 420 no-map; 421 }; 422 423 reserved_xbl_uefi_log: memory@80880000 { 424 reg = <0x0 0x80880000 0x0 0x14000>; 425 no-map; 426 }; 427 428 smem@80900000 { 429 compatible = "qcom,smem"; 430 reg = <0x0 0x80900000 0x0 0x200000>; 431 hwlocks = <&tcsr_mutex 3>; 432 no-map; 433 }; 434 435 cpucp_fw_mem: memory@80b00000 { 436 reg = <0x0 0x80b00000 0x0 0x100000>; 437 no-map; 438 }; 439 440 cdsp_secure_heap: memory@80c00000 { 441 reg = <0x0 0x80c00000 0x0 0x4600000>; 442 no-map; 443 }; 444 445 pil_camera_mem: mmeory@85200000 { 446 reg = <0x0 0x85200000 0x0 0x500000>; 447 no-map; 448 }; 449 450 pil_video_mem: memory@85700000 { 451 reg = <0x0 0x85700000 0x0 0x500000>; 452 no-map; 453 }; 454 455 pil_cvp_mem: memory@85c00000 { 456 reg = <0x0 0x85c00000 0x0 0x500000>; 457 no-map; 458 }; 459 460 pil_adsp_mem: memory@86100000 { 461 reg = <0x0 0x86100000 0x0 0x2100000>; 462 no-map; 463 }; 464 465 pil_slpi_mem: memory@88200000 { 466 reg = <0x0 0x88200000 0x0 0x1500000>; 467 no-map; 468 }; 469 470 pil_cdsp_mem: memory@89700000 { 471 reg = <0x0 0x89700000 0x0 0x1e00000>; 472 no-map; 473 }; 474 475 pil_ipa_fw_mem: memory@8b500000 { 476 reg = <0x0 0x8b500000 0x0 0x10000>; 477 no-map; 478 }; 479 480 pil_ipa_gsi_mem: memory@8b510000 { 481 reg = <0x0 0x8b510000 0x0 0xa000>; 482 no-map; 483 }; 484 485 pil_gpu_mem: memory@8b51a000 { 486 reg = <0x0 0x8b51a000 0x0 0x2000>; 487 no-map; 488 }; 489 490 pil_spss_mem: memory@8b600000 { 491 reg = <0x0 0x8b600000 0x0 0x100000>; 492 no-map; 493 }; 494 495 pil_modem_mem: memory@8b800000 { 496 reg = <0x0 0x8b800000 0x0 0x10000000>; 497 no-map; 498 }; 499 500 rmtfs_mem: memory@9b800000 { 501 compatible = "qcom,rmtfs-mem"; 502 reg = <0x0 0x9b800000 0x0 0x280000>; 503 no-map; 504 505 qcom,client-id = <1>; 506 qcom,vmid = <15>; 507 }; 508 509 hyp_reserved_mem: memory@d0000000 { 510 reg = <0x0 0xd0000000 0x0 0x800000>; 511 no-map; 512 }; 513 514 pil_trustedvm_mem: memory@d0800000 { 515 reg = <0x0 0xd0800000 0x0 0x76f7000>; 516 no-map; 517 }; 518 519 qrtr_shbuf: memory@d7ef7000 { 520 reg = <0x0 0xd7ef7000 0x0 0x9000>; 521 no-map; 522 }; 523 524 chan0_shbuf: memory@d7f00000 { 525 reg = <0x0 0xd7f00000 0x0 0x80000>; 526 no-map; 527 }; 528 529 chan1_shbuf: memory@d7f80000 { 530 reg = <0x0 0xd7f80000 0x0 0x80000>; 531 no-map; 532 }; 533 534 removed_mem: memory@d8800000 { 535 reg = <0x0 0xd8800000 0x0 0x6800000>; 536 no-map; 537 }; 538 }; 539 540 smp2p-adsp { 541 compatible = "qcom,smp2p"; 542 qcom,smem = <443>, <429>; 543 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 544 IPCC_MPROC_SIGNAL_SMP2P 545 IRQ_TYPE_EDGE_RISING>; 546 mboxes = <&ipcc IPCC_CLIENT_LPASS 547 IPCC_MPROC_SIGNAL_SMP2P>; 548 549 qcom,local-pid = <0>; 550 qcom,remote-pid = <2>; 551 552 smp2p_adsp_out: master-kernel { 553 qcom,entry-name = "master-kernel"; 554 #qcom,smem-state-cells = <1>; 555 }; 556 557 smp2p_adsp_in: slave-kernel { 558 qcom,entry-name = "slave-kernel"; 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 }; 562 }; 563 564 smp2p-cdsp { 565 compatible = "qcom,smp2p"; 566 qcom,smem = <94>, <432>; 567 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 568 IPCC_MPROC_SIGNAL_SMP2P 569 IRQ_TYPE_EDGE_RISING>; 570 mboxes = <&ipcc IPCC_CLIENT_CDSP 571 IPCC_MPROC_SIGNAL_SMP2P>; 572 573 qcom,local-pid = <0>; 574 qcom,remote-pid = <5>; 575 576 smp2p_cdsp_out: master-kernel { 577 qcom,entry-name = "master-kernel"; 578 #qcom,smem-state-cells = <1>; 579 }; 580 581 smp2p_cdsp_in: slave-kernel { 582 qcom,entry-name = "slave-kernel"; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 }; 587 588 smp2p-modem { 589 compatible = "qcom,smp2p"; 590 qcom,smem = <435>, <428>; 591 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 592 IPCC_MPROC_SIGNAL_SMP2P 593 IRQ_TYPE_EDGE_RISING>; 594 mboxes = <&ipcc IPCC_CLIENT_MPSS 595 IPCC_MPROC_SIGNAL_SMP2P>; 596 597 qcom,local-pid = <0>; 598 qcom,remote-pid = <1>; 599 600 smp2p_modem_out: master-kernel { 601 qcom,entry-name = "master-kernel"; 602 #qcom,smem-state-cells = <1>; 603 }; 604 605 smp2p_modem_in: slave-kernel { 606 qcom,entry-name = "slave-kernel"; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 611 ipa_smp2p_out: ipa-ap-to-modem { 612 qcom,entry-name = "ipa"; 613 #qcom,smem-state-cells = <1>; 614 }; 615 616 ipa_smp2p_in: ipa-modem-to-ap { 617 qcom,entry-name = "ipa"; 618 interrupt-controller; 619 #interrupt-cells = <2>; 620 }; 621 }; 622 623 smp2p-slpi { 624 compatible = "qcom,smp2p"; 625 qcom,smem = <481>, <430>; 626 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 627 IPCC_MPROC_SIGNAL_SMP2P 628 IRQ_TYPE_EDGE_RISING>; 629 mboxes = <&ipcc IPCC_CLIENT_SLPI 630 IPCC_MPROC_SIGNAL_SMP2P>; 631 632 qcom,local-pid = <0>; 633 qcom,remote-pid = <3>; 634 635 smp2p_slpi_out: master-kernel { 636 qcom,entry-name = "master-kernel"; 637 #qcom,smem-state-cells = <1>; 638 }; 639 640 smp2p_slpi_in: slave-kernel { 641 qcom,entry-name = "slave-kernel"; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 }; 645 }; 646 647 soc: soc@0 { 648 #address-cells = <2>; 649 #size-cells = <2>; 650 ranges = <0 0 0 0 0x10 0>; 651 dma-ranges = <0 0 0 0 0x10 0>; 652 compatible = "simple-bus"; 653 654 gcc: clock-controller@100000 { 655 compatible = "qcom,gcc-sm8350"; 656 reg = <0x0 0x00100000 0x0 0x1f0000>; 657 #clock-cells = <1>; 658 #reset-cells = <1>; 659 #power-domain-cells = <1>; 660 clock-names = "bi_tcxo", 661 "sleep_clk", 662 "pcie_0_pipe_clk", 663 "pcie_1_pipe_clk", 664 "ufs_card_rx_symbol_0_clk", 665 "ufs_card_rx_symbol_1_clk", 666 "ufs_card_tx_symbol_0_clk", 667 "ufs_phy_rx_symbol_0_clk", 668 "ufs_phy_rx_symbol_1_clk", 669 "ufs_phy_tx_symbol_0_clk", 670 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 671 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 672 clocks = <&rpmhcc RPMH_CXO_CLK>, 673 <&sleep_clk>, 674 <&pcie0_phy>, 675 <&pcie1_phy>, 676 <0>, 677 <0>, 678 <0>, 679 <&ufs_mem_phy_lanes 0>, 680 <&ufs_mem_phy_lanes 1>, 681 <&ufs_mem_phy_lanes 2>, 682 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 683 <0>; 684 }; 685 686 ipcc: mailbox@408000 { 687 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 688 reg = <0 0x00408000 0 0x1000>; 689 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-controller; 691 #interrupt-cells = <3>; 692 #mbox-cells = <2>; 693 }; 694 695 gpi_dma2: dma-controller@800000 { 696 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 697 reg = <0 0x00800000 0 0x60000>; 698 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 710 dma-channels = <12>; 711 dma-channel-mask = <0xff>; 712 iommus = <&apps_smmu 0x5f6 0x0>; 713 #dma-cells = <3>; 714 status = "disabled"; 715 }; 716 717 qupv3_id_2: geniqup@8c0000 { 718 compatible = "qcom,geni-se-qup"; 719 reg = <0x0 0x008c0000 0x0 0x6000>; 720 clock-names = "m-ahb", "s-ahb"; 721 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 722 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 723 iommus = <&apps_smmu 0x5e3 0x0>; 724 #address-cells = <2>; 725 #size-cells = <2>; 726 ranges; 727 status = "disabled"; 728 729 i2c14: i2c@880000 { 730 compatible = "qcom,geni-i2c"; 731 reg = <0 0x00880000 0 0x4000>; 732 clock-names = "se"; 733 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&qup_i2c14_default>; 736 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 737 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 738 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 739 dma-names = "tx", "rx"; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 status = "disabled"; 743 }; 744 745 spi14: spi@880000 { 746 compatible = "qcom,geni-spi"; 747 reg = <0 0x00880000 0 0x4000>; 748 clock-names = "se"; 749 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 750 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 751 power-domains = <&rpmhpd RPMHPD_CX>; 752 operating-points-v2 = <&qup_opp_table_120mhz>; 753 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 754 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 755 dma-names = "tx", "rx"; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 i2c15: i2c@884000 { 762 compatible = "qcom,geni-i2c"; 763 reg = <0 0x00884000 0 0x4000>; 764 clock-names = "se"; 765 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&qup_i2c15_default>; 768 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 769 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 770 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 771 dma-names = "tx", "rx"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 spi15: spi@884000 { 778 compatible = "qcom,geni-spi"; 779 reg = <0 0x00884000 0 0x4000>; 780 clock-names = "se"; 781 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 782 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 783 power-domains = <&rpmhpd RPMHPD_CX>; 784 operating-points-v2 = <&qup_opp_table_120mhz>; 785 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 786 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 787 dma-names = "tx", "rx"; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 i2c16: i2c@888000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0 0x00888000 0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_i2c16_default>; 800 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 801 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 802 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 803 dma-names = "tx", "rx"; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 spi16: spi@888000 { 810 compatible = "qcom,geni-spi"; 811 reg = <0 0x00888000 0 0x4000>; 812 clock-names = "se"; 813 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 814 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 815 power-domains = <&rpmhpd RPMHPD_CX>; 816 operating-points-v2 = <&qup_opp_table_100mhz>; 817 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 818 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 819 dma-names = "tx", "rx"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 i2c17: i2c@88c000 { 826 compatible = "qcom,geni-i2c"; 827 reg = <0 0x0088c000 0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&qup_i2c17_default>; 832 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 833 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 834 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 835 dma-names = "tx", "rx"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 spi17: spi@88c000 { 842 compatible = "qcom,geni-spi"; 843 reg = <0 0x0088c000 0 0x4000>; 844 clock-names = "se"; 845 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 846 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 847 power-domains = <&rpmhpd RPMHPD_CX>; 848 operating-points-v2 = <&qup_opp_table_100mhz>; 849 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 850 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 851 dma-names = "tx", "rx"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 status = "disabled"; 855 }; 856 857 /* QUP no. 18 seems to be strictly SPI/UART-only */ 858 859 spi18: spi@890000 { 860 compatible = "qcom,geni-spi"; 861 reg = <0 0x00890000 0 0x4000>; 862 clock-names = "se"; 863 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 864 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 865 power-domains = <&rpmhpd RPMHPD_CX>; 866 operating-points-v2 = <&qup_opp_table_100mhz>; 867 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 868 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 869 dma-names = "tx", "rx"; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 status = "disabled"; 873 }; 874 875 uart18: serial@890000 { 876 compatible = "qcom,geni-uart"; 877 reg = <0 0x00890000 0 0x4000>; 878 clock-names = "se"; 879 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&qup_uart18_default>; 882 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 883 power-domains = <&rpmhpd RPMHPD_CX>; 884 operating-points-v2 = <&qup_opp_table_100mhz>; 885 status = "disabled"; 886 }; 887 888 i2c19: i2c@894000 { 889 compatible = "qcom,geni-i2c"; 890 reg = <0 0x00894000 0 0x4000>; 891 clock-names = "se"; 892 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&qup_i2c19_default>; 895 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 896 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 897 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 898 dma-names = "tx", "rx"; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 status = "disabled"; 902 }; 903 904 spi19: spi@894000 { 905 compatible = "qcom,geni-spi"; 906 reg = <0 0x00894000 0 0x4000>; 907 clock-names = "se"; 908 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 909 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 910 power-domains = <&rpmhpd RPMHPD_CX>; 911 operating-points-v2 = <&qup_opp_table_100mhz>; 912 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 913 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 914 dma-names = "tx", "rx"; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 }; 920 921 gpi_dma0: dma-controller@9800000 { 922 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 923 reg = <0 0x09800000 0 0x60000>; 924 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 936 dma-channels = <12>; 937 dma-channel-mask = <0x7e>; 938 iommus = <&apps_smmu 0x5b6 0x0>; 939 #dma-cells = <3>; 940 status = "disabled"; 941 }; 942 943 qupv3_id_0: geniqup@9c0000 { 944 compatible = "qcom,geni-se-qup"; 945 reg = <0x0 0x009c0000 0x0 0x6000>; 946 clock-names = "m-ahb", "s-ahb"; 947 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 948 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 949 iommus = <&apps_smmu 0x5a3 0>; 950 #address-cells = <2>; 951 #size-cells = <2>; 952 ranges; 953 status = "disabled"; 954 955 i2c0: i2c@980000 { 956 compatible = "qcom,geni-i2c"; 957 reg = <0 0x00980000 0 0x4000>; 958 clock-names = "se"; 959 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_i2c0_default>; 962 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 963 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 964 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 965 dma-names = "tx", "rx"; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970 971 spi0: spi@980000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0 0x00980000 0 0x4000>; 974 clock-names = "se"; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 976 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 977 power-domains = <&rpmhpd RPMHPD_CX>; 978 operating-points-v2 = <&qup_opp_table_100mhz>; 979 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 980 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 981 dma-names = "tx", "rx"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c1: i2c@984000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00984000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c1_default>; 994 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 995 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 996 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 spi1: spi@984000 { 1004 compatible = "qcom,geni-spi"; 1005 reg = <0 0x00984000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1008 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1009 power-domains = <&rpmhpd RPMHPD_CX>; 1010 operating-points-v2 = <&qup_opp_table_100mhz>; 1011 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1012 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1013 dma-names = "tx", "rx"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c2: i2c@988000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00988000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_i2c2_default>; 1026 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1027 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1028 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 spi2: spi@988000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x00988000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1040 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1041 power-domains = <&rpmhpd RPMHPD_CX>; 1042 operating-points-v2 = <&qup_opp_table_100mhz>; 1043 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1044 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1045 dma-names = "tx", "rx"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 uart2: serial@98c000 { 1052 compatible = "qcom,geni-debug-uart"; 1053 reg = <0 0x0098c000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_uart3_default_state>; 1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1059 power-domains = <&rpmhpd RPMHPD_CX>; 1060 operating-points-v2 = <&qup_opp_table_100mhz>; 1061 status = "disabled"; 1062 }; 1063 1064 /* QUP no. 3 seems to be strictly SPI-only */ 1065 1066 spi3: spi@98c000 { 1067 compatible = "qcom,geni-spi"; 1068 reg = <0 0x0098c000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1071 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 operating-points-v2 = <&qup_opp_table_100mhz>; 1074 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1075 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1076 dma-names = "tx", "rx"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 i2c4: i2c@990000 { 1083 compatible = "qcom,geni-i2c"; 1084 reg = <0 0x00990000 0 0x4000>; 1085 clock-names = "se"; 1086 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_i2c4_default>; 1089 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1090 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1091 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 spi4: spi@990000 { 1099 compatible = "qcom,geni-spi"; 1100 reg = <0 0x00990000 0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1103 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmhpd RPMHPD_CX>; 1105 operating-points-v2 = <&qup_opp_table_100mhz>; 1106 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1107 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1108 dma-names = "tx", "rx"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 i2c5: i2c@994000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0 0x00994000 0 0x4000>; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&qup_i2c5_default>; 1121 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1122 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1123 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1124 dma-names = "tx", "rx"; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 spi5: spi@994000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00994000 0 0x4000>; 1133 clock-names = "se"; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1135 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1136 power-domains = <&rpmhpd RPMHPD_CX>; 1137 operating-points-v2 = <&qup_opp_table_100mhz>; 1138 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1139 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1140 dma-names = "tx", "rx"; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 1146 i2c6: i2c@998000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x00998000 0 0x4000>; 1149 clock-names = "se"; 1150 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_i2c6_default>; 1153 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1154 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1155 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 spi6: spi@998000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00998000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1167 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1168 power-domains = <&rpmhpd RPMHPD_CX>; 1169 operating-points-v2 = <&qup_opp_table_100mhz>; 1170 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1171 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1172 dma-names = "tx", "rx"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 uart6: serial@998000 { 1179 compatible = "qcom,geni-uart"; 1180 reg = <0 0x00998000 0 0x4000>; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_uart6_default>; 1185 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1186 power-domains = <&rpmhpd RPMHPD_CX>; 1187 operating-points-v2 = <&qup_opp_table_100mhz>; 1188 status = "disabled"; 1189 }; 1190 1191 i2c7: i2c@99c000 { 1192 compatible = "qcom,geni-i2c"; 1193 reg = <0 0x0099c000 0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_i2c7_default>; 1198 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1199 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1200 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1201 dma-names = "tx", "rx"; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 status = "disabled"; 1205 }; 1206 1207 spi7: spi@99c000 { 1208 compatible = "qcom,geni-spi"; 1209 reg = <0 0x0099c000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1212 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1213 power-domains = <&rpmhpd RPMHPD_CX>; 1214 operating-points-v2 = <&qup_opp_table_100mhz>; 1215 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1216 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1217 dma-names = "tx", "rx"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 }; 1223 1224 gpi_dma1: dma-controller@a00000 { 1225 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1226 reg = <0 0x00a00000 0 0x60000>; 1227 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1239 dma-channels = <12>; 1240 dma-channel-mask = <0xff>; 1241 iommus = <&apps_smmu 0x56 0x0>; 1242 #dma-cells = <3>; 1243 status = "disabled"; 1244 }; 1245 1246 qupv3_id_1: geniqup@ac0000 { 1247 compatible = "qcom,geni-se-qup"; 1248 reg = <0x0 0x00ac0000 0x0 0x6000>; 1249 clock-names = "m-ahb", "s-ahb"; 1250 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1251 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1252 iommus = <&apps_smmu 0x43 0>; 1253 #address-cells = <2>; 1254 #size-cells = <2>; 1255 ranges; 1256 status = "disabled"; 1257 1258 i2c8: i2c@a80000 { 1259 compatible = "qcom,geni-i2c"; 1260 reg = <0 0x00a80000 0 0x4000>; 1261 clock-names = "se"; 1262 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&qup_i2c8_default>; 1265 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1266 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1267 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1268 dma-names = "tx", "rx"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 spi8: spi@a80000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0 0x00a80000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1279 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1280 power-domains = <&rpmhpd RPMHPD_CX>; 1281 operating-points-v2 = <&qup_opp_table_120mhz>; 1282 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1283 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1284 dma-names = "tx", "rx"; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 i2c9: i2c@a84000 { 1291 compatible = "qcom,geni-i2c"; 1292 reg = <0 0x00a84000 0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&qup_i2c9_default>; 1297 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1299 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1300 dma-names = "tx", "rx"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 spi9: spi@a84000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0 0x00a84000 0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1311 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1312 power-domains = <&rpmhpd RPMHPD_CX>; 1313 operating-points-v2 = <&qup_opp_table_100mhz>; 1314 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1315 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1316 dma-names = "tx", "rx"; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 status = "disabled"; 1320 }; 1321 1322 i2c10: i2c@a88000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0 0x00a88000 0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c10_default>; 1329 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1330 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1331 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1332 dma-names = "tx", "rx"; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 status = "disabled"; 1336 }; 1337 1338 spi10: spi@a88000 { 1339 compatible = "qcom,geni-spi"; 1340 reg = <0 0x00a88000 0 0x4000>; 1341 clock-names = "se"; 1342 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1343 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd RPMHPD_CX>; 1345 operating-points-v2 = <&qup_opp_table_100mhz>; 1346 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1347 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1348 dma-names = "tx", "rx"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 status = "disabled"; 1352 }; 1353 1354 i2c11: i2c@a8c000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00a8c000 0 0x4000>; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_i2c11_default>; 1361 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1362 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1363 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1364 dma-names = "tx", "rx"; 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 status = "disabled"; 1368 }; 1369 1370 spi11: spi@a8c000 { 1371 compatible = "qcom,geni-spi"; 1372 reg = <0 0x00a8c000 0 0x4000>; 1373 clock-names = "se"; 1374 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1375 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1376 power-domains = <&rpmhpd RPMHPD_CX>; 1377 operating-points-v2 = <&qup_opp_table_100mhz>; 1378 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1379 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1380 dma-names = "tx", "rx"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 i2c12: i2c@a90000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x00a90000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c12_default>; 1393 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1394 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1395 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1396 dma-names = "tx", "rx"; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 1402 spi12: spi@a90000 { 1403 compatible = "qcom,geni-spi"; 1404 reg = <0 0x00a90000 0 0x4000>; 1405 clock-names = "se"; 1406 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1407 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1408 power-domains = <&rpmhpd RPMHPD_CX>; 1409 operating-points-v2 = <&qup_opp_table_100mhz>; 1410 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1411 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1412 dma-names = "tx", "rx"; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 i2c13: i2c@a94000 { 1419 compatible = "qcom,geni-i2c"; 1420 reg = <0 0x00a94000 0 0x4000>; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_i2c13_default>; 1425 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1426 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1427 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1428 dma-names = "tx", "rx"; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 status = "disabled"; 1432 }; 1433 1434 spi13: spi@a94000 { 1435 compatible = "qcom,geni-spi"; 1436 reg = <0 0x00a94000 0 0x4000>; 1437 clock-names = "se"; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1439 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd RPMHPD_CX>; 1441 operating-points-v2 = <&qup_opp_table_100mhz>; 1442 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1443 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1444 dma-names = "tx", "rx"; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 status = "disabled"; 1448 }; 1449 }; 1450 1451 rng: rng@10d3000 { 1452 compatible = "qcom,prng-ee"; 1453 reg = <0 0x010d3000 0 0x1000>; 1454 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1455 clock-names = "core"; 1456 }; 1457 1458 config_noc: interconnect@1500000 { 1459 compatible = "qcom,sm8350-config-noc"; 1460 reg = <0 0x01500000 0 0xa580>; 1461 #interconnect-cells = <2>; 1462 qcom,bcm-voters = <&apps_bcm_voter>; 1463 }; 1464 1465 mc_virt: interconnect@1580000 { 1466 compatible = "qcom,sm8350-mc-virt"; 1467 reg = <0 0x01580000 0 0x1000>; 1468 #interconnect-cells = <2>; 1469 qcom,bcm-voters = <&apps_bcm_voter>; 1470 }; 1471 1472 system_noc: interconnect@1680000 { 1473 compatible = "qcom,sm8350-system-noc"; 1474 reg = <0 0x01680000 0 0x1c200>; 1475 #interconnect-cells = <2>; 1476 qcom,bcm-voters = <&apps_bcm_voter>; 1477 }; 1478 1479 aggre1_noc: interconnect@16e0000 { 1480 compatible = "qcom,sm8350-aggre1-noc"; 1481 reg = <0 0x016e0000 0 0x1f180>; 1482 #interconnect-cells = <2>; 1483 qcom,bcm-voters = <&apps_bcm_voter>; 1484 }; 1485 1486 aggre2_noc: interconnect@1700000 { 1487 compatible = "qcom,sm8350-aggre2-noc"; 1488 reg = <0 0x01700000 0 0x33000>; 1489 #interconnect-cells = <2>; 1490 qcom,bcm-voters = <&apps_bcm_voter>; 1491 }; 1492 1493 mmss_noc: interconnect@1740000 { 1494 compatible = "qcom,sm8350-mmss-noc"; 1495 reg = <0 0x01740000 0 0x1f080>; 1496 #interconnect-cells = <2>; 1497 qcom,bcm-voters = <&apps_bcm_voter>; 1498 }; 1499 1500 pcie0: pci@1c00000 { 1501 compatible = "qcom,pcie-sm8350"; 1502 reg = <0 0x01c00000 0 0x3000>, 1503 <0 0x60000000 0 0xf1d>, 1504 <0 0x60000f20 0 0xa8>, 1505 <0 0x60001000 0 0x1000>, 1506 <0 0x60100000 0 0x100000>; 1507 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1508 device_type = "pci"; 1509 linux,pci-domain = <0>; 1510 bus-range = <0x00 0xff>; 1511 num-lanes = <1>; 1512 1513 #address-cells = <3>; 1514 #size-cells = <2>; 1515 1516 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1517 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1518 1519 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1527 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1528 "msi4", "msi5", "msi6", "msi7"; 1529 #interrupt-cells = <1>; 1530 interrupt-map-mask = <0 0 0 0x7>; 1531 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1532 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1533 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1534 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1535 1536 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1537 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1538 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1539 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1540 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1541 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1542 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1543 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1544 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1545 clock-names = "aux", 1546 "cfg", 1547 "bus_master", 1548 "bus_slave", 1549 "slave_q2a", 1550 "tbu", 1551 "ddrss_sf_tbu", 1552 "aggre1", 1553 "aggre0"; 1554 1555 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1556 <0x100 &apps_smmu 0x1c01 0x1>; 1557 1558 resets = <&gcc GCC_PCIE_0_BCR>; 1559 reset-names = "pci"; 1560 1561 power-domains = <&gcc PCIE_0_GDSC>; 1562 1563 phys = <&pcie0_phy>; 1564 phy-names = "pciephy"; 1565 1566 status = "disabled"; 1567 }; 1568 1569 pcie0_phy: phy@1c06000 { 1570 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1571 reg = <0 0x01c06000 0 0x2000>; 1572 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1573 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1574 <&gcc GCC_PCIE_0_CLKREF_EN>, 1575 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1576 <&gcc GCC_PCIE_0_PIPE_CLK>; 1577 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1578 1579 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1580 reset-names = "phy"; 1581 1582 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1583 assigned-clock-rates = <100000000>; 1584 1585 #clock-cells = <0>; 1586 clock-output-names = "pcie_0_pipe_clk"; 1587 1588 #phy-cells = <0>; 1589 1590 status = "disabled"; 1591 }; 1592 1593 pcie1: pci@1c08000 { 1594 compatible = "qcom,pcie-sm8350"; 1595 reg = <0 0x01c08000 0 0x3000>, 1596 <0 0x40000000 0 0xf1d>, 1597 <0 0x40000f20 0 0xa8>, 1598 <0 0x40001000 0 0x1000>, 1599 <0 0x40100000 0 0x100000>; 1600 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1601 device_type = "pci"; 1602 linux,pci-domain = <1>; 1603 bus-range = <0x00 0xff>; 1604 num-lanes = <2>; 1605 1606 #address-cells = <3>; 1607 #size-cells = <2>; 1608 1609 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1610 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1611 1612 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1613 interrupt-names = "msi"; 1614 #interrupt-cells = <1>; 1615 interrupt-map-mask = <0 0 0 0x7>; 1616 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1617 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1618 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1619 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1620 1621 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1622 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1623 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1624 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1625 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1626 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1627 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1628 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1629 clock-names = "aux", 1630 "cfg", 1631 "bus_master", 1632 "bus_slave", 1633 "slave_q2a", 1634 "tbu", 1635 "ddrss_sf_tbu", 1636 "aggre1"; 1637 1638 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1639 <0x100 &apps_smmu 0x1c81 0x1>; 1640 1641 resets = <&gcc GCC_PCIE_1_BCR>; 1642 reset-names = "pci"; 1643 1644 power-domains = <&gcc PCIE_1_GDSC>; 1645 1646 phys = <&pcie1_phy>; 1647 phy-names = "pciephy"; 1648 1649 status = "disabled"; 1650 }; 1651 1652 pcie1_phy: phy@1c0e000 { 1653 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1654 reg = <0 0x01c0e000 0 0x2000>; 1655 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1656 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1657 <&gcc GCC_PCIE_1_CLKREF_EN>, 1658 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1659 <&gcc GCC_PCIE_1_PIPE_CLK>; 1660 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1661 1662 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1663 reset-names = "phy"; 1664 1665 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1666 assigned-clock-rates = <100000000>; 1667 1668 #clock-cells = <0>; 1669 clock-output-names = "pcie_1_pipe_clk"; 1670 1671 #phy-cells = <0>; 1672 1673 status = "disabled"; 1674 }; 1675 1676 ufs_mem_hc: ufshc@1d84000 { 1677 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1678 "jedec,ufs-2.0"; 1679 reg = <0 0x01d84000 0 0x3000>; 1680 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1681 phys = <&ufs_mem_phy_lanes>; 1682 phy-names = "ufsphy"; 1683 lanes-per-direction = <2>; 1684 #reset-cells = <1>; 1685 resets = <&gcc GCC_UFS_PHY_BCR>; 1686 reset-names = "rst"; 1687 1688 power-domains = <&gcc UFS_PHY_GDSC>; 1689 1690 iommus = <&apps_smmu 0xe0 0x0>; 1691 dma-coherent; 1692 1693 clock-names = 1694 "core_clk", 1695 "bus_aggr_clk", 1696 "iface_clk", 1697 "core_clk_unipro", 1698 "ref_clk", 1699 "tx_lane0_sync_clk", 1700 "rx_lane0_sync_clk", 1701 "rx_lane1_sync_clk"; 1702 clocks = 1703 <&gcc GCC_UFS_PHY_AXI_CLK>, 1704 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1705 <&gcc GCC_UFS_PHY_AHB_CLK>, 1706 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1707 <&rpmhcc RPMH_CXO_CLK>, 1708 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1709 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1710 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1711 freq-table-hz = 1712 <75000000 300000000>, 1713 <0 0>, 1714 <0 0>, 1715 <75000000 300000000>, 1716 <0 0>, 1717 <0 0>, 1718 <0 0>, 1719 <0 0>; 1720 status = "disabled"; 1721 }; 1722 1723 ufs_mem_phy: phy@1d87000 { 1724 compatible = "qcom,sm8350-qmp-ufs-phy"; 1725 reg = <0 0x01d87000 0 0x1c4>; 1726 #address-cells = <2>; 1727 #size-cells = <2>; 1728 ranges; 1729 clock-names = "ref", 1730 "ref_aux"; 1731 clocks = <&rpmhcc RPMH_CXO_CLK>, 1732 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1733 1734 resets = <&ufs_mem_hc 0>; 1735 reset-names = "ufsphy"; 1736 status = "disabled"; 1737 1738 ufs_mem_phy_lanes: phy@1d87400 { 1739 reg = <0 0x01d87400 0 0x188>, 1740 <0 0x01d87600 0 0x200>, 1741 <0 0x01d87c00 0 0x200>, 1742 <0 0x01d87800 0 0x188>, 1743 <0 0x01d87a00 0 0x200>; 1744 #clock-cells = <1>; 1745 #phy-cells = <0>; 1746 }; 1747 }; 1748 1749 cryptobam: dma-controller@1dc4000 { 1750 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1751 reg = <0 0x01dc4000 0 0x24000>; 1752 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1753 #dma-cells = <1>; 1754 qcom,ee = <0>; 1755 qcom,controlled-remotely; 1756 iommus = <&apps_smmu 0x594 0x0011>, 1757 <&apps_smmu 0x596 0x0011>; 1758 }; 1759 1760 crypto: crypto@1dfa000 { 1761 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1762 reg = <0 0x01dfa000 0 0x6000>; 1763 dmas = <&cryptobam 4>, <&cryptobam 5>; 1764 dma-names = "rx", "tx"; 1765 iommus = <&apps_smmu 0x594 0x0011>, 1766 <&apps_smmu 0x596 0x0011>; 1767 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1768 interconnect-names = "memory"; 1769 }; 1770 1771 ipa: ipa@1e40000 { 1772 compatible = "qcom,sm8350-ipa"; 1773 1774 iommus = <&apps_smmu 0x5c0 0x0>, 1775 <&apps_smmu 0x5c2 0x0>; 1776 reg = <0 0x01e40000 0 0x8000>, 1777 <0 0x01e50000 0 0x4b20>, 1778 <0 0x01e04000 0 0x23000>; 1779 reg-names = "ipa-reg", 1780 "ipa-shared", 1781 "gsi"; 1782 1783 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1784 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1785 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1786 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1787 interrupt-names = "ipa", 1788 "gsi", 1789 "ipa-clock-query", 1790 "ipa-setup-ready"; 1791 1792 clocks = <&rpmhcc RPMH_IPA_CLK>; 1793 clock-names = "core"; 1794 1795 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1796 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1797 interconnect-names = "memory", 1798 "config"; 1799 1800 qcom,qmp = <&aoss_qmp>; 1801 1802 qcom,smem-states = <&ipa_smp2p_out 0>, 1803 <&ipa_smp2p_out 1>; 1804 qcom,smem-state-names = "ipa-clock-enabled-valid", 1805 "ipa-clock-enabled"; 1806 1807 status = "disabled"; 1808 }; 1809 1810 tcsr_mutex: hwlock@1f40000 { 1811 compatible = "qcom,tcsr-mutex"; 1812 reg = <0x0 0x01f40000 0x0 0x40000>; 1813 #hwlock-cells = <1>; 1814 }; 1815 1816 lpass_tlmm: pinctrl@33c0000 { 1817 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1818 reg = <0 0x033c0000 0 0x20000>, 1819 <0 0x03550000 0 0x10000>; 1820 1821 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1822 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1823 clock-names = "core", "audio"; 1824 1825 gpio-controller; 1826 #gpio-cells = <2>; 1827 gpio-ranges = <&lpass_tlmm 0 0 15>; 1828 }; 1829 1830 gpu: gpu@3d00000 { 1831 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1832 1833 reg = <0 0x03d00000 0 0x40000>, 1834 <0 0x03d9e000 0 0x1000>, 1835 <0 0x03d61000 0 0x800>; 1836 reg-names = "kgsl_3d0_reg_memory", 1837 "cx_mem", 1838 "cx_dbgc"; 1839 1840 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1841 1842 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1843 1844 operating-points-v2 = <&gpu_opp_table>; 1845 1846 qcom,gmu = <&gmu>; 1847 1848 status = "disabled"; 1849 1850 zap-shader { 1851 memory-region = <&pil_gpu_mem>; 1852 }; 1853 1854 /* note: downstream checks gpu binning for 670 Mhz */ 1855 gpu_opp_table: opp-table { 1856 compatible = "operating-points-v2"; 1857 1858 opp-840000000 { 1859 opp-hz = /bits/ 64 <840000000>; 1860 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1861 }; 1862 1863 opp-778000000 { 1864 opp-hz = /bits/ 64 <778000000>; 1865 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1866 }; 1867 1868 opp-738000000 { 1869 opp-hz = /bits/ 64 <738000000>; 1870 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1871 }; 1872 1873 opp-676000000 { 1874 opp-hz = /bits/ 64 <676000000>; 1875 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1876 }; 1877 1878 opp-608000000 { 1879 opp-hz = /bits/ 64 <608000000>; 1880 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1881 }; 1882 1883 opp-540000000 { 1884 opp-hz = /bits/ 64 <540000000>; 1885 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1886 }; 1887 1888 opp-491000000 { 1889 opp-hz = /bits/ 64 <491000000>; 1890 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1891 }; 1892 1893 opp-443000000 { 1894 opp-hz = /bits/ 64 <443000000>; 1895 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1896 }; 1897 1898 opp-379000000 { 1899 opp-hz = /bits/ 64 <379000000>; 1900 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1901 }; 1902 1903 opp-315000000 { 1904 opp-hz = /bits/ 64 <315000000>; 1905 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1906 }; 1907 }; 1908 }; 1909 1910 gmu: gmu@3d6a000 { 1911 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1912 1913 reg = <0 0x03d6a000 0 0x34000>, 1914 <0 0x03de0000 0 0x10000>, 1915 <0 0x0b290000 0 0x10000>; 1916 reg-names = "gmu", "rscc", "gmu_pdc"; 1917 1918 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1920 interrupt-names = "hfi", "gmu"; 1921 1922 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1923 <&gpucc GPU_CC_CXO_CLK>, 1924 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1925 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1926 <&gpucc GPU_CC_AHB_CLK>, 1927 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1928 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1929 clock-names = "gmu", 1930 "cxo", 1931 "axi", 1932 "memnoc", 1933 "ahb", 1934 "hub", 1935 "smmu_vote"; 1936 1937 power-domains = <&gpucc GPU_CX_GDSC>, 1938 <&gpucc GPU_GX_GDSC>; 1939 power-domain-names = "cx", 1940 "gx"; 1941 1942 iommus = <&adreno_smmu 5 0x400>; 1943 1944 operating-points-v2 = <&gmu_opp_table>; 1945 1946 gmu_opp_table: opp-table { 1947 compatible = "operating-points-v2"; 1948 1949 opp-200000000 { 1950 opp-hz = /bits/ 64 <200000000>; 1951 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1952 }; 1953 }; 1954 }; 1955 1956 gpucc: clock-controller@3d90000 { 1957 compatible = "qcom,sm8350-gpucc"; 1958 reg = <0 0x03d90000 0 0x9000>; 1959 clocks = <&rpmhcc RPMH_CXO_CLK>, 1960 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1961 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1962 clock-names = "bi_tcxo", 1963 "gcc_gpu_gpll0_clk_src", 1964 "gcc_gpu_gpll0_div_clk_src"; 1965 #clock-cells = <1>; 1966 #reset-cells = <1>; 1967 #power-domain-cells = <1>; 1968 }; 1969 1970 adreno_smmu: iommu@3da0000 { 1971 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1972 "qcom,smmu-500", "arm,mmu-500"; 1973 reg = <0 0x03da0000 0 0x20000>; 1974 #iommu-cells = <2>; 1975 #global-interrupts = <2>; 1976 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1988 1989 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1990 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1991 <&gpucc GPU_CC_AHB_CLK>, 1992 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1993 <&gpucc GPU_CC_CX_GMU_CLK>, 1994 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1995 <&gpucc GPU_CC_HUB_AON_CLK>; 1996 clock-names = "bus", 1997 "iface", 1998 "ahb", 1999 "hlos1_vote_gpu_smmu", 2000 "cx_gmu", 2001 "hub_cx_int", 2002 "hub_aon"; 2003 2004 power-domains = <&gpucc GPU_CX_GDSC>; 2005 dma-coherent; 2006 }; 2007 2008 lpass_ag_noc: interconnect@3c40000 { 2009 compatible = "qcom,sm8350-lpass-ag-noc"; 2010 reg = <0 0x03c40000 0 0xf080>; 2011 #interconnect-cells = <2>; 2012 qcom,bcm-voters = <&apps_bcm_voter>; 2013 }; 2014 2015 mpss: remoteproc@4080000 { 2016 compatible = "qcom,sm8350-mpss-pas"; 2017 reg = <0x0 0x04080000 0x0 0x4040>; 2018 2019 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2020 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2021 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2022 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2023 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2024 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2025 interrupt-names = "wdog", "fatal", "ready", "handover", 2026 "stop-ack", "shutdown-ack"; 2027 2028 clocks = <&rpmhcc RPMH_CXO_CLK>; 2029 clock-names = "xo"; 2030 2031 power-domains = <&rpmhpd RPMHPD_CX>, 2032 <&rpmhpd RPMHPD_MSS>; 2033 power-domain-names = "cx", "mss"; 2034 2035 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2036 2037 memory-region = <&pil_modem_mem>; 2038 2039 qcom,qmp = <&aoss_qmp>; 2040 2041 qcom,smem-states = <&smp2p_modem_out 0>; 2042 qcom,smem-state-names = "stop"; 2043 2044 status = "disabled"; 2045 2046 glink-edge { 2047 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2048 IPCC_MPROC_SIGNAL_GLINK_QMP 2049 IRQ_TYPE_EDGE_RISING>; 2050 mboxes = <&ipcc IPCC_CLIENT_MPSS 2051 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2052 label = "modem"; 2053 qcom,remote-pid = <1>; 2054 }; 2055 }; 2056 2057 slpi: remoteproc@5c00000 { 2058 compatible = "qcom,sm8350-slpi-pas"; 2059 reg = <0 0x05c00000 0 0x4000>; 2060 2061 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2062 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2063 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2064 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2065 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2066 interrupt-names = "wdog", "fatal", "ready", 2067 "handover", "stop-ack"; 2068 2069 clocks = <&rpmhcc RPMH_CXO_CLK>; 2070 clock-names = "xo"; 2071 2072 power-domains = <&rpmhpd RPMHPD_LCX>, 2073 <&rpmhpd RPMHPD_LMX>; 2074 power-domain-names = "lcx", "lmx"; 2075 2076 memory-region = <&pil_slpi_mem>; 2077 2078 qcom,qmp = <&aoss_qmp>; 2079 2080 qcom,smem-states = <&smp2p_slpi_out 0>; 2081 qcom,smem-state-names = "stop"; 2082 2083 status = "disabled"; 2084 2085 glink-edge { 2086 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2087 IPCC_MPROC_SIGNAL_GLINK_QMP 2088 IRQ_TYPE_EDGE_RISING>; 2089 mboxes = <&ipcc IPCC_CLIENT_SLPI 2090 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2091 2092 label = "slpi"; 2093 qcom,remote-pid = <3>; 2094 2095 fastrpc { 2096 compatible = "qcom,fastrpc"; 2097 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2098 label = "sdsp"; 2099 qcom,non-secure-domain; 2100 #address-cells = <1>; 2101 #size-cells = <0>; 2102 2103 compute-cb@1 { 2104 compatible = "qcom,fastrpc-compute-cb"; 2105 reg = <1>; 2106 iommus = <&apps_smmu 0x0541 0x0>; 2107 }; 2108 2109 compute-cb@2 { 2110 compatible = "qcom,fastrpc-compute-cb"; 2111 reg = <2>; 2112 iommus = <&apps_smmu 0x0542 0x0>; 2113 }; 2114 2115 compute-cb@3 { 2116 compatible = "qcom,fastrpc-compute-cb"; 2117 reg = <3>; 2118 iommus = <&apps_smmu 0x0543 0x0>; 2119 /* note: shared-cb = <4> in downstream */ 2120 }; 2121 }; 2122 }; 2123 }; 2124 2125 sdhc_2: mmc@8804000 { 2126 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2127 reg = <0 0x08804000 0 0x1000>; 2128 2129 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2131 interrupt-names = "hc_irq", "pwr_irq"; 2132 2133 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2134 <&gcc GCC_SDCC2_APPS_CLK>, 2135 <&rpmhcc RPMH_CXO_CLK>; 2136 clock-names = "iface", "core", "xo"; 2137 resets = <&gcc GCC_SDCC2_BCR>; 2138 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2139 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2140 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2141 iommus = <&apps_smmu 0x4a0 0x0>; 2142 power-domains = <&rpmhpd RPMHPD_CX>; 2143 operating-points-v2 = <&sdhc2_opp_table>; 2144 bus-width = <4>; 2145 dma-coherent; 2146 2147 status = "disabled"; 2148 2149 sdhc2_opp_table: opp-table { 2150 compatible = "operating-points-v2"; 2151 2152 opp-100000000 { 2153 opp-hz = /bits/ 64 <100000000>; 2154 required-opps = <&rpmhpd_opp_low_svs>; 2155 }; 2156 2157 opp-202000000 { 2158 opp-hz = /bits/ 64 <202000000>; 2159 required-opps = <&rpmhpd_opp_svs_l1>; 2160 }; 2161 }; 2162 }; 2163 2164 usb_1_hsphy: phy@88e3000 { 2165 compatible = "qcom,sm8350-usb-hs-phy", 2166 "qcom,usb-snps-hs-7nm-phy"; 2167 reg = <0 0x088e3000 0 0x400>; 2168 status = "disabled"; 2169 #phy-cells = <0>; 2170 2171 clocks = <&rpmhcc RPMH_CXO_CLK>; 2172 clock-names = "ref"; 2173 2174 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2175 }; 2176 2177 usb_2_hsphy: phy@88e4000 { 2178 compatible = "qcom,sm8250-usb-hs-phy", 2179 "qcom,usb-snps-hs-7nm-phy"; 2180 reg = <0 0x088e4000 0 0x400>; 2181 status = "disabled"; 2182 #phy-cells = <0>; 2183 2184 clocks = <&rpmhcc RPMH_CXO_CLK>; 2185 clock-names = "ref"; 2186 2187 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2188 }; 2189 2190 usb_1_qmpphy: phy@88e8000 { 2191 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2192 reg = <0 0x088e8000 0 0x3000>; 2193 2194 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2195 <&rpmhcc RPMH_CXO_CLK>, 2196 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2197 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2198 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2199 2200 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2201 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2202 reset-names = "phy", "common"; 2203 2204 #clock-cells = <1>; 2205 #phy-cells = <1>; 2206 2207 status = "disabled"; 2208 2209 ports { 2210 #address-cells = <1>; 2211 #size-cells = <0>; 2212 2213 port@0 { 2214 reg = <0>; 2215 2216 usb_1_qmpphy_out: endpoint { 2217 }; 2218 }; 2219 2220 port@1 { 2221 reg = <1>; 2222 2223 usb_1_qmpphy_usb_ss_in: endpoint { 2224 }; 2225 }; 2226 2227 port@2 { 2228 reg = <2>; 2229 2230 usb_1_qmpphy_dp_in: endpoint { 2231 }; 2232 }; 2233 }; 2234 }; 2235 2236 usb_2_qmpphy: phy-wrapper@88eb000 { 2237 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2238 reg = <0 0x088eb000 0 0x200>; 2239 status = "disabled"; 2240 #address-cells = <2>; 2241 #size-cells = <2>; 2242 ranges; 2243 2244 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2245 <&rpmhcc RPMH_CXO_CLK>, 2246 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2247 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2248 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2249 2250 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2251 <&gcc GCC_USB3_PHY_SEC_BCR>; 2252 reset-names = "phy", "common"; 2253 2254 usb_2_ssphy: phy@88ebe00 { 2255 reg = <0 0x088ebe00 0 0x200>, 2256 <0 0x088ec000 0 0x200>, 2257 <0 0x088eb200 0 0x1100>; 2258 #phy-cells = <0>; 2259 #clock-cells = <0>; 2260 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2261 clock-names = "pipe0"; 2262 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2263 }; 2264 }; 2265 2266 dc_noc: interconnect@90c0000 { 2267 compatible = "qcom,sm8350-dc-noc"; 2268 reg = <0 0x090c0000 0 0x4200>; 2269 #interconnect-cells = <2>; 2270 qcom,bcm-voters = <&apps_bcm_voter>; 2271 }; 2272 2273 gem_noc: interconnect@9100000 { 2274 compatible = "qcom,sm8350-gem-noc"; 2275 reg = <0 0x09100000 0 0xb4000>; 2276 #interconnect-cells = <2>; 2277 qcom,bcm-voters = <&apps_bcm_voter>; 2278 }; 2279 2280 system-cache-controller@9200000 { 2281 compatible = "qcom,sm8350-llcc"; 2282 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2283 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2284 <0 0x09600000 0 0x58000>; 2285 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2286 "llcc3_base", "llcc_broadcast_base"; 2287 }; 2288 2289 compute_noc: interconnect@a0c0000 { 2290 compatible = "qcom,sm8350-compute-noc"; 2291 reg = <0 0x0a0c0000 0 0xa180>; 2292 #interconnect-cells = <2>; 2293 qcom,bcm-voters = <&apps_bcm_voter>; 2294 }; 2295 2296 usb_1: usb@a6f8800 { 2297 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2298 reg = <0 0x0a6f8800 0 0x400>; 2299 status = "disabled"; 2300 #address-cells = <2>; 2301 #size-cells = <2>; 2302 ranges; 2303 2304 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2305 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2306 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2307 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2308 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2309 clock-names = "cfg_noc", 2310 "core", 2311 "iface", 2312 "sleep", 2313 "mock_utmi"; 2314 2315 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2316 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2317 assigned-clock-rates = <19200000>, <200000000>; 2318 2319 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2320 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2321 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2322 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2323 interrupt-names = "hs_phy_irq", 2324 "ss_phy_irq", 2325 "dm_hs_phy_irq", 2326 "dp_hs_phy_irq"; 2327 2328 power-domains = <&gcc USB30_PRIM_GDSC>; 2329 2330 resets = <&gcc GCC_USB30_PRIM_BCR>; 2331 2332 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2333 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2334 interconnect-names = "usb-ddr", "apps-usb"; 2335 2336 usb_1_dwc3: usb@a600000 { 2337 compatible = "snps,dwc3"; 2338 reg = <0 0x0a600000 0 0xcd00>; 2339 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2340 iommus = <&apps_smmu 0x0 0x0>; 2341 snps,dis_u2_susphy_quirk; 2342 snps,dis_enblslpm_quirk; 2343 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2344 phy-names = "usb2-phy", "usb3-phy"; 2345 2346 ports { 2347 #address-cells = <1>; 2348 #size-cells = <0>; 2349 2350 port@0 { 2351 reg = <0>; 2352 2353 usb_1_dwc3_hs: endpoint { 2354 }; 2355 }; 2356 2357 port@1 { 2358 reg = <1>; 2359 2360 usb_1_dwc3_ss: endpoint { 2361 }; 2362 }; 2363 }; 2364 }; 2365 }; 2366 2367 usb_2: usb@a8f8800 { 2368 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2369 reg = <0 0x0a8f8800 0 0x400>; 2370 status = "disabled"; 2371 #address-cells = <2>; 2372 #size-cells = <2>; 2373 ranges; 2374 2375 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2376 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2377 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2378 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2379 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2380 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2381 clock-names = "cfg_noc", 2382 "core", 2383 "iface", 2384 "sleep", 2385 "mock_utmi", 2386 "xo"; 2387 2388 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2389 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2390 assigned-clock-rates = <19200000>, <200000000>; 2391 2392 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2393 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2394 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2395 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2396 interrupt-names = "hs_phy_irq", 2397 "ss_phy_irq", 2398 "dm_hs_phy_irq", 2399 "dp_hs_phy_irq"; 2400 2401 power-domains = <&gcc USB30_SEC_GDSC>; 2402 2403 resets = <&gcc GCC_USB30_SEC_BCR>; 2404 2405 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2406 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2407 interconnect-names = "usb-ddr", "apps-usb"; 2408 2409 usb_2_dwc3: usb@a800000 { 2410 compatible = "snps,dwc3"; 2411 reg = <0 0x0a800000 0 0xcd00>; 2412 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2413 iommus = <&apps_smmu 0x20 0x0>; 2414 snps,dis_u2_susphy_quirk; 2415 snps,dis_enblslpm_quirk; 2416 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2417 phy-names = "usb2-phy", "usb3-phy"; 2418 }; 2419 }; 2420 2421 mdss: display-subsystem@ae00000 { 2422 compatible = "qcom,sm8350-mdss"; 2423 reg = <0 0x0ae00000 0 0x1000>; 2424 reg-names = "mdss"; 2425 2426 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2427 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2428 interconnect-names = "mdp0-mem", "mdp1-mem"; 2429 2430 power-domains = <&dispcc MDSS_GDSC>; 2431 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2432 2433 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2434 <&gcc GCC_DISP_HF_AXI_CLK>, 2435 <&gcc GCC_DISP_SF_AXI_CLK>, 2436 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2437 clock-names = "iface", "bus", "nrt_bus", "core"; 2438 2439 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2440 interrupt-controller; 2441 #interrupt-cells = <1>; 2442 2443 iommus = <&apps_smmu 0x820 0x402>; 2444 2445 status = "disabled"; 2446 2447 #address-cells = <2>; 2448 #size-cells = <2>; 2449 ranges; 2450 2451 dpu_opp_table: opp-table { 2452 compatible = "operating-points-v2"; 2453 2454 /* TODO: opp-200000000 should work with 2455 * &rpmhpd_opp_low_svs, but one some of 2456 * sm8350_hdk boards reboot using this 2457 * opp. 2458 */ 2459 opp-200000000 { 2460 opp-hz = /bits/ 64 <200000000>; 2461 required-opps = <&rpmhpd_opp_svs>; 2462 }; 2463 2464 opp-300000000 { 2465 opp-hz = /bits/ 64 <300000000>; 2466 required-opps = <&rpmhpd_opp_svs>; 2467 }; 2468 2469 opp-345000000 { 2470 opp-hz = /bits/ 64 <345000000>; 2471 required-opps = <&rpmhpd_opp_svs_l1>; 2472 }; 2473 2474 opp-460000000 { 2475 opp-hz = /bits/ 64 <460000000>; 2476 required-opps = <&rpmhpd_opp_nom>; 2477 }; 2478 }; 2479 2480 mdss_mdp: display-controller@ae01000 { 2481 compatible = "qcom,sm8350-dpu"; 2482 reg = <0 0x0ae01000 0 0x8f000>, 2483 <0 0x0aeb0000 0 0x2008>; 2484 reg-names = "mdp", "vbif"; 2485 2486 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2487 <&gcc GCC_DISP_SF_AXI_CLK>, 2488 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2489 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2490 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2491 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2492 clock-names = "bus", 2493 "nrt_bus", 2494 "iface", 2495 "lut", 2496 "core", 2497 "vsync"; 2498 2499 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2500 assigned-clock-rates = <19200000>; 2501 2502 operating-points-v2 = <&dpu_opp_table>; 2503 power-domains = <&rpmhpd RPMHPD_MMCX>; 2504 2505 interrupt-parent = <&mdss>; 2506 interrupts = <0>; 2507 2508 ports { 2509 #address-cells = <1>; 2510 #size-cells = <0>; 2511 2512 port@0 { 2513 reg = <0>; 2514 dpu_intf1_out: endpoint { 2515 remote-endpoint = <&mdss_dsi0_in>; 2516 }; 2517 }; 2518 2519 port@1 { 2520 reg = <1>; 2521 dpu_intf2_out: endpoint { 2522 remote-endpoint = <&mdss_dsi1_in>; 2523 }; 2524 }; 2525 2526 port@2 { 2527 reg = <2>; 2528 dpu_intf0_out: endpoint { 2529 remote-endpoint = <&mdss_dp_in>; 2530 }; 2531 }; 2532 }; 2533 }; 2534 2535 mdss_dp: displayport-controller@ae90000 { 2536 compatible = "qcom,sm8350-dp"; 2537 reg = <0 0xae90000 0 0x200>, 2538 <0 0xae90200 0 0x200>, 2539 <0 0xae90400 0 0x600>, 2540 <0 0xae91000 0 0x400>, 2541 <0 0xae91400 0 0x400>; 2542 interrupt-parent = <&mdss>; 2543 interrupts = <12>; 2544 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2545 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2546 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2547 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2548 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2549 clock-names = "core_iface", 2550 "core_aux", 2551 "ctrl_link", 2552 "ctrl_link_iface", 2553 "stream_pixel"; 2554 2555 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2556 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2557 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2558 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2559 2560 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2561 phy-names = "dp"; 2562 2563 #sound-dai-cells = <0>; 2564 2565 operating-points-v2 = <&dp_opp_table>; 2566 power-domains = <&rpmhpd RPMHPD_MMCX>; 2567 2568 status = "disabled"; 2569 2570 ports { 2571 #address-cells = <1>; 2572 #size-cells = <0>; 2573 2574 port@0 { 2575 reg = <0>; 2576 mdss_dp_in: endpoint { 2577 remote-endpoint = <&dpu_intf0_out>; 2578 }; 2579 }; 2580 }; 2581 2582 dp_opp_table: opp-table { 2583 compatible = "operating-points-v2"; 2584 2585 opp-160000000 { 2586 opp-hz = /bits/ 64 <160000000>; 2587 required-opps = <&rpmhpd_opp_low_svs>; 2588 }; 2589 2590 opp-270000000 { 2591 opp-hz = /bits/ 64 <270000000>; 2592 required-opps = <&rpmhpd_opp_svs>; 2593 }; 2594 2595 opp-540000000 { 2596 opp-hz = /bits/ 64 <540000000>; 2597 required-opps = <&rpmhpd_opp_svs_l1>; 2598 }; 2599 2600 opp-810000000 { 2601 opp-hz = /bits/ 64 <810000000>; 2602 required-opps = <&rpmhpd_opp_nom>; 2603 }; 2604 }; 2605 }; 2606 2607 mdss_dsi0: dsi@ae94000 { 2608 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2609 reg = <0 0x0ae94000 0 0x400>; 2610 reg-names = "dsi_ctrl"; 2611 2612 interrupt-parent = <&mdss>; 2613 interrupts = <4>; 2614 2615 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2616 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2617 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2618 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2619 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2620 <&gcc GCC_DISP_HF_AXI_CLK>; 2621 clock-names = "byte", 2622 "byte_intf", 2623 "pixel", 2624 "core", 2625 "iface", 2626 "bus"; 2627 2628 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2629 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2630 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2631 <&mdss_dsi0_phy 1>; 2632 2633 operating-points-v2 = <&dsi0_opp_table>; 2634 power-domains = <&rpmhpd RPMHPD_MMCX>; 2635 2636 phys = <&mdss_dsi0_phy>; 2637 2638 #address-cells = <1>; 2639 #size-cells = <0>; 2640 2641 status = "disabled"; 2642 2643 dsi0_opp_table: opp-table { 2644 compatible = "operating-points-v2"; 2645 2646 /* TODO: opp-187500000 should work with 2647 * &rpmhpd_opp_low_svs, but one some of 2648 * sm8350_hdk boards reboot using this 2649 * opp. 2650 */ 2651 opp-187500000 { 2652 opp-hz = /bits/ 64 <187500000>; 2653 required-opps = <&rpmhpd_opp_svs>; 2654 }; 2655 2656 opp-300000000 { 2657 opp-hz = /bits/ 64 <300000000>; 2658 required-opps = <&rpmhpd_opp_svs>; 2659 }; 2660 2661 opp-358000000 { 2662 opp-hz = /bits/ 64 <358000000>; 2663 required-opps = <&rpmhpd_opp_svs_l1>; 2664 }; 2665 }; 2666 2667 ports { 2668 #address-cells = <1>; 2669 #size-cells = <0>; 2670 2671 port@0 { 2672 reg = <0>; 2673 mdss_dsi0_in: endpoint { 2674 remote-endpoint = <&dpu_intf1_out>; 2675 }; 2676 }; 2677 2678 port@1 { 2679 reg = <1>; 2680 mdss_dsi0_out: endpoint { 2681 }; 2682 }; 2683 }; 2684 }; 2685 2686 mdss_dsi0_phy: phy@ae94400 { 2687 compatible = "qcom,sm8350-dsi-phy-5nm"; 2688 reg = <0 0x0ae94400 0 0x200>, 2689 <0 0x0ae94600 0 0x280>, 2690 <0 0x0ae94900 0 0x27c>; 2691 reg-names = "dsi_phy", 2692 "dsi_phy_lane", 2693 "dsi_pll"; 2694 2695 #clock-cells = <1>; 2696 #phy-cells = <0>; 2697 2698 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2699 <&rpmhcc RPMH_CXO_CLK>; 2700 clock-names = "iface", "ref"; 2701 2702 status = "disabled"; 2703 }; 2704 2705 mdss_dsi1: dsi@ae96000 { 2706 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2707 reg = <0 0x0ae96000 0 0x400>; 2708 reg-names = "dsi_ctrl"; 2709 2710 interrupt-parent = <&mdss>; 2711 interrupts = <5>; 2712 2713 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2714 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2715 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2716 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2717 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2718 <&gcc GCC_DISP_HF_AXI_CLK>; 2719 clock-names = "byte", 2720 "byte_intf", 2721 "pixel", 2722 "core", 2723 "iface", 2724 "bus"; 2725 2726 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2727 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2728 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2729 <&mdss_dsi1_phy 1>; 2730 2731 operating-points-v2 = <&dsi1_opp_table>; 2732 power-domains = <&rpmhpd RPMHPD_MMCX>; 2733 2734 phys = <&mdss_dsi1_phy>; 2735 2736 #address-cells = <1>; 2737 #size-cells = <0>; 2738 2739 status = "disabled"; 2740 2741 dsi1_opp_table: opp-table { 2742 compatible = "operating-points-v2"; 2743 2744 /* TODO: opp-187500000 should work with 2745 * &rpmhpd_opp_low_svs, but one some of 2746 * sm8350_hdk boards reboot using this 2747 * opp. 2748 */ 2749 opp-187500000 { 2750 opp-hz = /bits/ 64 <187500000>; 2751 required-opps = <&rpmhpd_opp_svs>; 2752 }; 2753 2754 opp-300000000 { 2755 opp-hz = /bits/ 64 <300000000>; 2756 required-opps = <&rpmhpd_opp_svs>; 2757 }; 2758 2759 opp-358000000 { 2760 opp-hz = /bits/ 64 <358000000>; 2761 required-opps = <&rpmhpd_opp_svs_l1>; 2762 }; 2763 }; 2764 2765 ports { 2766 #address-cells = <1>; 2767 #size-cells = <0>; 2768 2769 port@0 { 2770 reg = <0>; 2771 mdss_dsi1_in: endpoint { 2772 remote-endpoint = <&dpu_intf2_out>; 2773 }; 2774 }; 2775 2776 port@1 { 2777 reg = <1>; 2778 mdss_dsi1_out: endpoint { 2779 }; 2780 }; 2781 }; 2782 }; 2783 2784 mdss_dsi1_phy: phy@ae96400 { 2785 compatible = "qcom,sm8350-dsi-phy-5nm"; 2786 reg = <0 0x0ae96400 0 0x200>, 2787 <0 0x0ae96600 0 0x280>, 2788 <0 0x0ae96900 0 0x27c>; 2789 reg-names = "dsi_phy", 2790 "dsi_phy_lane", 2791 "dsi_pll"; 2792 2793 #clock-cells = <1>; 2794 #phy-cells = <0>; 2795 2796 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2797 <&rpmhcc RPMH_CXO_CLK>; 2798 clock-names = "iface", "ref"; 2799 2800 status = "disabled"; 2801 }; 2802 }; 2803 2804 dispcc: clock-controller@af00000 { 2805 compatible = "qcom,sm8350-dispcc"; 2806 reg = <0 0x0af00000 0 0x10000>; 2807 clocks = <&rpmhcc RPMH_CXO_CLK>, 2808 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2809 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2810 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2811 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2812 clock-names = "bi_tcxo", 2813 "dsi0_phy_pll_out_byteclk", 2814 "dsi0_phy_pll_out_dsiclk", 2815 "dsi1_phy_pll_out_byteclk", 2816 "dsi1_phy_pll_out_dsiclk", 2817 "dp_phy_pll_link_clk", 2818 "dp_phy_pll_vco_div_clk"; 2819 #clock-cells = <1>; 2820 #reset-cells = <1>; 2821 #power-domain-cells = <1>; 2822 2823 power-domains = <&rpmhpd RPMHPD_MMCX>; 2824 }; 2825 2826 pdc: interrupt-controller@b220000 { 2827 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2828 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2829 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2830 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2831 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2832 <156 716 12>; 2833 #interrupt-cells = <2>; 2834 interrupt-parent = <&intc>; 2835 interrupt-controller; 2836 }; 2837 2838 tsens0: thermal-sensor@c263000 { 2839 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2840 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2841 <0 0x0c222000 0 0x8>; /* SROT */ 2842 #qcom,sensors = <15>; 2843 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2844 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2845 interrupt-names = "uplow", "critical"; 2846 #thermal-sensor-cells = <1>; 2847 }; 2848 2849 tsens1: thermal-sensor@c265000 { 2850 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2851 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2852 <0 0x0c223000 0 0x8>; /* SROT */ 2853 #qcom,sensors = <14>; 2854 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2855 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2856 interrupt-names = "uplow", "critical"; 2857 #thermal-sensor-cells = <1>; 2858 }; 2859 2860 aoss_qmp: power-management@c300000 { 2861 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2862 reg = <0 0x0c300000 0 0x400>; 2863 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2864 IRQ_TYPE_EDGE_RISING>; 2865 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2866 2867 #clock-cells = <0>; 2868 }; 2869 2870 sram@c3f0000 { 2871 compatible = "qcom,rpmh-stats"; 2872 reg = <0 0x0c3f0000 0 0x400>; 2873 }; 2874 2875 spmi_bus: spmi@c440000 { 2876 compatible = "qcom,spmi-pmic-arb"; 2877 reg = <0x0 0x0c440000 0x0 0x1100>, 2878 <0x0 0x0c600000 0x0 0x2000000>, 2879 <0x0 0x0e600000 0x0 0x100000>, 2880 <0x0 0x0e700000 0x0 0xa0000>, 2881 <0x0 0x0c40a000 0x0 0x26000>; 2882 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2883 interrupt-names = "periph_irq"; 2884 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2885 qcom,ee = <0>; 2886 qcom,channel = <0>; 2887 #address-cells = <2>; 2888 #size-cells = <0>; 2889 interrupt-controller; 2890 #interrupt-cells = <4>; 2891 }; 2892 2893 tlmm: pinctrl@f100000 { 2894 compatible = "qcom,sm8350-tlmm"; 2895 reg = <0 0x0f100000 0 0x300000>; 2896 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2897 gpio-controller; 2898 #gpio-cells = <2>; 2899 interrupt-controller; 2900 #interrupt-cells = <2>; 2901 gpio-ranges = <&tlmm 0 0 204>; 2902 wakeup-parent = <&pdc>; 2903 2904 sdc2_default_state: sdc2-default-state { 2905 clk-pins { 2906 pins = "sdc2_clk"; 2907 drive-strength = <16>; 2908 bias-disable; 2909 }; 2910 2911 cmd-pins { 2912 pins = "sdc2_cmd"; 2913 drive-strength = <16>; 2914 bias-pull-up; 2915 }; 2916 2917 data-pins { 2918 pins = "sdc2_data"; 2919 drive-strength = <16>; 2920 bias-pull-up; 2921 }; 2922 }; 2923 2924 sdc2_sleep_state: sdc2-sleep-state { 2925 clk-pins { 2926 pins = "sdc2_clk"; 2927 drive-strength = <2>; 2928 bias-disable; 2929 }; 2930 2931 cmd-pins { 2932 pins = "sdc2_cmd"; 2933 drive-strength = <2>; 2934 bias-pull-up; 2935 }; 2936 2937 data-pins { 2938 pins = "sdc2_data"; 2939 drive-strength = <2>; 2940 bias-pull-up; 2941 }; 2942 }; 2943 2944 qup_uart3_default_state: qup-uart3-default-state { 2945 rx-pins { 2946 pins = "gpio18"; 2947 function = "qup3"; 2948 }; 2949 tx-pins { 2950 pins = "gpio19"; 2951 function = "qup3"; 2952 }; 2953 }; 2954 2955 qup_uart6_default: qup-uart6-default-state { 2956 pins = "gpio30", "gpio31"; 2957 function = "qup6"; 2958 drive-strength = <2>; 2959 bias-disable; 2960 }; 2961 2962 qup_uart18_default: qup-uart18-default-state { 2963 pins = "gpio58", "gpio59"; 2964 function = "qup18"; 2965 drive-strength = <2>; 2966 bias-disable; 2967 }; 2968 2969 qup_i2c0_default: qup-i2c0-default-state { 2970 pins = "gpio4", "gpio5"; 2971 function = "qup0"; 2972 drive-strength = <2>; 2973 bias-pull-up; 2974 }; 2975 2976 qup_i2c1_default: qup-i2c1-default-state { 2977 pins = "gpio8", "gpio9"; 2978 function = "qup1"; 2979 drive-strength = <2>; 2980 bias-pull-up; 2981 }; 2982 2983 qup_i2c2_default: qup-i2c2-default-state { 2984 pins = "gpio12", "gpio13"; 2985 function = "qup2"; 2986 drive-strength = <2>; 2987 bias-pull-up; 2988 }; 2989 2990 qup_i2c4_default: qup-i2c4-default-state { 2991 pins = "gpio20", "gpio21"; 2992 function = "qup4"; 2993 drive-strength = <2>; 2994 bias-pull-up; 2995 }; 2996 2997 qup_i2c5_default: qup-i2c5-default-state { 2998 pins = "gpio24", "gpio25"; 2999 function = "qup5"; 3000 drive-strength = <2>; 3001 bias-pull-up; 3002 }; 3003 3004 qup_i2c6_default: qup-i2c6-default-state { 3005 pins = "gpio28", "gpio29"; 3006 function = "qup6"; 3007 drive-strength = <2>; 3008 bias-pull-up; 3009 }; 3010 3011 qup_i2c7_default: qup-i2c7-default-state { 3012 pins = "gpio32", "gpio33"; 3013 function = "qup7"; 3014 drive-strength = <2>; 3015 bias-disable; 3016 }; 3017 3018 qup_i2c8_default: qup-i2c8-default-state { 3019 pins = "gpio36", "gpio37"; 3020 function = "qup8"; 3021 drive-strength = <2>; 3022 bias-pull-up; 3023 }; 3024 3025 qup_i2c9_default: qup-i2c9-default-state { 3026 pins = "gpio40", "gpio41"; 3027 function = "qup9"; 3028 drive-strength = <2>; 3029 bias-pull-up; 3030 }; 3031 3032 qup_i2c10_default: qup-i2c10-default-state { 3033 pins = "gpio44", "gpio45"; 3034 function = "qup10"; 3035 drive-strength = <2>; 3036 bias-pull-up; 3037 }; 3038 3039 qup_i2c11_default: qup-i2c11-default-state { 3040 pins = "gpio48", "gpio49"; 3041 function = "qup11"; 3042 drive-strength = <2>; 3043 bias-pull-up; 3044 }; 3045 3046 qup_i2c12_default: qup-i2c12-default-state { 3047 pins = "gpio52", "gpio53"; 3048 function = "qup12"; 3049 drive-strength = <2>; 3050 bias-pull-up; 3051 }; 3052 3053 qup_i2c13_default: qup-i2c13-default-state { 3054 pins = "gpio0", "gpio1"; 3055 function = "qup13"; 3056 drive-strength = <2>; 3057 bias-pull-up; 3058 }; 3059 3060 qup_i2c14_default: qup-i2c14-default-state { 3061 pins = "gpio56", "gpio57"; 3062 function = "qup14"; 3063 drive-strength = <2>; 3064 bias-disable; 3065 }; 3066 3067 qup_i2c15_default: qup-i2c15-default-state { 3068 pins = "gpio60", "gpio61"; 3069 function = "qup15"; 3070 drive-strength = <2>; 3071 bias-disable; 3072 }; 3073 3074 qup_i2c16_default: qup-i2c16-default-state { 3075 pins = "gpio64", "gpio65"; 3076 function = "qup16"; 3077 drive-strength = <2>; 3078 bias-disable; 3079 }; 3080 3081 qup_i2c17_default: qup-i2c17-default-state { 3082 pins = "gpio72", "gpio73"; 3083 function = "qup17"; 3084 drive-strength = <2>; 3085 bias-disable; 3086 }; 3087 3088 qup_i2c19_default: qup-i2c19-default-state { 3089 pins = "gpio76", "gpio77"; 3090 function = "qup19"; 3091 drive-strength = <2>; 3092 bias-disable; 3093 }; 3094 }; 3095 3096 apps_smmu: iommu@15000000 { 3097 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3098 reg = <0 0x15000000 0 0x100000>; 3099 #iommu-cells = <2>; 3100 #global-interrupts = <2>; 3101 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3199 }; 3200 3201 adsp: remoteproc@17300000 { 3202 compatible = "qcom,sm8350-adsp-pas"; 3203 reg = <0 0x17300000 0 0x100>; 3204 3205 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3206 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3207 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3208 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3209 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3210 interrupt-names = "wdog", "fatal", "ready", 3211 "handover", "stop-ack"; 3212 3213 clocks = <&rpmhcc RPMH_CXO_CLK>; 3214 clock-names = "xo"; 3215 3216 power-domains = <&rpmhpd RPMHPD_LCX>, 3217 <&rpmhpd RPMHPD_LMX>; 3218 power-domain-names = "lcx", "lmx"; 3219 3220 memory-region = <&pil_adsp_mem>; 3221 3222 qcom,qmp = <&aoss_qmp>; 3223 3224 qcom,smem-states = <&smp2p_adsp_out 0>; 3225 qcom,smem-state-names = "stop"; 3226 3227 status = "disabled"; 3228 3229 glink-edge { 3230 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3231 IPCC_MPROC_SIGNAL_GLINK_QMP 3232 IRQ_TYPE_EDGE_RISING>; 3233 mboxes = <&ipcc IPCC_CLIENT_LPASS 3234 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3235 3236 label = "lpass"; 3237 qcom,remote-pid = <2>; 3238 3239 apr { 3240 compatible = "qcom,apr-v2"; 3241 qcom,glink-channels = "apr_audio_svc"; 3242 qcom,domain = <APR_DOMAIN_ADSP>; 3243 #address-cells = <1>; 3244 #size-cells = <0>; 3245 3246 service@3 { 3247 reg = <APR_SVC_ADSP_CORE>; 3248 compatible = "qcom,q6core"; 3249 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3250 }; 3251 3252 q6afe: service@4 { 3253 compatible = "qcom,q6afe"; 3254 reg = <APR_SVC_AFE>; 3255 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3256 3257 q6afedai: dais { 3258 compatible = "qcom,q6afe-dais"; 3259 #address-cells = <1>; 3260 #size-cells = <0>; 3261 #sound-dai-cells = <1>; 3262 }; 3263 3264 q6afecc: clock-controller { 3265 compatible = "qcom,q6afe-clocks"; 3266 #clock-cells = <2>; 3267 }; 3268 }; 3269 3270 q6asm: service@7 { 3271 compatible = "qcom,q6asm"; 3272 reg = <APR_SVC_ASM>; 3273 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3274 3275 q6asmdai: dais { 3276 compatible = "qcom,q6asm-dais"; 3277 #address-cells = <1>; 3278 #size-cells = <0>; 3279 #sound-dai-cells = <1>; 3280 iommus = <&apps_smmu 0x1801 0x0>; 3281 3282 dai@0 { 3283 reg = <0>; 3284 }; 3285 3286 dai@1 { 3287 reg = <1>; 3288 }; 3289 3290 dai@2 { 3291 reg = <2>; 3292 }; 3293 }; 3294 }; 3295 3296 q6adm: service@8 { 3297 compatible = "qcom,q6adm"; 3298 reg = <APR_SVC_ADM>; 3299 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3300 3301 q6routing: routing { 3302 compatible = "qcom,q6adm-routing"; 3303 #sound-dai-cells = <0>; 3304 }; 3305 }; 3306 }; 3307 3308 fastrpc { 3309 compatible = "qcom,fastrpc"; 3310 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3311 label = "adsp"; 3312 qcom,non-secure-domain; 3313 #address-cells = <1>; 3314 #size-cells = <0>; 3315 3316 compute-cb@3 { 3317 compatible = "qcom,fastrpc-compute-cb"; 3318 reg = <3>; 3319 iommus = <&apps_smmu 0x1803 0x0>; 3320 }; 3321 3322 compute-cb@4 { 3323 compatible = "qcom,fastrpc-compute-cb"; 3324 reg = <4>; 3325 iommus = <&apps_smmu 0x1804 0x0>; 3326 }; 3327 3328 compute-cb@5 { 3329 compatible = "qcom,fastrpc-compute-cb"; 3330 reg = <5>; 3331 iommus = <&apps_smmu 0x1805 0x0>; 3332 }; 3333 }; 3334 }; 3335 }; 3336 3337 intc: interrupt-controller@17a00000 { 3338 compatible = "arm,gic-v3"; 3339 #interrupt-cells = <3>; 3340 interrupt-controller; 3341 #redistributor-regions = <1>; 3342 redistributor-stride = <0 0x20000>; 3343 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3344 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3345 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3346 }; 3347 3348 timer@17c20000 { 3349 compatible = "arm,armv7-timer-mem"; 3350 #address-cells = <1>; 3351 #size-cells = <1>; 3352 ranges = <0 0 0 0x20000000>; 3353 reg = <0x0 0x17c20000 0x0 0x1000>; 3354 clock-frequency = <19200000>; 3355 3356 frame@17c21000 { 3357 frame-number = <0>; 3358 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3360 reg = <0x17c21000 0x1000>, 3361 <0x17c22000 0x1000>; 3362 }; 3363 3364 frame@17c23000 { 3365 frame-number = <1>; 3366 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3367 reg = <0x17c23000 0x1000>; 3368 status = "disabled"; 3369 }; 3370 3371 frame@17c25000 { 3372 frame-number = <2>; 3373 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3374 reg = <0x17c25000 0x1000>; 3375 status = "disabled"; 3376 }; 3377 3378 frame@17c27000 { 3379 frame-number = <3>; 3380 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3381 reg = <0x17c27000 0x1000>; 3382 status = "disabled"; 3383 }; 3384 3385 frame@17c29000 { 3386 frame-number = <4>; 3387 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3388 reg = <0x17c29000 0x1000>; 3389 status = "disabled"; 3390 }; 3391 3392 frame@17c2b000 { 3393 frame-number = <5>; 3394 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3395 reg = <0x17c2b000 0x1000>; 3396 status = "disabled"; 3397 }; 3398 3399 frame@17c2d000 { 3400 frame-number = <6>; 3401 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3402 reg = <0x17c2d000 0x1000>; 3403 status = "disabled"; 3404 }; 3405 }; 3406 3407 apps_rsc: rsc@18200000 { 3408 label = "apps_rsc"; 3409 compatible = "qcom,rpmh-rsc"; 3410 reg = <0x0 0x18200000 0x0 0x10000>, 3411 <0x0 0x18210000 0x0 0x10000>, 3412 <0x0 0x18220000 0x0 0x10000>; 3413 reg-names = "drv-0", "drv-1", "drv-2"; 3414 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3417 qcom,tcs-offset = <0xd00>; 3418 qcom,drv-id = <2>; 3419 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3420 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3421 power-domains = <&CLUSTER_PD>; 3422 3423 rpmhcc: clock-controller { 3424 compatible = "qcom,sm8350-rpmh-clk"; 3425 #clock-cells = <1>; 3426 clock-names = "xo"; 3427 clocks = <&xo_board>; 3428 }; 3429 3430 rpmhpd: power-controller { 3431 compatible = "qcom,sm8350-rpmhpd"; 3432 #power-domain-cells = <1>; 3433 operating-points-v2 = <&rpmhpd_opp_table>; 3434 3435 rpmhpd_opp_table: opp-table { 3436 compatible = "operating-points-v2"; 3437 3438 rpmhpd_opp_ret: opp1 { 3439 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3440 }; 3441 3442 rpmhpd_opp_min_svs: opp2 { 3443 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3444 }; 3445 3446 rpmhpd_opp_low_svs: opp3 { 3447 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3448 }; 3449 3450 rpmhpd_opp_svs: opp4 { 3451 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3452 }; 3453 3454 rpmhpd_opp_svs_l1: opp5 { 3455 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3456 }; 3457 3458 rpmhpd_opp_nom: opp6 { 3459 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3460 }; 3461 3462 rpmhpd_opp_nom_l1: opp7 { 3463 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3464 }; 3465 3466 rpmhpd_opp_nom_l2: opp8 { 3467 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3468 }; 3469 3470 rpmhpd_opp_turbo: opp9 { 3471 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3472 }; 3473 3474 rpmhpd_opp_turbo_l1: opp10 { 3475 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3476 }; 3477 }; 3478 }; 3479 3480 apps_bcm_voter: bcm-voter { 3481 compatible = "qcom,bcm-voter"; 3482 }; 3483 }; 3484 3485 cpufreq_hw: cpufreq@18591000 { 3486 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3487 reg = <0 0x18591000 0 0x1000>, 3488 <0 0x18592000 0 0x1000>, 3489 <0 0x18593000 0 0x1000>; 3490 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3491 3492 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3495 interrupt-names = "dcvsh-irq-0", 3496 "dcvsh-irq-1", 3497 "dcvsh-irq-2"; 3498 3499 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3500 clock-names = "xo", "alternate"; 3501 3502 #freq-domain-cells = <1>; 3503 #clock-cells = <1>; 3504 }; 3505 3506 cdsp: remoteproc@98900000 { 3507 compatible = "qcom,sm8350-cdsp-pas"; 3508 reg = <0 0x98900000 0 0x1400000>; 3509 3510 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3511 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3512 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3513 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3514 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3515 interrupt-names = "wdog", "fatal", "ready", 3516 "handover", "stop-ack"; 3517 3518 clocks = <&rpmhcc RPMH_CXO_CLK>; 3519 clock-names = "xo"; 3520 3521 power-domains = <&rpmhpd RPMHPD_CX>, 3522 <&rpmhpd RPMHPD_MXC>; 3523 power-domain-names = "cx", "mxc"; 3524 3525 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3526 3527 memory-region = <&pil_cdsp_mem>; 3528 3529 qcom,qmp = <&aoss_qmp>; 3530 3531 qcom,smem-states = <&smp2p_cdsp_out 0>; 3532 qcom,smem-state-names = "stop"; 3533 3534 status = "disabled"; 3535 3536 glink-edge { 3537 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3538 IPCC_MPROC_SIGNAL_GLINK_QMP 3539 IRQ_TYPE_EDGE_RISING>; 3540 mboxes = <&ipcc IPCC_CLIENT_CDSP 3541 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3542 3543 label = "cdsp"; 3544 qcom,remote-pid = <5>; 3545 3546 fastrpc { 3547 compatible = "qcom,fastrpc"; 3548 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3549 label = "cdsp"; 3550 qcom,non-secure-domain; 3551 #address-cells = <1>; 3552 #size-cells = <0>; 3553 3554 compute-cb@1 { 3555 compatible = "qcom,fastrpc-compute-cb"; 3556 reg = <1>; 3557 iommus = <&apps_smmu 0x2161 0x0400>, 3558 <&apps_smmu 0x1181 0x0420>; 3559 }; 3560 3561 compute-cb@2 { 3562 compatible = "qcom,fastrpc-compute-cb"; 3563 reg = <2>; 3564 iommus = <&apps_smmu 0x2162 0x0400>, 3565 <&apps_smmu 0x1182 0x0420>; 3566 }; 3567 3568 compute-cb@3 { 3569 compatible = "qcom,fastrpc-compute-cb"; 3570 reg = <3>; 3571 iommus = <&apps_smmu 0x2163 0x0400>, 3572 <&apps_smmu 0x1183 0x0420>; 3573 }; 3574 3575 compute-cb@4 { 3576 compatible = "qcom,fastrpc-compute-cb"; 3577 reg = <4>; 3578 iommus = <&apps_smmu 0x2164 0x0400>, 3579 <&apps_smmu 0x1184 0x0420>; 3580 }; 3581 3582 compute-cb@5 { 3583 compatible = "qcom,fastrpc-compute-cb"; 3584 reg = <5>; 3585 iommus = <&apps_smmu 0x2165 0x0400>, 3586 <&apps_smmu 0x1185 0x0420>; 3587 }; 3588 3589 compute-cb@6 { 3590 compatible = "qcom,fastrpc-compute-cb"; 3591 reg = <6>; 3592 iommus = <&apps_smmu 0x2166 0x0400>, 3593 <&apps_smmu 0x1186 0x0420>; 3594 }; 3595 3596 compute-cb@7 { 3597 compatible = "qcom,fastrpc-compute-cb"; 3598 reg = <7>; 3599 iommus = <&apps_smmu 0x2167 0x0400>, 3600 <&apps_smmu 0x1187 0x0420>; 3601 }; 3602 3603 compute-cb@8 { 3604 compatible = "qcom,fastrpc-compute-cb"; 3605 reg = <8>; 3606 iommus = <&apps_smmu 0x2168 0x0400>, 3607 <&apps_smmu 0x1188 0x0420>; 3608 }; 3609 3610 /* note: secure cb9 in downstream */ 3611 }; 3612 }; 3613 }; 3614 }; 3615 3616 thermal_zones: thermal-zones { 3617 cpu0-thermal { 3618 polling-delay-passive = <250>; 3619 polling-delay = <1000>; 3620 3621 thermal-sensors = <&tsens0 1>; 3622 3623 trips { 3624 cpu0_alert0: trip-point0 { 3625 temperature = <90000>; 3626 hysteresis = <2000>; 3627 type = "passive"; 3628 }; 3629 3630 cpu0_alert1: trip-point1 { 3631 temperature = <95000>; 3632 hysteresis = <2000>; 3633 type = "passive"; 3634 }; 3635 3636 cpu0_crit: cpu-crit { 3637 temperature = <110000>; 3638 hysteresis = <1000>; 3639 type = "critical"; 3640 }; 3641 }; 3642 3643 cooling-maps { 3644 map0 { 3645 trip = <&cpu0_alert0>; 3646 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3647 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3648 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3649 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3650 }; 3651 map1 { 3652 trip = <&cpu0_alert1>; 3653 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3654 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3655 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3656 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3657 }; 3658 }; 3659 }; 3660 3661 cpu1-thermal { 3662 polling-delay-passive = <250>; 3663 polling-delay = <1000>; 3664 3665 thermal-sensors = <&tsens0 2>; 3666 3667 trips { 3668 cpu1_alert0: trip-point0 { 3669 temperature = <90000>; 3670 hysteresis = <2000>; 3671 type = "passive"; 3672 }; 3673 3674 cpu1_alert1: trip-point1 { 3675 temperature = <95000>; 3676 hysteresis = <2000>; 3677 type = "passive"; 3678 }; 3679 3680 cpu1_crit: cpu-crit { 3681 temperature = <110000>; 3682 hysteresis = <1000>; 3683 type = "critical"; 3684 }; 3685 }; 3686 3687 cooling-maps { 3688 map0 { 3689 trip = <&cpu1_alert0>; 3690 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3691 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3692 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3693 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3694 }; 3695 map1 { 3696 trip = <&cpu1_alert1>; 3697 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3699 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3700 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3701 }; 3702 }; 3703 }; 3704 3705 cpu2-thermal { 3706 polling-delay-passive = <250>; 3707 polling-delay = <1000>; 3708 3709 thermal-sensors = <&tsens0 3>; 3710 3711 trips { 3712 cpu2_alert0: trip-point0 { 3713 temperature = <90000>; 3714 hysteresis = <2000>; 3715 type = "passive"; 3716 }; 3717 3718 cpu2_alert1: trip-point1 { 3719 temperature = <95000>; 3720 hysteresis = <2000>; 3721 type = "passive"; 3722 }; 3723 3724 cpu2_crit: cpu-crit { 3725 temperature = <110000>; 3726 hysteresis = <1000>; 3727 type = "critical"; 3728 }; 3729 }; 3730 3731 cooling-maps { 3732 map0 { 3733 trip = <&cpu2_alert0>; 3734 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3735 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3736 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3738 }; 3739 map1 { 3740 trip = <&cpu2_alert1>; 3741 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3742 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3743 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3744 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3745 }; 3746 }; 3747 }; 3748 3749 cpu3-thermal { 3750 polling-delay-passive = <250>; 3751 polling-delay = <1000>; 3752 3753 thermal-sensors = <&tsens0 4>; 3754 3755 trips { 3756 cpu3_alert0: trip-point0 { 3757 temperature = <90000>; 3758 hysteresis = <2000>; 3759 type = "passive"; 3760 }; 3761 3762 cpu3_alert1: trip-point1 { 3763 temperature = <95000>; 3764 hysteresis = <2000>; 3765 type = "passive"; 3766 }; 3767 3768 cpu3_crit: cpu-crit { 3769 temperature = <110000>; 3770 hysteresis = <1000>; 3771 type = "critical"; 3772 }; 3773 }; 3774 3775 cooling-maps { 3776 map0 { 3777 trip = <&cpu3_alert0>; 3778 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3779 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3782 }; 3783 map1 { 3784 trip = <&cpu3_alert1>; 3785 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3787 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3788 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3789 }; 3790 }; 3791 }; 3792 3793 cpu4-top-thermal { 3794 polling-delay-passive = <250>; 3795 polling-delay = <1000>; 3796 3797 thermal-sensors = <&tsens0 7>; 3798 3799 trips { 3800 cpu4_top_alert0: trip-point0 { 3801 temperature = <90000>; 3802 hysteresis = <2000>; 3803 type = "passive"; 3804 }; 3805 3806 cpu4_top_alert1: trip-point1 { 3807 temperature = <95000>; 3808 hysteresis = <2000>; 3809 type = "passive"; 3810 }; 3811 3812 cpu4_top_crit: cpu-crit { 3813 temperature = <110000>; 3814 hysteresis = <1000>; 3815 type = "critical"; 3816 }; 3817 }; 3818 3819 cooling-maps { 3820 map0 { 3821 trip = <&cpu4_top_alert0>; 3822 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3826 }; 3827 map1 { 3828 trip = <&cpu4_top_alert1>; 3829 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3831 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3832 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3833 }; 3834 }; 3835 }; 3836 3837 cpu5-top-thermal { 3838 polling-delay-passive = <250>; 3839 polling-delay = <1000>; 3840 3841 thermal-sensors = <&tsens0 8>; 3842 3843 trips { 3844 cpu5_top_alert0: trip-point0 { 3845 temperature = <90000>; 3846 hysteresis = <2000>; 3847 type = "passive"; 3848 }; 3849 3850 cpu5_top_alert1: trip-point1 { 3851 temperature = <95000>; 3852 hysteresis = <2000>; 3853 type = "passive"; 3854 }; 3855 3856 cpu5_top_crit: cpu-crit { 3857 temperature = <110000>; 3858 hysteresis = <1000>; 3859 type = "critical"; 3860 }; 3861 }; 3862 3863 cooling-maps { 3864 map0 { 3865 trip = <&cpu5_top_alert0>; 3866 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3869 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3870 }; 3871 map1 { 3872 trip = <&cpu5_top_alert1>; 3873 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3875 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3876 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3877 }; 3878 }; 3879 }; 3880 3881 cpu6-top-thermal { 3882 polling-delay-passive = <250>; 3883 polling-delay = <1000>; 3884 3885 thermal-sensors = <&tsens0 9>; 3886 3887 trips { 3888 cpu6_top_alert0: trip-point0 { 3889 temperature = <90000>; 3890 hysteresis = <2000>; 3891 type = "passive"; 3892 }; 3893 3894 cpu6_top_alert1: trip-point1 { 3895 temperature = <95000>; 3896 hysteresis = <2000>; 3897 type = "passive"; 3898 }; 3899 3900 cpu6_top_crit: cpu-crit { 3901 temperature = <110000>; 3902 hysteresis = <1000>; 3903 type = "critical"; 3904 }; 3905 }; 3906 3907 cooling-maps { 3908 map0 { 3909 trip = <&cpu6_top_alert0>; 3910 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3914 }; 3915 map1 { 3916 trip = <&cpu6_top_alert1>; 3917 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3919 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3921 }; 3922 }; 3923 }; 3924 3925 cpu7-top-thermal { 3926 polling-delay-passive = <250>; 3927 polling-delay = <1000>; 3928 3929 thermal-sensors = <&tsens0 10>; 3930 3931 trips { 3932 cpu7_top_alert0: trip-point0 { 3933 temperature = <90000>; 3934 hysteresis = <2000>; 3935 type = "passive"; 3936 }; 3937 3938 cpu7_top_alert1: trip-point1 { 3939 temperature = <95000>; 3940 hysteresis = <2000>; 3941 type = "passive"; 3942 }; 3943 3944 cpu7_top_crit: cpu-crit { 3945 temperature = <110000>; 3946 hysteresis = <1000>; 3947 type = "critical"; 3948 }; 3949 }; 3950 3951 cooling-maps { 3952 map0 { 3953 trip = <&cpu7_top_alert0>; 3954 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3955 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3956 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3957 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3958 }; 3959 map1 { 3960 trip = <&cpu7_top_alert1>; 3961 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3964 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3965 }; 3966 }; 3967 }; 3968 3969 cpu4-bottom-thermal { 3970 polling-delay-passive = <250>; 3971 polling-delay = <1000>; 3972 3973 thermal-sensors = <&tsens0 11>; 3974 3975 trips { 3976 cpu4_bottom_alert0: trip-point0 { 3977 temperature = <90000>; 3978 hysteresis = <2000>; 3979 type = "passive"; 3980 }; 3981 3982 cpu4_bottom_alert1: trip-point1 { 3983 temperature = <95000>; 3984 hysteresis = <2000>; 3985 type = "passive"; 3986 }; 3987 3988 cpu4_bottom_crit: cpu-crit { 3989 temperature = <110000>; 3990 hysteresis = <1000>; 3991 type = "critical"; 3992 }; 3993 }; 3994 3995 cooling-maps { 3996 map0 { 3997 trip = <&cpu4_bottom_alert0>; 3998 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3999 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4000 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4001 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4002 }; 4003 map1 { 4004 trip = <&cpu4_bottom_alert1>; 4005 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4007 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4008 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4009 }; 4010 }; 4011 }; 4012 4013 cpu5-bottom-thermal { 4014 polling-delay-passive = <250>; 4015 polling-delay = <1000>; 4016 4017 thermal-sensors = <&tsens0 12>; 4018 4019 trips { 4020 cpu5_bottom_alert0: trip-point0 { 4021 temperature = <90000>; 4022 hysteresis = <2000>; 4023 type = "passive"; 4024 }; 4025 4026 cpu5_bottom_alert1: trip-point1 { 4027 temperature = <95000>; 4028 hysteresis = <2000>; 4029 type = "passive"; 4030 }; 4031 4032 cpu5_bottom_crit: cpu-crit { 4033 temperature = <110000>; 4034 hysteresis = <1000>; 4035 type = "critical"; 4036 }; 4037 }; 4038 4039 cooling-maps { 4040 map0 { 4041 trip = <&cpu5_bottom_alert0>; 4042 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4043 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4044 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4045 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4046 }; 4047 map1 { 4048 trip = <&cpu5_bottom_alert1>; 4049 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4050 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4051 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4052 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4053 }; 4054 }; 4055 }; 4056 4057 cpu6-bottom-thermal { 4058 polling-delay-passive = <250>; 4059 polling-delay = <1000>; 4060 4061 thermal-sensors = <&tsens0 13>; 4062 4063 trips { 4064 cpu6_bottom_alert0: trip-point0 { 4065 temperature = <90000>; 4066 hysteresis = <2000>; 4067 type = "passive"; 4068 }; 4069 4070 cpu6_bottom_alert1: trip-point1 { 4071 temperature = <95000>; 4072 hysteresis = <2000>; 4073 type = "passive"; 4074 }; 4075 4076 cpu6_bottom_crit: cpu-crit { 4077 temperature = <110000>; 4078 hysteresis = <1000>; 4079 type = "critical"; 4080 }; 4081 }; 4082 4083 cooling-maps { 4084 map0 { 4085 trip = <&cpu6_bottom_alert0>; 4086 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4087 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4088 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4089 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4090 }; 4091 map1 { 4092 trip = <&cpu6_bottom_alert1>; 4093 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4095 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4096 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4097 }; 4098 }; 4099 }; 4100 4101 cpu7-bottom-thermal { 4102 polling-delay-passive = <250>; 4103 polling-delay = <1000>; 4104 4105 thermal-sensors = <&tsens0 14>; 4106 4107 trips { 4108 cpu7_bottom_alert0: trip-point0 { 4109 temperature = <90000>; 4110 hysteresis = <2000>; 4111 type = "passive"; 4112 }; 4113 4114 cpu7_bottom_alert1: trip-point1 { 4115 temperature = <95000>; 4116 hysteresis = <2000>; 4117 type = "passive"; 4118 }; 4119 4120 cpu7_bottom_crit: cpu-crit { 4121 temperature = <110000>; 4122 hysteresis = <1000>; 4123 type = "critical"; 4124 }; 4125 }; 4126 4127 cooling-maps { 4128 map0 { 4129 trip = <&cpu7_bottom_alert0>; 4130 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4133 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4134 }; 4135 map1 { 4136 trip = <&cpu7_bottom_alert1>; 4137 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4139 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4140 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4141 }; 4142 }; 4143 }; 4144 4145 aoss0-thermal { 4146 polling-delay-passive = <250>; 4147 polling-delay = <1000>; 4148 4149 thermal-sensors = <&tsens0 0>; 4150 4151 trips { 4152 aoss0_alert0: trip-point0 { 4153 temperature = <90000>; 4154 hysteresis = <2000>; 4155 type = "hot"; 4156 }; 4157 }; 4158 }; 4159 4160 cluster0-thermal { 4161 polling-delay-passive = <250>; 4162 polling-delay = <1000>; 4163 4164 thermal-sensors = <&tsens0 5>; 4165 4166 trips { 4167 cluster0_alert0: trip-point0 { 4168 temperature = <90000>; 4169 hysteresis = <2000>; 4170 type = "hot"; 4171 }; 4172 cluster0_crit: cluster0_crit { 4173 temperature = <110000>; 4174 hysteresis = <2000>; 4175 type = "critical"; 4176 }; 4177 }; 4178 }; 4179 4180 cluster1-thermal { 4181 polling-delay-passive = <250>; 4182 polling-delay = <1000>; 4183 4184 thermal-sensors = <&tsens0 6>; 4185 4186 trips { 4187 cluster1_alert0: trip-point0 { 4188 temperature = <90000>; 4189 hysteresis = <2000>; 4190 type = "hot"; 4191 }; 4192 cluster1_crit: cluster1_crit { 4193 temperature = <110000>; 4194 hysteresis = <2000>; 4195 type = "critical"; 4196 }; 4197 }; 4198 }; 4199 4200 aoss1-thermal { 4201 polling-delay-passive = <250>; 4202 polling-delay = <1000>; 4203 4204 thermal-sensors = <&tsens1 0>; 4205 4206 trips { 4207 aoss1_alert0: trip-point0 { 4208 temperature = <90000>; 4209 hysteresis = <2000>; 4210 type = "hot"; 4211 }; 4212 }; 4213 }; 4214 4215 gpu-top-thermal { 4216 polling-delay-passive = <250>; 4217 polling-delay = <1000>; 4218 4219 thermal-sensors = <&tsens1 1>; 4220 4221 trips { 4222 gpu1_alert0: trip-point0 { 4223 temperature = <90000>; 4224 hysteresis = <1000>; 4225 type = "hot"; 4226 }; 4227 }; 4228 }; 4229 4230 gpu-bottom-thermal { 4231 polling-delay-passive = <250>; 4232 polling-delay = <1000>; 4233 4234 thermal-sensors = <&tsens1 2>; 4235 4236 trips { 4237 gpu2_alert0: trip-point0 { 4238 temperature = <90000>; 4239 hysteresis = <1000>; 4240 type = "hot"; 4241 }; 4242 }; 4243 }; 4244 4245 nspss1-thermal { 4246 polling-delay-passive = <250>; 4247 polling-delay = <1000>; 4248 4249 thermal-sensors = <&tsens1 3>; 4250 4251 trips { 4252 nspss1_alert0: trip-point0 { 4253 temperature = <90000>; 4254 hysteresis = <1000>; 4255 type = "hot"; 4256 }; 4257 }; 4258 }; 4259 4260 nspss2-thermal { 4261 polling-delay-passive = <250>; 4262 polling-delay = <1000>; 4263 4264 thermal-sensors = <&tsens1 4>; 4265 4266 trips { 4267 nspss2_alert0: trip-point0 { 4268 temperature = <90000>; 4269 hysteresis = <1000>; 4270 type = "hot"; 4271 }; 4272 }; 4273 }; 4274 4275 nspss3-thermal { 4276 polling-delay-passive = <250>; 4277 polling-delay = <1000>; 4278 4279 thermal-sensors = <&tsens1 5>; 4280 4281 trips { 4282 nspss3_alert0: trip-point0 { 4283 temperature = <90000>; 4284 hysteresis = <1000>; 4285 type = "hot"; 4286 }; 4287 }; 4288 }; 4289 4290 video-thermal { 4291 polling-delay-passive = <250>; 4292 polling-delay = <1000>; 4293 4294 thermal-sensors = <&tsens1 6>; 4295 4296 trips { 4297 video_alert0: trip-point0 { 4298 temperature = <90000>; 4299 hysteresis = <2000>; 4300 type = "hot"; 4301 }; 4302 }; 4303 }; 4304 4305 mem-thermal { 4306 polling-delay-passive = <250>; 4307 polling-delay = <1000>; 4308 4309 thermal-sensors = <&tsens1 7>; 4310 4311 trips { 4312 mem_alert0: trip-point0 { 4313 temperature = <90000>; 4314 hysteresis = <2000>; 4315 type = "hot"; 4316 }; 4317 }; 4318 }; 4319 4320 modem1-top-thermal { 4321 polling-delay-passive = <250>; 4322 polling-delay = <1000>; 4323 4324 thermal-sensors = <&tsens1 8>; 4325 4326 trips { 4327 modem1_alert0: trip-point0 { 4328 temperature = <90000>; 4329 hysteresis = <2000>; 4330 type = "hot"; 4331 }; 4332 }; 4333 }; 4334 4335 modem2-top-thermal { 4336 polling-delay-passive = <250>; 4337 polling-delay = <1000>; 4338 4339 thermal-sensors = <&tsens1 9>; 4340 4341 trips { 4342 modem2_alert0: trip-point0 { 4343 temperature = <90000>; 4344 hysteresis = <2000>; 4345 type = "hot"; 4346 }; 4347 }; 4348 }; 4349 4350 modem3-top-thermal { 4351 polling-delay-passive = <250>; 4352 polling-delay = <1000>; 4353 4354 thermal-sensors = <&tsens1 10>; 4355 4356 trips { 4357 modem3_alert0: trip-point0 { 4358 temperature = <90000>; 4359 hysteresis = <2000>; 4360 type = "hot"; 4361 }; 4362 }; 4363 }; 4364 4365 modem4-top-thermal { 4366 polling-delay-passive = <250>; 4367 polling-delay = <1000>; 4368 4369 thermal-sensors = <&tsens1 11>; 4370 4371 trips { 4372 modem4_alert0: trip-point0 { 4373 temperature = <90000>; 4374 hysteresis = <2000>; 4375 type = "hot"; 4376 }; 4377 }; 4378 }; 4379 4380 camera-top-thermal { 4381 polling-delay-passive = <250>; 4382 polling-delay = <1000>; 4383 4384 thermal-sensors = <&tsens1 12>; 4385 4386 trips { 4387 camera1_alert0: trip-point0 { 4388 temperature = <90000>; 4389 hysteresis = <2000>; 4390 type = "hot"; 4391 }; 4392 }; 4393 }; 4394 4395 cam-bottom-thermal { 4396 polling-delay-passive = <250>; 4397 polling-delay = <1000>; 4398 4399 thermal-sensors = <&tsens1 13>; 4400 4401 trips { 4402 camera2_alert0: trip-point0 { 4403 temperature = <90000>; 4404 hysteresis = <2000>; 4405 type = "hot"; 4406 }; 4407 }; 4408 }; 4409 }; 4410 4411 timer { 4412 compatible = "arm,armv8-timer"; 4413 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4414 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4415 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4416 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4417 }; 4418}; 4419