1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008, 2009 Provigent Ltd. 4 * 5 * Author: Baruch Siach <baruch@tkos.co.il> 6 * 7 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) 8 * 9 * Data sheet: ARM DDI 0190B, September 2000 10 */ 11 #include <linux/spinlock.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/ioport.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/module.h> 20 #include <linux/bitops.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/device.h> 23 #include <linux/amba/bus.h> 24 #include <linux/slab.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/pm.h> 27 28 #define GPIODIR 0x400 29 #define GPIOIS 0x404 30 #define GPIOIBE 0x408 31 #define GPIOIEV 0x40C 32 #define GPIOIE 0x410 33 #define GPIORIS 0x414 34 #define GPIOMIS 0x418 35 #define GPIOIC 0x41C 36 37 #define PL061_GPIO_NR 8 38 39 #ifdef CONFIG_PM 40 struct pl061_context_save_regs { 41 u8 gpio_data; 42 u8 gpio_dir; 43 u8 gpio_is; 44 u8 gpio_ibe; 45 u8 gpio_iev; 46 u8 gpio_ie; 47 }; 48 #endif 49 50 struct pl061 { 51 raw_spinlock_t lock; 52 53 void __iomem *base; 54 struct gpio_chip gc; 55 int parent_irq; 56 57 #ifdef CONFIG_PM 58 struct pl061_context_save_regs csave_regs; 59 #endif 60 }; 61 62 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) 63 { 64 struct pl061 *pl061 = gpiochip_get_data(gc); 65 66 if (readb(pl061->base + GPIODIR) & BIT(offset)) 67 return GPIO_LINE_DIRECTION_OUT; 68 69 return GPIO_LINE_DIRECTION_IN; 70 } 71 72 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) 73 { 74 struct pl061 *pl061 = gpiochip_get_data(gc); 75 unsigned long flags; 76 unsigned char gpiodir; 77 78 raw_spin_lock_irqsave(&pl061->lock, flags); 79 gpiodir = readb(pl061->base + GPIODIR); 80 gpiodir &= ~(BIT(offset)); 81 writeb(gpiodir, pl061->base + GPIODIR); 82 raw_spin_unlock_irqrestore(&pl061->lock, flags); 83 84 return 0; 85 } 86 87 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, 88 int value) 89 { 90 struct pl061 *pl061 = gpiochip_get_data(gc); 91 unsigned long flags; 92 unsigned char gpiodir; 93 94 raw_spin_lock_irqsave(&pl061->lock, flags); 95 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 96 gpiodir = readb(pl061->base + GPIODIR); 97 gpiodir |= BIT(offset); 98 writeb(gpiodir, pl061->base + GPIODIR); 99 100 /* 101 * gpio value is set again, because pl061 doesn't allow to set value of 102 * a gpio pin before configuring it in OUT mode. 103 */ 104 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 105 raw_spin_unlock_irqrestore(&pl061->lock, flags); 106 107 return 0; 108 } 109 110 static int pl061_get_value(struct gpio_chip *gc, unsigned offset) 111 { 112 struct pl061 *pl061 = gpiochip_get_data(gc); 113 114 return !!readb(pl061->base + (BIT(offset + 2))); 115 } 116 117 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) 118 { 119 struct pl061 *pl061 = gpiochip_get_data(gc); 120 121 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 122 } 123 124 static int pl061_irq_type(struct irq_data *d, unsigned trigger) 125 { 126 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 127 struct pl061 *pl061 = gpiochip_get_data(gc); 128 int offset = irqd_to_hwirq(d); 129 unsigned long flags; 130 u8 gpiois, gpioibe, gpioiev; 131 u8 bit = BIT(offset); 132 133 if (offset < 0 || offset >= PL061_GPIO_NR) 134 return -EINVAL; 135 136 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && 137 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) 138 { 139 dev_err(gc->parent, 140 "trying to configure line %d for both level and edge " 141 "detection, choose one!\n", 142 offset); 143 return -EINVAL; 144 } 145 146 147 raw_spin_lock_irqsave(&pl061->lock, flags); 148 149 gpioiev = readb(pl061->base + GPIOIEV); 150 gpiois = readb(pl061->base + GPIOIS); 151 gpioibe = readb(pl061->base + GPIOIBE); 152 153 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 154 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; 155 156 /* Disable edge detection */ 157 gpioibe &= ~bit; 158 /* Enable level detection */ 159 gpiois |= bit; 160 /* Select polarity */ 161 if (polarity) 162 gpioiev |= bit; 163 else 164 gpioiev &= ~bit; 165 irq_set_handler_locked(d, handle_level_irq); 166 dev_dbg(gc->parent, "line %d: IRQ on %s level\n", 167 offset, 168 polarity ? "HIGH" : "LOW"); 169 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 170 /* Disable level detection */ 171 gpiois &= ~bit; 172 /* Select both edges, setting this makes GPIOEV be ignored */ 173 gpioibe |= bit; 174 irq_set_handler_locked(d, handle_edge_irq); 175 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); 176 } else if ((trigger & IRQ_TYPE_EDGE_RISING) || 177 (trigger & IRQ_TYPE_EDGE_FALLING)) { 178 bool rising = trigger & IRQ_TYPE_EDGE_RISING; 179 180 /* Disable level detection */ 181 gpiois &= ~bit; 182 /* Clear detection on both edges */ 183 gpioibe &= ~bit; 184 /* Select edge */ 185 if (rising) 186 gpioiev |= bit; 187 else 188 gpioiev &= ~bit; 189 irq_set_handler_locked(d, handle_edge_irq); 190 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", 191 offset, 192 rising ? "RISING" : "FALLING"); 193 } else { 194 /* No trigger: disable everything */ 195 gpiois &= ~bit; 196 gpioibe &= ~bit; 197 gpioiev &= ~bit; 198 irq_set_handler_locked(d, handle_bad_irq); 199 dev_warn(gc->parent, "no trigger selected for line %d\n", 200 offset); 201 } 202 203 writeb(gpiois, pl061->base + GPIOIS); 204 writeb(gpioibe, pl061->base + GPIOIBE); 205 writeb(gpioiev, pl061->base + GPIOIEV); 206 207 raw_spin_unlock_irqrestore(&pl061->lock, flags); 208 209 return 0; 210 } 211 212 static void pl061_irq_handler(struct irq_desc *desc) 213 { 214 unsigned long pending; 215 int offset; 216 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 217 struct pl061 *pl061 = gpiochip_get_data(gc); 218 struct irq_chip *irqchip = irq_desc_get_chip(desc); 219 220 chained_irq_enter(irqchip, desc); 221 222 pending = readb(pl061->base + GPIOMIS); 223 if (pending) { 224 for_each_set_bit(offset, &pending, PL061_GPIO_NR) 225 generic_handle_domain_irq(gc->irq.domain, 226 offset); 227 } 228 229 chained_irq_exit(irqchip, desc); 230 } 231 232 static void pl061_irq_mask(struct irq_data *d) 233 { 234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 235 struct pl061 *pl061 = gpiochip_get_data(gc); 236 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 237 u8 gpioie; 238 239 raw_spin_lock(&pl061->lock); 240 gpioie = readb(pl061->base + GPIOIE) & ~mask; 241 writeb(gpioie, pl061->base + GPIOIE); 242 raw_spin_unlock(&pl061->lock); 243 244 gpiochip_disable_irq(gc, d->hwirq); 245 } 246 247 static void pl061_irq_unmask(struct irq_data *d) 248 { 249 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 250 struct pl061 *pl061 = gpiochip_get_data(gc); 251 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 252 u8 gpioie; 253 254 gpiochip_enable_irq(gc, d->hwirq); 255 256 raw_spin_lock(&pl061->lock); 257 gpioie = readb(pl061->base + GPIOIE) | mask; 258 writeb(gpioie, pl061->base + GPIOIE); 259 raw_spin_unlock(&pl061->lock); 260 } 261 262 /** 263 * pl061_irq_ack() - ACK an edge IRQ 264 * @d: IRQ data for this IRQ 265 * 266 * This gets called from the edge IRQ handler to ACK the edge IRQ 267 * in the GPIOIC (interrupt-clear) register. For level IRQs this is 268 * not needed: these go away when the level signal goes away. 269 */ 270 static void pl061_irq_ack(struct irq_data *d) 271 { 272 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 273 struct pl061 *pl061 = gpiochip_get_data(gc); 274 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 275 276 raw_spin_lock(&pl061->lock); 277 writeb(mask, pl061->base + GPIOIC); 278 raw_spin_unlock(&pl061->lock); 279 } 280 281 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) 282 { 283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 284 struct pl061 *pl061 = gpiochip_get_data(gc); 285 286 return irq_set_irq_wake(pl061->parent_irq, state); 287 } 288 289 static void pl061_irq_print_chip(struct irq_data *data, struct seq_file *p) 290 { 291 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 292 293 seq_printf(p, dev_name(gc->parent)); 294 } 295 296 static const struct irq_chip pl061_irq_chip = { 297 .irq_ack = pl061_irq_ack, 298 .irq_mask = pl061_irq_mask, 299 .irq_unmask = pl061_irq_unmask, 300 .irq_set_type = pl061_irq_type, 301 .irq_set_wake = pl061_irq_set_wake, 302 .irq_print_chip = pl061_irq_print_chip, 303 .flags = IRQCHIP_IMMUTABLE, 304 GPIOCHIP_IRQ_RESOURCE_HELPERS, 305 }; 306 307 static int pl061_probe(struct amba_device *adev, const struct amba_id *id) 308 { 309 struct device *dev = &adev->dev; 310 struct pl061 *pl061; 311 struct gpio_irq_chip *girq; 312 int ret, irq; 313 314 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); 315 if (pl061 == NULL) 316 return -ENOMEM; 317 318 pl061->base = devm_ioremap_resource(dev, &adev->res); 319 if (IS_ERR(pl061->base)) 320 return PTR_ERR(pl061->base); 321 322 raw_spin_lock_init(&pl061->lock); 323 pl061->gc.request = gpiochip_generic_request; 324 pl061->gc.free = gpiochip_generic_free; 325 pl061->gc.base = -1; 326 pl061->gc.get_direction = pl061_get_direction; 327 pl061->gc.direction_input = pl061_direction_input; 328 pl061->gc.direction_output = pl061_direction_output; 329 pl061->gc.get = pl061_get_value; 330 pl061->gc.set = pl061_set_value; 331 pl061->gc.ngpio = PL061_GPIO_NR; 332 pl061->gc.label = dev_name(dev); 333 pl061->gc.parent = dev; 334 pl061->gc.owner = THIS_MODULE; 335 336 /* 337 * irq_chip support 338 */ 339 writeb(0, pl061->base + GPIOIE); /* disable irqs */ 340 irq = adev->irq[0]; 341 if (!irq) 342 dev_warn(&adev->dev, "IRQ support disabled\n"); 343 pl061->parent_irq = irq; 344 345 girq = &pl061->gc.irq; 346 gpio_irq_chip_set_chip(girq, &pl061_irq_chip); 347 girq->parent_handler = pl061_irq_handler; 348 girq->num_parents = 1; 349 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 350 GFP_KERNEL); 351 if (!girq->parents) 352 return -ENOMEM; 353 girq->parents[0] = irq; 354 girq->default_type = IRQ_TYPE_NONE; 355 girq->handler = handle_bad_irq; 356 357 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); 358 if (ret) 359 return ret; 360 361 amba_set_drvdata(adev, pl061); 362 dev_info(dev, "PL061 GPIO chip registered\n"); 363 364 return 0; 365 } 366 367 #ifdef CONFIG_PM 368 static int pl061_suspend(struct device *dev) 369 { 370 struct pl061 *pl061 = dev_get_drvdata(dev); 371 int offset; 372 373 pl061->csave_regs.gpio_data = 0; 374 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); 375 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); 376 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); 377 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); 378 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); 379 380 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 381 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 382 pl061->csave_regs.gpio_data |= 383 pl061_get_value(&pl061->gc, offset) << offset; 384 } 385 386 return 0; 387 } 388 389 static int pl061_resume(struct device *dev) 390 { 391 struct pl061 *pl061 = dev_get_drvdata(dev); 392 int offset; 393 394 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 395 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 396 pl061_direction_output(&pl061->gc, offset, 397 pl061->csave_regs.gpio_data & 398 (BIT(offset))); 399 else 400 pl061_direction_input(&pl061->gc, offset); 401 } 402 403 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); 404 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); 405 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); 406 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); 407 408 return 0; 409 } 410 411 static const struct dev_pm_ops pl061_dev_pm_ops = { 412 .suspend = pl061_suspend, 413 .resume = pl061_resume, 414 .freeze = pl061_suspend, 415 .restore = pl061_resume, 416 }; 417 #endif 418 419 static const struct amba_id pl061_ids[] = { 420 { 421 .id = 0x00041061, 422 .mask = 0x000fffff, 423 }, 424 { 0, 0 }, 425 }; 426 MODULE_DEVICE_TABLE(amba, pl061_ids); 427 428 static struct amba_driver pl061_gpio_driver = { 429 .drv = { 430 .name = "pl061_gpio", 431 #ifdef CONFIG_PM 432 .pm = &pl061_dev_pm_ops, 433 #endif 434 }, 435 .id_table = pl061_ids, 436 .probe = pl061_probe, 437 }; 438 module_amba_driver(pl061_gpio_driver); 439 440 MODULE_LICENSE("GPL v2"); 441