1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MediaTek display pulse-width-modulation controller driver. 4 * Copyright (c) 2015 MediaTek Inc. 5 * Author: YH Huang <yh.huang@mediatek.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pwm.h> 17 #include <linux/slab.h> 18 19 #define DISP_PWM_EN 0x00 20 21 #define PWM_CLKDIV_SHIFT 16 22 #define PWM_CLKDIV_MAX 0x3ff 23 #define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT) 24 25 #define PWM_PERIOD_BIT_WIDTH 12 26 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1) 27 28 #define PWM_HIGH_WIDTH_SHIFT 16 29 #define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT) 30 31 struct mtk_pwm_data { 32 u32 enable_mask; 33 unsigned int con0; 34 u32 con0_sel; 35 unsigned int con1; 36 37 bool has_commit; 38 unsigned int commit; 39 unsigned int commit_mask; 40 41 unsigned int bls_debug; 42 u32 bls_debug_mask; 43 }; 44 45 struct mtk_disp_pwm { 46 struct pwm_chip chip; 47 const struct mtk_pwm_data *data; 48 struct clk *clk_main; 49 struct clk *clk_mm; 50 void __iomem *base; 51 bool enabled; 52 }; 53 54 static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip) 55 { 56 return container_of(chip, struct mtk_disp_pwm, chip); 57 } 58 59 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset, 60 u32 mask, u32 data) 61 { 62 void __iomem *address = mdp->base + offset; 63 u32 value; 64 65 value = readl(address); 66 value &= ~mask; 67 value |= data; 68 writel(value, address); 69 } 70 71 static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 72 const struct pwm_state *state) 73 { 74 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); 75 u32 clk_div, period, high_width, value; 76 u64 div, rate; 77 int err; 78 79 if (state->polarity != PWM_POLARITY_NORMAL) 80 return -EINVAL; 81 82 if (!state->enabled && mdp->enabled) { 83 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, 84 mdp->data->enable_mask, 0x0); 85 clk_disable_unprepare(mdp->clk_mm); 86 clk_disable_unprepare(mdp->clk_main); 87 88 mdp->enabled = false; 89 return 0; 90 } 91 92 if (!mdp->enabled) { 93 err = clk_prepare_enable(mdp->clk_main); 94 if (err < 0) { 95 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", 96 ERR_PTR(err)); 97 return err; 98 } 99 100 err = clk_prepare_enable(mdp->clk_mm); 101 if (err < 0) { 102 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", 103 ERR_PTR(err)); 104 clk_disable_unprepare(mdp->clk_main); 105 return err; 106 } 107 } 108 109 /* 110 * Find period, high_width and clk_div to suit duty_ns and period_ns. 111 * Calculate proper div value to keep period value in the bound. 112 * 113 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE 114 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE 115 * 116 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 117 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) 118 */ 119 rate = clk_get_rate(mdp->clk_main); 120 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> 121 PWM_PERIOD_BIT_WIDTH; 122 if (clk_div > PWM_CLKDIV_MAX) { 123 if (!mdp->enabled) { 124 clk_disable_unprepare(mdp->clk_mm); 125 clk_disable_unprepare(mdp->clk_main); 126 } 127 return -EINVAL; 128 } 129 130 div = NSEC_PER_SEC * (clk_div + 1); 131 period = mul_u64_u64_div_u64(state->period, rate, div); 132 if (period > 0) 133 period--; 134 135 high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div); 136 value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); 137 138 if (mdp->data->bls_debug && !mdp->data->has_commit) { 139 /* 140 * For MT2701, disable double buffer before writing register 141 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. 142 */ 143 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, 144 mdp->data->bls_debug_mask, 145 mdp->data->bls_debug_mask); 146 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, 147 mdp->data->con0_sel, 148 mdp->data->con0_sel); 149 } 150 151 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, 152 PWM_CLKDIV_MASK, 153 clk_div << PWM_CLKDIV_SHIFT); 154 mtk_disp_pwm_update_bits(mdp, mdp->data->con1, 155 PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK, 156 value); 157 158 if (mdp->data->has_commit) { 159 mtk_disp_pwm_update_bits(mdp, mdp->data->commit, 160 mdp->data->commit_mask, 161 mdp->data->commit_mask); 162 mtk_disp_pwm_update_bits(mdp, mdp->data->commit, 163 mdp->data->commit_mask, 164 0x0); 165 } 166 167 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, 168 mdp->data->enable_mask); 169 mdp->enabled = true; 170 171 return 0; 172 } 173 174 static int mtk_disp_pwm_get_state(struct pwm_chip *chip, 175 struct pwm_device *pwm, 176 struct pwm_state *state) 177 { 178 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); 179 u64 rate, period, high_width; 180 u32 clk_div, pwm_en, con0, con1; 181 int err; 182 183 err = clk_prepare_enable(mdp->clk_main); 184 if (err < 0) { 185 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); 186 return err; 187 } 188 189 err = clk_prepare_enable(mdp->clk_mm); 190 if (err < 0) { 191 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); 192 clk_disable_unprepare(mdp->clk_main); 193 return err; 194 } 195 196 /* 197 * Apply DISP_PWM_DEBUG settings to choose whether to enable or disable 198 * registers double buffer and manual commit to working register before 199 * performing any read/write operation 200 */ 201 if (mdp->data->bls_debug) 202 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, 203 mdp->data->bls_debug_mask, 204 mdp->data->bls_debug_mask); 205 206 rate = clk_get_rate(mdp->clk_main); 207 con0 = readl(mdp->base + mdp->data->con0); 208 con1 = readl(mdp->base + mdp->data->con1); 209 pwm_en = readl(mdp->base + DISP_PWM_EN); 210 state->enabled = !!(pwm_en & mdp->data->enable_mask); 211 clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0); 212 period = FIELD_GET(PWM_PERIOD_MASK, con1); 213 /* 214 * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30, 215 * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow. 216 */ 217 state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate); 218 high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1); 219 state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC, 220 rate); 221 state->polarity = PWM_POLARITY_NORMAL; 222 clk_disable_unprepare(mdp->clk_mm); 223 clk_disable_unprepare(mdp->clk_main); 224 225 return 0; 226 } 227 228 static const struct pwm_ops mtk_disp_pwm_ops = { 229 .apply = mtk_disp_pwm_apply, 230 .get_state = mtk_disp_pwm_get_state, 231 .owner = THIS_MODULE, 232 }; 233 234 static int mtk_disp_pwm_probe(struct platform_device *pdev) 235 { 236 struct mtk_disp_pwm *mdp; 237 int ret; 238 239 mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL); 240 if (!mdp) 241 return -ENOMEM; 242 243 mdp->data = of_device_get_match_data(&pdev->dev); 244 245 mdp->base = devm_platform_ioremap_resource(pdev, 0); 246 if (IS_ERR(mdp->base)) 247 return PTR_ERR(mdp->base); 248 249 mdp->clk_main = devm_clk_get(&pdev->dev, "main"); 250 if (IS_ERR(mdp->clk_main)) 251 return PTR_ERR(mdp->clk_main); 252 253 mdp->clk_mm = devm_clk_get(&pdev->dev, "mm"); 254 if (IS_ERR(mdp->clk_mm)) 255 return PTR_ERR(mdp->clk_mm); 256 257 mdp->chip.dev = &pdev->dev; 258 mdp->chip.ops = &mtk_disp_pwm_ops; 259 mdp->chip.npwm = 1; 260 261 ret = pwmchip_add(&mdp->chip); 262 if (ret < 0) { 263 dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret)); 264 return ret; 265 } 266 267 platform_set_drvdata(pdev, mdp); 268 269 return 0; 270 } 271 272 static void mtk_disp_pwm_remove(struct platform_device *pdev) 273 { 274 struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev); 275 276 pwmchip_remove(&mdp->chip); 277 } 278 279 static const struct mtk_pwm_data mt2701_pwm_data = { 280 .enable_mask = BIT(16), 281 .con0 = 0xa8, 282 .con0_sel = 0x2, 283 .con1 = 0xac, 284 .has_commit = false, 285 .bls_debug = 0xb0, 286 .bls_debug_mask = 0x3, 287 }; 288 289 static const struct mtk_pwm_data mt8173_pwm_data = { 290 .enable_mask = BIT(0), 291 .con0 = 0x10, 292 .con0_sel = 0x0, 293 .con1 = 0x14, 294 .has_commit = true, 295 .commit = 0x8, 296 .commit_mask = 0x1, 297 }; 298 299 static const struct mtk_pwm_data mt8183_pwm_data = { 300 .enable_mask = BIT(0), 301 .con0 = 0x18, 302 .con0_sel = 0x0, 303 .con1 = 0x1c, 304 .has_commit = false, 305 .bls_debug = 0x80, 306 .bls_debug_mask = 0x3, 307 }; 308 309 static const struct of_device_id mtk_disp_pwm_of_match[] = { 310 { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data}, 311 { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data}, 312 { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data}, 313 { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data}, 314 { } 315 }; 316 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match); 317 318 static struct platform_driver mtk_disp_pwm_driver = { 319 .driver = { 320 .name = "mediatek-disp-pwm", 321 .of_match_table = mtk_disp_pwm_of_match, 322 }, 323 .probe = mtk_disp_pwm_probe, 324 .remove_new = mtk_disp_pwm_remove, 325 }; 326 module_platform_driver(mtk_disp_pwm_driver); 327 328 MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>"); 329 MODULE_DESCRIPTION("MediaTek SoC display PWM driver"); 330 MODULE_LICENSE("GPL v2"); 331