1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 aliases { 33 mmc1 = &sdhc_1; 34 mmc2 = &sdhc_2; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi3 = &spi3; 50 spi5 = &spi5; 51 spi6 = &spi6; 52 spi8 = &spi8; 53 spi10 = &spi10; 54 spi11 = &spi11; 55 }; 56 57 clocks { 58 xo_board: xo-board { 59 compatible = "fixed-clock"; 60 clock-frequency = <38400000>; 61 #clock-cells = <0>; 62 }; 63 64 sleep_clk: sleep-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <32764>; 67 #clock-cells = <0>; 68 }; 69 }; 70 71 reserved_memory: reserved-memory { 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 hyp_mem: memory@80000000 { 77 reg = <0x0 0x80000000 0x0 0x600000>; 78 no-map; 79 }; 80 81 xbl_mem: memory@80600000 { 82 reg = <0x0 0x80600000 0x0 0x200000>; 83 no-map; 84 }; 85 86 aop_mem: memory@80800000 { 87 reg = <0x0 0x80800000 0x0 0x20000>; 88 no-map; 89 }; 90 91 aop_cmd_db_mem: memory@80820000 { 92 reg = <0x0 0x80820000 0x0 0x20000>; 93 compatible = "qcom,cmd-db"; 94 no-map; 95 }; 96 97 sec_apps_mem: memory@808ff000 { 98 reg = <0x0 0x808ff000 0x0 0x1000>; 99 no-map; 100 }; 101 102 smem_mem: memory@80900000 { 103 reg = <0x0 0x80900000 0x0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@80b00000 { 108 reg = <0x0 0x80b00000 0x0 0x3900000>; 109 no-map; 110 }; 111 112 ipa_fw_mem: memory@8b700000 { 113 reg = <0 0x8b700000 0 0x10000>; 114 no-map; 115 }; 116 117 rmtfs_mem: memory@94600000 { 118 compatible = "qcom,rmtfs-mem"; 119 reg = <0x0 0x94600000 0x0 0x200000>; 120 no-map; 121 122 qcom,client-id = <1>; 123 qcom,vmid = <15>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <2>; 129 #size-cells = <0>; 130 131 CPU0: cpu@0 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo468"; 134 reg = <0x0 0x0>; 135 enable-method = "psci"; 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 137 &LITTLE_CPU_SLEEP_1 138 &CLUSTER_SLEEP_0>; 139 capacity-dmips-mhz = <415>; 140 dynamic-power-coefficient = <137>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 144 next-level-cache = <&L2_0>; 145 #cooling-cells = <2>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 L2_0: l2-cache { 148 compatible = "cache"; 149 next-level-cache = <&L3_0>; 150 L3_0: l3-cache { 151 compatible = "cache"; 152 }; 153 }; 154 }; 155 156 CPU1: cpu@100 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo468"; 159 reg = <0x0 0x100>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 capacity-dmips-mhz = <415>; 165 dynamic-power-coefficient = <137>; 166 next-level-cache = <&L2_100>; 167 operating-points-v2 = <&cpu0_opp_table>; 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 #cooling-cells = <2>; 171 qcom,freq-domain = <&cpufreq_hw 0>; 172 L2_100: l2-cache { 173 compatible = "cache"; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU2: cpu@200 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo468"; 181 reg = <0x0 0x200>; 182 enable-method = "psci"; 183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 184 &LITTLE_CPU_SLEEP_1 185 &CLUSTER_SLEEP_0>; 186 capacity-dmips-mhz = <415>; 187 dynamic-power-coefficient = <137>; 188 next-level-cache = <&L2_200>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 192 #cooling-cells = <2>; 193 qcom,freq-domain = <&cpufreq_hw 0>; 194 L2_200: l2-cache { 195 compatible = "cache"; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU3: cpu@300 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo468"; 203 reg = <0x0 0x300>; 204 enable-method = "psci"; 205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 206 &LITTLE_CPU_SLEEP_1 207 &CLUSTER_SLEEP_0>; 208 capacity-dmips-mhz = <415>; 209 dynamic-power-coefficient = <137>; 210 next-level-cache = <&L2_300>; 211 operating-points-v2 = <&cpu0_opp_table>; 212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 #cooling-cells = <2>; 215 qcom,freq-domain = <&cpufreq_hw 0>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo468"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 228 &LITTLE_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 capacity-dmips-mhz = <415>; 231 dynamic-power-coefficient = <137>; 232 next-level-cache = <&L2_400>; 233 operating-points-v2 = <&cpu0_opp_table>; 234 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 236 #cooling-cells = <2>; 237 qcom,freq-domain = <&cpufreq_hw 0>; 238 L2_400: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU5: cpu@500 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo468"; 247 reg = <0x0 0x500>; 248 enable-method = "psci"; 249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 250 &LITTLE_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252 capacity-dmips-mhz = <415>; 253 dynamic-power-coefficient = <137>; 254 next-level-cache = <&L2_500>; 255 operating-points-v2 = <&cpu0_opp_table>; 256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 257 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 258 #cooling-cells = <2>; 259 qcom,freq-domain = <&cpufreq_hw 0>; 260 L2_500: l2-cache { 261 compatible = "cache"; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU6: cpu@600 { 267 device_type = "cpu"; 268 compatible = "qcom,kryo468"; 269 reg = <0x0 0x600>; 270 enable-method = "psci"; 271 cpu-idle-states = <&BIG_CPU_SLEEP_0 272 &BIG_CPU_SLEEP_1 273 &CLUSTER_SLEEP_0>; 274 capacity-dmips-mhz = <1024>; 275 dynamic-power-coefficient = <480>; 276 next-level-cache = <&L2_600>; 277 operating-points-v2 = <&cpu6_opp_table>; 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 280 #cooling-cells = <2>; 281 qcom,freq-domain = <&cpufreq_hw 1>; 282 L2_600: l2-cache { 283 compatible = "cache"; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU7: cpu@700 { 289 device_type = "cpu"; 290 compatible = "qcom,kryo468"; 291 reg = <0x0 0x700>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 capacity-dmips-mhz = <1024>; 297 dynamic-power-coefficient = <480>; 298 next-level-cache = <&L2_700>; 299 operating-points-v2 = <&cpu6_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 302 #cooling-cells = <2>; 303 qcom,freq-domain = <&cpufreq_hw 1>; 304 L2_700: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 cpu-map { 311 cluster0 { 312 core0 { 313 cpu = <&CPU0>; 314 }; 315 316 core1 { 317 cpu = <&CPU1>; 318 }; 319 320 core2 { 321 cpu = <&CPU2>; 322 }; 323 324 core3 { 325 cpu = <&CPU3>; 326 }; 327 328 core4 { 329 cpu = <&CPU4>; 330 }; 331 332 core5 { 333 cpu = <&CPU5>; 334 }; 335 336 core6 { 337 cpu = <&CPU6>; 338 }; 339 340 core7 { 341 cpu = <&CPU7>; 342 }; 343 }; 344 }; 345 346 idle-states { 347 entry-method = "psci"; 348 349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "little-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <549>; 354 exit-latency-us = <901>; 355 min-residency-us = <1774>; 356 local-timer-stop; 357 }; 358 359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "little-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <702>; 364 exit-latency-us = <915>; 365 min-residency-us = <4001>; 366 local-timer-stop; 367 }; 368 369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "big-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <523>; 374 exit-latency-us = <1244>; 375 min-residency-us = <2207>; 376 local-timer-stop; 377 }; 378 379 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "big-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <526>; 384 exit-latency-us = <1854>; 385 min-residency-us = <5555>; 386 local-timer-stop; 387 }; 388 389 CLUSTER_SLEEP_0: cluster-sleep-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "cluster-power-down"; 392 arm,psci-suspend-param = <0x40003444>; 393 entry-latency-us = <3263>; 394 exit-latency-us = <6562>; 395 min-residency-us = <9926>; 396 local-timer-stop; 397 }; 398 }; 399 }; 400 401 cpu0_opp_table: opp-table-cpu0 { 402 compatible = "operating-points-v2"; 403 opp-shared; 404 405 cpu0_opp1: opp-300000000 { 406 opp-hz = /bits/ 64 <300000000>; 407 opp-peak-kBps = <1200000 4800000>; 408 }; 409 410 cpu0_opp2: opp-576000000 { 411 opp-hz = /bits/ 64 <576000000>; 412 opp-peak-kBps = <1200000 4800000>; 413 }; 414 415 cpu0_opp3: opp-768000000 { 416 opp-hz = /bits/ 64 <768000000>; 417 opp-peak-kBps = <1200000 4800000>; 418 }; 419 420 cpu0_opp4: opp-1017600000 { 421 opp-hz = /bits/ 64 <1017600000>; 422 opp-peak-kBps = <1804000 8908800>; 423 }; 424 425 cpu0_opp5: opp-1248000000 { 426 opp-hz = /bits/ 64 <1248000000>; 427 opp-peak-kBps = <2188000 12902400>; 428 }; 429 430 cpu0_opp6: opp-1324800000 { 431 opp-hz = /bits/ 64 <1324800000>; 432 opp-peak-kBps = <2188000 12902400>; 433 }; 434 435 cpu0_opp7: opp-1516800000 { 436 opp-hz = /bits/ 64 <1516800000>; 437 opp-peak-kBps = <3072000 15052800>; 438 }; 439 440 cpu0_opp8: opp-1612800000 { 441 opp-hz = /bits/ 64 <1612800000>; 442 opp-peak-kBps = <3072000 15052800>; 443 }; 444 445 cpu0_opp9: opp-1708800000 { 446 opp-hz = /bits/ 64 <1708800000>; 447 opp-peak-kBps = <3072000 15052800>; 448 }; 449 450 cpu0_opp10: opp-1804800000 { 451 opp-hz = /bits/ 64 <1804800000>; 452 opp-peak-kBps = <4068000 22425600>; 453 }; 454 }; 455 456 cpu6_opp_table: opp-table-cpu6 { 457 compatible = "operating-points-v2"; 458 opp-shared; 459 460 cpu6_opp1: opp-300000000 { 461 opp-hz = /bits/ 64 <300000000>; 462 opp-peak-kBps = <2188000 8908800>; 463 }; 464 465 cpu6_opp2: opp-652800000 { 466 opp-hz = /bits/ 64 <652800000>; 467 opp-peak-kBps = <2188000 8908800>; 468 }; 469 470 cpu6_opp3: opp-825600000 { 471 opp-hz = /bits/ 64 <825600000>; 472 opp-peak-kBps = <2188000 8908800>; 473 }; 474 475 cpu6_opp4: opp-979200000 { 476 opp-hz = /bits/ 64 <979200000>; 477 opp-peak-kBps = <2188000 8908800>; 478 }; 479 480 cpu6_opp5: opp-1113600000 { 481 opp-hz = /bits/ 64 <1113600000>; 482 opp-peak-kBps = <2188000 8908800>; 483 }; 484 485 cpu6_opp6: opp-1267200000 { 486 opp-hz = /bits/ 64 <1267200000>; 487 opp-peak-kBps = <4068000 12902400>; 488 }; 489 490 cpu6_opp7: opp-1555200000 { 491 opp-hz = /bits/ 64 <1555200000>; 492 opp-peak-kBps = <4068000 15052800>; 493 }; 494 495 cpu6_opp8: opp-1708800000 { 496 opp-hz = /bits/ 64 <1708800000>; 497 opp-peak-kBps = <6220000 19353600>; 498 }; 499 500 cpu6_opp9: opp-1843200000 { 501 opp-hz = /bits/ 64 <1843200000>; 502 opp-peak-kBps = <6220000 19353600>; 503 }; 504 505 cpu6_opp10: opp-1900800000 { 506 opp-hz = /bits/ 64 <1900800000>; 507 opp-peak-kBps = <6220000 22425600>; 508 }; 509 510 cpu6_opp11: opp-1996800000 { 511 opp-hz = /bits/ 64 <1996800000>; 512 opp-peak-kBps = <6220000 22425600>; 513 }; 514 515 cpu6_opp12: opp-2112000000 { 516 opp-hz = /bits/ 64 <2112000000>; 517 opp-peak-kBps = <6220000 22425600>; 518 }; 519 520 cpu6_opp13: opp-2208000000 { 521 opp-hz = /bits/ 64 <2208000000>; 522 opp-peak-kBps = <7216000 22425600>; 523 }; 524 525 cpu6_opp14: opp-2323200000 { 526 opp-hz = /bits/ 64 <2323200000>; 527 opp-peak-kBps = <7216000 22425600>; 528 }; 529 530 cpu6_opp15: opp-2400000000 { 531 opp-hz = /bits/ 64 <2400000000>; 532 opp-peak-kBps = <8532000 23347200>; 533 }; 534 535 cpu6_opp16: opp-2553600000 { 536 opp-hz = /bits/ 64 <2553600000>; 537 opp-peak-kBps = <8532000 23347200>; 538 }; 539 }; 540 541 memory@80000000 { 542 device_type = "memory"; 543 /* We expect the bootloader to fill in the size */ 544 reg = <0 0x80000000 0 0>; 545 }; 546 547 pmu { 548 compatible = "arm,armv8-pmuv3"; 549 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 550 }; 551 552 firmware { 553 scm { 554 compatible = "qcom,scm-sc7180", "qcom,scm"; 555 }; 556 }; 557 558 tcsr_mutex: hwlock { 559 compatible = "qcom,tcsr-mutex"; 560 syscon = <&tcsr_mutex_regs 0 0x1000>; 561 #hwlock-cells = <1>; 562 }; 563 564 smem { 565 compatible = "qcom,smem"; 566 memory-region = <&smem_mem>; 567 hwlocks = <&tcsr_mutex 3>; 568 }; 569 570 smp2p-cdsp { 571 compatible = "qcom,smp2p"; 572 qcom,smem = <94>, <432>; 573 574 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 575 576 mboxes = <&apss_shared 6>; 577 578 qcom,local-pid = <0>; 579 qcom,remote-pid = <5>; 580 581 cdsp_smp2p_out: master-kernel { 582 qcom,entry-name = "master-kernel"; 583 #qcom,smem-state-cells = <1>; 584 }; 585 586 cdsp_smp2p_in: slave-kernel { 587 qcom,entry-name = "slave-kernel"; 588 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 }; 592 }; 593 594 smp2p-lpass { 595 compatible = "qcom,smp2p"; 596 qcom,smem = <443>, <429>; 597 598 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 599 600 mboxes = <&apss_shared 10>; 601 602 qcom,local-pid = <0>; 603 qcom,remote-pid = <2>; 604 605 adsp_smp2p_out: master-kernel { 606 qcom,entry-name = "master-kernel"; 607 #qcom,smem-state-cells = <1>; 608 }; 609 610 adsp_smp2p_in: slave-kernel { 611 qcom,entry-name = "slave-kernel"; 612 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 }; 616 }; 617 618 smp2p-mpss { 619 compatible = "qcom,smp2p"; 620 qcom,smem = <435>, <428>; 621 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 622 mboxes = <&apss_shared 14>; 623 qcom,local-pid = <0>; 624 qcom,remote-pid = <1>; 625 626 modem_smp2p_out: master-kernel { 627 qcom,entry-name = "master-kernel"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 modem_smp2p_in: slave-kernel { 632 qcom,entry-name = "slave-kernel"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 637 ipa_smp2p_out: ipa-ap-to-modem { 638 qcom,entry-name = "ipa"; 639 #qcom,smem-state-cells = <1>; 640 }; 641 642 ipa_smp2p_in: ipa-modem-to-ap { 643 qcom,entry-name = "ipa"; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 }; 648 649 psci { 650 compatible = "arm,psci-1.0"; 651 method = "smc"; 652 }; 653 654 soc: soc@0 { 655 #address-cells = <2>; 656 #size-cells = <2>; 657 ranges = <0 0 0 0 0x10 0>; 658 dma-ranges = <0 0 0 0 0x10 0>; 659 compatible = "simple-bus"; 660 661 gcc: clock-controller@100000 { 662 compatible = "qcom,gcc-sc7180"; 663 reg = <0 0x00100000 0 0x1f0000>; 664 clocks = <&rpmhcc RPMH_CXO_CLK>, 665 <&rpmhcc RPMH_CXO_CLK_A>, 666 <&sleep_clk>; 667 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 668 #clock-cells = <1>; 669 #reset-cells = <1>; 670 #power-domain-cells = <1>; 671 }; 672 673 qfprom: efuse@784000 { 674 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 675 reg = <0 0x00784000 0 0x7a0>, 676 <0 0x00780000 0 0x7a0>, 677 <0 0x00782000 0 0x100>, 678 <0 0x00786000 0 0x1fff>; 679 680 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 681 clock-names = "core"; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 685 qusb2p_hstx_trim: hstx-trim-primary@25b { 686 reg = <0x25b 0x1>; 687 bits = <1 3>; 688 }; 689 690 gpu_speed_bin: gpu_speed_bin@1d2 { 691 reg = <0x1d2 0x2>; 692 bits = <5 8>; 693 }; 694 }; 695 696 sdhc_1: mmc@7c4000 { 697 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 698 reg = <0 0x7c4000 0 0x1000>, 699 <0 0x07c5000 0 0x1000>; 700 reg-names = "hc", "cqhci"; 701 702 iommus = <&apps_smmu 0x60 0x0>; 703 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-names = "hc_irq", "pwr_irq"; 706 707 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 708 <&gcc GCC_SDCC1_APPS_CLK>, 709 <&rpmhcc RPMH_CXO_CLK>; 710 clock-names = "iface", "core", "xo"; 711 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 712 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 713 interconnect-names = "sdhc-ddr","cpu-sdhc"; 714 power-domains = <&rpmhpd SC7180_CX>; 715 operating-points-v2 = <&sdhc1_opp_table>; 716 717 bus-width = <8>; 718 non-removable; 719 supports-cqe; 720 721 mmc-ddr-1_8v; 722 mmc-hs200-1_8v; 723 mmc-hs400-1_8v; 724 mmc-hs400-enhanced-strobe; 725 726 status = "disabled"; 727 728 sdhc1_opp_table: opp-table { 729 compatible = "operating-points-v2"; 730 731 opp-100000000 { 732 opp-hz = /bits/ 64 <100000000>; 733 required-opps = <&rpmhpd_opp_low_svs>; 734 opp-peak-kBps = <1800000 600000>; 735 opp-avg-kBps = <100000 0>; 736 }; 737 738 opp-384000000 { 739 opp-hz = /bits/ 64 <384000000>; 740 required-opps = <&rpmhpd_opp_nom>; 741 opp-peak-kBps = <5400000 1600000>; 742 opp-avg-kBps = <390000 0>; 743 }; 744 }; 745 }; 746 747 qup_opp_table: opp-table-qup { 748 compatible = "operating-points-v2"; 749 750 opp-75000000 { 751 opp-hz = /bits/ 64 <75000000>; 752 required-opps = <&rpmhpd_opp_low_svs>; 753 }; 754 755 opp-100000000 { 756 opp-hz = /bits/ 64 <100000000>; 757 required-opps = <&rpmhpd_opp_svs>; 758 }; 759 760 opp-128000000 { 761 opp-hz = /bits/ 64 <128000000>; 762 required-opps = <&rpmhpd_opp_nom>; 763 }; 764 }; 765 766 qupv3_id_0: geniqup@8c0000 { 767 compatible = "qcom,geni-se-qup"; 768 reg = <0 0x008c0000 0 0x6000>; 769 clock-names = "m-ahb", "s-ahb"; 770 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 771 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 772 #address-cells = <2>; 773 #size-cells = <2>; 774 ranges; 775 iommus = <&apps_smmu 0x43 0x0>; 776 status = "disabled"; 777 778 i2c0: i2c@880000 { 779 compatible = "qcom,geni-i2c"; 780 reg = <0 0x00880000 0 0x4000>; 781 clock-names = "se"; 782 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&qup_i2c0_default>; 785 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 789 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 790 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 791 interconnect-names = "qup-core", "qup-config", 792 "qup-memory"; 793 power-domains = <&rpmhpd SC7180_CX>; 794 required-opps = <&rpmhpd_opp_low_svs>; 795 status = "disabled"; 796 }; 797 798 spi0: spi@880000 { 799 compatible = "qcom,geni-spi"; 800 reg = <0 0x00880000 0 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_spi0_default>; 805 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 power-domains = <&rpmhpd SC7180_CX>; 809 operating-points-v2 = <&qup_opp_table>; 810 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 811 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 812 interconnect-names = "qup-core", "qup-config"; 813 status = "disabled"; 814 }; 815 816 uart0: serial@880000 { 817 compatible = "qcom,geni-uart"; 818 reg = <0 0x00880000 0 0x4000>; 819 clock-names = "se"; 820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&qup_uart0_default>; 823 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 824 power-domains = <&rpmhpd SC7180_CX>; 825 operating-points-v2 = <&qup_opp_table>; 826 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 827 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 828 interconnect-names = "qup-core", "qup-config"; 829 status = "disabled"; 830 }; 831 832 i2c1: i2c@884000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0 0x00884000 0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c1_default>; 839 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 843 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 844 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 845 interconnect-names = "qup-core", "qup-config", 846 "qup-memory"; 847 power-domains = <&rpmhpd SC7180_CX>; 848 required-opps = <&rpmhpd_opp_low_svs>; 849 status = "disabled"; 850 }; 851 852 spi1: spi@884000 { 853 compatible = "qcom,geni-spi"; 854 reg = <0 0x00884000 0 0x4000>; 855 clock-names = "se"; 856 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 857 pinctrl-names = "default"; 858 pinctrl-0 = <&qup_spi1_default>; 859 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 power-domains = <&rpmhpd SC7180_CX>; 863 operating-points-v2 = <&qup_opp_table>; 864 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 865 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 866 interconnect-names = "qup-core", "qup-config"; 867 status = "disabled"; 868 }; 869 870 uart1: serial@884000 { 871 compatible = "qcom,geni-uart"; 872 reg = <0 0x00884000 0 0x4000>; 873 clock-names = "se"; 874 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&qup_uart1_default>; 877 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 878 power-domains = <&rpmhpd SC7180_CX>; 879 operating-points-v2 = <&qup_opp_table>; 880 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 881 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 882 interconnect-names = "qup-core", "qup-config"; 883 status = "disabled"; 884 }; 885 886 i2c2: i2c@888000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0 0x00888000 0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c2_default>; 893 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", 900 "qup-memory"; 901 power-domains = <&rpmhpd SC7180_CX>; 902 required-opps = <&rpmhpd_opp_low_svs>; 903 status = "disabled"; 904 }; 905 906 uart2: serial@888000 { 907 compatible = "qcom,geni-uart"; 908 reg = <0 0x00888000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_uart2_default>; 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 914 power-domains = <&rpmhpd SC7180_CX>; 915 operating-points-v2 = <&qup_opp_table>; 916 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 917 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 918 interconnect-names = "qup-core", "qup-config"; 919 status = "disabled"; 920 }; 921 922 i2c3: i2c@88c000 { 923 compatible = "qcom,geni-i2c"; 924 reg = <0 0x0088c000 0 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_i2c3_default>; 929 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 934 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", 936 "qup-memory"; 937 power-domains = <&rpmhpd SC7180_CX>; 938 required-opps = <&rpmhpd_opp_low_svs>; 939 status = "disabled"; 940 }; 941 942 spi3: spi@88c000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x0088c000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_spi3_default>; 949 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 power-domains = <&rpmhpd SC7180_CX>; 953 operating-points-v2 = <&qup_opp_table>; 954 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 956 interconnect-names = "qup-core", "qup-config"; 957 status = "disabled"; 958 }; 959 960 uart3: serial@88c000 { 961 compatible = "qcom,geni-uart"; 962 reg = <0 0x0088c000 0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_uart3_default>; 967 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 968 power-domains = <&rpmhpd SC7180_CX>; 969 operating-points-v2 = <&qup_opp_table>; 970 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 972 interconnect-names = "qup-core", "qup-config"; 973 status = "disabled"; 974 }; 975 976 i2c4: i2c@890000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0 0x00890000 0 0x4000>; 979 clock-names = "se"; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_i2c4_default>; 983 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 988 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 989 interconnect-names = "qup-core", "qup-config", 990 "qup-memory"; 991 power-domains = <&rpmhpd SC7180_CX>; 992 required-opps = <&rpmhpd_opp_low_svs>; 993 status = "disabled"; 994 }; 995 996 uart4: serial@890000 { 997 compatible = "qcom,geni-uart"; 998 reg = <0 0x00890000 0 0x4000>; 999 clock-names = "se"; 1000 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&qup_uart4_default>; 1003 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1004 power-domains = <&rpmhpd SC7180_CX>; 1005 operating-points-v2 = <&qup_opp_table>; 1006 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1007 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1008 interconnect-names = "qup-core", "qup-config"; 1009 status = "disabled"; 1010 }; 1011 1012 i2c5: i2c@894000 { 1013 compatible = "qcom,geni-i2c"; 1014 reg = <0 0x00894000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_i2c5_default>; 1019 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1023 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1024 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1025 interconnect-names = "qup-core", "qup-config", 1026 "qup-memory"; 1027 power-domains = <&rpmhpd SC7180_CX>; 1028 required-opps = <&rpmhpd_opp_low_svs>; 1029 status = "disabled"; 1030 }; 1031 1032 spi5: spi@894000 { 1033 compatible = "qcom,geni-spi"; 1034 reg = <0 0x00894000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_spi5_default>; 1039 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 power-domains = <&rpmhpd SC7180_CX>; 1043 operating-points-v2 = <&qup_opp_table>; 1044 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1046 interconnect-names = "qup-core", "qup-config"; 1047 status = "disabled"; 1048 }; 1049 1050 uart5: serial@894000 { 1051 compatible = "qcom,geni-uart"; 1052 reg = <0 0x00894000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&qup_uart5_default>; 1057 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1058 power-domains = <&rpmhpd SC7180_CX>; 1059 operating-points-v2 = <&qup_opp_table>; 1060 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1062 interconnect-names = "qup-core", "qup-config"; 1063 status = "disabled"; 1064 }; 1065 }; 1066 1067 qupv3_id_1: geniqup@ac0000 { 1068 compatible = "qcom,geni-se-qup"; 1069 reg = <0 0x00ac0000 0 0x6000>; 1070 clock-names = "m-ahb", "s-ahb"; 1071 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1072 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1073 #address-cells = <2>; 1074 #size-cells = <2>; 1075 ranges; 1076 iommus = <&apps_smmu 0x4c3 0x0>; 1077 status = "disabled"; 1078 1079 i2c6: i2c@a80000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x00a80000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_i2c6_default>; 1086 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1090 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1091 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1092 interconnect-names = "qup-core", "qup-config", 1093 "qup-memory"; 1094 power-domains = <&rpmhpd SC7180_CX>; 1095 required-opps = <&rpmhpd_opp_low_svs>; 1096 status = "disabled"; 1097 }; 1098 1099 spi6: spi@a80000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0 0x00a80000 0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_spi6_default>; 1106 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 power-domains = <&rpmhpd SC7180_CX>; 1110 operating-points-v2 = <&qup_opp_table>; 1111 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1112 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1113 interconnect-names = "qup-core", "qup-config"; 1114 status = "disabled"; 1115 }; 1116 1117 uart6: serial@a80000 { 1118 compatible = "qcom,geni-uart"; 1119 reg = <0 0x00a80000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_uart6_default>; 1124 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1125 power-domains = <&rpmhpd SC7180_CX>; 1126 operating-points-v2 = <&qup_opp_table>; 1127 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1128 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1129 interconnect-names = "qup-core", "qup-config"; 1130 status = "disabled"; 1131 }; 1132 1133 i2c7: i2c@a84000 { 1134 compatible = "qcom,geni-i2c"; 1135 reg = <0 0x00a84000 0 0x4000>; 1136 clock-names = "se"; 1137 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_i2c7_default>; 1140 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1145 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1146 interconnect-names = "qup-core", "qup-config", 1147 "qup-memory"; 1148 power-domains = <&rpmhpd SC7180_CX>; 1149 required-opps = <&rpmhpd_opp_low_svs>; 1150 status = "disabled"; 1151 }; 1152 1153 uart7: serial@a84000 { 1154 compatible = "qcom,geni-uart"; 1155 reg = <0 0x00a84000 0 0x4000>; 1156 clock-names = "se"; 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_uart7_default>; 1160 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1161 power-domains = <&rpmhpd SC7180_CX>; 1162 operating-points-v2 = <&qup_opp_table>; 1163 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1165 interconnect-names = "qup-core", "qup-config"; 1166 status = "disabled"; 1167 }; 1168 1169 i2c8: i2c@a88000 { 1170 compatible = "qcom,geni-i2c"; 1171 reg = <0 0x00a88000 0 0x4000>; 1172 clock-names = "se"; 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_i2c8_default>; 1176 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1180 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1181 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1182 interconnect-names = "qup-core", "qup-config", 1183 "qup-memory"; 1184 power-domains = <&rpmhpd SC7180_CX>; 1185 required-opps = <&rpmhpd_opp_low_svs>; 1186 status = "disabled"; 1187 }; 1188 1189 spi8: spi@a88000 { 1190 compatible = "qcom,geni-spi"; 1191 reg = <0 0x00a88000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_spi8_default>; 1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 power-domains = <&rpmhpd SC7180_CX>; 1200 operating-points-v2 = <&qup_opp_table>; 1201 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1202 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1203 interconnect-names = "qup-core", "qup-config"; 1204 status = "disabled"; 1205 }; 1206 1207 uart8: serial@a88000 { 1208 compatible = "qcom,geni-debug-uart"; 1209 reg = <0 0x00a88000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_uart8_default>; 1214 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd SC7180_CX>; 1216 operating-points-v2 = <&qup_opp_table>; 1217 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1218 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1219 interconnect-names = "qup-core", "qup-config"; 1220 status = "disabled"; 1221 }; 1222 1223 i2c9: i2c@a8c000 { 1224 compatible = "qcom,geni-i2c"; 1225 reg = <0 0x00a8c000 0 0x4000>; 1226 clock-names = "se"; 1227 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&qup_i2c9_default>; 1230 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1234 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1235 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1236 interconnect-names = "qup-core", "qup-config", 1237 "qup-memory"; 1238 power-domains = <&rpmhpd SC7180_CX>; 1239 required-opps = <&rpmhpd_opp_low_svs>; 1240 status = "disabled"; 1241 }; 1242 1243 uart9: serial@a8c000 { 1244 compatible = "qcom,geni-uart"; 1245 reg = <0 0x00a8c000 0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_uart9_default>; 1250 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1251 power-domains = <&rpmhpd SC7180_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1255 interconnect-names = "qup-core", "qup-config"; 1256 status = "disabled"; 1257 }; 1258 1259 i2c10: i2c@a90000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0 0x00a90000 0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_i2c10_default>; 1266 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1270 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1271 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1272 interconnect-names = "qup-core", "qup-config", 1273 "qup-memory"; 1274 power-domains = <&rpmhpd SC7180_CX>; 1275 required-opps = <&rpmhpd_opp_low_svs>; 1276 status = "disabled"; 1277 }; 1278 1279 spi10: spi@a90000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0 0x00a90000 0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi10_default>; 1286 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 power-domains = <&rpmhpd SC7180_CX>; 1290 operating-points-v2 = <&qup_opp_table>; 1291 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1292 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1293 interconnect-names = "qup-core", "qup-config"; 1294 status = "disabled"; 1295 }; 1296 1297 uart10: serial@a90000 { 1298 compatible = "qcom,geni-uart"; 1299 reg = <0 0x00a90000 0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_uart10_default>; 1304 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1305 power-domains = <&rpmhpd SC7180_CX>; 1306 operating-points-v2 = <&qup_opp_table>; 1307 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1308 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 status = "disabled"; 1311 }; 1312 1313 i2c11: i2c@a94000 { 1314 compatible = "qcom,geni-i2c"; 1315 reg = <0 0x00a94000 0 0x4000>; 1316 clock-names = "se"; 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_i2c11_default>; 1320 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1324 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1325 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1326 interconnect-names = "qup-core", "qup-config", 1327 "qup-memory"; 1328 power-domains = <&rpmhpd SC7180_CX>; 1329 required-opps = <&rpmhpd_opp_low_svs>; 1330 status = "disabled"; 1331 }; 1332 1333 spi11: spi@a94000 { 1334 compatible = "qcom,geni-spi"; 1335 reg = <0 0x00a94000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_spi11_default>; 1340 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 power-domains = <&rpmhpd SC7180_CX>; 1344 operating-points-v2 = <&qup_opp_table>; 1345 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1346 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1347 interconnect-names = "qup-core", "qup-config"; 1348 status = "disabled"; 1349 }; 1350 1351 uart11: serial@a94000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0 0x00a94000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&qup_uart11_default>; 1358 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1359 power-domains = <&rpmhpd SC7180_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 status = "disabled"; 1365 }; 1366 }; 1367 1368 config_noc: interconnect@1500000 { 1369 compatible = "qcom,sc7180-config-noc"; 1370 reg = <0 0x01500000 0 0x28000>; 1371 #interconnect-cells = <2>; 1372 qcom,bcm-voters = <&apps_bcm_voter>; 1373 }; 1374 1375 system_noc: interconnect@1620000 { 1376 compatible = "qcom,sc7180-system-noc"; 1377 reg = <0 0x01620000 0 0x17080>; 1378 #interconnect-cells = <2>; 1379 qcom,bcm-voters = <&apps_bcm_voter>; 1380 }; 1381 1382 mc_virt: interconnect@1638000 { 1383 compatible = "qcom,sc7180-mc-virt"; 1384 reg = <0 0x01638000 0 0x1000>; 1385 #interconnect-cells = <2>; 1386 qcom,bcm-voters = <&apps_bcm_voter>; 1387 }; 1388 1389 qup_virt: interconnect@1650000 { 1390 compatible = "qcom,sc7180-qup-virt"; 1391 reg = <0 0x01650000 0 0x1000>; 1392 #interconnect-cells = <2>; 1393 qcom,bcm-voters = <&apps_bcm_voter>; 1394 }; 1395 1396 aggre1_noc: interconnect@16e0000 { 1397 compatible = "qcom,sc7180-aggre1-noc"; 1398 reg = <0 0x016e0000 0 0x15080>; 1399 #interconnect-cells = <2>; 1400 qcom,bcm-voters = <&apps_bcm_voter>; 1401 }; 1402 1403 aggre2_noc: interconnect@1705000 { 1404 compatible = "qcom,sc7180-aggre2-noc"; 1405 reg = <0 0x01705000 0 0x9000>; 1406 #interconnect-cells = <2>; 1407 qcom,bcm-voters = <&apps_bcm_voter>; 1408 }; 1409 1410 compute_noc: interconnect@170e000 { 1411 compatible = "qcom,sc7180-compute-noc"; 1412 reg = <0 0x0170e000 0 0x6000>; 1413 #interconnect-cells = <2>; 1414 qcom,bcm-voters = <&apps_bcm_voter>; 1415 }; 1416 1417 mmss_noc: interconnect@1740000 { 1418 compatible = "qcom,sc7180-mmss-noc"; 1419 reg = <0 0x01740000 0 0x1c100>; 1420 #interconnect-cells = <2>; 1421 qcom,bcm-voters = <&apps_bcm_voter>; 1422 }; 1423 1424 ipa: ipa@1e40000 { 1425 compatible = "qcom,sc7180-ipa"; 1426 1427 iommus = <&apps_smmu 0x440 0x0>, 1428 <&apps_smmu 0x442 0x0>; 1429 reg = <0 0x1e40000 0 0x7000>, 1430 <0 0x1e47000 0 0x2000>, 1431 <0 0x1e04000 0 0x2c000>; 1432 reg-names = "ipa-reg", 1433 "ipa-shared", 1434 "gsi"; 1435 1436 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1437 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1438 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1439 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1440 interrupt-names = "ipa", 1441 "gsi", 1442 "ipa-clock-query", 1443 "ipa-setup-ready"; 1444 1445 clocks = <&rpmhcc RPMH_IPA_CLK>; 1446 clock-names = "core"; 1447 1448 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1449 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1450 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1451 interconnect-names = "memory", 1452 "imem", 1453 "config"; 1454 1455 qcom,qmp = <&aoss_qmp>; 1456 1457 qcom,smem-states = <&ipa_smp2p_out 0>, 1458 <&ipa_smp2p_out 1>; 1459 qcom,smem-state-names = "ipa-clock-enabled-valid", 1460 "ipa-clock-enabled"; 1461 1462 status = "disabled"; 1463 }; 1464 1465 tcsr_mutex_regs: syscon@1f40000 { 1466 compatible = "syscon"; 1467 reg = <0 0x01f40000 0 0x40000>; 1468 }; 1469 1470 tcsr_regs: syscon@1fc0000 { 1471 compatible = "syscon"; 1472 reg = <0 0x01fc0000 0 0x40000>; 1473 }; 1474 1475 tlmm: pinctrl@3500000 { 1476 compatible = "qcom,sc7180-pinctrl"; 1477 reg = <0 0x03500000 0 0x300000>, 1478 <0 0x03900000 0 0x300000>, 1479 <0 0x03d00000 0 0x300000>; 1480 reg-names = "west", "north", "south"; 1481 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1482 gpio-controller; 1483 #gpio-cells = <2>; 1484 interrupt-controller; 1485 #interrupt-cells = <2>; 1486 gpio-ranges = <&tlmm 0 0 120>; 1487 wakeup-parent = <&pdc>; 1488 1489 dp_hot_plug_det: dp-hot-plug-det { 1490 pinmux { 1491 pins = "gpio117"; 1492 function = "dp_hot"; 1493 }; 1494 }; 1495 1496 qspi_clk: qspi-clk { 1497 pinmux { 1498 pins = "gpio63"; 1499 function = "qspi_clk"; 1500 }; 1501 }; 1502 1503 qspi_cs0: qspi-cs0 { 1504 pinmux { 1505 pins = "gpio68"; 1506 function = "qspi_cs"; 1507 }; 1508 }; 1509 1510 qspi_cs1: qspi-cs1 { 1511 pinmux { 1512 pins = "gpio72"; 1513 function = "qspi_cs"; 1514 }; 1515 }; 1516 1517 qspi_data01: qspi-data01 { 1518 pinmux-data { 1519 pins = "gpio64", "gpio65"; 1520 function = "qspi_data"; 1521 }; 1522 }; 1523 1524 qspi_data12: qspi-data12 { 1525 pinmux-data { 1526 pins = "gpio66", "gpio67"; 1527 function = "qspi_data"; 1528 }; 1529 }; 1530 1531 qup_i2c0_default: qup-i2c0-default { 1532 pinmux { 1533 pins = "gpio34", "gpio35"; 1534 function = "qup00"; 1535 }; 1536 }; 1537 1538 qup_i2c1_default: qup-i2c1-default { 1539 pinmux { 1540 pins = "gpio0", "gpio1"; 1541 function = "qup01"; 1542 }; 1543 }; 1544 1545 qup_i2c2_default: qup-i2c2-default { 1546 pinmux { 1547 pins = "gpio15", "gpio16"; 1548 function = "qup02_i2c"; 1549 }; 1550 }; 1551 1552 qup_i2c3_default: qup-i2c3-default { 1553 pinmux { 1554 pins = "gpio38", "gpio39"; 1555 function = "qup03"; 1556 }; 1557 }; 1558 1559 qup_i2c4_default: qup-i2c4-default { 1560 pinmux { 1561 pins = "gpio115", "gpio116"; 1562 function = "qup04_i2c"; 1563 }; 1564 }; 1565 1566 qup_i2c5_default: qup-i2c5-default { 1567 pinmux { 1568 pins = "gpio25", "gpio26"; 1569 function = "qup05"; 1570 }; 1571 }; 1572 1573 qup_i2c6_default: qup-i2c6-default { 1574 pinmux { 1575 pins = "gpio59", "gpio60"; 1576 function = "qup10"; 1577 }; 1578 }; 1579 1580 qup_i2c7_default: qup-i2c7-default { 1581 pinmux { 1582 pins = "gpio6", "gpio7"; 1583 function = "qup11_i2c"; 1584 }; 1585 }; 1586 1587 qup_i2c8_default: qup-i2c8-default { 1588 pinmux { 1589 pins = "gpio42", "gpio43"; 1590 function = "qup12"; 1591 }; 1592 }; 1593 1594 qup_i2c9_default: qup-i2c9-default { 1595 pinmux { 1596 pins = "gpio46", "gpio47"; 1597 function = "qup13_i2c"; 1598 }; 1599 }; 1600 1601 qup_i2c10_default: qup-i2c10-default { 1602 pinmux { 1603 pins = "gpio86", "gpio87"; 1604 function = "qup14"; 1605 }; 1606 }; 1607 1608 qup_i2c11_default: qup-i2c11-default { 1609 pinmux { 1610 pins = "gpio53", "gpio54"; 1611 function = "qup15"; 1612 }; 1613 }; 1614 1615 qup_spi0_default: qup-spi0-default { 1616 pinmux { 1617 pins = "gpio34", "gpio35", 1618 "gpio36", "gpio37"; 1619 function = "qup00"; 1620 }; 1621 }; 1622 1623 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 1624 pinmux { 1625 pins = "gpio34", "gpio35", 1626 "gpio36"; 1627 function = "qup00"; 1628 }; 1629 1630 pinmux-cs { 1631 pins = "gpio37"; 1632 function = "gpio"; 1633 }; 1634 }; 1635 1636 qup_spi1_default: qup-spi1-default { 1637 pinmux { 1638 pins = "gpio0", "gpio1", 1639 "gpio2", "gpio3"; 1640 function = "qup01"; 1641 }; 1642 }; 1643 1644 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 1645 pinmux { 1646 pins = "gpio0", "gpio1", 1647 "gpio2"; 1648 function = "qup01"; 1649 }; 1650 1651 pinmux-cs { 1652 pins = "gpio3"; 1653 function = "gpio"; 1654 }; 1655 }; 1656 1657 qup_spi3_default: qup-spi3-default { 1658 pinmux { 1659 pins = "gpio38", "gpio39", 1660 "gpio40", "gpio41"; 1661 function = "qup03"; 1662 }; 1663 }; 1664 1665 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 1666 pinmux { 1667 pins = "gpio38", "gpio39", 1668 "gpio40"; 1669 function = "qup03"; 1670 }; 1671 1672 pinmux-cs { 1673 pins = "gpio41"; 1674 function = "gpio"; 1675 }; 1676 }; 1677 1678 qup_spi5_default: qup-spi5-default { 1679 pinmux { 1680 pins = "gpio25", "gpio26", 1681 "gpio27", "gpio28"; 1682 function = "qup05"; 1683 }; 1684 }; 1685 1686 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 1687 pinmux { 1688 pins = "gpio25", "gpio26", 1689 "gpio27"; 1690 function = "qup05"; 1691 }; 1692 1693 pinmux-cs { 1694 pins = "gpio28"; 1695 function = "gpio"; 1696 }; 1697 }; 1698 1699 qup_spi6_default: qup-spi6-default { 1700 pinmux { 1701 pins = "gpio59", "gpio60", 1702 "gpio61", "gpio62"; 1703 function = "qup10"; 1704 }; 1705 }; 1706 1707 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 1708 pinmux { 1709 pins = "gpio59", "gpio60", 1710 "gpio61"; 1711 function = "qup10"; 1712 }; 1713 1714 pinmux-cs { 1715 pins = "gpio62"; 1716 function = "gpio"; 1717 }; 1718 }; 1719 1720 qup_spi8_default: qup-spi8-default { 1721 pinmux { 1722 pins = "gpio42", "gpio43", 1723 "gpio44", "gpio45"; 1724 function = "qup12"; 1725 }; 1726 }; 1727 1728 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 1729 pinmux { 1730 pins = "gpio42", "gpio43", 1731 "gpio44"; 1732 function = "qup12"; 1733 }; 1734 1735 pinmux-cs { 1736 pins = "gpio45"; 1737 function = "gpio"; 1738 }; 1739 }; 1740 1741 qup_spi10_default: qup-spi10-default { 1742 pinmux { 1743 pins = "gpio86", "gpio87", 1744 "gpio88", "gpio89"; 1745 function = "qup14"; 1746 }; 1747 }; 1748 1749 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 1750 pinmux { 1751 pins = "gpio86", "gpio87", 1752 "gpio88"; 1753 function = "qup14"; 1754 }; 1755 1756 pinmux-cs { 1757 pins = "gpio89"; 1758 function = "gpio"; 1759 }; 1760 }; 1761 1762 qup_spi11_default: qup-spi11-default { 1763 pinmux { 1764 pins = "gpio53", "gpio54", 1765 "gpio55", "gpio56"; 1766 function = "qup15"; 1767 }; 1768 }; 1769 1770 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 1771 pinmux { 1772 pins = "gpio53", "gpio54", 1773 "gpio55"; 1774 function = "qup15"; 1775 }; 1776 1777 pinmux-cs { 1778 pins = "gpio56"; 1779 function = "gpio"; 1780 }; 1781 }; 1782 1783 qup_uart0_default: qup-uart0-default { 1784 pinmux { 1785 pins = "gpio34", "gpio35", 1786 "gpio36", "gpio37"; 1787 function = "qup00"; 1788 }; 1789 }; 1790 1791 qup_uart1_default: qup-uart1-default { 1792 pinmux { 1793 pins = "gpio0", "gpio1", 1794 "gpio2", "gpio3"; 1795 function = "qup01"; 1796 }; 1797 }; 1798 1799 qup_uart2_default: qup-uart2-default { 1800 pinmux { 1801 pins = "gpio15", "gpio16"; 1802 function = "qup02_uart"; 1803 }; 1804 }; 1805 1806 qup_uart3_default: qup-uart3-default { 1807 pinmux { 1808 pins = "gpio38", "gpio39", 1809 "gpio40", "gpio41"; 1810 function = "qup03"; 1811 }; 1812 }; 1813 1814 qup_uart4_default: qup-uart4-default { 1815 pinmux { 1816 pins = "gpio115", "gpio116"; 1817 function = "qup04_uart"; 1818 }; 1819 }; 1820 1821 qup_uart5_default: qup-uart5-default { 1822 pinmux { 1823 pins = "gpio25", "gpio26", 1824 "gpio27", "gpio28"; 1825 function = "qup05"; 1826 }; 1827 }; 1828 1829 qup_uart6_default: qup-uart6-default { 1830 pinmux { 1831 pins = "gpio59", "gpio60", 1832 "gpio61", "gpio62"; 1833 function = "qup10"; 1834 }; 1835 }; 1836 1837 qup_uart7_default: qup-uart7-default { 1838 pinmux { 1839 pins = "gpio6", "gpio7"; 1840 function = "qup11_uart"; 1841 }; 1842 }; 1843 1844 qup_uart8_default: qup-uart8-default { 1845 pinmux { 1846 pins = "gpio44", "gpio45"; 1847 function = "qup12"; 1848 }; 1849 }; 1850 1851 qup_uart9_default: qup-uart9-default { 1852 pinmux { 1853 pins = "gpio46", "gpio47"; 1854 function = "qup13_uart"; 1855 }; 1856 }; 1857 1858 qup_uart10_default: qup-uart10-default { 1859 pinmux { 1860 pins = "gpio86", "gpio87", 1861 "gpio88", "gpio89"; 1862 function = "qup14"; 1863 }; 1864 }; 1865 1866 qup_uart11_default: qup-uart11-default { 1867 pinmux { 1868 pins = "gpio53", "gpio54", 1869 "gpio55", "gpio56"; 1870 function = "qup15"; 1871 }; 1872 }; 1873 1874 sec_mi2s_active: sec-mi2s-active { 1875 pinmux { 1876 pins = "gpio49", "gpio50", "gpio51"; 1877 function = "mi2s_1"; 1878 }; 1879 }; 1880 1881 pri_mi2s_active: pri-mi2s-active { 1882 pinmux { 1883 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1884 function = "mi2s_0"; 1885 }; 1886 }; 1887 1888 pri_mi2s_mclk_active: pri-mi2s-mclk-active { 1889 pinmux { 1890 pins = "gpio57"; 1891 function = "lpass_ext"; 1892 }; 1893 }; 1894 }; 1895 1896 remoteproc_mpss: remoteproc@4080000 { 1897 compatible = "qcom,sc7180-mpss-pas"; 1898 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1899 reg-names = "qdsp6", "rmb"; 1900 1901 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1902 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1903 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1904 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1905 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1906 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1907 interrupt-names = "wdog", "fatal", "ready", "handover", 1908 "stop-ack", "shutdown-ack"; 1909 1910 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1911 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1912 <&gcc GCC_MSS_NAV_AXI_CLK>, 1913 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1914 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1915 <&rpmhcc RPMH_CXO_CLK>; 1916 clock-names = "iface", "bus", "nav", "snoc_axi", 1917 "mnoc_axi", "xo"; 1918 1919 power-domains = <&rpmhpd SC7180_CX>, 1920 <&rpmhpd SC7180_MX>, 1921 <&rpmhpd SC7180_MSS>; 1922 power-domain-names = "cx", "mx", "mss"; 1923 1924 memory-region = <&mpss_mem>; 1925 1926 qcom,qmp = <&aoss_qmp>; 1927 1928 qcom,smem-states = <&modem_smp2p_out 0>; 1929 qcom,smem-state-names = "stop"; 1930 1931 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1932 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1933 reset-names = "mss_restart", "pdc_reset"; 1934 1935 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1936 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 1937 1938 status = "disabled"; 1939 1940 glink-edge { 1941 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1942 label = "modem"; 1943 qcom,remote-pid = <1>; 1944 mboxes = <&apss_shared 12>; 1945 }; 1946 }; 1947 1948 gpu: gpu@5000000 { 1949 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1950 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1951 <0 0x05061000 0 0x800>; 1952 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1953 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1954 iommus = <&adreno_smmu 0>; 1955 operating-points-v2 = <&gpu_opp_table>; 1956 qcom,gmu = <&gmu>; 1957 1958 #cooling-cells = <2>; 1959 1960 nvmem-cells = <&gpu_speed_bin>; 1961 nvmem-cell-names = "speed_bin"; 1962 1963 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1964 interconnect-names = "gfx-mem"; 1965 1966 gpu_opp_table: opp-table { 1967 compatible = "operating-points-v2"; 1968 1969 opp-825000000 { 1970 opp-hz = /bits/ 64 <825000000>; 1971 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1972 opp-peak-kBps = <8532000>; 1973 opp-supported-hw = <0x04>; 1974 }; 1975 1976 opp-800000000 { 1977 opp-hz = /bits/ 64 <800000000>; 1978 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1979 opp-peak-kBps = <8532000>; 1980 opp-supported-hw = <0x07>; 1981 }; 1982 1983 opp-650000000 { 1984 opp-hz = /bits/ 64 <650000000>; 1985 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1986 opp-peak-kBps = <7216000>; 1987 opp-supported-hw = <0x07>; 1988 }; 1989 1990 opp-565000000 { 1991 opp-hz = /bits/ 64 <565000000>; 1992 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1993 opp-peak-kBps = <5412000>; 1994 opp-supported-hw = <0x07>; 1995 }; 1996 1997 opp-430000000 { 1998 opp-hz = /bits/ 64 <430000000>; 1999 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2000 opp-peak-kBps = <5412000>; 2001 opp-supported-hw = <0x07>; 2002 }; 2003 2004 opp-355000000 { 2005 opp-hz = /bits/ 64 <355000000>; 2006 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2007 opp-peak-kBps = <3072000>; 2008 opp-supported-hw = <0x07>; 2009 }; 2010 2011 opp-267000000 { 2012 opp-hz = /bits/ 64 <267000000>; 2013 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2014 opp-peak-kBps = <3072000>; 2015 opp-supported-hw = <0x07>; 2016 }; 2017 2018 opp-180000000 { 2019 opp-hz = /bits/ 64 <180000000>; 2020 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2021 opp-peak-kBps = <1804000>; 2022 opp-supported-hw = <0x07>; 2023 }; 2024 }; 2025 }; 2026 2027 adreno_smmu: iommu@5040000 { 2028 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2029 reg = <0 0x05040000 0 0x10000>; 2030 #iommu-cells = <1>; 2031 #global-interrupts = <2>; 2032 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2042 2043 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2044 <&gcc GCC_GPU_CFG_AHB_CLK>; 2045 clock-names = "bus", "iface"; 2046 2047 power-domains = <&gpucc CX_GDSC>; 2048 }; 2049 2050 gmu: gmu@506a000 { 2051 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2052 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2053 <0 0x0b490000 0 0x10000>; 2054 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2055 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2057 interrupt-names = "hfi", "gmu"; 2058 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2059 <&gpucc GPU_CC_CXO_CLK>, 2060 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2061 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2062 clock-names = "gmu", "cxo", "axi", "memnoc"; 2063 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2064 power-domain-names = "cx", "gx"; 2065 iommus = <&adreno_smmu 5>; 2066 operating-points-v2 = <&gmu_opp_table>; 2067 2068 gmu_opp_table: opp-table { 2069 compatible = "operating-points-v2"; 2070 2071 opp-200000000 { 2072 opp-hz = /bits/ 64 <200000000>; 2073 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2074 }; 2075 }; 2076 }; 2077 2078 gpucc: clock-controller@5090000 { 2079 compatible = "qcom,sc7180-gpucc"; 2080 reg = <0 0x05090000 0 0x9000>; 2081 clocks = <&rpmhcc RPMH_CXO_CLK>, 2082 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2083 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2084 clock-names = "bi_tcxo", 2085 "gcc_gpu_gpll0_clk_src", 2086 "gcc_gpu_gpll0_div_clk_src"; 2087 #clock-cells = <1>; 2088 #reset-cells = <1>; 2089 #power-domain-cells = <1>; 2090 }; 2091 2092 stm@6002000 { 2093 compatible = "arm,coresight-stm", "arm,primecell"; 2094 reg = <0 0x06002000 0 0x1000>, 2095 <0 0x16280000 0 0x180000>; 2096 reg-names = "stm-base", "stm-stimulus-base"; 2097 2098 clocks = <&aoss_qmp>; 2099 clock-names = "apb_pclk"; 2100 2101 out-ports { 2102 port { 2103 stm_out: endpoint { 2104 remote-endpoint = <&funnel0_in7>; 2105 }; 2106 }; 2107 }; 2108 }; 2109 2110 funnel@6041000 { 2111 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2112 reg = <0 0x06041000 0 0x1000>; 2113 2114 clocks = <&aoss_qmp>; 2115 clock-names = "apb_pclk"; 2116 2117 out-ports { 2118 port { 2119 funnel0_out: endpoint { 2120 remote-endpoint = <&merge_funnel_in0>; 2121 }; 2122 }; 2123 }; 2124 2125 in-ports { 2126 #address-cells = <1>; 2127 #size-cells = <0>; 2128 2129 port@7 { 2130 reg = <7>; 2131 funnel0_in7: endpoint { 2132 remote-endpoint = <&stm_out>; 2133 }; 2134 }; 2135 }; 2136 }; 2137 2138 funnel@6042000 { 2139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2140 reg = <0 0x06042000 0 0x1000>; 2141 2142 clocks = <&aoss_qmp>; 2143 clock-names = "apb_pclk"; 2144 2145 out-ports { 2146 port { 2147 funnel1_out: endpoint { 2148 remote-endpoint = <&merge_funnel_in1>; 2149 }; 2150 }; 2151 }; 2152 2153 in-ports { 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 2157 port@4 { 2158 reg = <4>; 2159 funnel1_in4: endpoint { 2160 remote-endpoint = <&apss_merge_funnel_out>; 2161 }; 2162 }; 2163 }; 2164 }; 2165 2166 funnel@6045000 { 2167 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2168 reg = <0 0x06045000 0 0x1000>; 2169 2170 clocks = <&aoss_qmp>; 2171 clock-names = "apb_pclk"; 2172 2173 out-ports { 2174 port { 2175 merge_funnel_out: endpoint { 2176 remote-endpoint = <&swao_funnel_in>; 2177 }; 2178 }; 2179 }; 2180 2181 in-ports { 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 2185 port@0 { 2186 reg = <0>; 2187 merge_funnel_in0: endpoint { 2188 remote-endpoint = <&funnel0_out>; 2189 }; 2190 }; 2191 2192 port@1 { 2193 reg = <1>; 2194 merge_funnel_in1: endpoint { 2195 remote-endpoint = <&funnel1_out>; 2196 }; 2197 }; 2198 }; 2199 }; 2200 2201 replicator@6046000 { 2202 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2203 reg = <0 0x06046000 0 0x1000>; 2204 2205 clocks = <&aoss_qmp>; 2206 clock-names = "apb_pclk"; 2207 2208 out-ports { 2209 port { 2210 replicator_out: endpoint { 2211 remote-endpoint = <&etr_in>; 2212 }; 2213 }; 2214 }; 2215 2216 in-ports { 2217 port { 2218 replicator_in: endpoint { 2219 remote-endpoint = <&swao_replicator_out>; 2220 }; 2221 }; 2222 }; 2223 }; 2224 2225 etr@6048000 { 2226 compatible = "arm,coresight-tmc", "arm,primecell"; 2227 reg = <0 0x06048000 0 0x1000>; 2228 iommus = <&apps_smmu 0x04a0 0x20>; 2229 2230 clocks = <&aoss_qmp>; 2231 clock-names = "apb_pclk"; 2232 arm,scatter-gather; 2233 2234 in-ports { 2235 port { 2236 etr_in: endpoint { 2237 remote-endpoint = <&replicator_out>; 2238 }; 2239 }; 2240 }; 2241 }; 2242 2243 funnel@6b04000 { 2244 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2245 reg = <0 0x06b04000 0 0x1000>; 2246 2247 clocks = <&aoss_qmp>; 2248 clock-names = "apb_pclk"; 2249 2250 out-ports { 2251 port { 2252 swao_funnel_out: endpoint { 2253 remote-endpoint = <&etf_in>; 2254 }; 2255 }; 2256 }; 2257 2258 in-ports { 2259 #address-cells = <1>; 2260 #size-cells = <0>; 2261 2262 port@7 { 2263 reg = <7>; 2264 swao_funnel_in: endpoint { 2265 remote-endpoint = <&merge_funnel_out>; 2266 }; 2267 }; 2268 }; 2269 }; 2270 2271 etf@6b05000 { 2272 compatible = "arm,coresight-tmc", "arm,primecell"; 2273 reg = <0 0x06b05000 0 0x1000>; 2274 2275 clocks = <&aoss_qmp>; 2276 clock-names = "apb_pclk"; 2277 2278 out-ports { 2279 port { 2280 etf_out: endpoint { 2281 remote-endpoint = <&swao_replicator_in>; 2282 }; 2283 }; 2284 }; 2285 2286 in-ports { 2287 port { 2288 etf_in: endpoint { 2289 remote-endpoint = <&swao_funnel_out>; 2290 }; 2291 }; 2292 }; 2293 }; 2294 2295 replicator@6b06000 { 2296 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2297 reg = <0 0x06b06000 0 0x1000>; 2298 2299 clocks = <&aoss_qmp>; 2300 clock-names = "apb_pclk"; 2301 qcom,replicator-loses-context; 2302 2303 out-ports { 2304 port { 2305 swao_replicator_out: endpoint { 2306 remote-endpoint = <&replicator_in>; 2307 }; 2308 }; 2309 }; 2310 2311 in-ports { 2312 port { 2313 swao_replicator_in: endpoint { 2314 remote-endpoint = <&etf_out>; 2315 }; 2316 }; 2317 }; 2318 }; 2319 2320 etm@7040000 { 2321 compatible = "arm,coresight-etm4x", "arm,primecell"; 2322 reg = <0 0x07040000 0 0x1000>; 2323 2324 cpu = <&CPU0>; 2325 2326 clocks = <&aoss_qmp>; 2327 clock-names = "apb_pclk"; 2328 arm,coresight-loses-context-with-cpu; 2329 qcom,skip-power-up; 2330 2331 out-ports { 2332 port { 2333 etm0_out: endpoint { 2334 remote-endpoint = <&apss_funnel_in0>; 2335 }; 2336 }; 2337 }; 2338 }; 2339 2340 etm@7140000 { 2341 compatible = "arm,coresight-etm4x", "arm,primecell"; 2342 reg = <0 0x07140000 0 0x1000>; 2343 2344 cpu = <&CPU1>; 2345 2346 clocks = <&aoss_qmp>; 2347 clock-names = "apb_pclk"; 2348 arm,coresight-loses-context-with-cpu; 2349 qcom,skip-power-up; 2350 2351 out-ports { 2352 port { 2353 etm1_out: endpoint { 2354 remote-endpoint = <&apss_funnel_in1>; 2355 }; 2356 }; 2357 }; 2358 }; 2359 2360 etm@7240000 { 2361 compatible = "arm,coresight-etm4x", "arm,primecell"; 2362 reg = <0 0x07240000 0 0x1000>; 2363 2364 cpu = <&CPU2>; 2365 2366 clocks = <&aoss_qmp>; 2367 clock-names = "apb_pclk"; 2368 arm,coresight-loses-context-with-cpu; 2369 qcom,skip-power-up; 2370 2371 out-ports { 2372 port { 2373 etm2_out: endpoint { 2374 remote-endpoint = <&apss_funnel_in2>; 2375 }; 2376 }; 2377 }; 2378 }; 2379 2380 etm@7340000 { 2381 compatible = "arm,coresight-etm4x", "arm,primecell"; 2382 reg = <0 0x07340000 0 0x1000>; 2383 2384 cpu = <&CPU3>; 2385 2386 clocks = <&aoss_qmp>; 2387 clock-names = "apb_pclk"; 2388 arm,coresight-loses-context-with-cpu; 2389 qcom,skip-power-up; 2390 2391 out-ports { 2392 port { 2393 etm3_out: endpoint { 2394 remote-endpoint = <&apss_funnel_in3>; 2395 }; 2396 }; 2397 }; 2398 }; 2399 2400 etm@7440000 { 2401 compatible = "arm,coresight-etm4x", "arm,primecell"; 2402 reg = <0 0x07440000 0 0x1000>; 2403 2404 cpu = <&CPU4>; 2405 2406 clocks = <&aoss_qmp>; 2407 clock-names = "apb_pclk"; 2408 arm,coresight-loses-context-with-cpu; 2409 qcom,skip-power-up; 2410 2411 out-ports { 2412 port { 2413 etm4_out: endpoint { 2414 remote-endpoint = <&apss_funnel_in4>; 2415 }; 2416 }; 2417 }; 2418 }; 2419 2420 etm@7540000 { 2421 compatible = "arm,coresight-etm4x", "arm,primecell"; 2422 reg = <0 0x07540000 0 0x1000>; 2423 2424 cpu = <&CPU5>; 2425 2426 clocks = <&aoss_qmp>; 2427 clock-names = "apb_pclk"; 2428 arm,coresight-loses-context-with-cpu; 2429 qcom,skip-power-up; 2430 2431 out-ports { 2432 port { 2433 etm5_out: endpoint { 2434 remote-endpoint = <&apss_funnel_in5>; 2435 }; 2436 }; 2437 }; 2438 }; 2439 2440 etm@7640000 { 2441 compatible = "arm,coresight-etm4x", "arm,primecell"; 2442 reg = <0 0x07640000 0 0x1000>; 2443 2444 cpu = <&CPU6>; 2445 2446 clocks = <&aoss_qmp>; 2447 clock-names = "apb_pclk"; 2448 arm,coresight-loses-context-with-cpu; 2449 qcom,skip-power-up; 2450 2451 out-ports { 2452 port { 2453 etm6_out: endpoint { 2454 remote-endpoint = <&apss_funnel_in6>; 2455 }; 2456 }; 2457 }; 2458 }; 2459 2460 etm@7740000 { 2461 compatible = "arm,coresight-etm4x", "arm,primecell"; 2462 reg = <0 0x07740000 0 0x1000>; 2463 2464 cpu = <&CPU7>; 2465 2466 clocks = <&aoss_qmp>; 2467 clock-names = "apb_pclk"; 2468 arm,coresight-loses-context-with-cpu; 2469 qcom,skip-power-up; 2470 2471 out-ports { 2472 port { 2473 etm7_out: endpoint { 2474 remote-endpoint = <&apss_funnel_in7>; 2475 }; 2476 }; 2477 }; 2478 }; 2479 2480 funnel@7800000 { /* APSS Funnel */ 2481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2482 reg = <0 0x07800000 0 0x1000>; 2483 2484 clocks = <&aoss_qmp>; 2485 clock-names = "apb_pclk"; 2486 2487 out-ports { 2488 port { 2489 apss_funnel_out: endpoint { 2490 remote-endpoint = <&apss_merge_funnel_in>; 2491 }; 2492 }; 2493 }; 2494 2495 in-ports { 2496 #address-cells = <1>; 2497 #size-cells = <0>; 2498 2499 port@0 { 2500 reg = <0>; 2501 apss_funnel_in0: endpoint { 2502 remote-endpoint = <&etm0_out>; 2503 }; 2504 }; 2505 2506 port@1 { 2507 reg = <1>; 2508 apss_funnel_in1: endpoint { 2509 remote-endpoint = <&etm1_out>; 2510 }; 2511 }; 2512 2513 port@2 { 2514 reg = <2>; 2515 apss_funnel_in2: endpoint { 2516 remote-endpoint = <&etm2_out>; 2517 }; 2518 }; 2519 2520 port@3 { 2521 reg = <3>; 2522 apss_funnel_in3: endpoint { 2523 remote-endpoint = <&etm3_out>; 2524 }; 2525 }; 2526 2527 port@4 { 2528 reg = <4>; 2529 apss_funnel_in4: endpoint { 2530 remote-endpoint = <&etm4_out>; 2531 }; 2532 }; 2533 2534 port@5 { 2535 reg = <5>; 2536 apss_funnel_in5: endpoint { 2537 remote-endpoint = <&etm5_out>; 2538 }; 2539 }; 2540 2541 port@6 { 2542 reg = <6>; 2543 apss_funnel_in6: endpoint { 2544 remote-endpoint = <&etm6_out>; 2545 }; 2546 }; 2547 2548 port@7 { 2549 reg = <7>; 2550 apss_funnel_in7: endpoint { 2551 remote-endpoint = <&etm7_out>; 2552 }; 2553 }; 2554 }; 2555 }; 2556 2557 funnel@7810000 { 2558 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2559 reg = <0 0x07810000 0 0x1000>; 2560 2561 clocks = <&aoss_qmp>; 2562 clock-names = "apb_pclk"; 2563 2564 out-ports { 2565 port { 2566 apss_merge_funnel_out: endpoint { 2567 remote-endpoint = <&funnel1_in4>; 2568 }; 2569 }; 2570 }; 2571 2572 in-ports { 2573 port { 2574 apss_merge_funnel_in: endpoint { 2575 remote-endpoint = <&apss_funnel_out>; 2576 }; 2577 }; 2578 }; 2579 }; 2580 2581 sdhc_2: mmc@8804000 { 2582 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2583 reg = <0 0x08804000 0 0x1000>; 2584 2585 iommus = <&apps_smmu 0x80 0>; 2586 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2588 interrupt-names = "hc_irq", "pwr_irq"; 2589 2590 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2591 <&gcc GCC_SDCC2_APPS_CLK>, 2592 <&rpmhcc RPMH_CXO_CLK>; 2593 clock-names = "iface", "core", "xo"; 2594 2595 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2596 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2597 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2598 power-domains = <&rpmhpd SC7180_CX>; 2599 operating-points-v2 = <&sdhc2_opp_table>; 2600 2601 bus-width = <4>; 2602 2603 status = "disabled"; 2604 2605 sdhc2_opp_table: opp-table { 2606 compatible = "operating-points-v2"; 2607 2608 opp-100000000 { 2609 opp-hz = /bits/ 64 <100000000>; 2610 required-opps = <&rpmhpd_opp_low_svs>; 2611 opp-peak-kBps = <1800000 600000>; 2612 opp-avg-kBps = <100000 0>; 2613 }; 2614 2615 opp-202000000 { 2616 opp-hz = /bits/ 64 <202000000>; 2617 required-opps = <&rpmhpd_opp_nom>; 2618 opp-peak-kBps = <5400000 1600000>; 2619 opp-avg-kBps = <200000 0>; 2620 }; 2621 }; 2622 }; 2623 2624 qspi_opp_table: opp-table-qspi { 2625 compatible = "operating-points-v2"; 2626 2627 opp-75000000 { 2628 opp-hz = /bits/ 64 <75000000>; 2629 required-opps = <&rpmhpd_opp_low_svs>; 2630 }; 2631 2632 opp-150000000 { 2633 opp-hz = /bits/ 64 <150000000>; 2634 required-opps = <&rpmhpd_opp_svs>; 2635 }; 2636 2637 opp-300000000 { 2638 opp-hz = /bits/ 64 <300000000>; 2639 required-opps = <&rpmhpd_opp_nom>; 2640 }; 2641 }; 2642 2643 qspi: spi@88dc000 { 2644 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2645 reg = <0 0x088dc000 0 0x600>; 2646 #address-cells = <1>; 2647 #size-cells = <0>; 2648 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2649 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2650 <&gcc GCC_QSPI_CORE_CLK>; 2651 clock-names = "iface", "core"; 2652 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2653 &config_noc SLAVE_QSPI_0 0>; 2654 interconnect-names = "qspi-config"; 2655 power-domains = <&rpmhpd SC7180_CX>; 2656 operating-points-v2 = <&qspi_opp_table>; 2657 status = "disabled"; 2658 }; 2659 2660 usb_1_hsphy: phy@88e3000 { 2661 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2662 reg = <0 0x088e3000 0 0x400>; 2663 status = "disabled"; 2664 #phy-cells = <0>; 2665 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2666 <&rpmhcc RPMH_CXO_CLK>; 2667 clock-names = "cfg_ahb", "ref"; 2668 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2669 2670 nvmem-cells = <&qusb2p_hstx_trim>; 2671 }; 2672 2673 usb_1_qmpphy: phy-wrapper@88e9000 { 2674 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2675 reg = <0 0x088e9000 0 0x18c>, 2676 <0 0x088e8000 0 0x3c>, 2677 <0 0x088ea000 0 0x18c>; 2678 status = "disabled"; 2679 #address-cells = <2>; 2680 #size-cells = <2>; 2681 ranges; 2682 2683 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2684 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2685 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2686 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2687 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2688 2689 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2690 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2691 reset-names = "phy", "common"; 2692 2693 usb_1_ssphy: usb3-phy@88e9200 { 2694 reg = <0 0x088e9200 0 0x128>, 2695 <0 0x088e9400 0 0x200>, 2696 <0 0x088e9c00 0 0x218>, 2697 <0 0x088e9600 0 0x128>, 2698 <0 0x088e9800 0 0x200>, 2699 <0 0x088e9a00 0 0x18>; 2700 #clock-cells = <0>; 2701 #phy-cells = <0>; 2702 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2703 clock-names = "pipe0"; 2704 clock-output-names = "usb3_phy_pipe_clk_src"; 2705 }; 2706 2707 dp_phy: dp-phy@88ea200 { 2708 reg = <0 0x088ea200 0 0x200>, 2709 <0 0x088ea400 0 0x200>, 2710 <0 0x088eaa00 0 0x200>, 2711 <0 0x088ea600 0 0x200>, 2712 <0 0x088ea800 0 0x200>; 2713 #clock-cells = <1>; 2714 #phy-cells = <0>; 2715 }; 2716 }; 2717 2718 dc_noc: interconnect@9160000 { 2719 compatible = "qcom,sc7180-dc-noc"; 2720 reg = <0 0x09160000 0 0x03200>; 2721 #interconnect-cells = <2>; 2722 qcom,bcm-voters = <&apps_bcm_voter>; 2723 }; 2724 2725 system-cache-controller@9200000 { 2726 compatible = "qcom,sc7180-llcc"; 2727 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2728 reg-names = "llcc_base", "llcc_broadcast_base"; 2729 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2730 }; 2731 2732 gem_noc: interconnect@9680000 { 2733 compatible = "qcom,sc7180-gem-noc"; 2734 reg = <0 0x09680000 0 0x3e200>; 2735 #interconnect-cells = <2>; 2736 qcom,bcm-voters = <&apps_bcm_voter>; 2737 }; 2738 2739 npu_noc: interconnect@9990000 { 2740 compatible = "qcom,sc7180-npu-noc"; 2741 reg = <0 0x09990000 0 0x1600>; 2742 #interconnect-cells = <2>; 2743 qcom,bcm-voters = <&apps_bcm_voter>; 2744 }; 2745 2746 usb_1: usb@a6f8800 { 2747 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2748 reg = <0 0x0a6f8800 0 0x400>; 2749 status = "disabled"; 2750 #address-cells = <2>; 2751 #size-cells = <2>; 2752 ranges; 2753 dma-ranges; 2754 2755 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2756 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2757 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2758 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2759 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2760 clock-names = "cfg_noc", 2761 "core", 2762 "iface", 2763 "sleep", 2764 "mock_utmi"; 2765 2766 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2767 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2768 assigned-clock-rates = <19200000>, <150000000>; 2769 2770 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2771 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2772 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2773 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2774 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2775 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2776 2777 power-domains = <&gcc USB30_PRIM_GDSC>; 2778 2779 resets = <&gcc GCC_USB30_PRIM_BCR>; 2780 2781 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2782 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2783 interconnect-names = "usb-ddr", "apps-usb"; 2784 2785 usb_1_dwc3: usb@a600000 { 2786 compatible = "snps,dwc3"; 2787 reg = <0 0x0a600000 0 0xe000>; 2788 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2789 iommus = <&apps_smmu 0x540 0>; 2790 snps,dis_u2_susphy_quirk; 2791 snps,dis_enblslpm_quirk; 2792 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2793 phy-names = "usb2-phy", "usb3-phy"; 2794 maximum-speed = "super-speed"; 2795 }; 2796 }; 2797 2798 venus: video-codec@aa00000 { 2799 compatible = "qcom,sc7180-venus"; 2800 reg = <0 0x0aa00000 0 0xff000>; 2801 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2802 power-domains = <&videocc VENUS_GDSC>, 2803 <&videocc VCODEC0_GDSC>, 2804 <&rpmhpd SC7180_CX>; 2805 power-domain-names = "venus", "vcodec0", "cx"; 2806 operating-points-v2 = <&venus_opp_table>; 2807 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2808 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2809 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2810 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2811 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2812 clock-names = "core", "iface", "bus", 2813 "vcodec0_core", "vcodec0_bus"; 2814 iommus = <&apps_smmu 0x0c00 0x60>; 2815 memory-region = <&venus_mem>; 2816 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2817 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2818 interconnect-names = "video-mem", "cpu-cfg"; 2819 2820 video-decoder { 2821 compatible = "venus-decoder"; 2822 }; 2823 2824 video-encoder { 2825 compatible = "venus-encoder"; 2826 }; 2827 2828 venus_opp_table: opp-table { 2829 compatible = "operating-points-v2"; 2830 2831 opp-150000000 { 2832 opp-hz = /bits/ 64 <150000000>; 2833 required-opps = <&rpmhpd_opp_low_svs>; 2834 }; 2835 2836 opp-270000000 { 2837 opp-hz = /bits/ 64 <270000000>; 2838 required-opps = <&rpmhpd_opp_svs>; 2839 }; 2840 2841 opp-340000000 { 2842 opp-hz = /bits/ 64 <340000000>; 2843 required-opps = <&rpmhpd_opp_svs_l1>; 2844 }; 2845 2846 opp-434000000 { 2847 opp-hz = /bits/ 64 <434000000>; 2848 required-opps = <&rpmhpd_opp_nom>; 2849 }; 2850 2851 opp-500000097 { 2852 opp-hz = /bits/ 64 <500000097>; 2853 required-opps = <&rpmhpd_opp_turbo>; 2854 }; 2855 }; 2856 }; 2857 2858 videocc: clock-controller@ab00000 { 2859 compatible = "qcom,sc7180-videocc"; 2860 reg = <0 0x0ab00000 0 0x10000>; 2861 clocks = <&rpmhcc RPMH_CXO_CLK>; 2862 clock-names = "bi_tcxo"; 2863 #clock-cells = <1>; 2864 #reset-cells = <1>; 2865 #power-domain-cells = <1>; 2866 }; 2867 2868 camnoc_virt: interconnect@ac00000 { 2869 compatible = "qcom,sc7180-camnoc-virt"; 2870 reg = <0 0x0ac00000 0 0x1000>; 2871 #interconnect-cells = <2>; 2872 qcom,bcm-voters = <&apps_bcm_voter>; 2873 }; 2874 2875 camcc: clock-controller@ad00000 { 2876 compatible = "qcom,sc7180-camcc"; 2877 reg = <0 0x0ad00000 0 0x10000>; 2878 clocks = <&rpmhcc RPMH_CXO_CLK>, 2879 <&gcc GCC_CAMERA_AHB_CLK>, 2880 <&gcc GCC_CAMERA_XO_CLK>; 2881 clock-names = "bi_tcxo", "iface", "xo"; 2882 #clock-cells = <1>; 2883 #reset-cells = <1>; 2884 #power-domain-cells = <1>; 2885 }; 2886 2887 mdss: mdss@ae00000 { 2888 compatible = "qcom,sc7180-mdss"; 2889 reg = <0 0x0ae00000 0 0x1000>; 2890 reg-names = "mdss"; 2891 2892 power-domains = <&dispcc MDSS_GDSC>; 2893 2894 clocks = <&gcc GCC_DISP_AHB_CLK>, 2895 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2896 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2897 clock-names = "iface", "ahb", "core"; 2898 2899 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2900 interrupt-controller; 2901 #interrupt-cells = <1>; 2902 2903 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2904 interconnect-names = "mdp0-mem"; 2905 2906 iommus = <&apps_smmu 0x800 0x2>; 2907 2908 #address-cells = <2>; 2909 #size-cells = <2>; 2910 ranges; 2911 2912 status = "disabled"; 2913 2914 mdp: display-controller@ae01000 { 2915 compatible = "qcom,sc7180-dpu"; 2916 reg = <0 0x0ae01000 0 0x8f000>, 2917 <0 0x0aeb0000 0 0x2008>; 2918 reg-names = "mdp", "vbif"; 2919 2920 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2921 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2922 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2923 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2924 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2925 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2926 clock-names = "bus", "iface", "rot", "lut", "core", 2927 "vsync"; 2928 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2929 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2930 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2931 assigned-clock-rates = <19200000>, 2932 <19200000>, 2933 <19200000>; 2934 operating-points-v2 = <&mdp_opp_table>; 2935 power-domains = <&rpmhpd SC7180_CX>; 2936 2937 interrupt-parent = <&mdss>; 2938 interrupts = <0>; 2939 2940 status = "disabled"; 2941 2942 ports { 2943 #address-cells = <1>; 2944 #size-cells = <0>; 2945 2946 port@0 { 2947 reg = <0>; 2948 dpu_intf1_out: endpoint { 2949 remote-endpoint = <&dsi0_in>; 2950 }; 2951 }; 2952 2953 port@2 { 2954 reg = <2>; 2955 dpu_intf0_out: endpoint { 2956 remote-endpoint = <&dp_in>; 2957 }; 2958 }; 2959 }; 2960 2961 mdp_opp_table: opp-table { 2962 compatible = "operating-points-v2"; 2963 2964 opp-200000000 { 2965 opp-hz = /bits/ 64 <200000000>; 2966 required-opps = <&rpmhpd_opp_low_svs>; 2967 }; 2968 2969 opp-300000000 { 2970 opp-hz = /bits/ 64 <300000000>; 2971 required-opps = <&rpmhpd_opp_svs>; 2972 }; 2973 2974 opp-345000000 { 2975 opp-hz = /bits/ 64 <345000000>; 2976 required-opps = <&rpmhpd_opp_svs_l1>; 2977 }; 2978 2979 opp-460000000 { 2980 opp-hz = /bits/ 64 <460000000>; 2981 required-opps = <&rpmhpd_opp_nom>; 2982 }; 2983 }; 2984 2985 }; 2986 2987 dsi0: dsi@ae94000 { 2988 compatible = "qcom,mdss-dsi-ctrl"; 2989 reg = <0 0x0ae94000 0 0x400>; 2990 reg-names = "dsi_ctrl"; 2991 2992 interrupt-parent = <&mdss>; 2993 interrupts = <4>; 2994 2995 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2996 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2997 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2998 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2999 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3000 <&gcc GCC_DISP_HF_AXI_CLK>; 3001 clock-names = "byte", 3002 "byte_intf", 3003 "pixel", 3004 "core", 3005 "iface", 3006 "bus"; 3007 3008 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3009 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 3010 3011 operating-points-v2 = <&dsi_opp_table>; 3012 power-domains = <&rpmhpd SC7180_CX>; 3013 3014 phys = <&dsi_phy>; 3015 phy-names = "dsi"; 3016 3017 #address-cells = <1>; 3018 #size-cells = <0>; 3019 3020 status = "disabled"; 3021 3022 ports { 3023 #address-cells = <1>; 3024 #size-cells = <0>; 3025 3026 port@0 { 3027 reg = <0>; 3028 dsi0_in: endpoint { 3029 remote-endpoint = <&dpu_intf1_out>; 3030 }; 3031 }; 3032 3033 port@1 { 3034 reg = <1>; 3035 dsi0_out: endpoint { 3036 }; 3037 }; 3038 }; 3039 3040 dsi_opp_table: opp-table { 3041 compatible = "operating-points-v2"; 3042 3043 opp-187500000 { 3044 opp-hz = /bits/ 64 <187500000>; 3045 required-opps = <&rpmhpd_opp_low_svs>; 3046 }; 3047 3048 opp-300000000 { 3049 opp-hz = /bits/ 64 <300000000>; 3050 required-opps = <&rpmhpd_opp_svs>; 3051 }; 3052 3053 opp-358000000 { 3054 opp-hz = /bits/ 64 <358000000>; 3055 required-opps = <&rpmhpd_opp_svs_l1>; 3056 }; 3057 }; 3058 }; 3059 3060 dsi_phy: dsi-phy@ae94400 { 3061 compatible = "qcom,dsi-phy-10nm"; 3062 reg = <0 0x0ae94400 0 0x200>, 3063 <0 0x0ae94600 0 0x280>, 3064 <0 0x0ae94a00 0 0x1e0>; 3065 reg-names = "dsi_phy", 3066 "dsi_phy_lane", 3067 "dsi_pll"; 3068 3069 #clock-cells = <1>; 3070 #phy-cells = <0>; 3071 3072 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3073 <&rpmhcc RPMH_CXO_CLK>; 3074 clock-names = "iface", "ref"; 3075 3076 status = "disabled"; 3077 }; 3078 3079 mdss_dp: displayport-controller@ae90000 { 3080 compatible = "qcom,sc7180-dp"; 3081 status = "disabled"; 3082 3083 reg = <0 0xae90000 0 0x200>, 3084 <0 0xae90200 0 0x200>, 3085 <0 0xae90400 0 0xc00>, 3086 <0 0xae91000 0 0x400>, 3087 <0 0xae91400 0 0x400>; 3088 3089 interrupt-parent = <&mdss>; 3090 interrupts = <12>; 3091 3092 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3093 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3094 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3095 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3096 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3097 clock-names = "core_iface", "core_aux", "ctrl_link", 3098 "ctrl_link_iface", "stream_pixel"; 3099 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3100 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3101 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3102 phys = <&dp_phy>; 3103 phy-names = "dp"; 3104 3105 operating-points-v2 = <&dp_opp_table>; 3106 power-domains = <&rpmhpd SC7180_CX>; 3107 3108 #sound-dai-cells = <0>; 3109 3110 ports { 3111 #address-cells = <1>; 3112 #size-cells = <0>; 3113 port@0 { 3114 reg = <0>; 3115 dp_in: endpoint { 3116 remote-endpoint = <&dpu_intf0_out>; 3117 }; 3118 }; 3119 3120 port@1 { 3121 reg = <1>; 3122 dp_out: endpoint { }; 3123 }; 3124 }; 3125 3126 dp_opp_table: opp-table { 3127 compatible = "operating-points-v2"; 3128 3129 opp-160000000 { 3130 opp-hz = /bits/ 64 <160000000>; 3131 required-opps = <&rpmhpd_opp_low_svs>; 3132 }; 3133 3134 opp-270000000 { 3135 opp-hz = /bits/ 64 <270000000>; 3136 required-opps = <&rpmhpd_opp_svs>; 3137 }; 3138 3139 opp-540000000 { 3140 opp-hz = /bits/ 64 <540000000>; 3141 required-opps = <&rpmhpd_opp_svs_l1>; 3142 }; 3143 3144 opp-810000000 { 3145 opp-hz = /bits/ 64 <810000000>; 3146 required-opps = <&rpmhpd_opp_nom>; 3147 }; 3148 }; 3149 }; 3150 }; 3151 3152 dispcc: clock-controller@af00000 { 3153 compatible = "qcom,sc7180-dispcc"; 3154 reg = <0 0x0af00000 0 0x200000>; 3155 clocks = <&rpmhcc RPMH_CXO_CLK>, 3156 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3157 <&dsi_phy 0>, 3158 <&dsi_phy 1>, 3159 <&dp_phy 0>, 3160 <&dp_phy 1>; 3161 clock-names = "bi_tcxo", 3162 "gcc_disp_gpll0_clk_src", 3163 "dsi0_phy_pll_out_byteclk", 3164 "dsi0_phy_pll_out_dsiclk", 3165 "dp_phy_pll_link_clk", 3166 "dp_phy_pll_vco_div_clk"; 3167 #clock-cells = <1>; 3168 #reset-cells = <1>; 3169 #power-domain-cells = <1>; 3170 }; 3171 3172 pdc: interrupt-controller@b220000 { 3173 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3174 reg = <0 0x0b220000 0 0x30000>; 3175 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3176 #interrupt-cells = <2>; 3177 interrupt-parent = <&intc>; 3178 interrupt-controller; 3179 }; 3180 3181 pdc_reset: reset-controller@b2e0000 { 3182 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3183 reg = <0 0x0b2e0000 0 0x20000>; 3184 #reset-cells = <1>; 3185 }; 3186 3187 tsens0: thermal-sensor@c263000 { 3188 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3189 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3190 <0 0x0c222000 0 0x1ff>; /* SROT */ 3191 #qcom,sensors = <15>; 3192 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3194 interrupt-names = "uplow","critical"; 3195 #thermal-sensor-cells = <1>; 3196 }; 3197 3198 tsens1: thermal-sensor@c265000 { 3199 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3200 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3201 <0 0x0c223000 0 0x1ff>; /* SROT */ 3202 #qcom,sensors = <10>; 3203 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3204 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3205 interrupt-names = "uplow","critical"; 3206 #thermal-sensor-cells = <1>; 3207 }; 3208 3209 aoss_reset: reset-controller@c2a0000 { 3210 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3211 reg = <0 0x0c2a0000 0 0x31000>; 3212 #reset-cells = <1>; 3213 }; 3214 3215 aoss_qmp: power-controller@c300000 { 3216 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3217 reg = <0 0x0c300000 0 0x400>; 3218 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3219 mboxes = <&apss_shared 0>; 3220 3221 #clock-cells = <0>; 3222 }; 3223 3224 sram@c3f0000 { 3225 compatible = "qcom,rpmh-stats"; 3226 reg = <0 0x0c3f0000 0 0x400>; 3227 }; 3228 3229 spmi_bus: spmi@c440000 { 3230 compatible = "qcom,spmi-pmic-arb"; 3231 reg = <0 0x0c440000 0 0x1100>, 3232 <0 0x0c600000 0 0x2000000>, 3233 <0 0x0e600000 0 0x100000>, 3234 <0 0x0e700000 0 0xa0000>, 3235 <0 0x0c40a000 0 0x26000>; 3236 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3237 interrupt-names = "periph_irq"; 3238 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3239 qcom,ee = <0>; 3240 qcom,channel = <0>; 3241 #address-cells = <1>; 3242 #size-cells = <1>; 3243 interrupt-controller; 3244 #interrupt-cells = <4>; 3245 cell-index = <0>; 3246 }; 3247 3248 sram@146aa000 { 3249 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3250 reg = <0 0x146aa000 0 0x2000>; 3251 3252 #address-cells = <1>; 3253 #size-cells = <1>; 3254 3255 ranges = <0 0 0x146aa000 0x2000>; 3256 3257 pil-reloc@94c { 3258 compatible = "qcom,pil-reloc-info"; 3259 reg = <0x94c 0xc8>; 3260 }; 3261 }; 3262 3263 apps_smmu: iommu@15000000 { 3264 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3265 reg = <0 0x15000000 0 0x100000>; 3266 #iommu-cells = <2>; 3267 #global-interrupts = <1>; 3268 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3349 }; 3350 3351 intc: interrupt-controller@17a00000 { 3352 compatible = "arm,gic-v3"; 3353 #address-cells = <2>; 3354 #size-cells = <2>; 3355 ranges; 3356 #interrupt-cells = <3>; 3357 interrupt-controller; 3358 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3359 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3360 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3361 3362 msi-controller@17a40000 { 3363 compatible = "arm,gic-v3-its"; 3364 msi-controller; 3365 #msi-cells = <1>; 3366 reg = <0 0x17a40000 0 0x20000>; 3367 status = "disabled"; 3368 }; 3369 }; 3370 3371 apss_shared: mailbox@17c00000 { 3372 compatible = "qcom,sc7180-apss-shared"; 3373 reg = <0 0x17c00000 0 0x10000>; 3374 #mbox-cells = <1>; 3375 }; 3376 3377 watchdog@17c10000 { 3378 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3379 reg = <0 0x17c10000 0 0x1000>; 3380 clocks = <&sleep_clk>; 3381 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3382 }; 3383 3384 timer@17c20000{ 3385 #address-cells = <1>; 3386 #size-cells = <1>; 3387 ranges = <0 0 0 0x20000000>; 3388 compatible = "arm,armv7-timer-mem"; 3389 reg = <0 0x17c20000 0 0x1000>; 3390 3391 frame@17c21000 { 3392 frame-number = <0>; 3393 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3395 reg = <0x17c21000 0x1000>, 3396 <0x17c22000 0x1000>; 3397 }; 3398 3399 frame@17c23000 { 3400 frame-number = <1>; 3401 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3402 reg = <0x17c23000 0x1000>; 3403 status = "disabled"; 3404 }; 3405 3406 frame@17c25000 { 3407 frame-number = <2>; 3408 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3409 reg = <0x17c25000 0x1000>; 3410 status = "disabled"; 3411 }; 3412 3413 frame@17c27000 { 3414 frame-number = <3>; 3415 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3416 reg = <0x17c27000 0x1000>; 3417 status = "disabled"; 3418 }; 3419 3420 frame@17c29000 { 3421 frame-number = <4>; 3422 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3423 reg = <0x17c29000 0x1000>; 3424 status = "disabled"; 3425 }; 3426 3427 frame@17c2b000 { 3428 frame-number = <5>; 3429 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3430 reg = <0x17c2b000 0x1000>; 3431 status = "disabled"; 3432 }; 3433 3434 frame@17c2d000 { 3435 frame-number = <6>; 3436 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3437 reg = <0x17c2d000 0x1000>; 3438 status = "disabled"; 3439 }; 3440 }; 3441 3442 apps_rsc: rsc@18200000 { 3443 compatible = "qcom,rpmh-rsc"; 3444 reg = <0 0x18200000 0 0x10000>, 3445 <0 0x18210000 0 0x10000>, 3446 <0 0x18220000 0 0x10000>; 3447 reg-names = "drv-0", "drv-1", "drv-2"; 3448 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3451 qcom,tcs-offset = <0xd00>; 3452 qcom,drv-id = <2>; 3453 qcom,tcs-config = <ACTIVE_TCS 2>, 3454 <SLEEP_TCS 3>, 3455 <WAKE_TCS 3>, 3456 <CONTROL_TCS 1>; 3457 3458 rpmhcc: clock-controller { 3459 compatible = "qcom,sc7180-rpmh-clk"; 3460 clocks = <&xo_board>; 3461 clock-names = "xo"; 3462 #clock-cells = <1>; 3463 }; 3464 3465 rpmhpd: power-controller { 3466 compatible = "qcom,sc7180-rpmhpd"; 3467 #power-domain-cells = <1>; 3468 operating-points-v2 = <&rpmhpd_opp_table>; 3469 3470 rpmhpd_opp_table: opp-table { 3471 compatible = "operating-points-v2"; 3472 3473 rpmhpd_opp_ret: opp1 { 3474 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3475 }; 3476 3477 rpmhpd_opp_min_svs: opp2 { 3478 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3479 }; 3480 3481 rpmhpd_opp_low_svs: opp3 { 3482 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3483 }; 3484 3485 rpmhpd_opp_svs: opp4 { 3486 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3487 }; 3488 3489 rpmhpd_opp_svs_l1: opp5 { 3490 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3491 }; 3492 3493 rpmhpd_opp_svs_l2: opp6 { 3494 opp-level = <224>; 3495 }; 3496 3497 rpmhpd_opp_nom: opp7 { 3498 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3499 }; 3500 3501 rpmhpd_opp_nom_l1: opp8 { 3502 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3503 }; 3504 3505 rpmhpd_opp_nom_l2: opp9 { 3506 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3507 }; 3508 3509 rpmhpd_opp_turbo: opp10 { 3510 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3511 }; 3512 3513 rpmhpd_opp_turbo_l1: opp11 { 3514 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3515 }; 3516 }; 3517 }; 3518 3519 apps_bcm_voter: bcm-voter { 3520 compatible = "qcom,bcm-voter"; 3521 }; 3522 }; 3523 3524 osm_l3: interconnect@18321000 { 3525 compatible = "qcom,sc7180-osm-l3"; 3526 reg = <0 0x18321000 0 0x1400>; 3527 3528 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3529 clock-names = "xo", "alternate"; 3530 3531 #interconnect-cells = <1>; 3532 }; 3533 3534 cpufreq_hw: cpufreq@18323000 { 3535 compatible = "qcom,cpufreq-hw"; 3536 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3537 reg-names = "freq-domain0", "freq-domain1"; 3538 3539 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3540 clock-names = "xo", "alternate"; 3541 3542 #freq-domain-cells = <1>; 3543 }; 3544 3545 wifi: wifi@18800000 { 3546 compatible = "qcom,wcn3990-wifi"; 3547 reg = <0 0x18800000 0 0x800000>; 3548 reg-names = "membase"; 3549 iommus = <&apps_smmu 0xc0 0x1>; 3550 interrupts = 3551 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3552 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3553 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3554 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3555 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3556 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3557 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3558 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3559 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3560 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3561 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3562 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3563 memory-region = <&wlan_mem>; 3564 qcom,msa-fixed-perm; 3565 status = "disabled"; 3566 }; 3567 3568 lpasscc: clock-controller@62d00000 { 3569 compatible = "qcom,sc7180-lpasscorecc"; 3570 reg = <0 0x62d00000 0 0x50000>, 3571 <0 0x62780000 0 0x30000>; 3572 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3573 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3574 <&rpmhcc RPMH_CXO_CLK>; 3575 clock-names = "iface", "bi_tcxo"; 3576 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3577 #clock-cells = <1>; 3578 #power-domain-cells = <1>; 3579 }; 3580 3581 lpass_cpu: lpass@62d87000 { 3582 compatible = "qcom,sc7180-lpass-cpu"; 3583 3584 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3585 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3586 3587 iommus = <&apps_smmu 0x1020 0>, 3588 <&apps_smmu 0x1021 0>, 3589 <&apps_smmu 0x1032 0>; 3590 3591 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3592 3593 status = "disabled"; 3594 3595 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3596 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3597 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3598 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3599 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3600 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3601 3602 clock-names = "pcnoc-sway-clk", "audio-core", 3603 "mclk0", "pcnoc-mport-clk", 3604 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3605 3606 3607 #sound-dai-cells = <1>; 3608 #address-cells = <1>; 3609 #size-cells = <0>; 3610 3611 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3613 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3614 }; 3615 3616 lpass_hm: clock-controller@63000000 { 3617 compatible = "qcom,sc7180-lpasshm"; 3618 reg = <0 0x63000000 0 0x28>; 3619 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3620 <&rpmhcc RPMH_CXO_CLK>; 3621 clock-names = "iface", "bi_tcxo"; 3622 #clock-cells = <1>; 3623 #power-domain-cells = <1>; 3624 }; 3625 }; 3626 3627 thermal-zones { 3628 cpu0_thermal: cpu0-thermal { 3629 polling-delay-passive = <250>; 3630 polling-delay = <0>; 3631 3632 thermal-sensors = <&tsens0 1>; 3633 sustainable-power = <1052>; 3634 3635 trips { 3636 cpu0_alert0: trip-point0 { 3637 temperature = <90000>; 3638 hysteresis = <2000>; 3639 type = "passive"; 3640 }; 3641 3642 cpu0_alert1: trip-point1 { 3643 temperature = <95000>; 3644 hysteresis = <2000>; 3645 type = "passive"; 3646 }; 3647 3648 cpu0_crit: cpu_crit { 3649 temperature = <110000>; 3650 hysteresis = <1000>; 3651 type = "critical"; 3652 }; 3653 }; 3654 3655 cooling-maps { 3656 map0 { 3657 trip = <&cpu0_alert0>; 3658 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3659 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3660 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3661 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3662 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3663 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3664 }; 3665 map1 { 3666 trip = <&cpu0_alert1>; 3667 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3668 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3669 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3670 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3671 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3672 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3673 }; 3674 }; 3675 }; 3676 3677 cpu1_thermal: cpu1-thermal { 3678 polling-delay-passive = <250>; 3679 polling-delay = <0>; 3680 3681 thermal-sensors = <&tsens0 2>; 3682 sustainable-power = <1052>; 3683 3684 trips { 3685 cpu1_alert0: trip-point0 { 3686 temperature = <90000>; 3687 hysteresis = <2000>; 3688 type = "passive"; 3689 }; 3690 3691 cpu1_alert1: trip-point1 { 3692 temperature = <95000>; 3693 hysteresis = <2000>; 3694 type = "passive"; 3695 }; 3696 3697 cpu1_crit: cpu_crit { 3698 temperature = <110000>; 3699 hysteresis = <1000>; 3700 type = "critical"; 3701 }; 3702 }; 3703 3704 cooling-maps { 3705 map0 { 3706 trip = <&cpu1_alert0>; 3707 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3708 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3709 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3710 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3711 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3712 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3713 }; 3714 map1 { 3715 trip = <&cpu1_alert1>; 3716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3720 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3721 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3722 }; 3723 }; 3724 }; 3725 3726 cpu2_thermal: cpu2-thermal { 3727 polling-delay-passive = <250>; 3728 polling-delay = <0>; 3729 3730 thermal-sensors = <&tsens0 3>; 3731 sustainable-power = <1052>; 3732 3733 trips { 3734 cpu2_alert0: trip-point0 { 3735 temperature = <90000>; 3736 hysteresis = <2000>; 3737 type = "passive"; 3738 }; 3739 3740 cpu2_alert1: trip-point1 { 3741 temperature = <95000>; 3742 hysteresis = <2000>; 3743 type = "passive"; 3744 }; 3745 3746 cpu2_crit: cpu_crit { 3747 temperature = <110000>; 3748 hysteresis = <1000>; 3749 type = "critical"; 3750 }; 3751 }; 3752 3753 cooling-maps { 3754 map0 { 3755 trip = <&cpu2_alert0>; 3756 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3757 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3758 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3759 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3760 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3762 }; 3763 map1 { 3764 trip = <&cpu2_alert1>; 3765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3767 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3768 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3769 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3770 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3771 }; 3772 }; 3773 }; 3774 3775 cpu3_thermal: cpu3-thermal { 3776 polling-delay-passive = <250>; 3777 polling-delay = <0>; 3778 3779 thermal-sensors = <&tsens0 4>; 3780 sustainable-power = <1052>; 3781 3782 trips { 3783 cpu3_alert0: trip-point0 { 3784 temperature = <90000>; 3785 hysteresis = <2000>; 3786 type = "passive"; 3787 }; 3788 3789 cpu3_alert1: trip-point1 { 3790 temperature = <95000>; 3791 hysteresis = <2000>; 3792 type = "passive"; 3793 }; 3794 3795 cpu3_crit: cpu_crit { 3796 temperature = <110000>; 3797 hysteresis = <1000>; 3798 type = "critical"; 3799 }; 3800 }; 3801 3802 cooling-maps { 3803 map0 { 3804 trip = <&cpu3_alert0>; 3805 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3808 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3809 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3811 }; 3812 map1 { 3813 trip = <&cpu3_alert1>; 3814 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3816 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3817 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3818 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3819 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3820 }; 3821 }; 3822 }; 3823 3824 cpu4_thermal: cpu4-thermal { 3825 polling-delay-passive = <250>; 3826 polling-delay = <0>; 3827 3828 thermal-sensors = <&tsens0 5>; 3829 sustainable-power = <1052>; 3830 3831 trips { 3832 cpu4_alert0: trip-point0 { 3833 temperature = <90000>; 3834 hysteresis = <2000>; 3835 type = "passive"; 3836 }; 3837 3838 cpu4_alert1: trip-point1 { 3839 temperature = <95000>; 3840 hysteresis = <2000>; 3841 type = "passive"; 3842 }; 3843 3844 cpu4_crit: cpu_crit { 3845 temperature = <110000>; 3846 hysteresis = <1000>; 3847 type = "critical"; 3848 }; 3849 }; 3850 3851 cooling-maps { 3852 map0 { 3853 trip = <&cpu4_alert0>; 3854 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3855 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3860 }; 3861 map1 { 3862 trip = <&cpu4_alert1>; 3863 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3864 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3865 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3869 }; 3870 }; 3871 }; 3872 3873 cpu5_thermal: cpu5-thermal { 3874 polling-delay-passive = <250>; 3875 polling-delay = <0>; 3876 3877 thermal-sensors = <&tsens0 6>; 3878 sustainable-power = <1052>; 3879 3880 trips { 3881 cpu5_alert0: trip-point0 { 3882 temperature = <90000>; 3883 hysteresis = <2000>; 3884 type = "passive"; 3885 }; 3886 3887 cpu5_alert1: trip-point1 { 3888 temperature = <95000>; 3889 hysteresis = <2000>; 3890 type = "passive"; 3891 }; 3892 3893 cpu5_crit: cpu_crit { 3894 temperature = <110000>; 3895 hysteresis = <1000>; 3896 type = "critical"; 3897 }; 3898 }; 3899 3900 cooling-maps { 3901 map0 { 3902 trip = <&cpu5_alert0>; 3903 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3904 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3905 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3906 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3907 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3908 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3909 }; 3910 map1 { 3911 trip = <&cpu5_alert1>; 3912 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3914 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3915 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3916 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3917 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3918 }; 3919 }; 3920 }; 3921 3922 cpu6_thermal: cpu6-thermal { 3923 polling-delay-passive = <250>; 3924 polling-delay = <0>; 3925 3926 thermal-sensors = <&tsens0 9>; 3927 sustainable-power = <1425>; 3928 3929 trips { 3930 cpu6_alert0: trip-point0 { 3931 temperature = <90000>; 3932 hysteresis = <2000>; 3933 type = "passive"; 3934 }; 3935 3936 cpu6_alert1: trip-point1 { 3937 temperature = <95000>; 3938 hysteresis = <2000>; 3939 type = "passive"; 3940 }; 3941 3942 cpu6_crit: cpu_crit { 3943 temperature = <110000>; 3944 hysteresis = <1000>; 3945 type = "critical"; 3946 }; 3947 }; 3948 3949 cooling-maps { 3950 map0 { 3951 trip = <&cpu6_alert0>; 3952 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3953 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3954 }; 3955 map1 { 3956 trip = <&cpu6_alert1>; 3957 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3958 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3959 }; 3960 }; 3961 }; 3962 3963 cpu7_thermal: cpu7-thermal { 3964 polling-delay-passive = <250>; 3965 polling-delay = <0>; 3966 3967 thermal-sensors = <&tsens0 10>; 3968 sustainable-power = <1425>; 3969 3970 trips { 3971 cpu7_alert0: trip-point0 { 3972 temperature = <90000>; 3973 hysteresis = <2000>; 3974 type = "passive"; 3975 }; 3976 3977 cpu7_alert1: trip-point1 { 3978 temperature = <95000>; 3979 hysteresis = <2000>; 3980 type = "passive"; 3981 }; 3982 3983 cpu7_crit: cpu_crit { 3984 temperature = <110000>; 3985 hysteresis = <1000>; 3986 type = "critical"; 3987 }; 3988 }; 3989 3990 cooling-maps { 3991 map0 { 3992 trip = <&cpu7_alert0>; 3993 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3994 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3995 }; 3996 map1 { 3997 trip = <&cpu7_alert1>; 3998 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4000 }; 4001 }; 4002 }; 4003 4004 cpu8_thermal: cpu8-thermal { 4005 polling-delay-passive = <250>; 4006 polling-delay = <0>; 4007 4008 thermal-sensors = <&tsens0 11>; 4009 sustainable-power = <1425>; 4010 4011 trips { 4012 cpu8_alert0: trip-point0 { 4013 temperature = <90000>; 4014 hysteresis = <2000>; 4015 type = "passive"; 4016 }; 4017 4018 cpu8_alert1: trip-point1 { 4019 temperature = <95000>; 4020 hysteresis = <2000>; 4021 type = "passive"; 4022 }; 4023 4024 cpu8_crit: cpu_crit { 4025 temperature = <110000>; 4026 hysteresis = <1000>; 4027 type = "critical"; 4028 }; 4029 }; 4030 4031 cooling-maps { 4032 map0 { 4033 trip = <&cpu8_alert0>; 4034 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4036 }; 4037 map1 { 4038 trip = <&cpu8_alert1>; 4039 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4041 }; 4042 }; 4043 }; 4044 4045 cpu9_thermal: cpu9-thermal { 4046 polling-delay-passive = <250>; 4047 polling-delay = <0>; 4048 4049 thermal-sensors = <&tsens0 12>; 4050 sustainable-power = <1425>; 4051 4052 trips { 4053 cpu9_alert0: trip-point0 { 4054 temperature = <90000>; 4055 hysteresis = <2000>; 4056 type = "passive"; 4057 }; 4058 4059 cpu9_alert1: trip-point1 { 4060 temperature = <95000>; 4061 hysteresis = <2000>; 4062 type = "passive"; 4063 }; 4064 4065 cpu9_crit: cpu_crit { 4066 temperature = <110000>; 4067 hysteresis = <1000>; 4068 type = "critical"; 4069 }; 4070 }; 4071 4072 cooling-maps { 4073 map0 { 4074 trip = <&cpu9_alert0>; 4075 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4077 }; 4078 map1 { 4079 trip = <&cpu9_alert1>; 4080 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4082 }; 4083 }; 4084 }; 4085 4086 aoss0-thermal { 4087 polling-delay-passive = <250>; 4088 polling-delay = <0>; 4089 4090 thermal-sensors = <&tsens0 0>; 4091 4092 trips { 4093 aoss0_alert0: trip-point0 { 4094 temperature = <90000>; 4095 hysteresis = <2000>; 4096 type = "hot"; 4097 }; 4098 4099 aoss0_crit: aoss0_crit { 4100 temperature = <110000>; 4101 hysteresis = <2000>; 4102 type = "critical"; 4103 }; 4104 }; 4105 }; 4106 4107 cpuss0-thermal { 4108 polling-delay-passive = <250>; 4109 polling-delay = <0>; 4110 4111 thermal-sensors = <&tsens0 7>; 4112 4113 trips { 4114 cpuss0_alert0: trip-point0 { 4115 temperature = <90000>; 4116 hysteresis = <2000>; 4117 type = "hot"; 4118 }; 4119 cpuss0_crit: cluster0_crit { 4120 temperature = <110000>; 4121 hysteresis = <2000>; 4122 type = "critical"; 4123 }; 4124 }; 4125 }; 4126 4127 cpuss1-thermal { 4128 polling-delay-passive = <250>; 4129 polling-delay = <0>; 4130 4131 thermal-sensors = <&tsens0 8>; 4132 4133 trips { 4134 cpuss1_alert0: trip-point0 { 4135 temperature = <90000>; 4136 hysteresis = <2000>; 4137 type = "hot"; 4138 }; 4139 cpuss1_crit: cluster0_crit { 4140 temperature = <110000>; 4141 hysteresis = <2000>; 4142 type = "critical"; 4143 }; 4144 }; 4145 }; 4146 4147 gpuss0-thermal { 4148 polling-delay-passive = <250>; 4149 polling-delay = <0>; 4150 4151 thermal-sensors = <&tsens0 13>; 4152 4153 trips { 4154 gpuss0_alert0: trip-point0 { 4155 temperature = <95000>; 4156 hysteresis = <2000>; 4157 type = "passive"; 4158 }; 4159 4160 gpuss0_crit: gpuss0_crit { 4161 temperature = <110000>; 4162 hysteresis = <2000>; 4163 type = "critical"; 4164 }; 4165 }; 4166 4167 cooling-maps { 4168 map0 { 4169 trip = <&gpuss0_alert0>; 4170 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4171 }; 4172 }; 4173 }; 4174 4175 gpuss1-thermal { 4176 polling-delay-passive = <250>; 4177 polling-delay = <0>; 4178 4179 thermal-sensors = <&tsens0 14>; 4180 4181 trips { 4182 gpuss1_alert0: trip-point0 { 4183 temperature = <95000>; 4184 hysteresis = <2000>; 4185 type = "passive"; 4186 }; 4187 4188 gpuss1_crit: gpuss1_crit { 4189 temperature = <110000>; 4190 hysteresis = <2000>; 4191 type = "critical"; 4192 }; 4193 }; 4194 4195 cooling-maps { 4196 map0 { 4197 trip = <&gpuss1_alert0>; 4198 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4199 }; 4200 }; 4201 }; 4202 4203 aoss1-thermal { 4204 polling-delay-passive = <250>; 4205 polling-delay = <0>; 4206 4207 thermal-sensors = <&tsens1 0>; 4208 4209 trips { 4210 aoss1_alert0: trip-point0 { 4211 temperature = <90000>; 4212 hysteresis = <2000>; 4213 type = "hot"; 4214 }; 4215 4216 aoss1_crit: aoss1_crit { 4217 temperature = <110000>; 4218 hysteresis = <2000>; 4219 type = "critical"; 4220 }; 4221 }; 4222 }; 4223 4224 cwlan-thermal { 4225 polling-delay-passive = <250>; 4226 polling-delay = <0>; 4227 4228 thermal-sensors = <&tsens1 1>; 4229 4230 trips { 4231 cwlan_alert0: trip-point0 { 4232 temperature = <90000>; 4233 hysteresis = <2000>; 4234 type = "hot"; 4235 }; 4236 4237 cwlan_crit: cwlan_crit { 4238 temperature = <110000>; 4239 hysteresis = <2000>; 4240 type = "critical"; 4241 }; 4242 }; 4243 }; 4244 4245 audio-thermal { 4246 polling-delay-passive = <250>; 4247 polling-delay = <0>; 4248 4249 thermal-sensors = <&tsens1 2>; 4250 4251 trips { 4252 audio_alert0: trip-point0 { 4253 temperature = <90000>; 4254 hysteresis = <2000>; 4255 type = "hot"; 4256 }; 4257 4258 audio_crit: audio_crit { 4259 temperature = <110000>; 4260 hysteresis = <2000>; 4261 type = "critical"; 4262 }; 4263 }; 4264 }; 4265 4266 ddr-thermal { 4267 polling-delay-passive = <250>; 4268 polling-delay = <0>; 4269 4270 thermal-sensors = <&tsens1 3>; 4271 4272 trips { 4273 ddr_alert0: trip-point0 { 4274 temperature = <90000>; 4275 hysteresis = <2000>; 4276 type = "hot"; 4277 }; 4278 4279 ddr_crit: ddr_crit { 4280 temperature = <110000>; 4281 hysteresis = <2000>; 4282 type = "critical"; 4283 }; 4284 }; 4285 }; 4286 4287 q6-hvx-thermal { 4288 polling-delay-passive = <250>; 4289 polling-delay = <0>; 4290 4291 thermal-sensors = <&tsens1 4>; 4292 4293 trips { 4294 q6_hvx_alert0: trip-point0 { 4295 temperature = <90000>; 4296 hysteresis = <2000>; 4297 type = "hot"; 4298 }; 4299 4300 q6_hvx_crit: q6_hvx_crit { 4301 temperature = <110000>; 4302 hysteresis = <2000>; 4303 type = "critical"; 4304 }; 4305 }; 4306 }; 4307 4308 camera-thermal { 4309 polling-delay-passive = <250>; 4310 polling-delay = <0>; 4311 4312 thermal-sensors = <&tsens1 5>; 4313 4314 trips { 4315 camera_alert0: trip-point0 { 4316 temperature = <90000>; 4317 hysteresis = <2000>; 4318 type = "hot"; 4319 }; 4320 4321 camera_crit: camera_crit { 4322 temperature = <110000>; 4323 hysteresis = <2000>; 4324 type = "critical"; 4325 }; 4326 }; 4327 }; 4328 4329 mdm-core-thermal { 4330 polling-delay-passive = <250>; 4331 polling-delay = <0>; 4332 4333 thermal-sensors = <&tsens1 6>; 4334 4335 trips { 4336 mdm_alert0: trip-point0 { 4337 temperature = <90000>; 4338 hysteresis = <2000>; 4339 type = "hot"; 4340 }; 4341 4342 mdm_crit: mdm_crit { 4343 temperature = <110000>; 4344 hysteresis = <2000>; 4345 type = "critical"; 4346 }; 4347 }; 4348 }; 4349 4350 mdm-dsp-thermal { 4351 polling-delay-passive = <250>; 4352 polling-delay = <0>; 4353 4354 thermal-sensors = <&tsens1 7>; 4355 4356 trips { 4357 mdm_dsp_alert0: trip-point0 { 4358 temperature = <90000>; 4359 hysteresis = <2000>; 4360 type = "hot"; 4361 }; 4362 4363 mdm_dsp_crit: mdm_dsp_crit { 4364 temperature = <110000>; 4365 hysteresis = <2000>; 4366 type = "critical"; 4367 }; 4368 }; 4369 }; 4370 4371 npu-thermal { 4372 polling-delay-passive = <250>; 4373 polling-delay = <0>; 4374 4375 thermal-sensors = <&tsens1 8>; 4376 4377 trips { 4378 npu_alert0: trip-point0 { 4379 temperature = <90000>; 4380 hysteresis = <2000>; 4381 type = "hot"; 4382 }; 4383 4384 npu_crit: npu_crit { 4385 temperature = <110000>; 4386 hysteresis = <2000>; 4387 type = "critical"; 4388 }; 4389 }; 4390 }; 4391 4392 video-thermal { 4393 polling-delay-passive = <250>; 4394 polling-delay = <0>; 4395 4396 thermal-sensors = <&tsens1 9>; 4397 4398 trips { 4399 video_alert0: trip-point0 { 4400 temperature = <90000>; 4401 hysteresis = <2000>; 4402 type = "hot"; 4403 }; 4404 4405 video_crit: video_crit { 4406 temperature = <110000>; 4407 hysteresis = <2000>; 4408 type = "critical"; 4409 }; 4410 }; 4411 }; 4412 }; 4413 4414 timer { 4415 compatible = "arm,armv8-timer"; 4416 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4417 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4418 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4419 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4420 }; 4421}; 4422