1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16
17allOf:
18  - $ref: /schemas/pci/snps,dw-pcie.yaml#
19
20properties:
21  compatible:
22    enum:
23      - fsl,imx6q-pcie
24      - fsl,imx6sx-pcie
25      - fsl,imx6qp-pcie
26      - fsl,imx7d-pcie
27      - fsl,imx8mq-pcie
28
29  reg:
30    items:
31      - description: Data Bus Interface (DBI) registers.
32      - description: PCIe configuration space region.
33
34  reg-names:
35    items:
36      - const: dbi
37      - const: config
38
39  interrupts:
40    items:
41      - description: builtin MSI controller.
42
43  interrupt-names:
44    minItems: 1
45    items:
46      - const: msi
47
48  clocks:
49    minItems: 3
50    items:
51      - description: PCIe bridge clock.
52      - description: PCIe bus clock.
53      - description: PCIe PHY clock.
54      - description: Additional required clock entry for imx6sx-pcie,
55          imx8mq-pcie.
56
57  clock-names:
58    minItems: 3
59    items:
60      - const: pcie
61      - const: pcie_bus
62      - const: pcie_phy
63      - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
64
65  num-lanes:
66    const: 1
67
68  fsl,imx7d-pcie-phy:
69    $ref: /schemas/types.yaml#/definitions/phandle
70    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
71      required properties for imx7d-pcie and imx8mq-pcie.
72
73  power-domains:
74    items:
75      - description: The phandle pointing to the DISPLAY domain for
76          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
77          imx8mq-pcie.
78      - description: The phandle pointing to the PCIE_PHY power domains
79          for imx6sx-pcie.
80
81  power-domain-names:
82    items:
83      - const: pcie
84      - const: pcie_phy
85
86  resets:
87    maxItems: 3
88    description: Phandles to PCIe-related reset lines exposed by SRC
89      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
90
91  reset-names:
92    items:
93      - const: pciephy
94      - const: apps
95      - const: turnoff
96
97  fsl,tx-deemph-gen1:
98    description: Gen1 De-emphasis value (optional required).
99    $ref: /schemas/types.yaml#/definitions/uint32
100    default: 0
101
102  fsl,tx-deemph-gen2-3p5db:
103    description: Gen2 (3.5db) De-emphasis value (optional required).
104    $ref: /schemas/types.yaml#/definitions/uint32
105    default: 0
106
107  fsl,tx-deemph-gen2-6db:
108    description: Gen2 (6db) De-emphasis value (optional required).
109    $ref: /schemas/types.yaml#/definitions/uint32
110    default: 20
111
112  fsl,tx-swing-full:
113    description: Gen2 TX SWING FULL value (optional required).
114    $ref: /schemas/types.yaml#/definitions/uint32
115    default: 127
116
117  fsl,tx-swing-low:
118    description: TX launch amplitude swing_low value (optional required).
119    $ref: /schemas/types.yaml#/definitions/uint32
120    default: 127
121
122  fsl,max-link-speed:
123    description: Specify PCI Gen for link capability (optional required).
124      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
125      requirements and thus for gen2 capability a gen2 compliant clock
126      generator should be used and configured.
127    $ref: /schemas/types.yaml#/definitions/uint32
128    enum: [1, 2, 3, 4]
129    default: 1
130
131  reset-gpio:
132    description: Should specify the GPIO for controlling the PCI bus device
133      reset signal. It's not polarity aware and defaults to active-low reset
134      sequence (L=reset state, H=operation state) (optional required).
135
136  reset-gpio-active-high:
137    description: If present then the reset sequence using the GPIO
138      specified in the "reset-gpio" property is reversed (H=reset state,
139      L=operation state) (optional required).
140
141  vpcie-supply:
142    description: Should specify the regulator in charge of PCIe port power.
143      The regulator will be enabled when initializing the PCIe host and
144      disabled either as part of the init process or when shutting down
145      the host (optional required).
146
147  vph-supply:
148    description: Should specify the regulator in charge of VPH one of
149      the three PCIe PHY powers. This regulator can be supplied by both
150      1.8v and 3.3v voltage supplies (optional required).
151
152required:
153  - compatible
154  - reg
155  - reg-names
156  - "#address-cells"
157  - "#size-cells"
158  - device_type
159  - bus-range
160  - ranges
161  - num-lanes
162  - interrupts
163  - interrupt-names
164  - "#interrupt-cells"
165  - interrupt-map-mask
166  - interrupt-map
167  - clocks
168  - clock-names
169
170unevaluatedProperties: false
171
172examples:
173  - |
174    #include <dt-bindings/clock/imx6qdl-clock.h>
175    #include <dt-bindings/interrupt-controller/arm-gic.h>
176
177    pcie: pcie@1ffc000 {
178        compatible = "fsl,imx6q-pcie";
179        reg = <0x01ffc000 0x04000>,
180              <0x01f00000 0x80000>;
181        reg-names = "dbi", "config";
182        #address-cells = <3>;
183        #size-cells = <2>;
184        device_type = "pci";
185        bus-range = <0x00 0xff>;
186        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
187                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
188        num-lanes = <1>;
189        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
190        interrupt-names = "msi";
191        #interrupt-cells = <1>;
192        interrupt-map-mask = <0 0 0 0x7>;
193        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
194                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
195                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
196                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
197        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
198                <&clks IMX6QDL_CLK_LVDS1_GATE>,
199                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
200        clock-names = "pcie", "pcie_bus", "pcie_phy";
201    };
202...
203